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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-next-defconfig
in repository toolchain/ci/base-artifacts.
from 26e96993ed2 65: onsuccess: #22: boot: [TCWG CI] https://ci.linaro.org/j [...]
new 73053187fd3 66: onsuccess: #23: boot: [TCWG CI] https://ci.linaro.org/j [...]
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Summary of changes:
01-reset_artifacts/console.log.xz | Bin 1984 -> 2136 bytes
02-prepare_abe/console.log.xz | Bin 2436 -> 2432 bytes
03-build_abe-binutils/console.log.xz | Bin 27536 -> 28148 bytes
04-build_abe-stage1/console.log.xz | Bin 89996 -> 89944 bytes
05-build_abe-qemu/console.log.xz | Bin 31876 -> 31628 bytes
06-build_linux/console.log.xz | Bin 3192 -> 3176 bytes
07-boot_linux/console.log.xz | Bin 5732 -> 5676 bytes
08-check_regression/console.log.xz | Bin 436 -> 436 bytes
09-update_baseline/console.log | 14 --------------
git/binutils_rev | 2 +-
git/gcc_rev | 2 +-
git/linux_rev | 2 +-
git/qemu_rev | 2 +-
manifest.sh | 28 ++++++++++++++--------------
14 files changed, 18 insertions(+), 32 deletions(-)
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unknown user pushed a change to branch master
in repository gcc.
from a2676383adf RISC-V: Fix incorrect implementation of TARGET_VECTORIZE_SU [...]
new 04655110837 RISC-V: Insert vsetivli zero, 0 for vmv.x.s/vfmv.f.s instru [...]
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Summary of changes:
gcc/config/riscv/riscv-vsetvl.cc | 5 ++++
.../gcc.target/riscv/rvv/base/scalar_move-10.c | 31 ++++++++++++++++++++++
.../gcc.target/riscv/rvv/base/scalar_move-11.c | 20 ++++++++++++++
3 files changed, 56 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-10.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/scalar_move-11.c
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unknown user pushed a change to branch master
in repository gcc.
from 3ef0ebf901f New testcase
new 69f3914414a RISC-V: Fix dead loop for user vsetvli intrinsic avl checki [...]
new a2676383adf RISC-V: Fix incorrect implementation of TARGET_VECTORIZE_SU [...]
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Summary of changes:
gcc/config/riscv/riscv-vsetvl.cc | 25 +++++++++++++++++++++
gcc/config/riscv/riscv.cc | 21 ++++++-----------
gcc/testsuite/gcc.target/riscv/rvv/autovec/v-2.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/zve32f-2.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/zve32f-3.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/zve32x-2.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/zve32x-3.c | 2 +-
.../gcc.target/riscv/rvv/autovec/zve64d-2.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/zve64d-3.c | 4 ++--
.../riscv/rvv/autovec/zve64d_zvl128b-2.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/zve64f-2.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/zve64f-3.c | 4 ++--
.../riscv/rvv/autovec/zve64f_zvl128b-2.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/zve64x-2.c | 4 ++--
.../gcc.target/riscv/rvv/autovec/zve64x-3.c | 2 +-
.../riscv/rvv/autovec/zve64x_zvl128b-2.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/pr109773-1.c | 20 +++++++++++++++++
.../gcc.target/riscv/rvv/vsetvl/pr109773-2.c | 26 ++++++++++++++++++++++
18 files changed, 103 insertions(+), 39 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr109773-2.c
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