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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-defconfig
in repository toolchain/ci/base-artifacts.
from 6f88827099 48: onsuccess: #524: boot: Success after binutils/gcc/linux/ [...]
new b6b671d297 49: onsuccess: #525: boot: Success after binutils/gcc/linux/ [...]
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Summary of changes:
01-reset_artifacts/console.log.xz | Bin 1768 -> 1760 bytes
02-prepare_abe/console.log.xz | Bin 2780 -> 2780 bytes
03-build_abe-binutils/console.log.xz | Bin 31364 -> 31068 bytes
04-build_abe-stage1/console.log.xz | Bin 71400 -> 71716 bytes
05-build_abe-qemu/console.log.xz | Bin 32432 -> 31880 bytes
06-build_linux/console.log.xz | Bin 6316 -> 6312 bytes
07-boot_linux/console.log.xz | Bin 6132 -> 6132 bytes
08-check_regression/console.log.xz | Bin 4364 -> 4404 bytes
dashboard/dashboard-generate.sh | 2 +-
git/binutils_rev | 2 +-
git/gcc_rev | 2 +-
git/linux_rev | 2 +-
git/qemu_rev | 2 +-
mail/jira-body.txt | 2 +-
mail/mail-body.txt | 2 +-
mail/mail-subject.txt | 2 +-
manifest.sh | 32 ++++++++++++++++----------------
17 files changed, 24 insertions(+), 24 deletions(-)
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unknown user pushed a change to branch master
in repository gcc.
from 3da77f217c8 vect: inbranch SIMD clones
new aee5ee35602 Rust: In 'type_for_mode' langhook also consider all 'int_n' [...]
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Summary of changes:
gcc/rust/rust-lang.cc | 15 +++++++++++++++
1 file changed, 15 insertions(+)
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unknown user pushed a change to branch master
in repository gcc.
from c57fbdd6f11 RISC-V: Make the test condition more strict for gcc.target/ [...]
new dc244cdc05a RISC-V: Add floating-point RVV C/C++ api
new c878c6586de RISC-V: Add RVV reduction C/C++ intrinsics support
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Summary of changes:
gcc/config/riscv/iterators.md | 8 +-
gcc/config/riscv/riscv-vector-builtins-bases.cc | 867 ++++++++--
gcc/config/riscv/riscv-vector-builtins-bases.h | 76 +
.../riscv/riscv-vector-builtins-functions.def | 172 +-
gcc/config/riscv/riscv-vector-builtins-shapes.cc | 53 +-
gcc/config/riscv/riscv-vector-builtins-shapes.h | 1 +
gcc/config/riscv/riscv-vector-builtins-types.def | 152 ++
gcc/config/riscv/riscv-vector-builtins.cc | 498 +++++-
gcc/config/riscv/riscv-vector-builtins.def | 6 +-
gcc/config/riscv/riscv-vector-builtins.h | 14 +
gcc/config/riscv/riscv.md | 6 +-
gcc/config/riscv/vector-iterators.md | 229 ++-
gcc/config/riscv/vector.md | 1793 +++++++++++++++++++-
.../riscv/rvv/base/ternop_vv_constraint-3.c | 83 +
.../riscv/rvv/base/ternop_vv_constraint-4.c | 83 +
.../riscv/rvv/base/ternop_vv_constraint-5.c | 83 +
.../riscv/rvv/base/ternop_vv_constraint-6.c | 83 +
.../riscv/rvv/base/ternop_vx_constraint-8.c | 71 +
.../riscv/rvv/base/ternop_vx_constraint-9.c | 71 +
19 files changed, 4132 insertions(+), 217 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-4.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-5.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vv_constraint-6.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-8.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/ternop_vx_constraint-9.c
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