[binutils-gdb] branch master updated (779b2502783 -> be01687991a)
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unknown user pushed a change to branch master
in repository binutils-gdb.
from 779b2502783 RISC-V: Reduce effective linker relaxation passses
new be01687991a [gdb/cli] Add maint info frame-unwinders
The 1 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
gdb/NEWS | 4 ++++
gdb/doc/gdb.texinfo | 4 ++++
gdb/frame-unwind.c | 32 ++++++++++++++++++++++++++++++++
gdb/frame.c | 4 ++--
gdb/frame.h | 4 ++++
5 files changed, 46 insertions(+), 2 deletions(-)
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[gcc] branch master updated (2a37a4a3cbf -> edfc4402504)
by git＠git.linaro.org
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unknown user pushed a change to branch master
in repository gcc.
from 2a37a4a3cbf Revert "docs: add caveat for __builtin_cpu_supports"
new dc87e1391c5 tree-optimization/108724 - vectorized code getting piecewis [...]
new a035d133809 RISC-V: Add binary vx C/C++ support
new 649107f6d1f RISC-V: Add vmul.vv C API tests
new 1b0bd520f5a RISC-V: Add vmul.vv C++ API tests
new e9d5e4ac357 RISC-V: Add vxor.vx C API tests
new fe9e2eccb9e RISC-V: Add vsub.vx C API tests
new d2d6b0915e0 RISC-V: Add vrsub.vx C API tests
new b65e8a19002 RISC-V: Add vremu.vx C API tests
new dc4d66d543b RISC-V: Add vrem.vx C API tests
new 76cd8e80058 RISC-V: Add vor.vx C API tests
new ac843ce70e6 RISC-V: Add vmul.vx C API tests
new f82338eca2f RISC-V: Add vminu.vx C API tests
new 5255664d4ab RISC-V: Add vmin.vx C API tests
new a524f0c44f1 RISC-V: Add vmaxu.vx C API tests
new e6a085499cb RISC-V: Add vmax.vx C API tests
new 8f1320e0976 RISC-V: Add vdivu C API tests
new 5442df6cbdf RISC-V: Add vdiv.vx C API tests
new 9f35eb5d51b RISC-V: Add vand.vx C API tests
new f7bff05f5e9 RISC-V: Add vadd.vx C API tests
new ce4b00f393b RISC-V: Add binary op vx constraint tests
new 7d8c4a59fdf RISC-V: Add vxor.vx C++ API tests
new 525274d82f3 RISC-V: Add vsub.vx C++ API tests
new f0cd94672fc RISC-V: Add vrsub.vx C++ API tests
new 1e6324f7f36 RISC-V: Add vadd.vx C++ API tests
new d862fd1832a RISC-V: Add vremu.vx C++ API tests.
new 988cc529af6 RISC-V: Add vrem.vx C++ API tests
new 6289b83ffe2 RISC-V: Add vor.vx C++ API tests
new 8c971d59a7c RISC-V: Add vmul.vx C++ API testcase
new 679ba598453 RISC-V: Add vminu.vx C++ API tests
new 0e5ae1fad00 RISC-V: Add vmin.vx C++ API tests
new 66979d72eb9 RISC-V: Add vmaxu.vx C++ API tests.
new ae3ea1340de RISC-V: Add vmax.vx C++ API tests.
new 8189380d868 RISC-V: Add vdivu.vx C++ API tests
new e0e32c3397e RISC-V: Add vdiv.vx C++ API test.
new edfc4402504 RISC-V: Add vand.vx C++ API test.
The 35 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
gcc/config/riscv/constraints.md | 17 +-
gcc/config/riscv/predicates.md | 16 +-
gcc/config/riscv/riscv-protos.h | 8 +-
gcc/config/riscv/riscv-v.cc | 90 +++-
gcc/config/riscv/riscv-vector-builtins-bases.cc | 16 +-
gcc/config/riscv/riscv-vector-builtins-bases.h | 1 +
.../riscv/riscv-vector-builtins-functions.def | 31 +-
gcc/config/riscv/riscv-vector-builtins.cc | 51 ++
gcc/config/riscv/riscv.h | 2 +-
gcc/config/riscv/vector-iterators.md | 37 +-
gcc/config/riscv/vector.md | 366 ++++++++++++-
.../base/{vadd_vv_mu-1.C => vadd_vx_mu_rv32-1.C} | 129 +++--
.../base/{vadd_vv_mu-2.C => vadd_vx_mu_rv32-2.C} | 129 +++--
.../base/{vadd_vv_mu-3.C => vadd_vx_mu_rv32-3.C} | 129 +++--
.../base/{vadd_vv_mu-1.C => vadd_vx_mu_rv64-1.C} | 134 ++---
.../base/{vadd_vv_mu-2.C => vadd_vx_mu_rv64-2.C} | 134 ++---
.../base/{vadd_vv_mu-3.C => vadd_vx_mu_rv64-3.C} | 134 ++---
.../g++.target/riscv/rvv/base/vadd_vx_rv32-1.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadd_vx_rv32-2.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadd_vx_rv32-3.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadd_vx_rv64-1.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadd_vx_rv64-2.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vadd_vx_rv64-3.C | 578 +++++++++++++++++++++
.../base/{vadd_vv_tu-1.C => vadd_vx_tu_rv32-1.C} | 129 +++--
.../base/{vadd_vv_tu-2.C => vadd_vx_tu_rv32-2.C} | 129 +++--
.../base/{vadd_vv_tu-3.C => vadd_vx_tu_rv32-3.C} | 129 +++--
.../base/{vadd_vv_tu-1.C => vadd_vx_tu_rv64-1.C} | 134 ++---
.../base/{vadd_vv_tu-2.C => vadd_vx_tu_rv64-2.C} | 134 ++---
.../base/{vadd_vv_tu-3.C => vadd_vx_tu_rv64-3.C} | 134 ++---
.../base/{vadd_vv_tum-1.C => vadd_vx_tum_rv32-1.C} | 129 +++--
.../base/{vadd_vv_tum-2.C => vadd_vx_tum_rv32-2.C} | 129 +++--
.../base/{vadd_vv_tum-3.C => vadd_vx_tum_rv32-3.C} | 129 +++--
.../base/{vadd_vv_tum-1.C => vadd_vx_tum_rv64-1.C} | 134 ++---
.../base/{vadd_vv_tum-2.C => vadd_vx_tum_rv64-2.C} | 134 ++---
.../base/{vadd_vv_tum-3.C => vadd_vx_tum_rv64-3.C} | 134 ++---
.../{vadd_vv_tumu-1.C => vadd_vx_tumu_rv32-1.C} | 129 +++--
.../{vadd_vv_tumu-2.C => vadd_vx_tumu_rv32-2.C} | 129 +++--
.../{vadd_vv_tumu-3.C => vadd_vx_tumu_rv32-3.C} | 129 +++--
.../{vadd_vv_tumu-1.C => vadd_vx_tumu_rv64-1.C} | 134 ++---
.../{vadd_vv_tumu-2.C => vadd_vx_tumu_rv64-2.C} | 134 ++---
.../{vadd_vv_tumu-3.C => vadd_vx_tumu_rv64-3.C} | 134 ++---
.../base/{vand_vv_mu-1.C => vand_vx_mu_rv32-1.C} | 129 +++--
.../base/{vand_vv_mu-2.C => vand_vx_mu_rv32-2.C} | 129 +++--
.../base/{vand_vv_mu-3.C => vand_vx_mu_rv32-3.C} | 129 +++--
.../base/{vand_vv_mu-1.C => vand_vx_mu_rv64-1.C} | 134 ++---
.../base/{vand_vv_mu-2.C => vand_vx_mu_rv64-2.C} | 134 ++---
.../base/{vand_vv_mu-3.C => vand_vx_mu_rv64-3.C} | 134 ++---
.../g++.target/riscv/rvv/base/vand_vx_rv32-1.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vand_vx_rv32-2.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vand_vx_rv32-3.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vand_vx_rv64-1.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vand_vx_rv64-2.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vand_vx_rv64-3.C | 578 +++++++++++++++++++++
.../base/{vand_vv_tu-1.C => vand_vx_tu_rv32-1.C} | 129 +++--
.../base/{vand_vv_tu-2.C => vand_vx_tu_rv32-2.C} | 129 +++--
.../base/{vand_vv_tu-3.C => vand_vx_tu_rv32-3.C} | 129 +++--
.../base/{vand_vv_tu-1.C => vand_vx_tu_rv64-1.C} | 134 ++---
.../base/{vand_vv_tu-2.C => vand_vx_tu_rv64-2.C} | 134 ++---
.../base/{vand_vv_tu-3.C => vand_vx_tu_rv64-3.C} | 134 ++---
.../base/{vand_vv_tum-1.C => vand_vx_tum_rv32-1.C} | 129 +++--
.../base/{vand_vv_tum-2.C => vand_vx_tum_rv32-2.C} | 129 +++--
.../base/{vand_vv_tum-3.C => vand_vx_tum_rv32-3.C} | 129 +++--
.../base/{vand_vv_tum-1.C => vand_vx_tum_rv64-1.C} | 134 ++---
.../base/{vand_vv_tum-2.C => vand_vx_tum_rv64-2.C} | 134 ++---
.../base/{vand_vv_tum-3.C => vand_vx_tum_rv64-3.C} | 134 ++---
.../{vand_vv_tumu-1.C => vand_vx_tumu_rv32-1.C} | 129 +++--
.../{vand_vv_tumu-2.C => vand_vx_tumu_rv32-2.C} | 129 +++--
.../{vand_vv_tumu-3.C => vand_vx_tumu_rv32-3.C} | 129 +++--
.../{vand_vv_tumu-1.C => vand_vx_tumu_rv64-1.C} | 134 ++---
.../{vand_vv_tumu-2.C => vand_vx_tumu_rv64-2.C} | 134 ++---
.../{vand_vv_tumu-3.C => vand_vx_tumu_rv64-3.C} | 134 ++---
.../base/{vdiv_vv_mu-1.C => vdiv_vx_mu_rv32-1.C} | 85 ++-
.../base/{vdiv_vv_mu-2.C => vdiv_vx_mu_rv32-2.C} | 85 ++-
.../base/{vdiv_vv_mu-3.C => vdiv_vx_mu_rv32-3.C} | 85 ++-
.../base/{vdiv_vv_mu-1.C => vdiv_vx_mu_rv64-1.C} | 90 ++--
.../base/{vdiv_vv_mu-2.C => vdiv_vx_mu_rv64-2.C} | 90 ++--
.../base/{vdiv_vv_mu-3.C => vdiv_vx_mu_rv64-3.C} | 90 ++--
.../g++.target/riscv/rvv/base/vdiv_vx_rv32-1.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vdiv_vx_rv32-2.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vdiv_vx_rv32-3.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vdiv_vx_rv64-1.C | 314 +++++++++++
.../g++.target/riscv/rvv/base/vdiv_vx_rv64-2.C | 314 +++++++++++
.../g++.target/riscv/rvv/base/vdiv_vx_rv64-3.C | 314 +++++++++++
.../base/{vdiv_vv_tu-1.C => vdiv_vx_tu_rv32-1.C} | 85 ++-
.../base/{vdiv_vv_tu-2.C => vdiv_vx_tu_rv32-2.C} | 85 ++-
.../base/{vdiv_vv_tu-3.C => vdiv_vx_tu_rv32-3.C} | 85 ++-
.../base/{vdiv_vv_tu-1.C => vdiv_vx_tu_rv64-1.C} | 90 ++--
.../base/{vdiv_vv_tu-2.C => vdiv_vx_tu_rv64-2.C} | 90 ++--
.../base/{vdiv_vv_tu-3.C => vdiv_vx_tu_rv64-3.C} | 90 ++--
.../base/{vdiv_vv_tum-1.C => vdiv_vx_tum_rv32-1.C} | 85 ++-
.../base/{vdiv_vv_tum-2.C => vdiv_vx_tum_rv32-2.C} | 85 ++-
.../base/{vdiv_vv_tum-3.C => vdiv_vx_tum_rv32-3.C} | 85 ++-
.../base/{vdiv_vv_tum-1.C => vdiv_vx_tum_rv64-1.C} | 90 ++--
.../base/{vdiv_vv_tum-2.C => vdiv_vx_tum_rv64-2.C} | 90 ++--
.../base/{vdiv_vv_tum-3.C => vdiv_vx_tum_rv64-3.C} | 90 ++--
.../{vdiv_vv_tumu-1.C => vdiv_vx_tumu_rv32-1.C} | 85 ++-
.../{vdiv_vv_tumu-2.C => vdiv_vx_tumu_rv32-2.C} | 85 ++-
.../{vdiv_vv_tumu-3.C => vdiv_vx_tumu_rv32-3.C} | 85 ++-
.../{vdiv_vv_tumu-1.C => vdiv_vx_tumu_rv64-1.C} | 90 ++--
.../{vdiv_vv_tumu-2.C => vdiv_vx_tumu_rv64-2.C} | 90 ++--
.../{vdiv_vv_tumu-3.C => vdiv_vx_tumu_rv64-3.C} | 90 ++--
.../base/{vdivu_vv_mu-1.C => vdivu_vx_mu_rv32-1.C} | 85 ++-
.../base/{vdivu_vv_mu-2.C => vdivu_vx_mu_rv32-2.C} | 85 ++-
.../base/{vdivu_vv_mu-3.C => vdivu_vx_mu_rv32-3.C} | 85 ++-
.../base/{vdivu_vv_mu-1.C => vdivu_vx_mu_rv64-1.C} | 90 ++--
.../base/{vdivu_vv_mu-2.C => vdivu_vx_mu_rv64-2.C} | 90 ++--
.../base/{vdivu_vv_mu-3.C => vdivu_vx_mu_rv64-3.C} | 90 ++--
.../g++.target/riscv/rvv/base/vdivu_vx_rv32-1.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vdivu_vx_rv32-2.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vdivu_vx_rv32-3.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vdivu_vx_rv64-1.C | 314 +++++++++++
.../g++.target/riscv/rvv/base/vdivu_vx_rv64-2.C | 314 +++++++++++
.../g++.target/riscv/rvv/base/vdivu_vx_rv64-3.C | 314 +++++++++++
.../base/{vdivu_vv_tu-1.C => vdivu_vx_tu_rv32-1.C} | 85 ++-
.../base/{vdivu_vv_tu-2.C => vdivu_vx_tu_rv32-2.C} | 85 ++-
.../base/{vdivu_vv_tu-3.C => vdivu_vx_tu_rv32-3.C} | 85 ++-
.../base/{vdivu_vv_tu-1.C => vdivu_vx_tu_rv64-1.C} | 90 ++--
.../base/{vdivu_vv_tu-2.C => vdivu_vx_tu_rv64-2.C} | 90 ++--
.../base/{vdivu_vv_tu-3.C => vdivu_vx_tu_rv64-3.C} | 90 ++--
.../{vdivu_vv_tum-1.C => vdivu_vx_tum_rv32-1.C} | 85 ++-
.../{vdivu_vv_tum-2.C => vdivu_vx_tum_rv32-2.C} | 85 ++-
.../{vdivu_vv_tum-3.C => vdivu_vx_tum_rv32-3.C} | 85 ++-
.../{vdivu_vv_tum-1.C => vdivu_vx_tum_rv64-1.C} | 90 ++--
.../{vdivu_vv_tum-2.C => vdivu_vx_tum_rv64-2.C} | 90 ++--
.../{vdivu_vv_tum-3.C => vdivu_vx_tum_rv64-3.C} | 90 ++--
.../{vdivu_vv_tumu-1.C => vdivu_vx_tumu_rv32-1.C} | 85 ++-
.../{vdivu_vv_tumu-2.C => vdivu_vx_tumu_rv32-2.C} | 85 ++-
.../{vdivu_vv_tumu-3.C => vdivu_vx_tumu_rv32-3.C} | 85 ++-
.../{vdivu_vv_tumu-1.C => vdivu_vx_tumu_rv64-1.C} | 90 ++--
.../{vdivu_vv_tumu-2.C => vdivu_vx_tumu_rv64-2.C} | 90 ++--
.../{vdivu_vv_tumu-3.C => vdivu_vx_tumu_rv64-3.C} | 90 ++--
.../base/{vmax_vv_mu-1.C => vmax_vx_mu_rv32-1.C} | 85 ++-
.../base/{vmax_vv_mu-2.C => vmax_vx_mu_rv32-2.C} | 85 ++-
.../base/{vmax_vv_mu-3.C => vmax_vx_mu_rv32-3.C} | 85 ++-
.../base/{vmax_vv_mu-1.C => vmax_vx_mu_rv64-1.C} | 90 ++--
.../base/{vmax_vv_mu-2.C => vmax_vx_mu_rv64-2.C} | 90 ++--
.../base/{vmax_vv_mu-3.C => vmax_vx_mu_rv64-3.C} | 90 ++--
.../g++.target/riscv/rvv/base/vmax_vx_rv32-1.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vmax_vx_rv32-2.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vmax_vx_rv32-3.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vmax_vx_rv64-1.C | 314 +++++++++++
.../g++.target/riscv/rvv/base/vmax_vx_rv64-2.C | 314 +++++++++++
.../g++.target/riscv/rvv/base/vmax_vx_rv64-3.C | 314 +++++++++++
.../base/{vmax_vv_tu-1.C => vmax_vx_tu_rv32-1.C} | 85 ++-
.../base/{vmax_vv_tu-2.C => vmax_vx_tu_rv32-2.C} | 85 ++-
.../base/{vmax_vv_tu-3.C => vmax_vx_tu_rv32-3.C} | 85 ++-
.../base/{vmax_vv_tu-1.C => vmax_vx_tu_rv64-1.C} | 90 ++--
.../base/{vmax_vv_tu-2.C => vmax_vx_tu_rv64-2.C} | 90 ++--
.../base/{vmax_vv_tu-3.C => vmax_vx_tu_rv64-3.C} | 90 ++--
.../base/{vmax_vv_tum-1.C => vmax_vx_tum_rv32-1.C} | 85 ++-
.../base/{vmax_vv_tum-2.C => vmax_vx_tum_rv32-2.C} | 85 ++-
.../base/{vmax_vv_tum-3.C => vmax_vx_tum_rv32-3.C} | 85 ++-
.../base/{vmax_vv_tum-1.C => vmax_vx_tum_rv64-1.C} | 90 ++--
.../base/{vmax_vv_tum-2.C => vmax_vx_tum_rv64-2.C} | 90 ++--
.../base/{vmax_vv_tum-3.C => vmax_vx_tum_rv64-3.C} | 90 ++--
.../{vmax_vv_tumu-1.C => vmax_vx_tumu_rv32-1.C} | 85 ++-
.../{vmax_vv_tumu-2.C => vmax_vx_tumu_rv32-2.C} | 85 ++-
.../{vmax_vv_tumu-3.C => vmax_vx_tumu_rv32-3.C} | 85 ++-
.../{vmax_vv_tumu-1.C => vmax_vx_tumu_rv64-1.C} | 90 ++--
.../{vmax_vv_tumu-2.C => vmax_vx_tumu_rv64-2.C} | 90 ++--
.../{vmax_vv_tumu-3.C => vmax_vx_tumu_rv64-3.C} | 90 ++--
.../base/{vmaxu_vv_mu-1.C => vmaxu_vx_mu_rv32-1.C} | 85 ++-
.../base/{vmaxu_vv_mu-2.C => vmaxu_vx_mu_rv32-2.C} | 85 ++-
.../base/{vmaxu_vv_mu-3.C => vmaxu_vx_mu_rv32-3.C} | 85 ++-
.../base/{vmaxu_vv_mu-1.C => vmaxu_vx_mu_rv64-1.C} | 90 ++--
.../base/{vmaxu_vv_mu-2.C => vmaxu_vx_mu_rv64-2.C} | 90 ++--
.../base/{vmaxu_vv_mu-3.C => vmaxu_vx_mu_rv64-3.C} | 90 ++--
.../g++.target/riscv/rvv/base/vmaxu_vx_rv32-1.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vmaxu_vx_rv32-2.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vmaxu_vx_rv32-3.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vmaxu_vx_rv64-1.C | 314 +++++++++++
.../g++.target/riscv/rvv/base/vmaxu_vx_rv64-2.C | 314 +++++++++++
.../g++.target/riscv/rvv/base/vmaxu_vx_rv64-3.C | 314 +++++++++++
.../base/{vmaxu_vv_tu-1.C => vmaxu_vx_tu_rv32-1.C} | 85 ++-
.../base/{vmaxu_vv_tu-2.C => vmaxu_vx_tu_rv32-2.C} | 85 ++-
.../base/{vmaxu_vv_tu-3.C => vmaxu_vx_tu_rv32-3.C} | 85 ++-
.../base/{vmaxu_vv_tu-1.C => vmaxu_vx_tu_rv64-1.C} | 90 ++--
.../base/{vmaxu_vv_tu-2.C => vmaxu_vx_tu_rv64-2.C} | 90 ++--
.../base/{vmaxu_vv_tu-3.C => vmaxu_vx_tu_rv64-3.C} | 90 ++--
.../{vmaxu_vv_tum-1.C => vmaxu_vx_tum_rv32-1.C} | 85 ++-
.../{vmaxu_vv_tum-2.C => vmaxu_vx_tum_rv32-2.C} | 85 ++-
.../{vmaxu_vv_tum-3.C => vmaxu_vx_tum_rv32-3.C} | 85 ++-
.../{vmaxu_vv_tum-1.C => vmaxu_vx_tum_rv64-1.C} | 90 ++--
.../{vmaxu_vv_tum-2.C => vmaxu_vx_tum_rv64-2.C} | 90 ++--
.../{vmaxu_vv_tum-3.C => vmaxu_vx_tum_rv64-3.C} | 90 ++--
.../{vmaxu_vv_tumu-1.C => vmaxu_vx_tumu_rv32-1.C} | 85 ++-
.../{vmaxu_vv_tumu-2.C => vmaxu_vx_tumu_rv32-2.C} | 85 ++-
.../{vmaxu_vv_tumu-3.C => vmaxu_vx_tumu_rv32-3.C} | 85 ++-
.../{vmaxu_vv_tumu-1.C => vmaxu_vx_tumu_rv64-1.C} | 90 ++--
.../{vmaxu_vv_tumu-2.C => vmaxu_vx_tumu_rv64-2.C} | 90 ++--
.../{vmaxu_vv_tumu-3.C => vmaxu_vx_tumu_rv64-3.C} | 90 ++--
.../base/{vmin_vv_mu-1.C => vmin_vx_mu_rv32-1.C} | 85 ++-
.../base/{vmin_vv_mu-2.C => vmin_vx_mu_rv32-2.C} | 85 ++-
.../base/{vmin_vv_mu-3.C => vmin_vx_mu_rv32-3.C} | 85 ++-
.../base/{vmin_vv_mu-1.C => vmin_vx_mu_rv64-1.C} | 90 ++--
.../base/{vmin_vv_mu-2.C => vmin_vx_mu_rv64-2.C} | 90 ++--
.../base/{vmin_vv_mu-3.C => vmin_vx_mu_rv64-3.C} | 90 ++--
.../g++.target/riscv/rvv/base/vmin_vx_rv32-1.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vmin_vx_rv32-2.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vmin_vx_rv32-3.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vmin_vx_rv64-1.C | 314 +++++++++++
.../g++.target/riscv/rvv/base/vmin_vx_rv64-2.C | 314 +++++++++++
.../g++.target/riscv/rvv/base/vmin_vx_rv64-3.C | 314 +++++++++++
.../base/{vmin_vv_tu-1.C => vmin_vx_tu_rv32-1.C} | 85 ++-
.../base/{vmin_vv_tu-2.C => vmin_vx_tu_rv32-2.C} | 85 ++-
.../base/{vmin_vv_tu-3.C => vmin_vx_tu_rv32-3.C} | 85 ++-
.../base/{vmin_vv_tu-1.C => vmin_vx_tu_rv64-1.C} | 90 ++--
.../base/{vmin_vv_tu-2.C => vmin_vx_tu_rv64-2.C} | 90 ++--
.../base/{vmin_vv_tu-3.C => vmin_vx_tu_rv64-3.C} | 90 ++--
.../base/{vmin_vv_tum-1.C => vmin_vx_tum_rv32-1.C} | 85 ++-
.../base/{vmin_vv_tum-2.C => vmin_vx_tum_rv32-2.C} | 85 ++-
.../base/{vmin_vv_tum-3.C => vmin_vx_tum_rv32-3.C} | 85 ++-
.../base/{vmin_vv_tum-1.C => vmin_vx_tum_rv64-1.C} | 90 ++--
.../base/{vmin_vv_tum-2.C => vmin_vx_tum_rv64-2.C} | 90 ++--
.../base/{vmin_vv_tum-3.C => vmin_vx_tum_rv64-3.C} | 90 ++--
.../{vmin_vv_tumu-1.C => vmin_vx_tumu_rv32-1.C} | 85 ++-
.../{vmin_vv_tumu-2.C => vmin_vx_tumu_rv32-2.C} | 85 ++-
.../{vmin_vv_tumu-3.C => vmin_vx_tumu_rv32-3.C} | 85 ++-
.../{vmin_vv_tumu-1.C => vmin_vx_tumu_rv64-1.C} | 90 ++--
.../{vmin_vv_tumu-2.C => vmin_vx_tumu_rv64-2.C} | 90 ++--
.../{vmin_vv_tumu-3.C => vmin_vx_tumu_rv64-3.C} | 90 ++--
.../base/{vminu_vv_mu-1.C => vminu_vx_mu_rv32-1.C} | 85 ++-
.../base/{vminu_vv_mu-2.C => vminu_vx_mu_rv32-2.C} | 85 ++-
.../base/{vminu_vv_mu-3.C => vminu_vx_mu_rv32-3.C} | 85 ++-
.../base/{vminu_vv_mu-1.C => vminu_vx_mu_rv64-1.C} | 90 ++--
.../base/{vminu_vv_mu-2.C => vminu_vx_mu_rv64-2.C} | 90 ++--
.../base/{vminu_vv_mu-3.C => vminu_vx_mu_rv64-3.C} | 90 ++--
.../g++.target/riscv/rvv/base/vminu_vx_rv32-1.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vminu_vx_rv32-2.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vminu_vx_rv32-3.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vminu_vx_rv64-1.C | 314 +++++++++++
.../g++.target/riscv/rvv/base/vminu_vx_rv64-2.C | 314 +++++++++++
.../g++.target/riscv/rvv/base/vminu_vx_rv64-3.C | 314 +++++++++++
.../base/{vminu_vv_tu-1.C => vminu_vx_tu_rv32-1.C} | 85 ++-
.../base/{vminu_vv_tu-2.C => vminu_vx_tu_rv32-2.C} | 85 ++-
.../base/{vminu_vv_tu-3.C => vminu_vx_tu_rv32-3.C} | 85 ++-
.../base/{vminu_vv_tu-1.C => vminu_vx_tu_rv64-1.C} | 90 ++--
.../base/{vminu_vv_tu-2.C => vminu_vx_tu_rv64-2.C} | 90 ++--
.../base/{vminu_vv_tu-3.C => vminu_vx_tu_rv64-3.C} | 90 ++--
.../{vminu_vv_tum-1.C => vminu_vx_tum_rv32-1.C} | 85 ++-
.../{vminu_vv_tum-2.C => vminu_vx_tum_rv32-2.C} | 85 ++-
.../{vminu_vv_tum-3.C => vminu_vx_tum_rv32-3.C} | 85 ++-
.../{vminu_vv_tum-1.C => vminu_vx_tum_rv64-1.C} | 90 ++--
.../{vminu_vv_tum-2.C => vminu_vx_tum_rv64-2.C} | 90 ++--
.../{vminu_vv_tum-3.C => vminu_vx_tum_rv64-3.C} | 90 ++--
.../{vminu_vv_tumu-1.C => vminu_vx_tumu_rv32-1.C} | 85 ++-
.../{vminu_vv_tumu-2.C => vminu_vx_tumu_rv32-2.C} | 85 ++-
.../{vminu_vv_tumu-3.C => vminu_vx_tumu_rv32-3.C} | 85 ++-
.../{vminu_vv_tumu-1.C => vminu_vx_tumu_rv64-1.C} | 90 ++--
.../{vminu_vv_tumu-2.C => vminu_vx_tumu_rv64-2.C} | 90 ++--
.../{vminu_vv_tumu-3.C => vminu_vx_tumu_rv64-3.C} | 90 ++--
.../g++.target/riscv/rvv/base/vmul_vv-1.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vmul_vv-2.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vmul_vv-3.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vmul_vv_mu-1.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vv_mu-2.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vv_mu-3.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vv_tu-1.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vv_tu-2.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vv_tu-3.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vv_tum-1.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vv_tum-2.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vv_tum-3.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vv_tumu-1.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vv_tumu-2.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vv_tumu-3.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_mu_rv32-1.C | 289 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_mu_rv32-2.C | 289 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_mu_rv32-3.C | 289 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_mu_rv64-1.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_mu_rv64-2.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_mu_rv64-3.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_rv32-1.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_rv32-2.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_rv32-3.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_rv64-1.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_rv64-2.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_rv64-3.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_tu_rv32-1.C | 289 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_tu_rv32-2.C | 289 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_tu_rv32-3.C | 289 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_tu_rv64-1.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_tu_rv64-2.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_tu_rv64-3.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_tum_rv32-1.C | 289 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_tum_rv32-2.C | 289 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_tum_rv32-3.C | 289 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_tum_rv64-1.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_tum_rv64-2.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vmul_vx_tum_rv64-3.C | 292 +++++++++++
.../riscv/rvv/base/vmul_vx_tumu_rv32-1.C | 289 +++++++++++
.../riscv/rvv/base/vmul_vx_tumu_rv32-2.C | 289 +++++++++++
.../riscv/rvv/base/vmul_vx_tumu_rv32-3.C | 289 +++++++++++
.../riscv/rvv/base/vmul_vx_tumu_rv64-1.C | 292 +++++++++++
.../riscv/rvv/base/vmul_vx_tumu_rv64-2.C | 292 +++++++++++
.../riscv/rvv/base/vmul_vx_tumu_rv64-3.C | 292 +++++++++++
.../rvv/base/{vor_vv_mu-1.C => vor_vx_mu_rv32-1.C} | 129 +++--
.../rvv/base/{vor_vv_mu-2.C => vor_vx_mu_rv32-2.C} | 129 +++--
.../rvv/base/{vor_vv_mu-3.C => vor_vx_mu_rv32-3.C} | 129 +++--
.../rvv/base/{vor_vv_mu-1.C => vor_vx_mu_rv64-1.C} | 134 ++---
.../rvv/base/{vor_vv_mu-2.C => vor_vx_mu_rv64-2.C} | 134 ++---
.../rvv/base/{vor_vv_mu-3.C => vor_vx_mu_rv64-3.C} | 134 ++---
.../g++.target/riscv/rvv/base/vor_vx_rv32-1.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vor_vx_rv32-2.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vor_vx_rv32-3.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vor_vx_rv64-1.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vor_vx_rv64-2.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vor_vx_rv64-3.C | 578 +++++++++++++++++++++
.../rvv/base/{vor_vv_tu-1.C => vor_vx_tu_rv32-1.C} | 129 +++--
.../rvv/base/{vor_vv_tu-2.C => vor_vx_tu_rv32-2.C} | 129 +++--
.../rvv/base/{vor_vv_tu-3.C => vor_vx_tu_rv32-3.C} | 129 +++--
.../rvv/base/{vor_vv_tu-1.C => vor_vx_tu_rv64-1.C} | 134 ++---
.../rvv/base/{vor_vv_tu-2.C => vor_vx_tu_rv64-2.C} | 134 ++---
.../rvv/base/{vor_vv_tu-3.C => vor_vx_tu_rv64-3.C} | 134 ++---
.../base/{vor_vv_tum-1.C => vor_vx_tum_rv32-1.C} | 129 +++--
.../base/{vor_vv_tum-2.C => vor_vx_tum_rv32-2.C} | 129 +++--
.../base/{vor_vv_tum-3.C => vor_vx_tum_rv32-3.C} | 129 +++--
.../base/{vor_vv_tum-1.C => vor_vx_tum_rv64-1.C} | 134 ++---
.../base/{vor_vv_tum-2.C => vor_vx_tum_rv64-2.C} | 134 ++---
.../base/{vor_vv_tum-3.C => vor_vx_tum_rv64-3.C} | 134 ++---
.../base/{vor_vv_tumu-1.C => vor_vx_tumu_rv32-1.C} | 129 +++--
.../base/{vor_vv_tumu-2.C => vor_vx_tumu_rv32-2.C} | 129 +++--
.../base/{vor_vv_tumu-3.C => vor_vx_tumu_rv32-3.C} | 129 +++--
.../base/{vor_vv_tumu-1.C => vor_vx_tumu_rv64-1.C} | 134 ++---
.../base/{vor_vv_tumu-2.C => vor_vx_tumu_rv64-2.C} | 134 ++---
.../base/{vor_vv_tumu-3.C => vor_vx_tumu_rv64-3.C} | 134 ++---
.../base/{vrem_vv_mu-1.C => vrem_vx_mu_rv32-1.C} | 85 ++-
.../base/{vrem_vv_mu-2.C => vrem_vx_mu_rv32-2.C} | 85 ++-
.../base/{vrem_vv_mu-3.C => vrem_vx_mu_rv32-3.C} | 85 ++-
.../base/{vrem_vv_mu-1.C => vrem_vx_mu_rv64-1.C} | 90 ++--
.../base/{vrem_vv_mu-2.C => vrem_vx_mu_rv64-2.C} | 90 ++--
.../base/{vrem_vv_mu-3.C => vrem_vx_mu_rv64-3.C} | 90 ++--
.../g++.target/riscv/rvv/base/vrem_vx_rv32-1.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vrem_vx_rv32-2.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vrem_vx_rv32-3.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vrem_vx_rv64-1.C | 314 +++++++++++
.../g++.target/riscv/rvv/base/vrem_vx_rv64-2.C | 314 +++++++++++
.../g++.target/riscv/rvv/base/vrem_vx_rv64-3.C | 314 +++++++++++
.../base/{vrem_vv_tu-1.C => vrem_vx_tu_rv32-1.C} | 85 ++-
.../base/{vrem_vv_tu-2.C => vrem_vx_tu_rv32-2.C} | 85 ++-
.../base/{vrem_vv_tu-3.C => vrem_vx_tu_rv32-3.C} | 85 ++-
.../base/{vrem_vv_tu-1.C => vrem_vx_tu_rv64-1.C} | 90 ++--
.../base/{vrem_vv_tu-2.C => vrem_vx_tu_rv64-2.C} | 90 ++--
.../base/{vrem_vv_tu-3.C => vrem_vx_tu_rv64-3.C} | 90 ++--
.../base/{vrem_vv_tum-1.C => vrem_vx_tum_rv32-1.C} | 85 ++-
.../base/{vrem_vv_tum-2.C => vrem_vx_tum_rv32-2.C} | 85 ++-
.../base/{vrem_vv_tum-3.C => vrem_vx_tum_rv32-3.C} | 85 ++-
.../base/{vrem_vv_tum-1.C => vrem_vx_tum_rv64-1.C} | 90 ++--
.../base/{vrem_vv_tum-2.C => vrem_vx_tum_rv64-2.C} | 90 ++--
.../base/{vrem_vv_tum-3.C => vrem_vx_tum_rv64-3.C} | 90 ++--
.../{vrem_vv_tumu-1.C => vrem_vx_tumu_rv32-1.C} | 85 ++-
.../{vrem_vv_tumu-2.C => vrem_vx_tumu_rv32-2.C} | 85 ++-
.../{vrem_vv_tumu-3.C => vrem_vx_tumu_rv32-3.C} | 85 ++-
.../{vrem_vv_tumu-1.C => vrem_vx_tumu_rv64-1.C} | 90 ++--
.../{vrem_vv_tumu-2.C => vrem_vx_tumu_rv64-2.C} | 90 ++--
.../{vrem_vv_tumu-3.C => vrem_vx_tumu_rv64-3.C} | 90 ++--
.../base/{vremu_vv_mu-1.C => vremu_vx_mu_rv32-1.C} | 85 ++-
.../base/{vremu_vv_mu-2.C => vremu_vx_mu_rv32-2.C} | 85 ++-
.../base/{vremu_vv_mu-3.C => vremu_vx_mu_rv32-3.C} | 85 ++-
.../base/{vremu_vv_mu-1.C => vremu_vx_mu_rv64-1.C} | 90 ++--
.../base/{vremu_vv_mu-2.C => vremu_vx_mu_rv64-2.C} | 90 ++--
.../base/{vremu_vv_mu-3.C => vremu_vx_mu_rv64-3.C} | 90 ++--
.../g++.target/riscv/rvv/base/vremu_vx_rv32-1.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vremu_vx_rv32-2.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vremu_vx_rv32-3.C | 308 +++++++++++
.../g++.target/riscv/rvv/base/vremu_vx_rv64-1.C | 314 +++++++++++
.../g++.target/riscv/rvv/base/vremu_vx_rv64-2.C | 314 +++++++++++
.../g++.target/riscv/rvv/base/vremu_vx_rv64-3.C | 314 +++++++++++
.../base/{vremu_vv_tu-1.C => vremu_vx_tu_rv32-1.C} | 85 ++-
.../base/{vremu_vv_tu-2.C => vremu_vx_tu_rv32-2.C} | 85 ++-
.../base/{vremu_vv_tu-3.C => vremu_vx_tu_rv32-3.C} | 85 ++-
.../base/{vremu_vv_tu-1.C => vremu_vx_tu_rv64-1.C} | 90 ++--
.../base/{vremu_vv_tu-2.C => vremu_vx_tu_rv64-2.C} | 90 ++--
.../base/{vremu_vv_tu-3.C => vremu_vx_tu_rv64-3.C} | 90 ++--
.../{vremu_vv_tum-1.C => vremu_vx_tum_rv32-1.C} | 85 ++-
.../{vremu_vv_tum-2.C => vremu_vx_tum_rv32-2.C} | 85 ++-
.../{vremu_vv_tum-3.C => vremu_vx_tum_rv32-3.C} | 85 ++-
.../{vremu_vv_tum-1.C => vremu_vx_tum_rv64-1.C} | 90 ++--
.../{vremu_vv_tum-2.C => vremu_vx_tum_rv64-2.C} | 90 ++--
.../{vremu_vv_tum-3.C => vremu_vx_tum_rv64-3.C} | 90 ++--
.../{vremu_vv_tumu-1.C => vremu_vx_tumu_rv32-1.C} | 85 ++-
.../{vremu_vv_tumu-2.C => vremu_vx_tumu_rv32-2.C} | 85 ++-
.../{vremu_vv_tumu-3.C => vremu_vx_tumu_rv32-3.C} | 85 ++-
.../{vremu_vv_tumu-1.C => vremu_vx_tumu_rv64-1.C} | 90 ++--
.../{vremu_vv_tumu-2.C => vremu_vx_tumu_rv64-2.C} | 90 ++--
.../{vremu_vv_tumu-3.C => vremu_vx_tumu_rv64-3.C} | 90 ++--
.../g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-1.C | 289 +++++++++++
.../g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-2.C | 289 +++++++++++
.../g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-3.C | 289 +++++++++++
.../g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-1.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-2.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-3.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vrsub_vx_rv32-1.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vrsub_vx_rv32-2.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vrsub_vx_rv32-3.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vrsub_vx_rv64-1.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vrsub_vx_rv64-2.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vrsub_vx_rv64-3.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-1.C | 289 +++++++++++
.../g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-2.C | 289 +++++++++++
.../g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-3.C | 289 +++++++++++
.../g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-1.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-2.C | 292 +++++++++++
.../g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-3.C | 292 +++++++++++
.../riscv/rvv/base/vrsub_vx_tum_rv32-1.C | 289 +++++++++++
.../riscv/rvv/base/vrsub_vx_tum_rv32-2.C | 289 +++++++++++
.../riscv/rvv/base/vrsub_vx_tum_rv32-3.C | 289 +++++++++++
.../riscv/rvv/base/vrsub_vx_tum_rv64-1.C | 292 +++++++++++
.../riscv/rvv/base/vrsub_vx_tum_rv64-2.C | 292 +++++++++++
.../riscv/rvv/base/vrsub_vx_tum_rv64-3.C | 292 +++++++++++
.../riscv/rvv/base/vrsub_vx_tumu_rv32-1.C | 289 +++++++++++
.../riscv/rvv/base/vrsub_vx_tumu_rv32-2.C | 289 +++++++++++
.../riscv/rvv/base/vrsub_vx_tumu_rv32-3.C | 289 +++++++++++
.../riscv/rvv/base/vrsub_vx_tumu_rv64-1.C | 292 +++++++++++
.../riscv/rvv/base/vrsub_vx_tumu_rv64-2.C | 292 +++++++++++
.../riscv/rvv/base/vrsub_vx_tumu_rv64-3.C | 292 +++++++++++
.../base/{vsub_vv_mu-1.C => vsub_vx_mu_rv32-1.C} | 129 +++--
.../base/{vsub_vv_mu-2.C => vsub_vx_mu_rv32-2.C} | 129 +++--
.../base/{vsub_vv_mu-3.C => vsub_vx_mu_rv32-3.C} | 129 +++--
.../base/{vsub_vv_mu-1.C => vsub_vx_mu_rv64-1.C} | 134 ++---
.../base/{vsub_vv_mu-2.C => vsub_vx_mu_rv64-2.C} | 134 ++---
.../base/{vsub_vv_mu-3.C => vsub_vx_mu_rv64-3.C} | 134 ++---
.../g++.target/riscv/rvv/base/vsub_vx_rv32-1.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vsub_vx_rv32-2.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vsub_vx_rv32-3.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vsub_vx_rv64-1.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vsub_vx_rv64-2.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vsub_vx_rv64-3.C | 578 +++++++++++++++++++++
.../base/{vsub_vv_tu-1.C => vsub_vx_tu_rv32-1.C} | 129 +++--
.../base/{vsub_vv_tu-2.C => vsub_vx_tu_rv32-2.C} | 129 +++--
.../base/{vsub_vv_tu-3.C => vsub_vx_tu_rv32-3.C} | 129 +++--
.../base/{vsub_vv_tu-1.C => vsub_vx_tu_rv64-1.C} | 134 ++---
.../base/{vsub_vv_tu-2.C => vsub_vx_tu_rv64-2.C} | 134 ++---
.../base/{vsub_vv_tu-3.C => vsub_vx_tu_rv64-3.C} | 134 ++---
.../base/{vsub_vv_tum-1.C => vsub_vx_tum_rv32-1.C} | 129 +++--
.../base/{vsub_vv_tum-2.C => vsub_vx_tum_rv32-2.C} | 129 +++--
.../base/{vsub_vv_tum-3.C => vsub_vx_tum_rv32-3.C} | 129 +++--
.../base/{vsub_vv_tum-1.C => vsub_vx_tum_rv64-1.C} | 134 ++---
.../base/{vsub_vv_tum-2.C => vsub_vx_tum_rv64-2.C} | 134 ++---
.../base/{vsub_vv_tum-3.C => vsub_vx_tum_rv64-3.C} | 134 ++---
.../{vsub_vv_tumu-1.C => vsub_vx_tumu_rv32-1.C} | 129 +++--
.../{vsub_vv_tumu-2.C => vsub_vx_tumu_rv32-2.C} | 129 +++--
.../{vsub_vv_tumu-3.C => vsub_vx_tumu_rv32-3.C} | 129 +++--
.../{vsub_vv_tumu-1.C => vsub_vx_tumu_rv64-1.C} | 134 ++---
.../{vsub_vv_tumu-2.C => vsub_vx_tumu_rv64-2.C} | 134 ++---
.../{vsub_vv_tumu-3.C => vsub_vx_tumu_rv64-3.C} | 134 ++---
.../base/{vxor_vv_mu-1.C => vxor_vx_mu_rv32-1.C} | 129 +++--
.../base/{vxor_vv_mu-2.C => vxor_vx_mu_rv32-2.C} | 129 +++--
.../base/{vxor_vv_mu-3.C => vxor_vx_mu_rv32-3.C} | 129 +++--
.../base/{vxor_vv_mu-1.C => vxor_vx_mu_rv64-1.C} | 134 ++---
.../base/{vxor_vv_mu-2.C => vxor_vx_mu_rv64-2.C} | 134 ++---
.../base/{vxor_vv_mu-3.C => vxor_vx_mu_rv64-3.C} | 134 ++---
.../g++.target/riscv/rvv/base/vxor_vx_rv32-1.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vxor_vx_rv32-2.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vxor_vx_rv32-3.C | 572 ++++++++++++++++++++
.../g++.target/riscv/rvv/base/vxor_vx_rv64-1.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vxor_vx_rv64-2.C | 578 +++++++++++++++++++++
.../g++.target/riscv/rvv/base/vxor_vx_rv64-3.C | 578 +++++++++++++++++++++
.../base/{vxor_vv_tu-1.C => vxor_vx_tu_rv32-1.C} | 129 +++--
.../base/{vxor_vv_tu-2.C => vxor_vx_tu_rv32-2.C} | 129 +++--
.../base/{vxor_vv_tu-3.C => vxor_vx_tu_rv32-3.C} | 129 +++--
.../base/{vxor_vv_tu-1.C => vxor_vx_tu_rv64-1.C} | 134 ++---
.../base/{vxor_vv_tu-2.C => vxor_vx_tu_rv64-2.C} | 134 ++---
.../base/{vxor_vv_tu-3.C => vxor_vx_tu_rv64-3.C} | 134 ++---
.../base/{vxor_vv_tum-1.C => vxor_vx_tum_rv32-1.C} | 129 +++--
.../base/{vxor_vv_tum-2.C => vxor_vx_tum_rv32-2.C} | 129 +++--
.../base/{vxor_vv_tum-3.C => vxor_vx_tum_rv32-3.C} | 129 +++--
.../base/{vxor_vv_tum-1.C => vxor_vx_tum_rv64-1.C} | 134 ++---
.../base/{vxor_vv_tum-2.C => vxor_vx_tum_rv64-2.C} | 134 ++---
.../base/{vxor_vv_tum-3.C => vxor_vx_tum_rv64-3.C} | 134 ++---
.../{vxor_vv_tumu-1.C => vxor_vx_tumu_rv32-1.C} | 129 +++--
.../{vxor_vv_tumu-2.C => vxor_vx_tumu_rv32-2.C} | 129 +++--
.../{vxor_vv_tumu-3.C => vxor_vx_tumu_rv32-3.C} | 129 +++--
.../{vxor_vv_tumu-1.C => vxor_vx_tumu_rv64-1.C} | 134 ++---
.../{vxor_vv_tumu-2.C => vxor_vx_tumu_rv64-2.C} | 134 ++---
.../{vxor_vv_tumu-3.C => vxor_vx_tumu_rv64-3.C} | 134 ++---
gcc/testsuite/gcc.target/i386/pr108724.c | 15 +
...t_vx_constraint-1.c => binop_vx_constraint-1.c} | 62 ++-
..._vv_constraint-1.c => binop_vx_constraint-10.c} | 60 +--
..._vv_constraint-1.c => binop_vx_constraint-11.c} | 60 +--
..._vv_constraint-1.c => binop_vx_constraint-12.c} | 88 ++--
..._vv_constraint-1.c => binop_vx_constraint-13.c} | 60 +--
..._vv_constraint-1.c => binop_vx_constraint-14.c} | 60 +--
..._vx_constraint-1.c => binop_vx_constraint-15.c} | 62 ++-
..._vx_constraint-1.c => binop_vx_constraint-16.c} | 90 ++--
..._vx_constraint-1.c => binop_vx_constraint-17.c} | 90 ++--
..._vx_constraint-1.c => binop_vx_constraint-18.c} | 62 ++-
..._vx_constraint-1.c => binop_vx_constraint-19.c} | 90 ++--
...t_vx_constraint-1.c => binop_vx_constraint-2.c} | 62 ++-
..._vx_constraint-1.c => binop_vx_constraint-20.c} | 62 ++-
..._vx_constraint-1.c => binop_vx_constraint-21.c} | 90 ++--
..._vx_constraint-1.c => binop_vx_constraint-22.c} | 62 ++-
.../riscv/rvv/base/binop_vx_constraint-23.c | 160 ++++++
.../riscv/rvv/base/binop_vx_constraint-24.c | 132 +++++
.../riscv/rvv/base/binop_vx_constraint-25.c | 160 ++++++
.../riscv/rvv/base/binop_vx_constraint-26.c | 132 +++++
..._vx_constraint-1.c => binop_vx_constraint-27.c} | 90 ++--
..._vx_constraint-1.c => binop_vx_constraint-28.c} | 62 ++-
.../riscv/rvv/base/binop_vx_constraint-29.c | 160 ++++++
...p_vv_constraint-1.c => binop_vx_constraint-3.c} | 60 +--
.../riscv/rvv/base/binop_vx_constraint-30.c | 132 +++++
.../riscv/rvv/base/binop_vx_constraint-31.c | 160 ++++++
.../riscv/rvv/base/binop_vx_constraint-32.c | 132 +++++
.../riscv/rvv/base/binop_vx_constraint-33.c | 160 ++++++
.../riscv/rvv/base/binop_vx_constraint-34.c | 132 +++++
.../riscv/rvv/base/binop_vx_constraint-35.c | 160 ++++++
.../riscv/rvv/base/binop_vx_constraint-36.c | 132 +++++
..._vx_constraint-1.c => binop_vx_constraint-37.c} | 62 ++-
..._vx_constraint-1.c => binop_vx_constraint-38.c} | 62 ++-
..._vv_constraint-1.c => binop_vx_constraint-39.c} | 60 +--
...p_vv_constraint-1.c => binop_vx_constraint-4.c} | 88 ++--
..._vv_constraint-1.c => binop_vx_constraint-40.c} | 88 ++--
..._vv_constraint-1.c => binop_vx_constraint-41.c} | 60 +--
..._vx_constraint-1.c => binop_vx_constraint-42.c} | 62 ++-
..._vx_constraint-1.c => binop_vx_constraint-43.c} | 62 ++-
..._vv_constraint-1.c => binop_vx_constraint-44.c} | 88 ++--
.../riscv/rvv/base/binop_vx_constraint-45.c | 123 +++++
.../riscv/rvv/base/binop_vx_constraint-46.c | 72 +++
.../riscv/rvv/base/binop_vx_constraint-47.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-48.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-49.c | 16 +
...t_vx_constraint-1.c => binop_vx_constraint-5.c} | 62 ++-
.../riscv/rvv/base/binop_vx_constraint-50.c | 18 +
.../riscv/rvv/base/binop_vx_constraint-51.c | 123 +++++
.../riscv/rvv/base/binop_vx_constraint-52.c | 72 +++
.../riscv/rvv/base/binop_vx_constraint-53.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-54.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-55.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-56.c | 18 +
.../riscv/rvv/base/binop_vx_constraint-57.c | 123 +++++
.../riscv/rvv/base/binop_vx_constraint-58.c | 72 +++
.../riscv/rvv/base/binop_vx_constraint-59.c | 16 +
...t_vx_constraint-1.c => binop_vx_constraint-6.c} | 62 ++-
.../riscv/rvv/base/binop_vx_constraint-60.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-61.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-62.c | 18 +
.../riscv/rvv/base/binop_vx_constraint-63.c | 123 +++++
.../riscv/rvv/base/binop_vx_constraint-64.c | 72 +++
.../riscv/rvv/base/binop_vx_constraint-65.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-66.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-67.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-68.c | 18 +
.../riscv/rvv/base/binop_vx_constraint-69.c | 123 +++++
...p_vv_constraint-1.c => binop_vx_constraint-7.c} | 60 +--
.../riscv/rvv/base/binop_vx_constraint-70.c | 72 +++
.../riscv/rvv/base/binop_vx_constraint-71.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-72.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-73.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-74.c | 18 +
.../riscv/rvv/base/binop_vx_constraint-75.c | 72 +++
.../riscv/rvv/base/binop_vx_constraint-76.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-77.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-78.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-79.c | 18 +
...p_vv_constraint-1.c => binop_vx_constraint-8.c} | 88 ++--
.../riscv/rvv/base/binop_vx_constraint-80.c | 72 +++
.../riscv/rvv/base/binop_vx_constraint-81.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-82.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-83.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-84.c | 18 +
.../riscv/rvv/base/binop_vx_constraint-85.c | 123 +++++
.../riscv/rvv/base/binop_vx_constraint-86.c | 72 +++
.../riscv/rvv/base/binop_vx_constraint-87.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-88.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-89.c | 16 +
...t_vx_constraint-1.c => binop_vx_constraint-9.c} | 62 ++-
.../riscv/rvv/base/binop_vx_constraint-90.c | 18 +
.../riscv/rvv/base/binop_vx_constraint-91.c | 123 +++++
.../riscv/rvv/base/binop_vx_constraint-92.c | 72 +++
.../riscv/rvv/base/binop_vx_constraint-93.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-94.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-95.c | 16 +
.../riscv/rvv/base/binop_vx_constraint-96.c | 18 +
.../gcc.target/riscv/rvv/base/vadd_vx_m_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_m_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_m_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_m_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_m_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_m_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_mu_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_mu_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_mu_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_mu_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_mu_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_mu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_tu_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_tu_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_tu_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_tu_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_tu_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_tu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_tum_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_tum_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_tum_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_tum_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_tum_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vadd_vx_tum_rv64-3.c | 292 +++++++++++
.../riscv/rvv/base/vadd_vx_tumu_rv32-1.c | 289 +++++++++++
.../riscv/rvv/base/vadd_vx_tumu_rv32-2.c | 289 +++++++++++
.../riscv/rvv/base/vadd_vx_tumu_rv32-3.c | 289 +++++++++++
.../riscv/rvv/base/vadd_vx_tumu_rv64-1.c | 292 +++++++++++
.../riscv/rvv/base/vadd_vx_tumu_rv64-2.c | 292 +++++++++++
.../riscv/rvv/base/vadd_vx_tumu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_m_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_m_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_m_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_m_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_m_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_m_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_mu_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_mu_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_mu_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_mu_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_mu_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_mu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_tu_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_tu_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_tu_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_tu_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_tu_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_tu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_tum_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_tum_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_tum_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_tum_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_tum_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vand_vx_tum_rv64-3.c | 292 +++++++++++
.../riscv/rvv/base/vand_vx_tumu_rv32-1.c | 289 +++++++++++
.../riscv/rvv/base/vand_vx_tumu_rv32-2.c | 289 +++++++++++
.../riscv/rvv/base/vand_vx_tumu_rv32-3.c | 289 +++++++++++
.../riscv/rvv/base/vand_vx_tumu_rv64-1.c | 292 +++++++++++
.../riscv/rvv/base/vand_vx_tumu_rv64-2.c | 292 +++++++++++
.../riscv/rvv/base/vand_vx_tumu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_m_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_m_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_m_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_m_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_m_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_m_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_mu_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_mu_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_mu_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_mu_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_mu_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_mu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_tu_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_tu_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_tu_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_tu_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_tu_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_tu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_tum_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_tum_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_tum_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_tum_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_tum_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdiv_vx_tum_rv64-3.c | 160 ++++++
.../riscv/rvv/base/vdiv_vx_tumu_rv32-1.c | 157 ++++++
.../riscv/rvv/base/vdiv_vx_tumu_rv32-2.c | 157 ++++++
.../riscv/rvv/base/vdiv_vx_tumu_rv32-3.c | 157 ++++++
.../riscv/rvv/base/vdiv_vx_tumu_rv64-1.c | 160 ++++++
.../riscv/rvv/base/vdiv_vx_tumu_rv64-2.c | 160 ++++++
.../riscv/rvv/base/vdiv_vx_tumu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_m_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_m_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_m_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_m_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_m_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_m_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_mu_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_mu_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_mu_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_mu_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_mu_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_mu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_tu_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_tu_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_tu_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_tu_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_tu_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vdivu_vx_tu_rv64-3.c | 160 ++++++
.../riscv/rvv/base/vdivu_vx_tum_rv32-1.c | 157 ++++++
.../riscv/rvv/base/vdivu_vx_tum_rv32-2.c | 157 ++++++
.../riscv/rvv/base/vdivu_vx_tum_rv32-3.c | 157 ++++++
.../riscv/rvv/base/vdivu_vx_tum_rv64-1.c | 160 ++++++
.../riscv/rvv/base/vdivu_vx_tum_rv64-2.c | 160 ++++++
.../riscv/rvv/base/vdivu_vx_tum_rv64-3.c | 160 ++++++
.../riscv/rvv/base/vdivu_vx_tumu_rv32-1.c | 157 ++++++
.../riscv/rvv/base/vdivu_vx_tumu_rv32-2.c | 157 ++++++
.../riscv/rvv/base/vdivu_vx_tumu_rv32-3.c | 157 ++++++
.../riscv/rvv/base/vdivu_vx_tumu_rv64-1.c | 160 ++++++
.../riscv/rvv/base/vdivu_vx_tumu_rv64-2.c | 160 ++++++
.../riscv/rvv/base/vdivu_vx_tumu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_m_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_m_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_m_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_m_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_m_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_m_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_mu_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_mu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_tu_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_tu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_tum_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmax_vx_tum_rv64-3.c | 160 ++++++
.../riscv/rvv/base/vmax_vx_tumu_rv32-1.c | 157 ++++++
.../riscv/rvv/base/vmax_vx_tumu_rv32-2.c | 157 ++++++
.../riscv/rvv/base/vmax_vx_tumu_rv32-3.c | 157 ++++++
.../riscv/rvv/base/vmax_vx_tumu_rv64-1.c | 160 ++++++
.../riscv/rvv/base/vmax_vx_tumu_rv64-2.c | 160 ++++++
.../riscv/rvv/base/vmax_vx_tumu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_m_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_m_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_m_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_m_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_m_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_m_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_mu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmaxu_vx_tu_rv64-3.c | 160 ++++++
.../riscv/rvv/base/vmaxu_vx_tum_rv32-1.c | 157 ++++++
.../riscv/rvv/base/vmaxu_vx_tum_rv32-2.c | 157 ++++++
.../riscv/rvv/base/vmaxu_vx_tum_rv32-3.c | 157 ++++++
.../riscv/rvv/base/vmaxu_vx_tum_rv64-1.c | 160 ++++++
.../riscv/rvv/base/vmaxu_vx_tum_rv64-2.c | 160 ++++++
.../riscv/rvv/base/vmaxu_vx_tum_rv64-3.c | 160 ++++++
.../riscv/rvv/base/vmaxu_vx_tumu_rv32-1.c | 157 ++++++
.../riscv/rvv/base/vmaxu_vx_tumu_rv32-2.c | 157 ++++++
.../riscv/rvv/base/vmaxu_vx_tumu_rv32-3.c | 157 ++++++
.../riscv/rvv/base/vmaxu_vx_tumu_rv64-1.c | 160 ++++++
.../riscv/rvv/base/vmaxu_vx_tumu_rv64-2.c | 160 ++++++
.../riscv/rvv/base/vmaxu_vx_tumu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_m_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_m_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_m_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_m_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_m_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_m_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_mu_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_mu_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_mu_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_mu_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_mu_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_mu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_tu_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_tu_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_tu_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_tu_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_tu_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_tu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_tum_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_tum_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_tum_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_tum_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_tum_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmin_vx_tum_rv64-3.c | 160 ++++++
.../riscv/rvv/base/vmin_vx_tumu_rv32-1.c | 157 ++++++
.../riscv/rvv/base/vmin_vx_tumu_rv32-2.c | 157 ++++++
.../riscv/rvv/base/vmin_vx_tumu_rv32-3.c | 157 ++++++
.../riscv/rvv/base/vmin_vx_tumu_rv64-1.c | 160 ++++++
.../riscv/rvv/base/vmin_vx_tumu_rv64-2.c | 160 ++++++
.../riscv/rvv/base/vmin_vx_tumu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_m_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_m_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_m_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_m_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_m_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_m_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_mu_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_mu_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_mu_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_mu_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_mu_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_mu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_tu_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_tu_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_tu_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_tu_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_tu_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vminu_vx_tu_rv64-3.c | 160 ++++++
.../riscv/rvv/base/vminu_vx_tum_rv32-1.c | 157 ++++++
.../riscv/rvv/base/vminu_vx_tum_rv32-2.c | 157 ++++++
.../riscv/rvv/base/vminu_vx_tum_rv32-3.c | 157 ++++++
.../riscv/rvv/base/vminu_vx_tum_rv64-1.c | 160 ++++++
.../riscv/rvv/base/vminu_vx_tum_rv64-2.c | 160 ++++++
.../riscv/rvv/base/vminu_vx_tum_rv64-3.c | 160 ++++++
.../riscv/rvv/base/vminu_vx_tumu_rv32-1.c | 157 ++++++
.../riscv/rvv/base/vminu_vx_tumu_rv32-2.c | 157 ++++++
.../riscv/rvv/base/vminu_vx_tumu_rv32-3.c | 157 ++++++
.../riscv/rvv/base/vminu_vx_tumu_rv64-1.c | 160 ++++++
.../riscv/rvv/base/vminu_vx_tumu_rv64-2.c | 160 ++++++
.../riscv/rvv/base/vminu_vx_tumu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vmul_vv-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vv-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vv-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vv_m-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vv_m-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vv_m-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vv_mu-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vv_mu-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vv_mu-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vv_tu-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vv_tu-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vv_tu-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vv_tum-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vv_tum-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vv_tum-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vv_tumu-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vv_tumu-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vv_tumu-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_m_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_m_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_m_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_m_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_m_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_m_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_mu_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_mu_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_mu_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_mu_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_mu_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_mu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_tu_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_tu_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_tu_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_tu_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_tu_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_tu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_tum_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_tum_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_tum_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_tum_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_tum_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vmul_vx_tum_rv64-3.c | 292 +++++++++++
.../riscv/rvv/base/vmul_vx_tumu_rv32-1.c | 289 +++++++++++
.../riscv/rvv/base/vmul_vx_tumu_rv32-2.c | 289 +++++++++++
.../riscv/rvv/base/vmul_vx_tumu_rv32-3.c | 289 +++++++++++
.../riscv/rvv/base/vmul_vx_tumu_rv64-1.c | 292 +++++++++++
.../riscv/rvv/base/vmul_vx_tumu_rv64-2.c | 292 +++++++++++
.../riscv/rvv/base/vmul_vx_tumu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_m_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_m_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_m_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_m_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_m_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_m_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_mu_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_mu_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_mu_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_mu_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_mu_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_mu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_tu_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_tu_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_tu_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_tu_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_tu_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_tu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_tum_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_tum_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_tum_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_tum_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_tum_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_tum_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_tumu_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_tumu_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_tumu_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_tumu_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_tumu_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vor_vx_tumu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vrem_vx_m_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_m_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_m_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_m_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_m_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_m_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_mu_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_mu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_tu_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_tu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_tum_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vrem_vx_tum_rv64-3.c | 160 ++++++
.../riscv/rvv/base/vrem_vx_tumu_rv32-1.c | 157 ++++++
.../riscv/rvv/base/vrem_vx_tumu_rv32-2.c | 157 ++++++
.../riscv/rvv/base/vrem_vx_tumu_rv32-3.c | 157 ++++++
.../riscv/rvv/base/vrem_vx_tumu_rv64-1.c | 160 ++++++
.../riscv/rvv/base/vrem_vx_tumu_rv64-2.c | 160 ++++++
.../riscv/rvv/base/vrem_vx_tumu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_m_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_m_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_m_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_m_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_m_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_m_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_mu_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_mu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-1.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-2.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_tu_rv32-3.c | 157 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-1.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-2.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vremu_vx_tu_rv64-3.c | 160 ++++++
.../riscv/rvv/base/vremu_vx_tum_rv32-1.c | 157 ++++++
.../riscv/rvv/base/vremu_vx_tum_rv32-2.c | 157 ++++++
.../riscv/rvv/base/vremu_vx_tum_rv32-3.c | 157 ++++++
.../riscv/rvv/base/vremu_vx_tum_rv64-1.c | 160 ++++++
.../riscv/rvv/base/vremu_vx_tum_rv64-2.c | 160 ++++++
.../riscv/rvv/base/vremu_vx_tum_rv64-3.c | 160 ++++++
.../riscv/rvv/base/vremu_vx_tumu_rv32-1.c | 157 ++++++
.../riscv/rvv/base/vremu_vx_tumu_rv32-2.c | 157 ++++++
.../riscv/rvv/base/vremu_vx_tumu_rv32-3.c | 157 ++++++
.../riscv/rvv/base/vremu_vx_tumu_rv64-1.c | 160 ++++++
.../riscv/rvv/base/vremu_vx_tumu_rv64-2.c | 160 ++++++
.../riscv/rvv/base/vremu_vx_tumu_rv64-3.c | 160 ++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_m_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_m_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_m_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_m_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_m_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_m_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_mu_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_mu_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_mu_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_mu_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_mu_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_mu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_tu_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_tu_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_tu_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_tu_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_tu_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vrsub_vx_tu_rv64-3.c | 292 +++++++++++
.../riscv/rvv/base/vrsub_vx_tum_rv32-1.c | 289 +++++++++++
.../riscv/rvv/base/vrsub_vx_tum_rv32-2.c | 289 +++++++++++
.../riscv/rvv/base/vrsub_vx_tum_rv32-3.c | 289 +++++++++++
.../riscv/rvv/base/vrsub_vx_tum_rv64-1.c | 292 +++++++++++
.../riscv/rvv/base/vrsub_vx_tum_rv64-2.c | 292 +++++++++++
.../riscv/rvv/base/vrsub_vx_tum_rv64-3.c | 292 +++++++++++
.../riscv/rvv/base/vrsub_vx_tumu_rv32-1.c | 289 +++++++++++
.../riscv/rvv/base/vrsub_vx_tumu_rv32-2.c | 289 +++++++++++
.../riscv/rvv/base/vrsub_vx_tumu_rv32-3.c | 289 +++++++++++
.../riscv/rvv/base/vrsub_vx_tumu_rv64-1.c | 292 +++++++++++
.../riscv/rvv/base/vrsub_vx_tumu_rv64-2.c | 292 +++++++++++
.../riscv/rvv/base/vrsub_vx_tumu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_m_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_m_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_m_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_m_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_m_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_m_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_mu_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_mu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_tu_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_tu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_tum_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vsub_vx_tum_rv64-3.c | 292 +++++++++++
.../riscv/rvv/base/vsub_vx_tumu_rv32-1.c | 289 +++++++++++
.../riscv/rvv/base/vsub_vx_tumu_rv32-2.c | 289 +++++++++++
.../riscv/rvv/base/vsub_vx_tumu_rv32-3.c | 289 +++++++++++
.../riscv/rvv/base/vsub_vx_tumu_rv64-1.c | 292 +++++++++++
.../riscv/rvv/base/vsub_vx_tumu_rv64-2.c | 292 +++++++++++
.../riscv/rvv/base/vsub_vx_tumu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_m_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_m_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_m_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_m_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_m_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_m_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_mu_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_mu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_tu_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_tu_rv64-3.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-1.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-2.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_tum_rv32-3.c | 289 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-1.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-2.c | 292 +++++++++++
.../gcc.target/riscv/rvv/base/vxor_vx_tum_rv64-3.c | 292 +++++++++++
.../riscv/rvv/base/vxor_vx_tumu_rv32-1.c | 289 +++++++++++
.../riscv/rvv/base/vxor_vx_tumu_rv32-2.c | 289 +++++++++++
.../riscv/rvv/base/vxor_vx_tumu_rv32-3.c | 289 +++++++++++
.../riscv/rvv/base/vxor_vx_tumu_rv64-1.c | 292 +++++++++++
.../riscv/rvv/base/vxor_vx_tumu_rv64-2.c | 292 +++++++++++
.../riscv/rvv/base/vxor_vx_tumu_rv64-3.c | 292 +++++++++++
gcc/tree-vect-stmts.cc | 14 +
1132 files changed, 204141 insertions(+), 17566 deletions(-)
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_mu-1.C => vadd_vx_mu_rv32-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_mu-2.C => vadd_vx_mu_rv32-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_mu-3.C => vadd_vx_mu_rv32-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_mu-1.C => vadd_vx_mu_rv64-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_mu-2.C => vadd_vx_mu_rv64-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_mu-3.C => vadd_vx_mu_rv64-3. [...]
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vadd_vx_rv64-3.C
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tu-1.C => vadd_vx_tu_rv32-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tu-2.C => vadd_vx_tu_rv32-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tu-3.C => vadd_vx_tu_rv32-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tu-1.C => vadd_vx_tu_rv64-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tu-2.C => vadd_vx_tu_rv64-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tu-3.C => vadd_vx_tu_rv64-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tum-1.C => vadd_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tum-2.C => vadd_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tum-3.C => vadd_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tum-1.C => vadd_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tum-2.C => vadd_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tum-3.C => vadd_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tumu-1.C => vadd_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tumu-2.C => vadd_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tumu-3.C => vadd_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tumu-1.C => vadd_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tumu-2.C => vadd_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vadd_vv_tumu-3.C => vadd_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_mu-1.C => vand_vx_mu_rv32-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_mu-2.C => vand_vx_mu_rv32-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_mu-3.C => vand_vx_mu_rv32-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_mu-1.C => vand_vx_mu_rv64-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_mu-2.C => vand_vx_mu_rv64-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_mu-3.C => vand_vx_mu_rv64-3. [...]
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vand_vx_rv64-3.C
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tu-1.C => vand_vx_tu_rv32-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tu-2.C => vand_vx_tu_rv32-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tu-3.C => vand_vx_tu_rv32-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tu-1.C => vand_vx_tu_rv64-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tu-2.C => vand_vx_tu_rv64-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tu-3.C => vand_vx_tu_rv64-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tum-1.C => vand_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tum-2.C => vand_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tum-3.C => vand_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tum-1.C => vand_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tum-2.C => vand_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tum-3.C => vand_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tumu-1.C => vand_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tumu-2.C => vand_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tumu-3.C => vand_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tumu-1.C => vand_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tumu-2.C => vand_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vand_vv_tumu-3.C => vand_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_mu-1.C => vdiv_vx_mu_rv32-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_mu-2.C => vdiv_vx_mu_rv32-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_mu-3.C => vdiv_vx_mu_rv32-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_mu-1.C => vdiv_vx_mu_rv64-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_mu-2.C => vdiv_vx_mu_rv64-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_mu-3.C => vdiv_vx_mu_rv64-3. [...]
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdiv_vx_rv64-3.C
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tu-1.C => vdiv_vx_tu_rv32-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tu-2.C => vdiv_vx_tu_rv32-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tu-3.C => vdiv_vx_tu_rv32-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tu-1.C => vdiv_vx_tu_rv64-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tu-2.C => vdiv_vx_tu_rv64-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tu-3.C => vdiv_vx_tu_rv64-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tum-1.C => vdiv_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tum-2.C => vdiv_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tum-3.C => vdiv_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tum-1.C => vdiv_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tum-2.C => vdiv_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tum-3.C => vdiv_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tumu-1.C => vdiv_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tumu-2.C => vdiv_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tumu-3.C => vdiv_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tumu-1.C => vdiv_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tumu-2.C => vdiv_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdiv_vv_tumu-3.C => vdiv_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_mu-1.C => vdivu_vx_mu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_mu-2.C => vdivu_vx_mu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_mu-3.C => vdivu_vx_mu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_mu-1.C => vdivu_vx_mu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_mu-2.C => vdivu_vx_mu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_mu-3.C => vdivu_vx_mu_rv64- [...]
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vdivu_vx_rv64-3.C
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tu-1.C => vdivu_vx_tu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tu-2.C => vdivu_vx_tu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tu-3.C => vdivu_vx_tu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tu-1.C => vdivu_vx_tu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tu-2.C => vdivu_vx_tu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tu-3.C => vdivu_vx_tu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tum-1.C => vdivu_vx_tum_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tum-2.C => vdivu_vx_tum_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tum-3.C => vdivu_vx_tum_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tum-1.C => vdivu_vx_tum_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tum-2.C => vdivu_vx_tum_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tum-3.C => vdivu_vx_tum_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tumu-1.C => vdivu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tumu-2.C => vdivu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tumu-3.C => vdivu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tumu-1.C => vdivu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tumu-2.C => vdivu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vdivu_vv_tumu-3.C => vdivu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_mu-1.C => vmax_vx_mu_rv32-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_mu-2.C => vmax_vx_mu_rv32-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_mu-3.C => vmax_vx_mu_rv32-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_mu-1.C => vmax_vx_mu_rv64-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_mu-2.C => vmax_vx_mu_rv64-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_mu-3.C => vmax_vx_mu_rv64-3. [...]
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmax_vx_rv64-3.C
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tu-1.C => vmax_vx_tu_rv32-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tu-2.C => vmax_vx_tu_rv32-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tu-3.C => vmax_vx_tu_rv32-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tu-1.C => vmax_vx_tu_rv64-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tu-2.C => vmax_vx_tu_rv64-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tu-3.C => vmax_vx_tu_rv64-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tum-1.C => vmax_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tum-2.C => vmax_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tum-3.C => vmax_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tum-1.C => vmax_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tum-2.C => vmax_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tum-3.C => vmax_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tumu-1.C => vmax_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tumu-2.C => vmax_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tumu-3.C => vmax_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tumu-1.C => vmax_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tumu-2.C => vmax_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmax_vv_tumu-3.C => vmax_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_mu-1.C => vmaxu_vx_mu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_mu-2.C => vmaxu_vx_mu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_mu-3.C => vmaxu_vx_mu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_mu-1.C => vmaxu_vx_mu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_mu-2.C => vmaxu_vx_mu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_mu-3.C => vmaxu_vx_mu_rv64- [...]
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmaxu_vx_rv64-3.C
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tu-1.C => vmaxu_vx_tu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tu-2.C => vmaxu_vx_tu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tu-3.C => vmaxu_vx_tu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tu-1.C => vmaxu_vx_tu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tu-2.C => vmaxu_vx_tu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tu-3.C => vmaxu_vx_tu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tum-1.C => vmaxu_vx_tum_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tum-2.C => vmaxu_vx_tum_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tum-3.C => vmaxu_vx_tum_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tum-1.C => vmaxu_vx_tum_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tum-2.C => vmaxu_vx_tum_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tum-3.C => vmaxu_vx_tum_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tumu-1.C => vmaxu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tumu-2.C => vmaxu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tumu-3.C => vmaxu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tumu-1.C => vmaxu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tumu-2.C => vmaxu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmaxu_vv_tumu-3.C => vmaxu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_mu-1.C => vmin_vx_mu_rv32-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_mu-2.C => vmin_vx_mu_rv32-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_mu-3.C => vmin_vx_mu_rv32-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_mu-1.C => vmin_vx_mu_rv64-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_mu-2.C => vmin_vx_mu_rv64-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_mu-3.C => vmin_vx_mu_rv64-3. [...]
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmin_vx_rv64-3.C
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tu-1.C => vmin_vx_tu_rv32-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tu-2.C => vmin_vx_tu_rv32-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tu-3.C => vmin_vx_tu_rv32-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tu-1.C => vmin_vx_tu_rv64-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tu-2.C => vmin_vx_tu_rv64-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tu-3.C => vmin_vx_tu_rv64-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tum-1.C => vmin_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tum-2.C => vmin_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tum-3.C => vmin_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tum-1.C => vmin_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tum-2.C => vmin_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tum-3.C => vmin_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tumu-1.C => vmin_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tumu-2.C => vmin_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tumu-3.C => vmin_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tumu-1.C => vmin_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tumu-2.C => vmin_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vmin_vv_tumu-3.C => vmin_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_mu-1.C => vminu_vx_mu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_mu-2.C => vminu_vx_mu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_mu-3.C => vminu_vx_mu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_mu-1.C => vminu_vx_mu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_mu-2.C => vminu_vx_mu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_mu-3.C => vminu_vx_mu_rv64- [...]
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vminu_vx_rv64-3.C
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tu-1.C => vminu_vx_tu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tu-2.C => vminu_vx_tu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tu-3.C => vminu_vx_tu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tu-1.C => vminu_vx_tu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tu-2.C => vminu_vx_tu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tu-3.C => vminu_vx_tu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tum-1.C => vminu_vx_tum_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tum-2.C => vminu_vx_tum_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tum-3.C => vminu_vx_tum_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tum-1.C => vminu_vx_tum_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tum-2.C => vminu_vx_tum_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tum-3.C => vminu_vx_tum_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tumu-1.C => vminu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tumu-2.C => vminu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tumu-3.C => vminu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tumu-1.C => vminu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tumu-2.C => vminu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vminu_vv_tumu-3.C => vminu_vx_tumu_r [...]
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_mu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_mu-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_mu-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tu-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tu-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tum-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tum-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tum-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tumu-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tumu-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vv_tumu-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_mu_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_mu_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_mu_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_mu_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_mu_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_mu_rv64-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_rv64-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tu_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tu_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tu_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tu_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tu_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tu_rv64-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tum_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tum_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tum_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tum_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tum_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tum_rv64-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tumu_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tumu_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tumu_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tumu_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tumu_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmul_vx_tumu_rv64-3.C
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_mu-1.C => vor_vx_mu_rv32-1.C} (61%)
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_mu-2.C => vor_vx_mu_rv32-2.C} (62%)
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_mu-3.C => vor_vx_mu_rv32-3.C} (61%)
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_mu-1.C => vor_vx_mu_rv64-1.C} (62%)
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_mu-2.C => vor_vx_mu_rv64-2.C} (64%)
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_mu-3.C => vor_vx_mu_rv64-3.C} (62%)
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vor_vx_rv64-3.C
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tu-1.C => vor_vx_tu_rv32-1.C} (50%)
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tu-2.C => vor_vx_tu_rv32-2.C} (51%)
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tu-3.C => vor_vx_tu_rv32-3.C} (50%)
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tu-1.C => vor_vx_tu_rv64-1.C} (52%)
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tu-2.C => vor_vx_tu_rv64-2.C} (53%)
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tu-3.C => vor_vx_tu_rv64-3.C} (52%)
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tum-1.C => vor_vx_tum_rv32-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tum-2.C => vor_vx_tum_rv32-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tum-3.C => vor_vx_tum_rv32-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tum-1.C => vor_vx_tum_rv64-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tum-2.C => vor_vx_tum_rv64-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tum-3.C => vor_vx_tum_rv64-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tumu-1.C => vor_vx_tumu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tumu-2.C => vor_vx_tumu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tumu-3.C => vor_vx_tumu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tumu-1.C => vor_vx_tumu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tumu-2.C => vor_vx_tumu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vor_vv_tumu-3.C => vor_vx_tumu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_mu-1.C => vrem_vx_mu_rv32-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_mu-2.C => vrem_vx_mu_rv32-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_mu-3.C => vrem_vx_mu_rv32-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_mu-1.C => vrem_vx_mu_rv64-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_mu-2.C => vrem_vx_mu_rv64-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_mu-3.C => vrem_vx_mu_rv64-3. [...]
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrem_vx_rv64-3.C
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tu-1.C => vrem_vx_tu_rv32-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tu-2.C => vrem_vx_tu_rv32-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tu-3.C => vrem_vx_tu_rv32-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tu-1.C => vrem_vx_tu_rv64-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tu-2.C => vrem_vx_tu_rv64-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tu-3.C => vrem_vx_tu_rv64-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tum-1.C => vrem_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tum-2.C => vrem_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tum-3.C => vrem_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tum-1.C => vrem_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tum-2.C => vrem_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tum-3.C => vrem_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tumu-1.C => vrem_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tumu-2.C => vrem_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tumu-3.C => vrem_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tumu-1.C => vrem_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tumu-2.C => vrem_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vrem_vv_tumu-3.C => vrem_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_mu-1.C => vremu_vx_mu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_mu-2.C => vremu_vx_mu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_mu-3.C => vremu_vx_mu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_mu-1.C => vremu_vx_mu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_mu-2.C => vremu_vx_mu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_mu-3.C => vremu_vx_mu_rv64- [...]
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vremu_vx_rv64-3.C
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tu-1.C => vremu_vx_tu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tu-2.C => vremu_vx_tu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tu-3.C => vremu_vx_tu_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tu-1.C => vremu_vx_tu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tu-2.C => vremu_vx_tu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tu-3.C => vremu_vx_tu_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tum-1.C => vremu_vx_tum_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tum-2.C => vremu_vx_tum_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tum-3.C => vremu_vx_tum_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tum-1.C => vremu_vx_tum_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tum-2.C => vremu_vx_tum_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tum-3.C => vremu_vx_tum_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tumu-1.C => vremu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tumu-2.C => vremu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tumu-3.C => vremu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tumu-1.C => vremu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tumu-2.C => vremu_vx_tumu_r [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vremu_vv_tumu-3.C => vremu_vx_tumu_r [...]
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_mu_rv64-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_rv64-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tu_rv64-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tum_rv64-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vrsub_vx_tumu_rv64-3.C
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_mu-1.C => vsub_vx_mu_rv32-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_mu-2.C => vsub_vx_mu_rv32-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_mu-3.C => vsub_vx_mu_rv32-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_mu-1.C => vsub_vx_mu_rv64-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_mu-2.C => vsub_vx_mu_rv64-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_mu-3.C => vsub_vx_mu_rv64-3. [...]
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsub_vx_rv64-3.C
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tu-1.C => vsub_vx_tu_rv32-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tu-2.C => vsub_vx_tu_rv32-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tu-3.C => vsub_vx_tu_rv32-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tu-1.C => vsub_vx_tu_rv64-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tu-2.C => vsub_vx_tu_rv64-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tu-3.C => vsub_vx_tu_rv64-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tum-1.C => vsub_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tum-2.C => vsub_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tum-3.C => vsub_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tum-1.C => vsub_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tum-2.C => vsub_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tum-3.C => vsub_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tumu-1.C => vsub_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tumu-2.C => vsub_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tumu-3.C => vsub_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tumu-1.C => vsub_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tumu-2.C => vsub_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vsub_vv_tumu-3.C => vsub_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_mu-1.C => vxor_vx_mu_rv32-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_mu-2.C => vxor_vx_mu_rv32-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_mu-3.C => vxor_vx_mu_rv32-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_mu-1.C => vxor_vx_mu_rv64-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_mu-2.C => vxor_vx_mu_rv64-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_mu-3.C => vxor_vx_mu_rv64-3. [...]
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv32-3.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-1.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-2.C
create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vxor_vx_rv64-3.C
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tu-1.C => vxor_vx_tu_rv32-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tu-2.C => vxor_vx_tu_rv32-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tu-3.C => vxor_vx_tu_rv32-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tu-1.C => vxor_vx_tu_rv64-1. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tu-2.C => vxor_vx_tu_rv64-2. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tu-3.C => vxor_vx_tu_rv64-3. [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tum-1.C => vxor_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tum-2.C => vxor_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tum-3.C => vxor_vx_tum_rv32- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tum-1.C => vxor_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tum-2.C => vxor_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tum-3.C => vxor_vx_tum_rv64- [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tumu-1.C => vxor_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tumu-2.C => vxor_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tumu-3.C => vxor_vx_tumu_rv3 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tumu-1.C => vxor_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tumu-2.C => vxor_vx_tumu_rv6 [...]
copy gcc/testsuite/g++.target/riscv/rvv/base/{vxor_vv_tumu-3.C => vxor_vx_tumu_rv6 [...]
create mode 100644 gcc/testsuite/gcc.target/i386/pr108724.c
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-23.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-24.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-25.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-26.c
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-29.c
copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-30.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-31.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-33.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-34.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-35.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-36.c
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-45.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-46.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-47.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-48.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-49.c
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-50.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-51.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-52.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-53.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-54.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-55.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-56.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-57.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-58.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-59.c
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-60.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-61.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-62.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-63.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-64.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-65.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-66.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-67.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-68.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-69.c
copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-70.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-71.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-72.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-73.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-74.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-75.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-76.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-77.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-78.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-79.c
copy gcc/testsuite/gcc.target/riscv/rvv/base/{binop_vv_constraint-1.c => binop_vx_ [...]
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-80.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-81.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-82.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-83.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-84.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-85.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-86.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-87.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-88.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-89.c
copy gcc/testsuite/gcc.target/riscv/rvv/base/{shift_vx_constraint-1.c => binop_vx_ [...]
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-90.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-91.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-92.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-93.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-94.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-95.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/binop_vx_constraint-96.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_m_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_m_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_m_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_m_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_m_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_m_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_mu_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_mu_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_mu_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_mu_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_mu_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_mu_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tu_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tu_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tu_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tu_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tu_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tu_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tum_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tum_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tum_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tum_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tum_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tum_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tumu_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tumu_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tumu_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tumu_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tumu_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vadd_vx_tumu_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_m_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_m_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_m_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_m_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_m_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_m_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_mu_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_mu_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_mu_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_mu_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_mu_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_mu_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_rv32-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_rv32-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_rv32-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_rv64-1.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_rv64-2.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_rv64-3.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vand_vx_tu_rv32-1.c
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create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_rv32-1.c
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create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vxor_vx_tumu_rv64-3.c
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[binutils-gdb] branch master updated (80aa6647b16 -> 779b2502783)
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from 80aa6647b16 Fix mmo memory leaks
new 779b2502783 RISC-V: Reduce effective linker relaxation passses
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ld/emultempl/riscvelf.em | 2 +-
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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk-code_size-spec2k6/gnu-aarch64-master-Os updated (eb4dd0a815 -> e84e7ee205)
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from eb4dd0a815 62: onsuccess: #14: 1: [TCWG CI] No change after binutils/gc [...]
new e84e7ee205 63: onsuccess: #15: 1: [TCWG CI] No change after binutils/gc [...]
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01-reset_artifacts/console.log.xz | Bin 1840 -> 1844 bytes
02-prepare_abe/console.log.xz | Bin 2800 -> 2772 bytes
03-build_abe-binutils/console.log.xz | Bin 31372 -> 31940 bytes
04-build_abe-stage1/console.log.xz | Bin 74404 -> 74484 bytes
05-clean_sysroot/console.log.xz | Bin 332 -> 332 bytes
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07-build_abe-glibc/console.log.xz | Bin 246892 -> 247000 bytes
08-build_abe-stage2/console.log.xz | Bin 183572 -> 183392 bytes
09-benchmark/benchmark-build.log | 102 +-
09-benchmark/benchmark.log | 100 +-
09-benchmark/console.log.xz | Bin 3820 -> 3772 bytes
10-check_regression/console.log.xz | Bin 15340 -> 15016 bytes
.../csv-results-vs-first-0/md5sum.csv | 2942 +-
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.../csv-results-vs-first-0/size.csv | 584574 +++++++--------
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.../csv-results-vs-first-1/perf.csv | 3781 +-
.../csv-results-vs-first-1/results.csv | 241684 +++----
.../csv-results-vs-first-1/size.csv | 636428 ++++++++--------
10-check_regression/csv-results-vs-first-1/sve.csv | 42 +-
.../csv-results-vs-first-1/vect.csv | 44 +-
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.../csv-results-vs-prev-0/results.csv | 477184 ++++++------
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.../csv-results-vs-prev-1/results.csv | 241684 +++----
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git/binutils_rev | 2 +-
git/gcc_rev | 2 +-
git/glibc_rev | 2 +-
git/linux_rev | 2 +-
mail/jira-body.txt | 48 +-
mail/mail-body.txt | 53 +-
mail/mail-subject.txt | 2 +-
manifest.sh | 36 +-
results_id | 2 +-
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save-temps/401.bzip2.tar.xz | Bin 0 -> 94476 bytes
save-temps/403.gcc.tar.xz | Bin 0 -> 3567072 bytes
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save-temps/433.milc.tar.xz | Bin 0 -> 167760 bytes
save-temps/434.zeusmp.tar.xz | Bin 0 -> 126512 bytes
save-temps/435.gromacs.tar.xz | Bin 0 -> 979240 bytes
save-temps/436.cactusADM.tar.xz | Bin 0 -> 725464 bytes
save-temps/437.leslie3d.tar.xz | Bin 0 -> 46336 bytes
save-temps/444.namd.tar.xz | Bin 0 -> 168352 bytes
save-temps/445.gobmk.tar.xz | Bin 0 -> 1833032 bytes
save-temps/447.dealII.tar.xz | Bin 0 -> 6165516 bytes
save-temps/450.soplex.tar.xz | Bin 0 -> 709924 bytes
save-temps/453.povray.tar.xz | Bin 0 -> 1335448 bytes
save-temps/454.calculix.tar.xz | Bin 0 -> 1232436 bytes
save-temps/456.hmmer.tar.xz | Bin 0 -> 379444 bytes
save-temps/458.sjeng.tar.xz | Bin 0 -> 148100 bytes
save-temps/459.GemsFDTD.tar.xz | Bin 0 -> 145032 bytes
save-temps/462.libquantum.tar.xz | Bin 0 -> 61684 bytes
save-temps/464.h264ref.tar.xz | Bin 0 -> 563352 bytes
save-temps/465.tonto.tar.xz | Bin 0 -> 2068872 bytes
save-temps/470.lbm.tar.xz | Bin 0 -> 26328 bytes
save-temps/471.omnetpp.tar.xz | Bin 0 -> 1066824 bytes
save-temps/473.astar.tar.xz | Bin 0 -> 88336 bytes
save-temps/481.wrf.tar.xz | Bin 0 -> 1583616 bytes
save-temps/482.sphinx3.tar.xz | Bin 0 -> 254240 bytes
.../size.csv => save-temps/483.xalancbmk.tar.xz | Bin 13474415 -> 11851876 bytes
126 files changed, 1969398 insertions(+), 2017028 deletions(-)
create mode 100644 save-temps/400.perlbench.tar.xz
create mode 100644 save-temps/401.bzip2.tar.xz
create mode 100644 save-temps/403.gcc.tar.xz
create mode 100644 save-temps/410.bwaves.tar.xz
create mode 100644 save-temps/416.gamess.tar.xz
create mode 100644 save-temps/429.mcf.tar.xz
create mode 100644 save-temps/433.milc.tar.xz
create mode 100644 save-temps/434.zeusmp.tar.xz
create mode 100644 save-temps/435.gromacs.tar.xz
create mode 100644 save-temps/436.cactusADM.tar.xz
create mode 100644 save-temps/437.leslie3d.tar.xz
create mode 100644 save-temps/444.namd.tar.xz
create mode 100644 save-temps/445.gobmk.tar.xz
create mode 100644 save-temps/447.dealII.tar.xz
create mode 100644 save-temps/450.soplex.tar.xz
create mode 100644 save-temps/453.povray.tar.xz
create mode 100644 save-temps/454.calculix.tar.xz
create mode 100644 save-temps/456.hmmer.tar.xz
create mode 100644 save-temps/458.sjeng.tar.xz
create mode 100644 save-temps/459.GemsFDTD.tar.xz
create mode 100644 save-temps/462.libquantum.tar.xz
create mode 100644 save-temps/464.h264ref.tar.xz
create mode 100644 save-temps/465.tonto.tar.xz
create mode 100644 save-temps/470.lbm.tar.xz
create mode 100644 save-temps/471.omnetpp.tar.xz
create mode 100644 save-temps/473.astar.tar.xz
create mode 100644 save-temps/481.wrf.tar.xz
create mode 100644 save-temps/482.sphinx3.tar.xz
copy 10-check_regression/csv-results-vs-first-0/size.csv => save-temps/483.xalancb [...]
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[gcc] branch master updated (e635681dd26 -> 2a37a4a3cbf)
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unknown user pushed a change to branch master
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from e635681dd26 Add x86_64-gnu target to contrib/config-list.mk
new 2a37a4a3cbf Revert "docs: add caveat for __builtin_cpu_supports"
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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-mainline-allnoconfig updated (3ee12a0bd2 -> d963555354)
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01-reset_artifacts/console.log.xz | Bin 1772 -> 1788 bytes
02-prepare_abe/console.log.xz | Bin 2764 -> 2792 bytes
03-build_abe-binutils/console.log.xz | Bin 31088 -> 32056 bytes
04-build_kernel_llvm/console.log.xz | Bin 65712 -> 65888 bytes
05-build_abe-qemu/console.log.xz | Bin 32048 -> 31972 bytes
06-build_linux/console.log.xz | Bin 3084 -> 3104 bytes
07-boot_linux/console.log.xz | Bin 504 -> 504 bytes
08-check_regression/console.log.xz | Bin 4288 -> 4444 bytes
09-update_baseline/console.log | 8 ++++----
dashboard/dashboard-generate.sh | 2 +-
git/binutils_rev | 2 +-
git/linux_rev | 2 +-
git/llvm_rev | 2 +-
git/qemu_rev | 2 +-
mail/jira-body.txt | 2 +-
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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk-fujitsu_speed-cpu2017rate/gnu-aarch64-master-O2 updated (6ed74d2b44 -> 77af556247)
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01-reset_artifacts/console.log.xz | Bin 1756 -> 1804 bytes
02-prepare_abe/console.log.xz | Bin 2768 -> 2752 bytes
03-build_abe-binutils/console.log.xz | Bin 31784 -> 31820 bytes
04-build_abe-stage1/console.log.xz | Bin 73956 -> 74076 bytes
05-clean_sysroot/console.log.xz | Bin 332 -> 332 bytes
06-build_abe-linux/console.log.xz | Bin 9192 -> 9128 bytes
07-build_abe-glibc/console.log.xz | Bin 247008 -> 247192 bytes
08-build_abe-stage2/console.log.xz | Bin 183872 -> 183716 bytes
09-benchmark/benchmark-build.log | 108 +-
09-benchmark/benchmark.log | 106 +-
09-benchmark/console.log.xz | Bin 3852 -> 3880 bytes
10-check_regression/console.log.xz | Bin 13704 -> 13156 bytes
.../csv-results-vs-first-1/md5sum.csv | 2054 +-
.../csv-results-vs-first-1/perf.csv | 2773 +-
.../csv-results-vs-first-1/results.csv | 15810 +-
.../csv-results-vs-first-1/size.csv | 423334 ++++++++-------
10-check_regression/csv-results-vs-first-1/sve.csv | 13986 +-
.../csv-results-vs-first-1/vect.csv | 256 +-
.../csv-results-vs-prev-0/md5sum.csv | 2379 +-
10-check_regression/csv-results-vs-prev-0/perf.csv | 2800 +-
.../csv-results-vs-prev-0/results.csv | 15794 +-
10-check_regression/csv-results-vs-prev-0/size.csv | 498384 +++++++++---------
10-check_regression/csv-results-vs-prev-0/sve.csv | 23130 +-
10-check_regression/csv-results-vs-prev-0/vect.csv | 274 +-
.../csv-results-vs-prev-1/md5sum.csv | 2054 +-
10-check_regression/csv-results-vs-prev-1/perf.csv | 2773 +-
.../csv-results-vs-prev-1/results.csv | 15810 +-
10-check_regression/csv-results-vs-prev-1/size.csv | 423334 ++++++++-------
10-check_regression/csv-results-vs-prev-1/sve.csv | 13986 +-
10-check_regression/csv-results-vs-prev-1/vect.csv | 256 +-
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10-check_regression/results-vs-first-full.csv | 2692 +-
10-check_regression/results-vs-first-internal.csv | 186 +-
10-check_regression/results-vs-first.csv | 186 +-
10-check_regression/results-vs-first.log | 1022 +-
10-check_regression/results-vs-prev-brief.csv | 56 +-
10-check_regression/results-vs-prev-compare.csv | 6 +-
10-check_regression/results-vs-prev-full.csv | 2862 +-
10-check_regression/results-vs-prev-internal.csv | 190 +-
10-check_regression/results-vs-prev.csv | 190 +-
10-check_regression/results-vs-prev.log | 1220 +-
10-check_regression/skipped-symbols.txt | 6 +-
dashboard/dashboard-generate.sh | 2 +-
.../500.perlbench_r/results-metadata.json | 10 +-
.../squad-vs-first/502.gcc_r/results-metadata.json | 10 +-
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dashboard/squad-vs-first/dashboard-push-squad.sh | 98 +-
git/linux_rev | 2 +-
mail/jira-body.txt | 11 +-
mail/mail-body.txt | 11 +-
mail/mail-subject.txt | 2 +-
manifest.sh | 10 +-
results_id | 2 +-
82 files changed, 721478 insertions(+), 746989 deletions(-)
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[binutils-gdb] branch master updated (fe8cdc8ec14 -> 80aa6647b16)
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[gcc] branch master updated (6a5cb782d14 -> e635681dd26)
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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig updated (861f28308e -> 4375442067)
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01-reset_artifacts/console.log.xz | Bin 2016 -> 1772 bytes
02-prepare_abe/console.log.xz | Bin 2772 -> 2812 bytes
03-build_abe-binutils/console.log.xz | Bin 30716 -> 31692 bytes
04-build_kernel_llvm/console.log.xz | Bin 63012 -> 65308 bytes
05-build_abe-qemu/console.log.xz | Bin 30448 -> 31124 bytes
06-build_linux/console.log.xz | Bin 3608 -> 3620 bytes
07-boot_linux/console.log.xz | Bin 496 -> 496 bytes
08-check_regression/console.log.xz | Bin 3836 -> 4516 bytes
09-update_baseline/console.log | 8 ++++----
dashboard/dashboard-generate.sh | 2 +-
git/binutils_rev | 2 +-
git/linux_rev | 2 +-
git/llvm_rev | 2 +-
git/qemu_rev | 2 +-
mail/jira-body.txt | 2 +-
mail/mail-body.txt | 2 +-
mail/mail-subject.txt | 2 +-
manifest.sh | 32 ++++++++++++++++----------------
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