Tcwg-commits February 2023

tcwg-commits@lists.linaro.org

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3393 discussions

[gcc] branch master updated (81f0945cd97 -> d482b20fd34)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 81f0945cd97 RISC-V: Add vmacc vv c++ api tests new d482b20fd34 warn-access: wrong -Wdangling-pointer with labels [PR106080] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/gimple-ssa-warn-access.cc | 19 +++++-------------- gcc/testsuite/c-c++-common/Wdangling-pointer-10.c | 12 ++++++++++++ gcc/testsuite/c-c++-common/Wdangling-pointer-9.c | 9 +++++++++ 3 files changed, 26 insertions(+), 14 deletions(-) create mode 100644 gcc/testsuite/c-c++-common/Wdangling-pointer-10.c create mode 100644 gcc/testsuite/c-c++-common/Wdangling-pointer-9.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[gcc] branch master updated (a75fa2518d4 -> 81f0945cd97)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from a75fa2518d4 RISC-V: Add vmseq vv C++ tests new 272e119d972 RISC-V: Finish all integer C/C++ intrinsics new a432d0d9e06 RISC-V: Add vwmacc vx C api tests new 645bfe04ce1 RISC-V: Add vwmacc vv C api tests new 51307617b4a RISC-V: Add vnmsub vv C api tests new a462e612073 RISC-V: Add vnmsub vx rv64 C api tests new 496ae797c20 RISC-V: Add vnmsub vx rv32 C api tests new 3a70551148e RISC-V: Add vnmsac rv64 C api tests new 1d403b1e79f RISC-V: Add vnmsac vx C api tests new 46444e3984a RISC-V: Add vnmsac vv C api tests new 0bca2036dc7 RISC-V: Add vmadd vx rv64 c api tests new 0033ab7b923 RISC-V: Add vmadd vx c api tests new abbfd706cee RISC-V: Add vmadd vv C api tests new 987f4bb2f8d RISC-V: Add vmacc vx c api tests new dce0e53cf62 RISC-V: Add vmacc vx rv32 c api tests new ddd7c2e9489 RISC-V: Add vmacc vv c api tests new 5cf9afc5965 RISC-V: Add ternary constraint tests new c4e2a63e462 RISC-V: Add vwmacc vx C++ api tests new a5012e90b25 RISC-V: Add vwmacc vv C++ api tests new 326fe0f2f55 RISC-V: Add vnmsub vx rv64 c++ api tests new 1ff4063f258 RISC-V: Add vnmsub vx rv32 c++ api tests new 249be04bb83 RISC-V: Add vnmsub vv c++ api tests new 7ce337324a8 RISC-V: Add vnmsac vx rv64 C++ api tests new 0fd29de569b RISC-V: Add vnmsac vx C++ api tests new 47919b0decb RISC-V: Add vnmsac vv c++ api tests new 4e43f0cb269 RISC-V: Add vmadd vx C++ api test new 5db1182b7ca RISC-V: Add vmadd vv c++ api test new 1ec316c538a RISC-V: Add vmacc vx rv32 c++ api tests new 4a9a9a787b9 RISC-V: Add vmacc vx rv64 c++ api tests new 81f0945cd97 RISC-V: Add vmacc vv c++ api tests The 29 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/riscv/predicates.md | 3 +- gcc/config/riscv/riscv-protos.h | 2 + gcc/config/riscv/riscv-v.cc | 4 +- gcc/config/riscv/riscv-vector-builtins-bases.cc | 142 +++++ gcc/config/riscv/riscv-vector-builtins-bases.h | 8 + .../riscv/riscv-vector-builtins-functions.def | 15 + gcc/config/riscv/riscv-vector-builtins.cc | 243 +++++++- gcc/config/riscv/riscv-vector-builtins.h | 2 + gcc/config/riscv/vector.md | 680 ++++++++++++++++++++- .../g++.target/riscv/rvv/base/vmacc_vv-1.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmacc_vv-2.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmacc_vv-3.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_mu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_mu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_mu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_tu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_tu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_tu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_tum-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_tum-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_tum-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_tumu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_tumu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vv_tumu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_mu_rv32-1.C | 289 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_mu_rv32-2.C | 289 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_mu_rv32-3.C | 289 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_mu_rv64-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_mu_rv64-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_mu_rv64-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_rv32-1.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_rv32-2.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_rv32-3.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_rv64-1.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_rv64-2.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_rv64-3.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_tu_rv32-1.C | 289 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_tu_rv32-2.C | 289 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_tu_rv32-3.C | 289 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_tu_rv64-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_tu_rv64-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmacc_vx_tu_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv64-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv-1.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmadd_vv-2.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmadd_vv-3.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_mu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_mu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_mu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_tu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_tu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_tu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_tum-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_tum-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_tum-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_tumu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_tumu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vv_tumu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vx_mu_rv64-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vx_mu_rv64-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vx_mu_rv64-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vx_rv64-1.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmadd_vx_rv64-2.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmadd_vx_rv64-3.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vmadd_vx_tu_rv64-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vx_tu_rv64-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vmadd_vx_tu_rv64-3.C | 292 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+++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv_tum-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv_tum-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv_tumu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv_tumu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsac_vv_tumu-3.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv64-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsac_vx_rv32-1.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsac_vx_rv32-2.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsac_vx_rv32-3.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsac_vx_rv64-1.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsac_vx_rv64-2.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsac_vx_rv64-3.C | 578 ++++++++++++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv64-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv-1.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv-2.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv-3.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_mu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_mu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_mu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_tu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_tu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_tu-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_tum-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_tum-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_tum-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_tumu-1.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_tumu-2.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vv_tumu-3.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv64-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vnmsub_vx_rv32-1.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsub_vx_rv32-2.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsub_vx_rv32-3.C | 572 +++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsub_vx_rv64-1.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsub_vx_rv64-2.C | 578 ++++++++++++++++++ .../g++.target/riscv/rvv/base/vnmsub_vx_rv64-3.C | 578 ++++++++++++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv64-3.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv32-1.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv32-2.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv32-3.C | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv64-1.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv64-2.C | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv64-3.C | 292 +++++++++ .../g++.target/riscv/rvv/base/vwmacc_vv-1.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmacc_vv-2.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmacc_vv-3.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmacc_vv_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vv_tumu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx-1.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmacc_vx-2.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmacc_vx-3.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmacc_vx_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmacc_vx_tumu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv-1.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv-2.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv-3.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx-1.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx-2.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx-3.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccsu_vx_tumu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv-1.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccu_vv-2.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccu_vv-3.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vv_tumu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx-1.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccu_vx-2.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccu_vx-3.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccu_vx_tumu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx-1.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccus_vx-2.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccus_vx-3.C | 216 +++++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_mu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_mu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_mu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_tu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_tu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_tu-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_tum-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_tum-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_tum-3.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_tumu-1.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_tumu-2.C | 111 ++++ .../g++.target/riscv/rvv/base/vwmaccus_vx_tumu-3.C | 111 ++++ .../riscv/rvv/base/ternop_vv_constraint-1.c | 83 +++ .../riscv/rvv/base/ternop_vv_constraint-2.c | 83 +++ .../riscv/rvv/base/ternop_vx_constraint-1.c | 71 +++ .../riscv/rvv/base/ternop_vx_constraint-2.c | 38 ++ ...vx_constraint-91.c => ternop_vx_constraint-3.c} | 58 +- ...vx_constraint-91.c => ternop_vx_constraint-4.c} | 62 +- ...vx_constraint-57.c => ternop_vx_constraint-5.c} | 62 +- .../riscv/rvv/base/ternop_vx_constraint-6.c | 130 ++++ .../riscv/rvv/base/ternop_vx_constraint-7.c | 130 ++++ .../gcc.target/riscv/rvv/base/vmacc_vv-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_m-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_m-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_m-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_mu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_mu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_mu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_tu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_tu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_tu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_tum-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_tum-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_tum-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_tumu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_tumu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vv_tumu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_m_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_m_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_m_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_m_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_m_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_m_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_mu_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_mu_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_mu_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_mu_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_mu_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_mu_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_tu_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_tu_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_tu_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_tu_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_tu_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmacc_vx_tu_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tum_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vmacc_vx_tumu_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_m-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_m-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_m-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_mu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_mu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_mu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_tu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_tu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_tu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_tum-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_tum-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_tum-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_tumu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_tumu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vv_tumu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_m_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_m_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_m_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_m_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_m_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_m_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_mu_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_mu_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_mu_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_mu_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_mu_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_mu_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_tu_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_tu_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_tu_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_tu_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_tu_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vmadd_vx_tu_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vmadd_vx_tum_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tum_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tum_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tum_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vmadd_vx_tum_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vmadd_vx_tum_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vmadd_vx_tumu_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tumu_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tumu_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vmadd_vx_tumu_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vmadd_vx_tumu_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vmadd_vx_tumu_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_m-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_m-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_m-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_mu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_mu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_mu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_tu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_tu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_tu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_tum-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_tum-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_tum-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_tumu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_tumu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vv_tumu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_m_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_m_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_m_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_m_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_mu_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsac_vx_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tu_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tum_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vnmsac_vx_tumu_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_m-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_m-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_m-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_mu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_mu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_mu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_tu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_tu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_tu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_tum-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_tum-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_tum-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_tumu-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_tumu-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vv_tumu-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_m_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_m_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_m_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_m_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_m_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_m_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_mu_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_rv32-1.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_rv32-2.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_rv32-3.c | 289 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_rv64-1.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_rv64-2.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vnmsub_vx_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tu_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tum_rv64-3.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv32-1.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv32-2.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv32-3.c | 289 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv64-1.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv64-2.c | 292 +++++++++ .../riscv/rvv/base/vnmsub_vx_tumu_rv64-3.c | 292 +++++++++ .../gcc.target/riscv/rvv/base/vwmacc_vv-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vv_tumu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmacc_vx_tumu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vv_tumu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccsu_vx_tumu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vv_tumu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccu_vx_tumu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_m-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_m-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_m-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_mu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_mu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_mu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_tu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_tu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_tu-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_tum-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_tum-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_tum-3.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-1.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-2.c | 111 ++++ .../gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-3.c | 111 ++++ 630 files changed, 149864 insertions(+), 110 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tum-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vv_tumu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_mu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tu_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tum_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmacc_vx_tum_rv32-2.C create mode 100644 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100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_mu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_mu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tu-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tum-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tum-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tum-3.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vwmaccus_vx_tumu-3.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allyesconfig updated (0bd520c2ff -> 6c0dd8dfaf)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allyesconfig in repository toolchain/ci/base-artifacts. from 0bd520c2ff 63: onsuccess: #554: 21422: Success after linux: 142737 commits new 6c0dd8dfaf 64: onsuccess: #555: 21422: Success after binutils/llvm/linu [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1712 -> 1772 bytes 02-prepare_abe/console.log.xz | Bin 2764 -> 2780 bytes 03-build_abe-binutils/console.log.xz | Bin 32116 -> 31464 bytes 04-build_kernel_llvm/console.log.xz | Bin 64372 -> 64332 bytes 05-build_abe-qemu/console.log.xz | Bin 31588 -> 32572 bytes 06-build_linux/console.log.xz | Bin 3628 -> 4476 bytes 08-check_regression/console.log.xz | Bin 2928 -> 4440 bytes 08-check_regression/mail-body.txt | 13 +------------ dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/linux_rev | 2 +- git/llvm_rev | 2 +- git/qemu_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 15 ++------------- mail/mail-subject.txt | 2 +- manifest.sh | 31 +++++++++++++++++-------------- 17 files changed, 27 insertions(+), 46 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 updated (d68dc19bd7 -> 30720ace6c)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-aarch64 in repository toolchain/ci/base-artifacts. discards d68dc19bd7 396: onsuccess: #2648: 1: Success after binutils/gcc/linux/g [...] discards f21bc893be 395: onsuccess: #2647: 1: Success after binutils/gcc/glibc/g [...] discards ac3fcd0404 394: onsuccess: #2646: 1: Success after binutils/gcc/glibc/g [...] discards 9e938ccc4e 393: onsuccess: #2645: 1: Success after binutils/gcc/linux/g [...] discards ef620fccba 392: onsuccess: #2643: 1: Success after binutils/gcc/linux/g [...] discards 69b477696f 391: onsuccess: #2642: 1: Success after binutils/gcc/gdb: 28 [...] discards 6843dd183b 390: onsuccess: #2641: 1: Success after binutils/gcc/gdb: 6 commits discards bf5990d0c5 389: onsuccess: #2640: 1: Success after binutils/gcc/linux/g [...] discards 2aa09b0972 388: onsuccess: #2639: 1: Success after gcc/glibc: 44 commits discards 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That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (d68dc19bd7) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_cross_check_gcc/mast [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 102 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1764 -> 1768 bytes 02-prepare_abe/console.log.xz | Bin 2776 -> 2768 bytes 03-build_abe-binutils/console.log.xz | Bin 31188 -> 31360 bytes 04-build_abe-stage1/console.log.xz | Bin 73408 -> 73316 bytes 06-build_abe-linux/console.log.xz | Bin 8544 -> 8608 bytes 07-build_abe-glibc/console.log.xz | Bin 244288 -> 245008 bytes 08-build_abe-stage2/console.log.xz | Bin 204504 -> 204972 bytes 09-build_abe-gdb/console.log.xz | Bin 38308 -> 38656 bytes 10-build_abe-qemu/console.log.xz | Bin 32452 -> 32608 bytes 11-build_abe-dejagnu/console.log.xz | Bin 3888 -> 3936 bytes 12-build_abe-check_gcc/console.log.xz | Bin 3056 -> 2640 bytes 13-check_regression/console.log.xz | Bin 7120 -> 6288 bytes 13-check_regression/fails.sum | 2 +- 13-check_regression/mail-body.txt | 71 +- 13-check_regression/results.compare | 36 +- 13-check_regression/results.compare2 | 74 +- 13-check_regression/results.regressions | 36 +- 14-update_baseline/console.log | 64 +- dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- git/gdb_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 73 +- mail/mail-subject.txt | 2 +- manifest.sh | 32 +- results | 36 +- sumfiles/g++.log.xz | Bin 3412204 -> 3382096 bytes sumfiles/g++.sum | 47 +- sumfiles/gcc.log.xz | Bin 3025540 -> 3023256 bytes sumfiles/gcc.sum | 4384 +++++++++++++++---------------- sumfiles/gfortran.log.xz | Bin 1039408 -> 1038624 bytes sumfiles/gfortran.sum | 4 +- sumfiles/libatomic.log.xz | Bin 2288 -> 2288 bytes sumfiles/libatomic.sum | 2 +- sumfiles/libgomp.log.xz | Bin 217664 -> 217592 bytes sumfiles/libgomp.sum | 7 +- sumfiles/libitm.log.xz | Bin 2656 -> 2656 bytes sumfiles/libitm.sum | 2 +- sumfiles/libstdc++.log.xz | Bin 437948 -> 436124 bytes sumfiles/libstdc++.sum | 66 +- 41 files changed, 2484 insertions(+), 2464 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap_ubsan updated (3080b03841 -> d6e52bc715)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap_ubsan in repository toolchain/ci/base-artifacts. discards 3080b03841 190: onsuccess: #613: 2: Success after binutils/gcc: 94 commits discards ad860ecab3 189: onsuccess: #612: 2: Success after binutils/gcc: 113 commits discards bf7c594549 188: onsuccess: #611: 2: Success after binutils/gcc: 57 commits discards 89b579635c 187: onsuccess: #610: 2: Success after binutils/gcc: 81 commits discards 7631e21f0e 186: onsuccess: #609: 2: Success after binutils/gcc: 10 commits discards 2aef0388b3 185: onsuccess: #608: 2: Success after binutils/gcc: 41 commits discards f3611cf540 184: onsuccess: #607: 2: Success after binutils/gcc: 15 commits discards f127057533 183: onsuccess: #606: 2: Success after binutils/gcc: 31 commits discards a6892ec4f6 182: onsuccess: #605: 2: Success after binutils/gcc: 6 commits discards e94e59fa01 181: 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binutils/gcc: 31 commits new bb6e5606ce 184: onsuccess: #607: 2: Success after binutils/gcc: 15 commits new f33caad880 185: onsuccess: #608: 2: Success after binutils/gcc: 41 commits new 1e50f6b854 186: onsuccess: #609: 2: Success after binutils/gcc: 10 commits new 4d5f1734b8 187: onsuccess: #610: 2: Success after binutils/gcc: 81 commits new b9bd6b1a0e 188: onsuccess: #611: 2: Success after binutils/gcc: 57 commits new a144a7b566 189: onsuccess: #612: 2: Success after binutils/gcc: 113 commits new 88ca50d09e 190: onsuccess: #613: 2: Success after binutils/gcc: 94 commits new d6e52bc715 191: onsuccess: #614: 2: Success after binutils/gcc: 31 commits This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (3080b03841) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_bootstrap/master-arm [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 102 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1744 -> 1756 bytes 02-prepare_abe/console.log.xz | Bin 2756 -> 2756 bytes 04-build_abe-binutils/console.log.xz | Bin 52220 -> 52948 bytes 05-build_abe-bootstrap_ubsan/console.log.xz | Bin 539952 -> 536972 bytes 06-check_regression/console.log.xz | Bin 3124 -> 3092 bytes 07-update_baseline/console.log | 56 ++++++++++++++-------------- dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 2 +- mail/mail-subject.txt | 2 +- manifest.sh | 18 ++++----- 13 files changed, 43 insertions(+), 43 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[newlib] branch master updated (d6d443614 -> 65446dd4f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository newlib. from d6d443614 Cygwin: glob: handle named character classes new 65446dd4f Cygwin: add glob/fnmatch named class support to release notes The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: winsup/cygwin/release/3.5.0 | 3 +++ winsup/doc/new-features.xml | 5 +++++ 2 files changed, 8 insertions(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[newlib] branch main updated (d6d443614 -> 65446dd4f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch main in repository newlib. from d6d443614 Cygwin: glob: handle named character classes new 65446dd4f Cygwin: add glob/fnmatch named class support to release notes The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: winsup/cygwin/release/3.5.0 | 3 +++ winsup/doc/new-features.xml | 5 +++++ 2 files changed, 8 insertions(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[gcc] branch master updated (142bd88c5f6 -> a75fa2518d4)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 142bd88c5f6 testsuite, objective-c: Fix a testcase on Windows. new acb51b5c801 RISC-V: Add integer compare C/C++ intrinsic support new fca68b0bbf8 RISC-V: Add vmsne.vx C api tests new 946ed63e616 RISC-V: Add vmsne vv C api tests new 13a256448a5 RISC-V: Add vmslt vx C api tests new 85a8ad0a351 RISC-V: Add vmslt vv C api tests new fec15ae4a38 RISC-V: Add vmsle vx C api tests new f7b8022bcd4 RISC-V: Add vmsle vv C api tests new 6dae0aa2484 RISC-V: Add vmsgt vx C api tests new fe1a6c2c8a2 RISC-V: Add vmsgt vv C api tests new 5893cfb26a1 RISC-V: Add vmsge vx C api tests new 52ba1d2e235 RISC-V: Add vmsge vv C api tests new 76db33c592d RISC-V: Add vmseq vx C api tests new 4d06fc37909 RISC-V: Add vmseq vv C api tests new 6ec7b7b3e46 RISC-V: Add binop constraints tests for integer compare new ecdbebde7cb RISC-V: Add vmsne vx C++ tests new f87fca5d7f2 RISC-V: Add vmsne vv C++ tests new 18f4691e31e RISC-V: Add vmslt vx C++ tests new 400f003ee55 RISC-V: Add vmslt vv C++ api tests new 6c4262a5259 RISC-V: Add vmsle vx C++ api tests new d6d9206d2b6 RISC-V: Add vmsle vv C++ api tests new cfbcbe8e27b RISC-V: Add vmsgt vx C++ tests new 0d689135ffd RISC-V: Add vmsgt vv C++ tests new 92e575eacf0 RISC-V: Add vmsge vx C++ api tests new 5e96553eba9 RISC-V: Add vmsge vv C++ tests new c4e770c4521 RISC-V: Add vmseq vx C++ tests new a75fa2518d4 RISC-V: Add vmseq vv C++ tests The 26 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/riscv/predicates.md | 25 +- gcc/config/riscv/riscv-v.cc | 32 +- gcc/config/riscv/riscv-vector-builtins-bases.cc | 54 ++ gcc/config/riscv/riscv-vector-builtins-bases.h | 10 + .../riscv/riscv-vector-builtins-functions.def | 20 + gcc/config/riscv/riscv-vector-builtins-shapes.cc | 2 + gcc/config/riscv/riscv-vector-builtins.cc | 77 ++ gcc/config/riscv/riscv-vector-builtins.h | 9 + gcc/config/riscv/riscv.cc | 7 +- gcc/config/riscv/riscv.md | 10 +- gcc/config/riscv/vector-iterators.md | 20 +- gcc/config/riscv/vector.md | 774 ++++++++++++++++++++- .../g++.target/riscv/rvv/base/vmseq_vv-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vv-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vv-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vv_m-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vv_m-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vv_m-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vv_mu-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vv_mu-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vv_mu-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_m_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_m_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_m_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_m_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_m_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_m_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_mu_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_mu_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_mu_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_mu_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_mu_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_mu_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmseq_vx_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsge_vv-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vv-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vv-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vv_m-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vv_m-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vv_m-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vv_mu-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vv_mu-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vv_mu-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_m_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_m_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_m_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_m_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_m_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_m_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_mu_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_mu_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_mu_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_mu_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_mu_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_mu_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsge_vx_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vv-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vv-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vv-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vv_m-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vv_m-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vv_m-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vv_mu-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vv_mu-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vv_mu-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_m_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_m_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_m_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_m_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_m_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_m_rv64-3.C | 160 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv32-1.C | 157 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv32-2.C | 157 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv32-3.C | 157 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv64-1.C | 160 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv64-2.C | 160 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgeu_vx_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vv-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vv-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vv-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vv_m-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vv_m-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vv_m-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vv_mu-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vv_mu-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vv_mu-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_m_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_m_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_mu_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_mu_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgt_vx_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vv-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vv-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vv-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vv_m-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vv_m-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vv_m-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vv_mu-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vv_mu-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vv_mu-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_m_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_m_rv64-3.C | 160 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv32-1.C | 157 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv32-2.C | 157 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv32-3.C | 157 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv64-1.C | 160 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv64-2.C | 160 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsgtu_vx_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vv-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vv-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vv-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vv_m-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vv_m-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vv_m-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vv_mu-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vv_mu-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vv_mu-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_m_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_m_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_m_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_m_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_m_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_m_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_mu_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_mu_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_mu_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_mu_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_mu_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_mu_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsle_vx_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vv-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vv-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vv-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vv_m-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vv_m-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vv_m-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vv_mu-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vv_mu-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vv_mu-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_m_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_m_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_m_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_m_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_m_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_m_rv64-3.C | 160 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv32-1.C | 157 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv32-2.C | 157 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv32-3.C | 157 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv64-1.C | 160 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv64-2.C | 160 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsleu_vx_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vv-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vv-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vv-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vv_m-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vv_m-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vv_m-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vv_mu-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vv_mu-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vv_mu-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_m_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_m_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_m_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_m_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_m_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_m_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_mu_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_mu_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_mu_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_mu_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_mu_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_mu_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmslt_vx_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vv-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vv-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vv-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vv_m-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vv_m-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vv_m-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vv_mu-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vv_mu-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vv_mu-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_m_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_m_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_m_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_m_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_m_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_m_rv64-3.C | 160 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv32-1.C | 157 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv32-2.C | 157 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv32-3.C | 157 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv64-1.C | 160 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv64-2.C | 160 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_rv32-1.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_rv32-2.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_rv32-3.C | 157 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_rv64-1.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_rv64-2.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsltu_vx_rv64-3.C | 160 +++++ .../g++.target/riscv/rvv/base/vmsne_vv-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vv-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vv-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vv_m-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vv_m-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vv_m-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vv_mu-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vv_mu-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vv_mu-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_m_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_m_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_m_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_m_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_m_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_m_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_mu_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_mu_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_mu_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_mu_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_mu_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_mu_rv64-3.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_rv32-1.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_rv32-2.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_rv32-3.C | 289 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_rv64-1.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_rv64-2.C | 292 ++++++++ .../g++.target/riscv/rvv/base/vmsne_vx_rv64-3.C | 292 ++++++++ .../riscv/rvv/base/binop_vv_constraint-2.c | 15 + .../riscv/rvv/base/binop_vv_constraint-3.c | 27 + .../riscv/rvv/base/binop_vv_constraint-4.c | 27 + .../riscv/rvv/base/binop_vv_constraint-5.c | 29 + .../riscv/rvv/base/binop_vv_constraint-6.c | 27 + .../riscv/rvv/base/binop_vv_constraint-7.c | 29 + .../riscv/rvv/base/binop_vx_constraint-123.c | 15 + .../riscv/rvv/base/binop_vx_constraint-124.c | 27 + .../riscv/rvv/base/binop_vx_constraint-125.c | 27 + .../riscv/rvv/base/binop_vx_constraint-126.c | 29 + .../riscv/rvv/base/binop_vx_constraint-127.c | 27 + .../riscv/rvv/base/binop_vx_constraint-128.c | 29 + .../riscv/rvv/base/binop_vx_constraint-129.c | 69 ++ .../riscv/rvv/base/binop_vx_constraint-130.c | 69 ++ .../riscv/rvv/base/binop_vx_constraint-131.c | 69 ++ .../riscv/rvv/base/binop_vx_constraint-132.c | 59 ++ .../riscv/rvv/base/binop_vx_constraint-133.c | 69 ++ .../riscv/rvv/base/binop_vx_constraint-134.c | 69 ++ .../riscv/rvv/base/binop_vx_constraint-135.c | 69 ++ .../riscv/rvv/base/binop_vx_constraint-136.c | 59 ++ .../riscv/rvv/base/binop_vx_constraint-137.c | 123 ++++ .../riscv/rvv/base/binop_vx_constraint-138.c | 123 ++++ .../riscv/rvv/base/binop_vx_constraint-139.c | 72 ++ .../riscv/rvv/base/binop_vx_constraint-140.c | 72 ++ ..._constraint-101.c => binop_vx_constraint-141.c} | 10 +- ..._constraint-101.c => binop_vx_constraint-142.c} | 10 +- ..._constraint-100.c => binop_vx_constraint-143.c} | 10 +- ..._constraint-112.c => binop_vx_constraint-144.c} | 10 +- ..._constraint-101.c => binop_vx_constraint-145.c} | 10 +- ..._constraint-113.c => binop_vx_constraint-146.c} | 10 +- .../riscv/rvv/base/binop_vx_constraint-147.c | 19 + .../riscv/rvv/base/binop_vx_constraint-148.c | 20 + .../riscv/rvv/base/binop_vx_constraint-149.c | 19 + .../riscv/rvv/base/binop_vx_constraint-150.c | 21 + .../riscv/rvv/base/binop_vx_constraint-151.c | 20 + .../riscv/rvv/base/binop_vx_constraint-152.c | 20 + .../riscv/rvv/base/binop_vx_constraint-153.c | 75 ++ .../riscv/rvv/base/binop_vx_constraint-154.c | 69 ++ .../riscv/rvv/base/binop_vx_constraint-155.c | 69 ++ .../riscv/rvv/base/binop_vx_constraint-156.c | 65 ++ .../riscv/rvv/base/binop_vx_constraint-157.c | 133 ++++ .../riscv/rvv/base/binop_vx_constraint-158.c | 69 ++ .../riscv/rvv/base/binop_vx_constraint-159.c | 65 ++ .../riscv/rvv/base/binop_vx_constraint-160.c | 133 ++++ .../riscv/rvv/base/binop_vx_constraint-161.c | 76 ++ ..._constraint-111.c => binop_vx_constraint-162.c} | 11 +- ..._constraint-100.c => binop_vx_constraint-163.c} | 10 +- ..._constraint-113.c => binop_vx_constraint-164.c} | 10 +- .../riscv/rvv/base/binop_vx_constraint-165.c | 13 + .../riscv/rvv/base/binop_vx_constraint-166.c | 15 + .../gcc.target/riscv/rvv/base/vmseq_vv-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vv-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vv-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vv_m-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vv_m-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vv_m-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vv_mu-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vv_mu-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vv_mu-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_m_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_m_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_m_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_m_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_m_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_m_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_mu_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_mu_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_mu_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_mu_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_mu_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_mu_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmseq_vx_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsge_vv-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vv-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vv-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vv_m-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vv_m-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vv_m-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vv_mu-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vv_mu-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vv_mu-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_m_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_mu_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsge_vx_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vv-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vv-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vv-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vv_m-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vv_m-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vv_m-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vv_mu-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vv_mu-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vv_mu-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_m_rv64-3.c | 160 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv32-1.c | 157 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv32-2.c | 157 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv32-3.c | 157 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv64-1.c | 160 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv64-2.c | 160 +++++ .../riscv/rvv/base/vmsgeu_vx_mu_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgeu_vx_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vv-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vv-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vv-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vv_m-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vv_m-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vv_m-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vv_mu-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vv_mu-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vv_mu-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_m_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_m_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_mu_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgt_vx_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vv-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vv-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vv-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vv_m-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vv_m-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vv_m-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vv_mu-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vv_mu-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vv_mu-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_m_rv64-3.c | 160 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv32-1.c | 157 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv32-2.c | 157 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv32-3.c | 157 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv64-1.c | 160 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv64-2.c | 160 +++++ .../riscv/rvv/base/vmsgtu_vx_mu_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsgtu_vx_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vv-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vv-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vv-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vv_m-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vv_m-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vv_m-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vv_mu-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vv_mu-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vv_mu-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_m_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_m_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_m_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_m_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_m_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_m_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_mu_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_mu_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_mu_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_mu_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_mu_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_mu_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsle_vx_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vv-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vv-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vv-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vv_m-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vv_m-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vv_m-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vv_mu-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vv_mu-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vv_mu-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_m_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_m_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_m_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_m_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_m_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_m_rv64-3.c | 160 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv32-1.c | 157 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv32-2.c | 157 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv32-3.c | 157 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv64-1.c | 160 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv64-2.c | 160 +++++ .../riscv/rvv/base/vmsleu_vx_mu_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsleu_vx_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vv-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vv-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vv-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vv_m-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vv_m-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vv_m-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vv_mu-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vv_mu-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vv_mu-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_m_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_m_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_m_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_m_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_m_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_m_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_mu_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_mu_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_mu_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_mu_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_mu_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_mu_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmslt_vx_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vv-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vv-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vv-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vv_m-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vv_m-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vv_m-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vv_mu-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vv_mu-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vv_mu-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_m_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_m_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_m_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_m_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_m_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_m_rv64-3.c | 160 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv32-1.c | 157 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv32-2.c | 157 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv32-3.c | 157 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv64-1.c | 160 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv64-2.c | 160 +++++ .../riscv/rvv/base/vmsltu_vx_mu_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_rv32-1.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_rv32-2.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_rv32-3.c | 157 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_rv64-1.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_rv64-2.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsltu_vx_rv64-3.c | 160 +++++ .../gcc.target/riscv/rvv/base/vmsne_vv-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv_m-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv_m-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv_m-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv_mu-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv_mu-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vv_mu-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_m_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_m_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_m_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_m_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_m_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_m_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_mu_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_mu_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_mu_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_mu_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_mu_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_mu_rv64-3.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_rv32-1.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_rv32-2.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_rv32-3.c | 289 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_rv64-1.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_rv64-2.c | 292 ++++++++ .../gcc.target/riscv/rvv/base/vmsne_vx_rv64-3.c | 292 ++++++++ 602 files changed, 103292 insertions(+), 86 deletions(-) create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_m-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vv_mu-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_m_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_m_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_m_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_m_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_m_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_m_rv64-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_mu_rv32-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_mu_rv32-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_mu_rv32-3.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_mu_rv64-1.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_mu_rv64-2.C create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vmseq_vx_mu_rv64-3.C create mode 100644 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1 year, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk-code_speed-spec2k6/llvm-arm-master-O3 updated (2e29d3769c -> 0258cebddf)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk-code_speed-spec2k6/llvm-arm-master-O3 in repository toolchain/ci/base-artifacts. from 2e29d3769c 55: onsuccess: #17: 1: [TCWG CI] No change after binutils/gc [...] new 0258cebddf 56: onsuccess: #18: 1: [TCWG CI] No change after binutils/gc [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1796 -> 1840 bytes 02-prepare_abe/console.log.xz | Bin 2772 -> 2772 bytes 03-build_abe-binutils/console.log.xz | Bin 31212 -> 31524 bytes 04-build_abe-stage1/console.log.xz | Bin 91792 -> 94160 bytes 06-build_abe-linux/console.log.xz | Bin 8676 -> 8684 bytes 07-build_abe-glibc/console.log.xz | Bin 235948 -> 237600 bytes 08-build_abe-stage2/console.log.xz | Bin 213788 -> 219684 bytes 09-build_llvm-true-false-cflags-/console.log.xz | Bin 64216 -> 63992 bytes 10-benchmark/benchmark-build.log | 131 +- 10-benchmark/benchmark.log | 129 +- 10-benchmark/console.log.xz | Bin 4056 -> 4032 bytes 11-check_regression/console.log.xz | Bin 14032 -> 14500 bytes .../csv-results-vs-first-0/md5sum.csv | 934 +- .../csv-results-vs-first-0/results.csv | 208642 ++++++------ .../csv-results-vs-first-0/size.csv | 255162 +++++++------- 11-check_regression/csv-results-vs-first-0/sve.csv | 16 +- .../csv-results-vs-first-0/vect.csv | 20072 +- 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111 files changed, 1073965 insertions(+), 1108365 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_native_fast_check_gdb/master-arm updated (43cea30343 -> 8c49a10ca1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_native_fast_check_gdb/master-arm in repository toolchain/ci/base-artifacts. from 43cea30343 97: onsuccess: #107: 1: Success after binutils/gcc/linux/gli [...] new 8c49a10ca1 98: onsuccess: #108: 1: Success after binutils/gcc/linux/gli [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1748 -> 1928 bytes 02-prepare_abe/console.log.xz | Bin 2756 -> 2756 bytes 03-build_abe-binutils/console.log.xz | Bin 51924 -> 52124 bytes 04-build_abe-gcc/console.log.xz | Bin 238612 -> 236824 bytes 05-clean_sysroot/console.log.xz | Bin 316 -> 316 bytes 06-build_abe-linux/console.log.xz | Bin 9036 -> 8572 bytes 07-build_abe-glibc/console.log.xz | Bin 235628 -> 236040 bytes 08-build_abe-gdb/console.log.xz | Bin 50236 -> 51472 bytes 09-build_abe-dejagnu/console.log.xz | Bin 3824 -> 3868 bytes 10-build_abe-check_gdb/console.log.xz | Bin 2696 -> 2708 bytes 11-check_regression/console.log.xz | Bin 6256 -> 6108 bytes 11-check_regression/results.compare | 4 ++-- 11-check_regression/results.compare2 | 6 +++--- 12-update_baseline/console.log | 9 +++++++++ dashboard/dashboard-generate.sh | 2 +- git/binutils_rev | 2 +- git/gcc_rev | 2 +- git/gdb_rev | 2 +- git/glibc_rev | 2 +- git/linux_rev | 2 +- mail/jira-body.txt | 2 +- mail/mail-body.txt | 2 +- mail/mail-subject.txt | 2 +- manifest.sh | 36 +++++++++++++++++----------------- sumfiles/gdb.log.xz | Bin 11936 -> 11932 bytes sumfiles/gdb.sum | 30 ++++++++++++++-------------- 26 files changed, 56 insertions(+), 47 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

1 year, 9 months

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