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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk-code_speed-cpu2017rate/gnu-aarch64-master-O2_LTO
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discards 8df6255 onsuccess: #108: 1: [TCWG CI] https://ci.linaro.org/job/tcwg_ [...]
discards 69a0e21 onsuccess: #107: 1: [TCWG CI] https://ci.linaro.org/job/tcwg_ [...]
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk-code_speed-cpu2017rate/gnu-aarch64-master-O2_LTO
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unknown user pushed a change to branch master
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from 11b8cf1685b tree-optimization/111715 - improve TBAA for access paths with pun
new 578aa2f8005 THead: Fix missing CFI directives for th.sdd in prologue.
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gcc/config/riscv/thead.cc | 11 +++++----
gcc/testsuite/gcc.target/riscv/xtheadmempair-4.c | 29 ++++++++++++++++++++++++
2 files changed, 35 insertions(+), 5 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-4.c
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk-code_speed-cpu2017rate/gnu-aarch64-master-O2_LTO
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discards afbf947 onsuccess: #103: 1: [TCWG CI] https://ci.linaro.org/job/tcwg_ [...]
discards b4efab4 onsuccess: #102: 1: [TCWG CI] https://ci.linaro.org/job/tcwg_ [...]
new 3c01e17 onsuccess: #102: 1: [TCWG CI] https://ci.linaro.org/job/tcwg_ [...]
new 7d5cd5d onsuccess: #103: 1: [TCWG CI] https://ci.linaro.org/job/tcwg_ [...]
new 2aa0fc2 onsuccess: #104: 1: [TCWG CI] https://ci.linaro.org/job/tcwg_ [...]
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unknown user pushed a change to branch master
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from 3f99b709c87 testsuite: Fix vect_cond_arith_* dump checks for RVV.
new 1543f3e331b RISC-V Regression test: Fix FAIL of pr45752.c for RVV
new 841668aa02a RISC-V: Refine bswap16 auto vectorization code gen
new 11b8cf1685b tree-optimization/111715 - improve TBAA for access paths with pun
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gcc/alias.cc | 17 +++-
gcc/config/riscv/riscv-v.cc | 91 ++++++++++++++++++++++
gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-102.c | 32 ++++++++
gcc/testsuite/gcc.dg/vect/pr45752.c | 2 +-
.../gcc.target/riscv/rvv/autovec/unop/bswap16-0.c | 17 ++++
.../riscv/rvv/autovec/unop/bswap16-run-0.c | 44 +++++++++++
.../autovec/vls/{cond_convert-12.c => bswap16-0.c} | 32 ++++----
.../gcc.target/riscv/rvv/autovec/vls/perm-4.c | 4 +-
8 files changed, 218 insertions(+), 21 deletions(-)
create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-102.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-0.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/bswap16-run-0.c
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