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from e1e127de18d x86: set spincount 1 for x86 hybrid platform
new 32207b15b72 vect: Ensure vect store is supported for some VMAT_ELEMENTW [...]
new 3bf2366685b vect: Move vect_model_store_cost next to the transform in v [...]
new e00820c8e5c vect: Adjust vectorizable_store costing on VMAT_GATHER_SCATTER
new 7184d2257a0 vect: Simplify costing on vectorizable_scan_store
new 8b151eb96b9 vect: Adjust vectorizable_store costing on VMAT_ELEMENTWISE [...]
new 6a88202e5a4 vect: Adjust vectorizable_store costing on VMAT_LOAD_STORE_LANES
new 0a96eedb347 vect: Adjust vectorizable_store costing on VMAT_CONTIGUOUS_PERMUTE
new 0bdb9bb5607 vect: Get rid of vect_model_store_cost
new f1a05dc1805 vect: Consider vec_perm costing for VMAT_CONTIGUOUS_REVERSE
new 610b845a426 testsuite: Avoid uninit var in pr60510.f [PR111427]
new 530babc2058 rs6000: Make 32 bit stack_protect support prefixed insn [PR111367]
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Summary of changes:
gcc/config/rs6000/rs6000.md | 73 +--
gcc/testsuite/g++.target/powerpc/pr111367.C | 22 +
.../vect/costmodel/ppc/costmodel-vect-store-1.c | 23 +
.../vect/costmodel/ppc/costmodel-vect-store-2.c | 29 +
gcc/testsuite/gfortran.dg/vect/pr60510.f | 1 +
gcc/tree-vect-stmts.cc | 717 +++++++++++++--------
6 files changed, 542 insertions(+), 323 deletions(-)
create mode 100644 gcc/testsuite/g++.target/powerpc/pr111367.C
create mode 100644 gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-store-1.c
create mode 100644 gcc/testsuite/gcc.dg/vect/costmodel/ppc/costmodel-vect-store-2.c
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unknown user pushed a change to branch master
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from 6a3302a41a6 RISC-V: Support FP llrint auto vectorization
new e1e127de18d x86: set spincount 1 for x86 hybrid platform
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Summary of changes:
.../darwin/plugin-suffix.h => include/spincount.h | 13 +++++++--
.../config/{nvptx/task.c => linux/x86/spincount.h} | 32 +++++++++++++---------
libgomp/env.c | 6 +++-
3 files changed, 34 insertions(+), 17 deletions(-)
copy libgomp/config/darwin/plugin-suffix.h => include/spincount.h (80%)
copy libgomp/config/{nvptx/task.c => linux/x86/spincount.h} (64%)
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unknown user pushed a change to branch master
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from d6b7fe11efe RISC-V: Support FP irintf auto vectorization
new 180b08f6440 [APX] Support Intel APX PUSH2POP2
new 6a3302a41a6 RISC-V: Support FP llrint auto vectorization
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
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Summary of changes:
gcc/config/i386/i386.cc | 252 +++++++++++++++++++--
gcc/config/i386/i386.md | 26 +++
gcc/testsuite/gcc.target/i386/apx-push2pop2-1.c | 45 ++++
.../gcc.target/i386/apx-push2pop2_force_drap-1.c | 29 +++
.../gcc.target/i386/apx-push2pop2_interrupt-1.c | 28 +++
.../unop/{math-lrint-0.c => math-llrint-0.c} | 4 +-
.../riscv/rvv/autovec/unop/math-llrint-run-0.c | 63 ++++++
.../gcc.target/riscv/rvv/autovec/unop/test-math.h | 2 +
.../vls/{math-irint-0.c => math-llrint-0.c} | 20 +-
9 files changed, 442 insertions(+), 27 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/i386/apx-push2pop2-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/apx-push2pop2_force_drap-1.c
create mode 100644 gcc/testsuite/gcc.target/i386/apx-push2pop2_interrupt-1.c
copy gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/{math-lrint-0.c => math-llrin [...]
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/unop/math-llrint-run-0.c
copy gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/{math-irint-0.c => math-llrint [...]
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