Tcwg-commits July 2022

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[gcc] branch master updated (5beddee9f43 -> 8467574d8da)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 5beddee9f43 gcc.dg/analyzer/allocation-size-1..5.c: Fix for 32-bit newl [...] new 8467574d8da Daily bump. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ChangeLog | 4 + contrib/ChangeLog | 4 + gcc/ChangeLog | 171 +++++++++++++++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 248 ++++++++++++++++++++++++++++++++++++++++++++++++ gcc/c/ChangeLog | 9 ++ gcc/cp/ChangeLog | 9 ++ gcc/fortran/ChangeLog | 21 ++++ gcc/testsuite/ChangeLog | 55 +++++++++++ include/ChangeLog | 9 ++ libgomp/ChangeLog | 42 ++++++++ libiberty/ChangeLog | 10 ++ liboffloadmic/ChangeLog | 7 ++ 13 files changed, 590 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_bmk_llvm_fx/llvm-master-aarch64-cpu2017-O2 updated (e1f61d864214 -> 12d26ce9b0ec)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_fx/llvm-master-aarch64-cpu2017-O2 in repository toolchain/ci/llvm-project. from e1f61d864214 [gn build] Port 2aea8af25136 adds c1c3134ac422 [InstCombine] add tests for and-of-negated-lowbitmask; NFC adds f9f40aa10d98 [InstCombine] fold negated low-bit-mask to cmp+select adds b1f0efc06acc [clang-format] Tweak help text a bit adds 134363208b92 [clang] Fix gcc-6 compilation error. (NFC) adds a65a3bffd31f [clang-tidy] Don't treat invalid branches as identical adds f7a80c3d08d4 [clang-tidy] Properly forward clang-tidy output when runni [...] adds 2c3784cff859 [SCEV] recognize llvm.annotation intrinsic adds e98e13ac8f38 [mlir][Vector] Fold ShuffleOp(SplatOp(X), SplatOp(X)) to S [...] adds d2a35e4d39fe [AIX] Handling the label alignment of a global variable wi [...] adds 93d6fdfc232c [Driver] Ignore the clang modules validation-related flags [...] adds 8eb4dcb73747 [RISCV] Move some SHXADD matching cases into a ComplexPatt [...] adds d36e09cfe591 [RISCV] Add more SHXADD patterns. adds 1063dfc02853 [mlir][openmp] Added omp.taskloop adds 7283f48a05de [IR] Remove support for insertvalue constant expression adds b4694229aa9d [LV] Simplify setDebugLocFromInst by using early exit (NFC). adds f0089fae1d7e [AArch64] Add additional tests for D120481. adds 7fbf55c927f2 [mlir][Tensor] Move ParallelInsertSlice to the tensor dialect adds 9604601c9394 [SimplifyCFG] Remove redundant checks for hoisting (NFCI) adds 4887d047a31f [libc++][NFC] Replace enable_if with __enable_if_t in a fe [...] adds 04f6bf482b86 Revise outdated parts of the developer policy. adds 5f0a054f8954 [pseudo] Remove duplicated code in ClangPseudo.cpp adds c9fb3c6ea6cc [mlir][Tensor] Update ParallelInsertSlicOp semantics to ma [...] adds f4dd977537dc [AST] Use canonical constraint declaration for ASTContext: [...] adds 42f5b0509ded [mlir][NFC] Fix various warnings generated by GCC 9 adds cce64e7a9cba [DAG] visitTRUNCATE - move GetDemandedBits AFTER SimplifyD [...] adds f90f0e8fe7f5 [AMDGPU][GFX10][DOC][NFC] Update assembler syntax description adds bf89d24f5319 [AArch64] NFC: Move safe predicate casting to a separate f [...] adds 740633ff08ff [flang] Add TODO for derived types with final procedure adds 4905bcac00e6 [ConstantFolding] Check return value of ConstantFoldInstOp [...] adds 8e70258b18ba [AMDGPUCodeGenPrepare] Check result of ConstantFoldBinaryO [...] adds 19a1e20b8a0f [VectorCombine] Improve shuffle select shuffle-of-shuffles adds 25607d143d1d [libc++] Implement `std::ranges::merge` adds 3912928aa891 [gn build] Port 25607d143d1d adds 32a76fc292d9 [SCEVExpander] Avoid ConstantExpr::get() (NFCI) adds 93cbdaef0455 [Reassociate] Avoid ConstantExpr::get() adds 2de05afc192d [SLP] Peek into loads when hitting the RecursionMaxDepth adds 2ab260eecfab [llvm-ar][test] Add additional MRI script testing adds 4e6c30c8354f [libc] Add a separate algorithm_test. adds d7697c175db9 [flang] Avoid segfault when defining op is not a fir::Convert adds f93cd56262d1 [BPI] Avoid ConstantExpr::get() adds aa78c5298ea3 Fix MLIR Python CMake bug causing duplicate sources target. adds 644a965c1efe [LV] Vectorize cases with larger number of RT checks, exec [...] adds c06d0b4d02ea [RISCV] Add ADDI instr for computing FrameIndex address adds c146af3f469a [LoopVectorize][NFC] Reinstate TTICapture workaround for gcc-6 adds 8471c6861992 [LTO] Update remark test after 644a965c1efef6. adds 89cb8cae606b [Bitcode] Use bitcode input for test (NFC) adds abbd684c02c7 [InstCombine] Avoid ConstantExpr::get() in phi binop fold adds 10ebaf76860e [SLP] add test for load combining + shuffling; NFC adds fdf505f3f223 [mlir][OpenMP] omp.task translation to LLVM IR adds 2bfca3561466 [X86] Disable combineVectorSizedSetCCEquality for soft float. adds 5785717e18d5 [AArch64] Add support for insert/extract for nxv1i1 types. adds 2fde26dfcabe [mlir][Linalg][NFC] Make getReassociationMapForFoldingUnit [...] adds 9eb657278611 [LV] Add back CantReorderMemOps remark. adds c3839c0b46a9 CombineContractBroadcast should not create dims unused in LHS+RHS adds bc70ba814dc1 Use add_llvm_install_targets for install-llvmlibc adds b37dafd5dc83 [pseudo] Store shift and goto actions in a compact structu [...] adds 12d26ce9b0ec [flang] Make code more homogenous in CodeGen No new revisions were added by this update. Summary of changes: .../clang-tidy/bugprone/BranchCloneCheck.cpp | 11 + clang-tools-extra/docs/ReleaseNotes.rst | 4 + .../pseudo/include/clang-pseudo/grammar/LRTable.h | 120 +++- clang-tools-extra/pseudo/lib/GLR.cpp | 16 +- clang-tools-extra/pseudo/lib/grammar/LRTable.cpp | 65 +- .../pseudo/lib/grammar/LRTableBuild.cpp | 61 +- clang-tools-extra/pseudo/tool/ClangPseudo.cpp | 48 +- clang-tools-extra/pseudo/unittests/LRTableTest.cpp | 2 +- .../test/clang-tidy/check_clang_tidy.py | 10 +- .../bugprone/branch-clone-unknown-expr.cpp | 9 + clang/lib/AST/ASTContext.cpp | 3 + clang/lib/AST/Interp/ByteCodeExprGen.cpp | 2 +- clang/lib/Driver/ToolChains/Clang.cpp | 63 +- clang/lib/Format/Format.cpp | 25 +- clang/test/Driver/modules.m | 30 +- clang/test/Frontend/optimization-remark-options.c | 2 +- clang/test/Modules/concept.cppm | 50 +- clang/tools/clang-format/ClangFormat.cpp | 10 +- flang/lib/Lower/ConvertType.cpp | 4 + flang/lib/Optimizer/Builder/FIRBuilder.cpp | 5 +- flang/lib/Optimizer/CodeGen/CodeGen.cpp | 49 +- flang/test/Lower/extent_triplets.f90 | 11 + libc/lib/CMakeLists.txt | 9 +- libc/test/src/string/memory_utils/CMakeLists.txt | 17 +- libcxx/docs/Status/RangesAlgorithms.csv | 10 +- libcxx/include/CMakeLists.txt | 1 + libcxx/include/__algorithm/ranges_merge.h | 142 ++++ libcxx/include/__hash_table | 16 +- libcxx/include/__mutex_base | 12 +- libcxx/include/__split_buffer | 26 +- libcxx/include/__tree | 32 +- libcxx/include/__tuple | 6 +- libcxx/include/algorithm | 18 + libcxx/include/array | 7 +- libcxx/include/exception | 4 +- libcxx/include/forward_list | 42 +- libcxx/include/list | 16 +- libcxx/include/map | 52 +- libcxx/include/module.modulemap.in | 1 + libcxx/include/tuple | 16 +- libcxx/include/unordered_map | 12 +- ...ges_robust_against_copying_comparators.pass.cpp | 6 +- ...ges_robust_against_copying_projections.pass.cpp | 6 +- libcxx/test/libcxx/private_headers.verify.cpp | 1 + .../alg.sorting/alg.merge/ranges_merge.pass.cpp | 613 +++++++++++++++++ .../niebloid.compile.pass.cpp | 2 +- llvm/bindings/go/llvm/ir.go | 10 - llvm/bindings/ocaml/llvm/llvm.ml | 2 - llvm/bindings/ocaml/llvm/llvm.mli | 5 - llvm/bindings/ocaml/llvm/llvm_ocaml.c | 17 - llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst | 764 +++++++++++---------- llvm/docs/AMDGPU/gfx10_hwreg.rst | 42 +- .../AMDGPU/{gfx10_opt.rst => gfx10_opt_0d447d.rst} | 4 +- .../AMDGPU/{gfx10_opt.rst => gfx10_opt_847aed.rst} | 2 +- ...soffset_c40a5a.rst => gfx10_soffset_73dae7.rst} | 6 +- ...soffset_59fade.rst => gfx10_soffset_d01a5c.rst} | 6 +- ...x10_vdata_c61803.rst => gfx10_vdata_0aba12.rst} | 4 +- ...x10_vdata_b2a787.rst => gfx10_vdata_16d321.rst} | 4 +- ...x10_vdata_325b78.rst => gfx10_vdata_35851e.rst} | 6 +- ...x10_vdata_87fb90.rst => gfx10_vdata_890652.rst} | 4 +- ...x10_vdata_4d8ecf.rst => gfx10_vdata_a9ff5a.rst} | 6 +- ...gfx10_vdst_48d3a8.rst => gfx10_vdst_2ea017.rst} | 6 +- ...gfx10_vdst_5d50a1.rst => gfx10_vdst_322561.rst} | 6 +- ...gfx10_vdst_5d50a1.rst => gfx10_vdst_709347.rst} | 4 +- llvm/docs/AMDGPU/gfx10_vdst_719833.rst | 21 - ...gfx10_vdst_d7c57e.rst => gfx10_vdst_81a6ed.rst} | 4 +- ...gfx10_vdst_f47754.rst => gfx10_vdst_d71f1c.rst} | 4 +- ...gfx10_vdst_a49b76.rst => gfx10_vdst_dd8a32.rst} | 4 +- llvm/docs/DeveloperPolicy.rst | 38 +- llvm/docs/LangRef.rst | 16 +- llvm/docs/ReleaseNotes.rst | 2 + llvm/include/llvm-c/Core.h | 3 - llvm/include/llvm/CodeGen/AsmPrinter.h | 7 +- llvm/include/llvm/IR/Constants.h | 11 - .../Vectorize/LoopVectorizationLegality.h | 7 - llvm/lib/Analysis/BranchProbabilityInfo.cpp | 6 +- llvm/lib/Analysis/ConstantFolding.cpp | 8 +- llvm/lib/Analysis/ScalarEvolution.cpp | 8 +- llvm/lib/AsmParser/LLParser.cpp | 28 +- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 3 - llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 91 ++- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 24 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 9 +- .../lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h | 2 +- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 8 +- llvm/lib/IR/AsmWriter.cpp | 4 - llvm/lib/IR/Constants.cpp | 44 +- llvm/lib/IR/ConstantsContext.h | 60 +- llvm/lib/IR/Core.cpp | 12 - llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 88 ++- llvm/lib/Target/AArch64/AArch64ISelLowering.h | 5 + llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 59 +- llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 4 +- llvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp | 4 - llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 45 +- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 62 +- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 12 +- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 - llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td | 36 +- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td | 24 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 10 +- .../Transforms/InstCombine/InstCombineAndOrXor.cpp | 10 + .../InstCombine/InstructionCombining.cpp | 8 +- llvm/lib/Transforms/Scalar/Reassociate.cpp | 19 +- .../Transforms/Utils/ScalarEvolutionExpander.cpp | 3 +- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 5 +- .../Vectorize/LoopVectorizationLegality.cpp | 1 - .../Vectorize/LoopVectorizationPlanner.h | 10 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 234 +++++-- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 14 +- llvm/lib/Transforms/Vectorize/VPlan.cpp | 38 +- llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 164 ++++- .../ScalarEvolution/annotation-intrinsics.ll | 4 +- llvm/test/Assembler/insertextractvalue.ll | 28 - llvm/test/Assembler/insertvalue-invalid-type-1.ll | 7 - llvm/test/Assembler/unsupported-constexprs.ll | 17 +- .../Inputs/bitcode-parseconstant-delay-select.bc | Bin 0 -> 1420 bytes .../Bitcode/bitcode-parseconstant-delay-select.ll | 2 +- .../CodeGen/AArch64/sve-extract-scalable-vector.ll | 336 +++++++++ llvm/test/CodeGen/AArch64/sve-insert-vector.ll | 668 ++++++++++++++++++ llvm/test/CodeGen/AArch64/vselect-ext.ll | 241 ++++++- llvm/test/CodeGen/PowerPC/aix-alias-alignment-2.ll | 79 +++ llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll | 74 ++ llvm/test/CodeGen/PowerPC/aix-alias.ll | 16 +- llvm/test/CodeGen/RISCV/rv64zba.ll | 67 ++ .../RISCV/rvv/access-fixed-objects-by-rvv.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll | 98 +-- llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll | 62 +- llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll | 162 ++--- llvm/test/CodeGen/RISCV/rvv/calling-conv.ll | 18 +- llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll | 24 - llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll | 12 - llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll | 24 - .../CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll | 16 +- .../RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll | 111 ++- .../RISCV/rvv/fixed-vectors-calling-conv.ll | 301 ++++---- .../CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll | 148 ++-- .../CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll | 36 +- .../RISCV/rvv/fixed-vectors-insert-subvector.ll | 5 +- .../CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll | 10 +- .../RISCV/rvv/fixed-vectors-mask-buildvec.ll | 24 +- .../RISCV/rvv/fixed-vectors-masked-gather.ll | 112 +-- .../RISCV/rvv/fixed-vectors-masked-scatter.ll | 122 ++-- .../RISCV/rvv/fixed-vectors-reduction-int-vp.ll | 32 +- .../RISCV/rvv/fixed-vectors-reduction-int.ll | 24 +- .../RISCV/rvv/fixed-vectors-setcc-int-vp.ll | 36 +- .../CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll | 16 +- .../test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll | 8 +- .../CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll | 8 +- .../test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll | 8 +- .../test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll | 8 +- .../CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll | 3 +- llvm/test/CodeGen/RISCV/rvv/localvar.ll | 68 +- llvm/test/CodeGen/RISCV/rvv/masked-tama.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/memory-args.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll | 19 +- llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll | 72 +- llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll | 40 +- llvm/test/CodeGen/RISCV/rvv/stepvector.ll | 7 +- llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll | 10 +- llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll | 18 +- llvm/test/CodeGen/RISCV/rvv/vaadd.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vaaddu.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vadd.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vand-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vasub.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vasubu.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll | 8 +- .../test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll | 18 +- llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll | 18 +- llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll | 12 +- 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llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll | 16 +- .../test/CodeGen/RISCV/srem-seteq-illegal-types.ll | 74 +- .../test/CodeGen/RISCV/urem-seteq-illegal-types.ll | 4 +- llvm/test/CodeGen/X86/nonconst-static-iv.ll | 8 - llvm/test/CodeGen/X86/pr56351.ll | 18 + llvm/test/LTO/X86/diagnostic-handler-remarks.ll | 4 +- llvm/test/Transforms/InstCombine/and.ll | 60 ++ .../AArch64/runtime-check-size-based-threshold.ll | 18 +- .../AArch64/sve-tail-folding-forced.ll | 2 +- .../AArch64/sve-tail-folding-unroll.ll | 4 +- .../LoopVectorize/AArch64/sve-tail-folding.ll | 22 +- .../Transforms/LoopVectorize/X86/gather_scatter.ll | 2 +- .../X86/pointer-runtime-checks-unprofitable.ll | 60 +- llvm/test/Transforms/LoopVectorize/X86/pr23997.ll | 2 +- llvm/test/Transforms/LoopVectorize/X86/pr35432.ll | 2 +- llvm/test/Transforms/LoopVectorize/X86/pr54634.ll | 2 +- .../Transforms/LoopVectorize/X86/runtime-limit.ll | 22 +- .../Transforms/SLPVectorizer/AArch64/loadorder.ll | 151 ++-- .../X86/load-partial-vector-shuffle.ll | 73 ++ .../VectorCombine/AArch64/select-shuffle.ll | 260 ++++--- llvm/test/tools/llvm-ar/Inputs/mri-crlf.mri | 2 + llvm/test/tools/llvm-ar/mri-crlf.test | 9 +- llvm/test/tools/llvm-ar/mri-delete.test | 188 ++++- llvm/test/tools/llvm-ar/mri-end.test | 140 ++-- llvm/test/tools/llvm-ar/mri-nonascii.test | 37 +- llvm/utils/gn/secondary/libcxx/include/BUILD.gn | 1 + mlir/cmake/modules/AddMLIRPython.cmake | 2 +- mlir/include/mlir/Dialect/Linalg/Utils/Utils.h | 9 + mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td | 180 ++++- .../mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td | 2 +- mlir/include/mlir/Dialect/SCF/IR/SCFOps.td | 109 --- mlir/include/mlir/Dialect/Tensor/IR/Tensor.h | 1 + mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td | 149 ++++ mlir/include/mlir/Dialect/Vector/IR/VectorOps.td | 1 + mlir/include/mlir/IR/AffineMap.h | 6 + mlir/lib/Dialect/Affine/IR/AffineOps.cpp | 2 +- .../lib/Dialect/Linalg/Transforms/DropUnitDims.cpp | 28 - mlir/lib/Dialect/Linalg/Utils/Utils.cpp | 28 + mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp | 55 +- mlir/lib/Dialect/SCF/IR/CMakeLists.txt | 1 - mlir/lib/Dialect/SCF/IR/SCF.cpp | 143 +--- .../SCF/Transforms/BufferizableOpInterfaceImpl.cpp | 246 +------ mlir/lib/Dialect/Tensor/IR/CMakeLists.txt | 1 + mlir/lib/Dialect/Tensor/IR/TensorOps.cpp | 256 +++++-- .../Transforms/BufferizableOpInterfaceImpl.cpp | 244 +++++++ mlir/lib/Dialect/Vector/IR/VectorOps.cpp | 37 +- .../Dialect/Vector/Transforms/VectorTransforms.cpp | 21 +- mlir/lib/ExecutionEngine/OptUtils.cpp | 2 +- mlir/lib/ExecutionEngine/SparseTensorUtils.cpp | 2 +- mlir/lib/IR/AffineMap.cpp | 19 +- .../Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp | 27 + mlir/test/Dialect/OpenMP/invalid.mlir | 125 ++++ mlir/test/Dialect/OpenMP/ops.mlir | 142 +++- mlir/test/Dialect/SCF/canonicalize.mlir | 25 - .../SCF/foreach-thread-canonicalization.mlir | 50 +- mlir/test/Dialect/SCF/invalid.mlir | 8 +- .../one-shot-bufferize-tensor-copy-insertion.mlir | 4 +- mlir/test/Dialect/SCF/one-shot-bufferize.mlir | 6 +- mlir/test/Dialect/SCF/ops.mlir | 4 +- mlir/test/Dialect/Tensor/canonicalize.mlir | 27 + mlir/test/Dialect/Vector/canonicalize.mlir | 14 + mlir/test/Dialect/Vector/invalid.mlir | 2 +- .../Dialect/Vector/vector-reduce-to-contract.mlir | 35 + mlir/test/Target/LLVMIR/openmp-llvm.mlir | 88 +++ utils/bazel/llvm-project-overlay/mlir/BUILD.bazel | 2 + 322 files changed, 7612 insertions(+), 4096 deletions(-) create mode 100644 clang-tools-extra/test/clang-tidy/checkers/bugprone/branch-clon [...] create mode 100644 flang/test/Lower/extent_triplets.f90 create mode 100644 libcxx/include/__algorithm/ranges_merge.h create mode 100644 libcxx/test/std/algorithms/alg.sorting/alg.merge/ranges_merge.pass.cpp copy llvm/docs/AMDGPU/{gfx10_opt.rst => gfx10_opt_0d447d.rst} (83%) rename llvm/docs/AMDGPU/{gfx10_opt.rst => gfx10_opt_847aed.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_soffset_c40a5a.rst => gfx10_soffset_73dae7.rst} (72%) rename llvm/docs/AMDGPU/{gfx10_soffset_59fade.rst => gfx10_soffset_d01a5c.rst} (61%) rename llvm/docs/AMDGPU/{gfx10_vdata_c61803.rst => gfx10_vdata_0aba12.rst} (80%) rename llvm/docs/AMDGPU/{gfx10_vdata_b2a787.rst => gfx10_vdata_16d321.rst} (80%) rename llvm/docs/AMDGPU/{gfx10_vdata_325b78.rst => gfx10_vdata_35851e.rst} (81%) rename llvm/docs/AMDGPU/{gfx10_vdata_87fb90.rst => gfx10_vdata_890652.rst} (80%) rename llvm/docs/AMDGPU/{gfx10_vdata_4d8ecf.rst => gfx10_vdata_a9ff5a.rst} (81%) rename llvm/docs/AMDGPU/{gfx10_vdst_48d3a8.rst => gfx10_vdst_2ea017.rst} (76%) copy llvm/docs/AMDGPU/{gfx10_vdst_5d50a1.rst => gfx10_vdst_322561.rst} (71%) rename llvm/docs/AMDGPU/{gfx10_vdst_5d50a1.rst => gfx10_vdst_709347.rst} (76%) delete mode 100644 llvm/docs/AMDGPU/gfx10_vdst_719833.rst rename llvm/docs/AMDGPU/{gfx10_vdst_d7c57e.rst => gfx10_vdst_81a6ed.rst} (75%) rename llvm/docs/AMDGPU/{gfx10_vdst_f47754.rst => gfx10_vdst_d71f1c.rst} (75%) rename llvm/docs/AMDGPU/{gfx10_vdst_a49b76.rst => gfx10_vdst_dd8a32.rst} (75%) delete mode 100644 llvm/test/Assembler/insertvalue-invalid-type-1.ll create mode 100644 llvm/test/Bitcode/Inputs/bitcode-parseconstant-delay-select.bc create mode 100644 llvm/test/CodeGen/PowerPC/aix-alias-alignment-2.ll create mode 100644 llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll delete mode 100644 llvm/test/CodeGen/X86/nonconst-static-iv.ll create mode 100644 llvm/test/CodeGen/X86/pr56351.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/load-partial-vector-shuffle.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_llvm_fx/llvm-master-aarch64-cpu2017-O2 updated (a1bdd81664 -> 8ee2c043cf)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_fx/llvm-master-aarch64-cpu2017-O2 in repository toolchain/ci/glibc. from a1bdd81664 Refactor internal-signals.h adds c33ada0602 Use GCC 12 branch in build-many-glibcs.py adds bb1bd9ec0e argp: Remove old includes in !_LIBC case adds 8ee2c043cf Fix hurd namespace issues for internal signal functions No new revisions were added by this update. Summary of changes: argp/argp-namefrob.h | 5 ----- scripts/build-many-glibcs.py | 2 +- sysdeps/generic/internal-signals.h | 6 +++--- 3 files changed, 4 insertions(+), 9 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_llvm_fx/llvm-master-aarch64-cpu2017-O2 updated (3ae9def0856 -> ce8dbe7d834)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_fx/llvm-master-aarch64-cpu2017-O2 in repository toolchain/ci/gcc. from 3ae9def0856 Move range allocator code to value-range-storage.* adds f3a5e75cb66 x86: Support 2/4/8 byte constant vector stores adds 3731dd0bea8 Daily bump. adds bbe836bc7c5 Remove some deprecated irange methods. adds 73f942c08de i386: Extend cvtps2pd to memory adds d74d98784a9 tree-optimization/106055 - issue with autopar adds ad7ed87a436 [Ada] Adjust description of Pure_Function pragma adds 089a4a48ac3 [Ada] Create new unbounded functional sequence adds df69e326b39 [Ada] Fix for resolution of overloaded subprogram for Itera [...] adds bdd5056736b [Ada] Plug loophole for built-in-place return with limited_ [...] adds ddd88925273 [Ada] Incorrect accessibility check on return of discrimina [...] adds 82b63eb0f30 [Ada] Add GNAT specific pragmas to the equivalent Assertion [...] adds 2e9b2ab3b5b [Ada] Update the documentation of functional containers adds a8a1da109ef [Ada] Add Ada 2022 features to sets containers adds 4030e83c276 [Ada] Give missing error on ambiguous operand of equality operator adds e7428fff12c [Ada] Add a RM entry for the functional infinite sequences adds f7c05e82037 [Ada] Avoid unwanted warnings for statically-known-successf [...] adds 063c8f4c01b [Ada] Compiler rejects legal allocator in record component [...] adds cac397f3f6f [Ada] Fix length of title underlines. adds eb6e8a7acd1 [Ada] Add Ada 2022 Key function to sets containers adds c901877facf [Ada] Call-initialize all controlled objects in place adds 02e41e69d47 [Ada] Do not use front-end build-in-place mechanism for non [...] adds 3319015b0a4 [Ada] Fix missing error on 'Access of constrained array adds 1fde86bba55 [Ada] Single character argument in call to Quote_Argument r [...] adds 78f13b008ab [Ada] Tech debt: Remove code duplication adds 4b766285b08 [Ada] Assertions in Einfo.Utils adds f3451ba8aa3 [Ada] Enforce deferred constant completion rules adds 2cad8a59a80 [Ada] Use static stack allocation for small dynamic string [...] adds 0896e2b79a3 [Ada] Adjust previous change to Rewrite_As_Renaming adds a521dc37999 [Ada] Use static stack allocation for small string if-expressions adds e0cd23986ed [Ada] Refactor duplicated resolution of Count and Index attributes adds 2f94aea27c0 [Ada] Makefile.rtl: remove references t oVxworks RTP Cert . [...] adds aa683f5c036 [Ada] Small housekeeping work in Expand_N_Object_Declaration adds 4dab9bed7bd [Ada] vx7r2: do not include s-qnx.ads in the kernel and rtp [...] adds 1f03b43fc75 [Ada] Fix dispatching call to primitive function with contr [...] adds 8c6bef0a33e [Ada] Do not make procedure call with only tag-indeternmina [...] adds d2a89866660 Put virtual operands into loop-closed SSA adds 4e82205b680 Integrate nonzero bits with irange. adds 1a770b01ef4 Prevent another potential stack overflow issue when demangl [...] adds a7ccdfa17e5 MAINTAINERS: fix alphabetic sorting adds 483bd9a0283 Use default lower bound for vector types in debug info adds 104b9875c78 Fix crash on circular array types with -fdump switches adds 88b9d090aa1 gcc-descr: by default show revision for HEAD adds 10b502fb783 Keep virtual SSA up-to-date in vectorizer adds 683f1184397 OpenMP: Move omp requires checks to libgomp adds 3769ad4ccea Revert update-ssa assert in vectorizer adds b110e5283e3 tree-sra: Fix union handling in build_reconstructed_reference adds fc968115a74 Fix typo in recent code to add stack recursion limit to the [...] adds ac4c8f53b0f middle-end: Support ABIs that pass FP values as wider integers. adds ce8dbe7d834 Misc conversions to vrange. No new revisions were added by this update. Summary of changes: ChangeLog | 8 + MAINTAINERS | 2 +- contrib/git-descr.sh | 2 +- gcc/ChangeLog | 64 +++ gcc/DATESTAMP | 2 +- gcc/ada/Makefile.rtl | 9 +- gcc/ada/checks.adb | 99 +++- gcc/ada/debug.adb | 5 +- .../doc/gnat_rm/implementation_defined_pragmas.rst | 6 +- gcc/ada/doc/gnat_rm/the_gnat_library.rst | 68 ++- .../building_executable_programs_with_gnat.rst | 34 +- gcc/ada/einfo-utils.adb | 61 ++- gcc/ada/einfo-utils.ads | 57 ++- gcc/ada/exp_ch3.adb | 235 ++++----- gcc/ada/exp_ch4.adb | 550 +++++++++++++++++---- gcc/ada/exp_ch6.adb | 133 ++--- gcc/ada/exp_ch7.adb | 9 +- gcc/ada/exp_disp.adb | 10 +- gcc/ada/exp_tss.adb | 2 +- gcc/ada/exp_util.adb | 49 +- gcc/ada/gnat_rm.texi | 476 +++++++++--------- gcc/ada/gnat_ugn.texi | 38 +- gcc/ada/impunit.adb | 1 + gcc/ada/libgnat/a-cbhase.adb | 58 +++ gcc/ada/libgnat/a-cbhase.ads | 22 + gcc/ada/libgnat/a-cborse.adb | 56 +++ gcc/ada/libgnat/a-cborse.ads | 22 + gcc/ada/libgnat/a-cfinse.adb | 304 ++++++++++++ gcc/ada/libgnat/a-cfinse.ads | 377 ++++++++++++++ gcc/ada/libgnat/a-cihase.adb | 58 +++ gcc/ada/libgnat/a-cihase.ads | 22 + gcc/ada/libgnat/a-ciorse.adb | 55 +++ gcc/ada/libgnat/a-ciorse.ads | 22 + gcc/ada/libgnat/a-cohase.adb | 58 +++ gcc/ada/libgnat/a-cohase.ads | 22 + gcc/ada/libgnat/a-conhel.adb | 8 +- gcc/ada/libgnat/a-conhel.ads | 28 +- gcc/ada/libgnat/a-coorse.adb | 55 +++ gcc/ada/libgnat/a-coorse.ads | 22 + gcc/ada/libgnat/s-os_lib.adb | 2 +- gcc/ada/sem_attr.adb | 41 +- gcc/ada/sem_aux.adb | 6 +- gcc/ada/sem_ch13.adb | 1 + gcc/ada/sem_ch3.adb | 58 ++- gcc/ada/sem_ch4.adb | 17 +- gcc/ada/sem_disp.adb | 86 ++-- gcc/ada/sem_prag.adb | 37 +- gcc/ada/sem_prag.ads | 1 + gcc/ada/sem_res.adb | 41 +- gcc/ada/sem_util.adb | 66 +-- gcc/ada/sem_warn.adb | 9 +- gcc/ada/sinfo.ads | 4 +- gcc/ada/sprint.adb | 10 +- gcc/ada/types.ads | 5 + gcc/ada/uintp.ads | 2 + gcc/c/c-parser.cc | 19 +- gcc/calls.cc | 38 +- gcc/cfgexpand.cc | 13 +- gcc/config/gcn/mkoffload.cc | 27 +- gcc/config/i386/i386-protos.h | 2 + gcc/config/i386/i386.cc | 47 ++ gcc/config/i386/mmx.md | 37 ++ gcc/config/i386/predicates.md | 11 + gcc/config/i386/sse.md | 26 +- gcc/config/nvptx/mkoffload.cc | 29 +- gcc/cp/parser.cc | 19 +- gcc/dwarf2out.cc | 9 +- gcc/expr.cc | 35 ++ gcc/expr.h | 11 +- gcc/fortran/openmp.cc | 4 - gcc/fortran/parse.cc | 22 +- gcc/function.cc | 11 + gcc/gimple-loop-jam.cc | 2 +- gcc/gimple-range-fold.cc | 32 +- gcc/gimple-range.cc | 11 +- gcc/graphite.cc | 5 +- gcc/ipa-cp.cc | 2 +- gcc/ipa-prop.cc | 2 +- gcc/lto-cgraph.cc | 117 ++++- gcc/omp-low.cc | 5 + gcc/testsuite/ChangeLog | 26 + gcc/testsuite/c-c++-common/gomp/requires-4.c | 2 - .../c-c++-common/gomp/reverse-offload-1.c | 2 +- .../c-c++-common/gomp/target-device-ancestor-2.c | 10 +- .../c-c++-common/gomp/target-device-ancestor-3.c | 2 +- .../c-c++-common/gomp/target-device-ancestor-4.c | 4 +- .../c-c++-common/gomp/target-device-ancestor-5.c | 2 +- gcc/testsuite/gcc.dg/graphite/pr106055.c | 41 ++ .../gcc.dg/tree-ssa/alias-access-path-13.c | 31 ++ gcc/testsuite/gcc.dg/tree-ssa/pr105860.c | 63 +++ gcc/testsuite/gcc.target/i386/pr106022-1.c | 13 + gcc/testsuite/gcc.target/i386/pr106022-2.c | 14 + gcc/testsuite/gcc.target/i386/pr106022-3.c | 14 + gcc/testsuite/gcc.target/i386/pr106022-4.c | 14 + gcc/testsuite/gcc.target/i386/pr43618-1.c | 12 + gcc/testsuite/gfortran.dg/gomp/requires-8.f90 | 14 +- .../gfortran.dg/gomp/target-device-ancestor-2.f90 | 70 +-- .../gfortran.dg/gomp/target-device-ancestor-2a.f90 | 80 +++ .../gfortran.dg/gomp/target-device-ancestor-3.f90 | 6 +- .../gfortran.dg/gomp/target-device-ancestor-4.f90 | 6 +- .../gfortran.dg/gomp/target-device-ancestor-5.f90 | 8 +- gcc/tree-if-conv.cc | 2 +- gcc/tree-loop-distribution.cc | 2 +- gcc/tree-parloops.cc | 10 +- gcc/tree-pretty-print.cc | 6 +- gcc/tree-sra.cc | 13 +- gcc/tree-ssa-dce.cc | 3 +- gcc/tree-ssa-dom.cc | 2 +- gcc/tree-ssa-loop-manip.cc | 23 +- gcc/tree-ssa-loop-manip.h | 3 - gcc/tree-ssa-loop-unswitch.cc | 8 +- gcc/tree-vect-loop-manip.cc | 14 +- gcc/tree-vect-stmts.cc | 18 +- gcc/tree-vectorizer.h | 4 + gcc/tree-vrp.cc | 3 +- gcc/value-range-equiv.cc | 2 +- gcc/value-range-storage.cc | 9 +- gcc/value-range.cc | 179 ++++++- gcc/value-range.h | 36 +- gcc/vr-values.cc | 20 +- include/gomp-constants.h | 9 +- libgomp/libgomp-plugin.h | 2 +- libgomp/libgomp.texi | 8 +- libgomp/oacc-host.c | 4 +- libgomp/oacc-init.c | 16 +- libgomp/plugin/plugin-gcn.c | 6 +- libgomp/plugin/plugin-nvptx.c | 9 +- libgomp/target.c | 76 ++- .../libgomp.c-c++-common/requires-1-aux.c | 11 + .../testsuite/libgomp.c-c++-common/requires-1.c | 24 + .../libgomp.c-c++-common/requires-2-aux.c | 9 + .../testsuite/libgomp.c-c++-common/requires-2.c | 25 + .../libgomp.c-c++-common/requires-3-aux.c | 11 + .../testsuite/libgomp.c-c++-common/requires-3.c | 24 + .../libgomp.c-c++-common/requires-4-aux.c | 13 + .../testsuite/libgomp.c-c++-common/requires-4.c | 23 + .../libgomp.c-c++-common/requires-5-aux.c | 11 + .../testsuite/libgomp.c-c++-common/requires-5.c | 21 + .../testsuite/libgomp.c-c++-common/requires-6.c | 17 + .../libgomp.c-c++-common/requires-7-aux.c | 11 + .../testsuite/libgomp.c-c++-common/requires-7.c | 24 + .../testsuite/libgomp.fortran/requires-1-aux.f90 | 14 + libgomp/testsuite/libgomp.fortran/requires-1.f90 | 26 + libiberty/rust-demangle.c | 18 + liboffloadmic/plugin/libgomp-plugin-intelmic.cpp | 6 +- 145 files changed, 4062 insertions(+), 1178 deletions(-) create mode 100644 gcc/ada/libgnat/a-cfinse.adb create mode 100644 gcc/ada/libgnat/a-cfinse.ads create mode 100644 gcc/testsuite/gcc.dg/graphite/pr106055.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/alias-access-path-13.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr105860.c create mode 100644 gcc/testsuite/gcc.target/i386/pr106022-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr106022-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr106022-3.c create mode 100644 gcc/testsuite/gcc.target/i386/pr106022-4.c create mode 100644 gcc/testsuite/gcc.target/i386/pr43618-1.c create mode 100644 gcc/testsuite/gfortran.dg/gomp/target-device-ancestor-2a.f90 create mode 100644 libgomp/testsuite/libgomp.c-c++-common/requires-1-aux.c create mode 100644 libgomp/testsuite/libgomp.c-c++-common/requires-1.c create mode 100644 libgomp/testsuite/libgomp.c-c++-common/requires-2-aux.c create mode 100644 libgomp/testsuite/libgomp.c-c++-common/requires-2.c create mode 100644 libgomp/testsuite/libgomp.c-c++-common/requires-3-aux.c create mode 100644 libgomp/testsuite/libgomp.c-c++-common/requires-3.c create mode 100644 libgomp/testsuite/libgomp.c-c++-common/requires-4-aux.c create mode 100644 libgomp/testsuite/libgomp.c-c++-common/requires-4.c create mode 100644 libgomp/testsuite/libgomp.c-c++-common/requires-5-aux.c create mode 100644 libgomp/testsuite/libgomp.c-c++-common/requires-5.c create mode 100644 libgomp/testsuite/libgomp.c-c++-common/requires-6.c create mode 100644 libgomp/testsuite/libgomp.c-c++-common/requires-7-aux.c create mode 100644 libgomp/testsuite/libgomp.c-c++-common/requires-7.c create mode 100644 libgomp/testsuite/libgomp.fortran/requires-1-aux.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/requires-1.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk_llvm_fx/llvm-master-aarch64-cpu2017-O2 updated (dcc9b683dc -> 96c33f79de)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_fx/llvm-master-aarch64-cpu2017-O2 in repository toolchain/ci/binutils-gdb. from dcc9b683dc Automatic date update in version.in adds 1e3a4f12e7 Automatic date update in version.in adds 0f2f2e7019 RISC-V: Update Zihintpause extension version adds 9386188e95 x86-64: improve handling of branches to absolute addresses adds 02b83698ef x86: restore masking of displacement kinds adds a775efc84d x86: fold Disp32S and Disp32 adds 58098fd779 gas/testsuite: properly exclude aout in all/weakref1u adds 2c474c4694 [gdb/symtab] Add get/set functions for per_cu->lang/unit_type adds a0f3a4c646 opcodes/avr: Implement style support in the disassembler adds 407115429b Modified changes for split-dwarf and dwarf-5. adds d8efadbdd9 Synchronize libbierty sources with gcc. adds 0772daccb3 objcopy: bfd_alloc orelocation adds eeeaf705fe alloc gas seginfo on notes obstack adds 96c33f79de Fix snafu in rust demangler recursion limit code No new revisions were added by this update. Summary of changes: ChangeLog | 13 + bfd/elfxx-riscv.c | 2 +- bfd/version.h | 2 +- binutils/bucomm.c | 13 + binutils/bucomm.h | 2 + binutils/dwarf.c | 12 +- binutils/objcopy.c | 37 +- gas/as.h | 1 + gas/config/tc-i386-intel.c | 9 +- gas/config/tc-i386.c | 97 +- gas/output-file.c | 42 +- gas/subsegs.c | 37 +- gas/testsuite/gas/all/weakref1u.d | 2 +- gas/testsuite/gas/i386/i386.exp | 1 + gas/testsuite/gas/i386/x86-64-branch-6.d | 21 + gas/testsuite/gas/i386/x86-64-branch-6.e | 7 + gas/testsuite/gas/i386/x86-64-branch-6.s | 18 + gdb/dwarf2/cooked-index.c | 10 +- gdb/dwarf2/cu.c | 2 +- gdb/dwarf2/index-write.c | 2 +- gdb/dwarf2/read.c | 223 +- gdb/dwarf2/read.h | 41 +- libiberty/ChangeLog | 146 +- libiberty/configure | 1 + libiberty/configure.ac | 1 + libiberty/rust-demangle.c | 47 +- opcodes/ChangeLog | 9 + opcodes/avr-dis.c | 51 +- opcodes/disassemble.c | 5 + opcodes/i386-gen.c | 10 +- opcodes/i386-init.h | 132 +- opcodes/i386-opc.h | 5 +- opcodes/i386-opc.tbl | 15 +- opcodes/i386-tbl.h | 25585 +++++++++++++++-------------- 34 files changed, 13467 insertions(+), 13134 deletions(-) create mode 100644 gas/testsuite/gas/i386/x86-64-branch-6.d create mode 100644 gas/testsuite/gas/i386/x86-64-branch-6.e create mode 100644 gas/testsuite/gas/i386/x86-64-branch-6.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_llvm_fx/llvm-master-aarch64-cpu2017-O2 updated (2f673368 -> f297fd57)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_fx/llvm-master-aarch64-cpu2017-O2 in repository toolchain/ci/base-artifacts. discards 2f673368 0: init: binutils-gcc-linux-glibc-llvm: 1 new f297fd57 0: update: binutils-gcc-linux-glibc-llvm: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (2f673368) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk_llvm_fx/llvm-master- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1508 -> 1700 bytes 02-prepare_abe/console.log.xz | Bin 2732 -> 2732 bytes 03-build_abe-binutils/console.log.xz | Bin 30420 -> 31052 bytes 04-build_abe-stage1/console.log.xz | Bin 73080 -> 73624 bytes 05-clean_sysroot/console.log.xz | Bin 332 -> 332 bytes 06-build_abe-linux/console.log.xz | Bin 9132 -> 9148 bytes 07-build_abe-glibc/console.log.xz | Bin 238792 -> 240708 bytes 08-build_abe-stage2/console.log.xz | Bin 176568 -> 182040 bytes 09-build_llvm-true/console.log.xz | Bin 62500 -> 61972 bytes 10-benchmark/benchmark-build.log | 80 +- 10-benchmark/benchmark.log | 78 +- 10-benchmark/console.log.xz | Bin 3780 -> 3748 bytes 11-check_regression/console.log.xz | Bin 360 -> 3056 bytes 11-check_regression/csv-results-0/md5sum.csv | 31302 +++++++++ 11-check_regression/csv-results-0/perf.csv | 495 + 11-check_regression/csv-results-0/results.csv | 84845 ++++++++++++++++++++++++ 11-check_regression/csv-results-0/size.csv | 84752 +++++++++++++++++++++++ 11-check_regression/csv-results-0/vect.csv | 8 + 11-check_regression/csv-results-1/md5sum.csv | 31302 +++++++++ 11-check_regression/csv-results-1/perf.csv | 491 + 11-check_regression/csv-results-1/results.csv | 84844 +++++++++++++++++++++++ 11-check_regression/csv-results-1/size.csv | 84752 +++++++++++++++++++++++ 11-check_regression/csv-results-1/vect.csv | 8 + 11-check_regression/extra-bisect-params | 1 + 11-check_regression/jira-body.txt | 1 + 11-check_regression/mail-body.txt | 13 + 11-check_regression/results-brief.csv | 13 + 11-check_regression/results-compare.csv | 1 + 11-check_regression/results-full.csv | 490 + 11-check_regression/results-internal.csv | 31 + 11-check_regression/results.log | 1749 + 12-update_baseline/console.log | 878 +- 12-update_baseline/csv-results-0/md5sum.csv | 31302 +++++++++ 12-update_baseline/csv-results-0/perf.csv | 495 + 12-update_baseline/csv-results-0/results.csv | 84845 ++++++++++++++++++++++++ 12-update_baseline/csv-results-0/size.csv | 84752 +++++++++++++++++++++++ 12-update_baseline/csv-results-0/vect.csv | 8 + 12-update_baseline/csv-results-1/md5sum.csv | 31302 +++++++++ 12-update_baseline/csv-results-1/perf.csv | 491 + 12-update_baseline/csv-results-1/results.csv | 84844 +++++++++++++++++++++++ 12-update_baseline/csv-results-1/size.csv | 84752 +++++++++++++++++++++++ 12-update_baseline/csv-results-1/vect.csv | 8 + 12-update_baseline/extra-bisect-params | 1 + 12-update_baseline/jira-body.txt | 1 + 12-update_baseline/mail-body.txt | 13 + 12-update_baseline/results-brief.csv | 13 + 12-update_baseline/results-compare.csv | 1 + 12-update_baseline/results-full.csv | 490 + 12-update_baseline/results-internal.csv | 31 + 12-update_baseline/results.log | 1749 + jenkins/manifest.sh | 24 +- results | 2 +- results_id | 2 +- 53 files changed, 811163 insertions(+), 97 deletions(-) create mode 100644 11-check_regression/csv-results-0/md5sum.csv create mode 100644 11-check_regression/csv-results-0/perf.csv create mode 100644 11-check_regression/csv-results-0/results.csv create mode 100644 11-check_regression/csv-results-0/size.csv create mode 100644 11-check_regression/csv-results-0/vect.csv create mode 100644 11-check_regression/csv-results-1/md5sum.csv create mode 100644 11-check_regression/csv-results-1/perf.csv create mode 100644 11-check_regression/csv-results-1/results.csv create mode 100644 11-check_regression/csv-results-1/size.csv create mode 100644 11-check_regression/csv-results-1/vect.csv create mode 100644 11-check_regression/extra-bisect-params create mode 100644 11-check_regression/jira-body.txt create mode 100644 11-check_regression/mail-body.txt create mode 100644 11-check_regression/results-brief.csv create mode 100644 11-check_regression/results-compare.csv create mode 100644 11-check_regression/results-full.csv create mode 100644 11-check_regression/results-internal.csv create mode 100644 11-check_regression/results.log create mode 100644 12-update_baseline/csv-results-0/md5sum.csv create mode 100644 12-update_baseline/csv-results-0/perf.csv create mode 100644 12-update_baseline/csv-results-0/results.csv create mode 100644 12-update_baseline/csv-results-0/size.csv create mode 100644 12-update_baseline/csv-results-0/vect.csv create mode 100644 12-update_baseline/csv-results-1/md5sum.csv create mode 100644 12-update_baseline/csv-results-1/perf.csv create mode 100644 12-update_baseline/csv-results-1/results.csv create mode 100644 12-update_baseline/csv-results-1/size.csv create mode 100644 12-update_baseline/csv-results-1/vect.csv create mode 100644 12-update_baseline/extra-bisect-params create mode 100644 12-update_baseline/jira-body.txt create mode 100644 12-update_baseline/mail-body.txt create mode 100644 12-update_baseline/results-brief.csv create mode 100644 12-update_baseline/results-compare.csv create mode 100644 12-update_baseline/results-full.csv create mode 100644 12-update_baseline/results-internal.csv create mode 100644 12-update_baseline/results.log -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[binutils-gdb] branch master updated (96c33f79ded -> 10e52570b8c)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 96c33f79ded Fix snafu in rust demangler recursion limit code new 10e52570b8c Automatic date update in version.in The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: bfd/version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[binutils-gdb] branch gdb-12-branch updated (9c9114ea346 -> 176b5961ce2)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch gdb-12-branch in repository binutils-gdb. from 9c9114ea346 Automatic date update in version.in new 176b5961ce2 Automatic date update in version.in The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: bfd/version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[binutils-gdb] branch binutils-2_38-branch updated (37eaf1f0991 -> 178b942b8e9)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch binutils-2_38-branch in repository binutils-gdb. from 37eaf1f0991 Automatic date update in version.in new 178b942b8e9 Automatic date update in version.in The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: bfd/version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[gcc] branch master updated (c3297044f00 -> 5beddee9f43)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from c3297044f00 OpenMP/Fortran: Add support for OpenMP 5.2 linear clause syntax new 5beddee9f43 gcc.dg/analyzer/allocation-size-1..5.c: Fix for 32-bit newl [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/testsuite/gcc.dg/analyzer/allocation-size-1.c | 8 ++++---- gcc/testsuite/gcc.dg/analyzer/allocation-size-2.c | 8 ++++---- gcc/testsuite/gcc.dg/analyzer/allocation-size-3.c | 6 +++--- gcc/testsuite/gcc.dg/analyzer/allocation-size-4.c | 2 +- gcc/testsuite/gcc.dg/analyzer/allocation-size-5.c | 4 ++-- 5 files changed, 14 insertions(+), 14 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

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