Tcwg-commits July 2022

tcwg-commits@lists.linaro.org

6 participants
15101 discussions

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allmodconfig updated (72d93505 -> e13f2301)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allmodconfig in repository toolchain/ci/base-artifacts. discards 72d93505 0: update: linux-41fd7a957782eda138d581466cf80841a4dedf01: boot new e13f2301 0: update: binutils-4694a0e5fe233c5a33f0e4e4b99c9c92021b8c88: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (72d93505) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1632 -> 1856 bytes 02-prepare_abe/console.log.xz | Bin 2732 -> 2740 bytes 03-build_abe-binutils/console.log.xz | Bin 29880 -> 30820 bytes 04-build_kernel_llvm/console.log.xz | Bin 65724 -> 64440 bytes 05-build_abe-qemu/console.log.xz | Bin 34592 -> 35008 bytes 06-build_linux/console.log.xz | Bin 3720 -> 5928 bytes 07-boot_linux/console.log.xz | Bin 508 -> 508 bytes 08-check_regression/console.log.xz | Bin 416 -> 412 bytes 09-update_baseline/console.log | 71 +++++------------------------------ jenkins/manifest.sh | 8 ++-- 10 files changed, 13 insertions(+), 66 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap updated (c3d2600cfb4 -> 1d2aa262482)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap in repository toolchain/ci/gcc. from c3d2600cfb4 tree-optimization/106186 - propagate out virtual LC PHI nod [...] adds 1cc08ceb5ba Remove dead loop-based LC SSA rewrite adds 07dd0f7ba27 tree-optimization/106198 - CFG cleanup vs LC SSA adds 069f46c71e9 c++: Prune ordinary locations adds d458c53a6f3 PR rtl-optimization/96692: ((A|B)^C)^A using andn with -mbm [...] adds 02e2e15ec4b UNSPEC_PALIGNR optimizations and clean-ups on x86. adds c73e8d45ca0 Doubleword version of and;cmp to not;test optimization on x86. adds 1d2aa262482 Provide a relation verification mechanism. No new revisions were added by this update. Summary of changes: gcc/config/i386/i386-builtin.def | 2 +- gcc/config/i386/i386-expand.cc | 8 +- gcc/config/i386/i386.cc | 13 + gcc/config/i386/i386.md | 98 +++- gcc/config/i386/sse.md | 37 +- gcc/cp/module.cc | 629 +++++++++++++----------- gcc/testsuite/g++.dg/modules/loc-prune-1.C | 2 +- gcc/testsuite/g++.dg/modules/loc-prune-4.C | 22 + gcc/testsuite/g++.dg/modules/pr98718_a.C | 2 +- gcc/testsuite/g++.dg/modules/pr98718_b.C | 2 +- gcc/testsuite/g++.dg/modules/pr99072.H | 4 +- gcc/testsuite/gcc.dg/pr106198.c | 22 + gcc/testsuite/gcc.target/i386/bmi-andn-4.c | 9 + gcc/testsuite/gcc.target/i386/ssse3-palignr-2.c | 21 + gcc/testsuite/gcc.target/i386/testnot-3.c | 9 + gcc/tree-cfgcleanup.cc | 6 +- gcc/tree-ssa-loop-manip.cc | 109 +--- gcc/value-relation.cc | 70 ++- gcc/value-relation.h | 10 +- 19 files changed, 659 insertions(+), 416 deletions(-) create mode 100644 gcc/testsuite/g++.dg/modules/loc-prune-4.C create mode 100644 gcc/testsuite/gcc.dg/pr106198.c create mode 100644 gcc/testsuite/gcc.target/i386/bmi-andn-4.c create mode 100644 gcc/testsuite/gcc.target/i386/ssse3-palignr-2.c create mode 100644 gcc/testsuite/gcc.target/i386/testnot-3.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap updated (4694a0e5fe -> 99298c958c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap in repository toolchain/ci/binutils-gdb. from 4694a0e5fe Support for location and range lists for split-dwarf and dwarf-5. adds 736918239b gdb: LoongArch: add orig_a0 into register set adds 3acd9a692d Make 'import gdb.events' work adds 99298c958c Add gdb.Objfile.is_file attribute No new revisions were added by this update. Summary of changes: gdb/NEWS | 3 +++ gdb/doc/python.texi | 7 +++++++ gdb/features/loongarch/base32.c | 1 + gdb/features/loongarch/base32.xml | 1 + gdb/features/loongarch/base64.c | 1 + gdb/features/loongarch/base64.xml | 1 + gdb/loongarch-linux-nat.c | 2 ++ gdb/loongarch-linux-tdep.c | 8 ++++++++ gdb/loongarch-tdep.c | 1 + gdb/loongarch-tdep.h | 7 ++++--- gdb/python/lib/gdb/__init__.py | 5 +++++ gdb/python/py-evtregistry.c | 4 +++- gdb/python/py-evts.c | 28 +++++++++++++--------------- gdb/python/py-objfile.c | 14 ++++++++++++++ gdb/python/python-internal.h | 4 ++-- gdb/python/python.c | 16 ++++++++++++---- gdb/testsuite/gdb.base/jit-reader.exp | 12 ++++++++++++ gdb/testsuite/gdb.python/py-events.exp | 2 ++ 18 files changed, 92 insertions(+), 25 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap updated (cbae9059 -> 85783edf)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap in repository toolchain/ci/base-artifacts. discards cbae9059 0: update: binutils-gcc: 2 new 85783edf 0: update: binutils-gcc: 2 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (cbae9059) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_bootstrap/master-aar [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1608 -> 1604 bytes 02-prepare_abe/console.log.xz | Bin 2724 -> 2720 bytes 04-build_abe-binutils/console.log.xz | Bin 38304 -> 37536 bytes 05-build_abe-bootstrap/console.log.xz | Bin 273036 -> 271720 bytes 06-check_regression/console.log.xz | Bin 416 -> 416 bytes 07-update_baseline/console.log | 37 ++++++++++++++++++++++++++++++++++ jenkins/manifest.sh | 12 +++++------ 7 files changed, 43 insertions(+), 6 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[binutils-gdb] branch master updated (99298c958c5 -> 22f8e2e7266)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 99298c958c5 Add gdb.Objfile.is_file attribute new 22f8e2e7266 [gdb/exp] Fix internal error when printing C++ pointer-to-member The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/cp-valprint.c | 5 ++++- .../interrupt-a.c => gdb.cp/pointer-to-member.cc} | 17 ++++++++++++----- .../gdb.cp/{typed-enum.exp => pointer-to-member.exp} | 11 ++++++----- 3 files changed, 22 insertions(+), 11 deletions(-) copy gdb/testsuite/{gdb.base/interrupt-a.c => gdb.cp/pointer-to-member.cc} (88%) copy gdb/testsuite/gdb.cp/{typed-enum.exp => pointer-to-member.exp} (79%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap_profiled updated (dcc9b683dc -> 96c33f79de)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap_profiled in repository toolchain/ci/binutils-gdb. from dcc9b683dc Automatic date update in version.in adds 1e3a4f12e7 Automatic date update in version.in adds 0f2f2e7019 RISC-V: Update Zihintpause extension version adds 9386188e95 x86-64: improve handling of branches to absolute addresses adds 02b83698ef x86: restore masking of displacement kinds adds a775efc84d x86: fold Disp32S and Disp32 adds 58098fd779 gas/testsuite: properly exclude aout in all/weakref1u adds 2c474c4694 [gdb/symtab] Add get/set functions for per_cu->lang/unit_type adds a0f3a4c646 opcodes/avr: Implement style support in the disassembler adds 407115429b Modified changes for split-dwarf and dwarf-5. adds d8efadbdd9 Synchronize libbierty sources with gcc. adds 0772daccb3 objcopy: bfd_alloc orelocation adds eeeaf705fe alloc gas seginfo on notes obstack adds 96c33f79de Fix snafu in rust demangler recursion limit code No new revisions were added by this update. Summary of changes: ChangeLog | 13 + bfd/elfxx-riscv.c | 2 +- bfd/version.h | 2 +- binutils/bucomm.c | 13 + binutils/bucomm.h | 2 + binutils/dwarf.c | 12 +- binutils/objcopy.c | 37 +- gas/as.h | 1 + gas/config/tc-i386-intel.c | 9 +- gas/config/tc-i386.c | 97 +- gas/output-file.c | 42 +- gas/subsegs.c | 37 +- gas/testsuite/gas/all/weakref1u.d | 2 +- gas/testsuite/gas/i386/i386.exp | 1 + gas/testsuite/gas/i386/x86-64-branch-6.d | 21 + gas/testsuite/gas/i386/x86-64-branch-6.e | 7 + gas/testsuite/gas/i386/x86-64-branch-6.s | 18 + gdb/dwarf2/cooked-index.c | 10 +- gdb/dwarf2/cu.c | 2 +- gdb/dwarf2/index-write.c | 2 +- gdb/dwarf2/read.c | 223 +- gdb/dwarf2/read.h | 41 +- libiberty/ChangeLog | 146 +- libiberty/configure | 1 + libiberty/configure.ac | 1 + libiberty/rust-demangle.c | 47 +- opcodes/ChangeLog | 9 + opcodes/avr-dis.c | 51 +- opcodes/disassemble.c | 5 + opcodes/i386-gen.c | 10 +- opcodes/i386-init.h | 132 +- opcodes/i386-opc.h | 5 +- opcodes/i386-opc.tbl | 15 +- opcodes/i386-tbl.h | 25585 +++++++++++++++-------------- 34 files changed, 13467 insertions(+), 13134 deletions(-) create mode 100644 gas/testsuite/gas/i386/x86-64-branch-6.d create mode 100644 gas/testsuite/gas/i386/x86-64-branch-6.e create mode 100644 gas/testsuite/gas/i386/x86-64-branch-6.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap_profiled updated (ef209ac4 -> 35494fc4)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-arm-bootstrap_profiled in repository toolchain/ci/base-artifacts. discards ef209ac4 0: update: binutils-gcc: 2 new 35494fc4 0: update: binutils-96c33f79ded357e871c43af04238dfdedebac86c: 2 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (ef209ac4) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_bootstrap/master-arm [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1616 -> 1612 bytes 02-prepare_abe/console.log.xz | Bin 2712 -> 2744 bytes 04-build_abe-binutils/console.log.xz | Bin 52316 -> 52128 bytes 05-build_abe-bootstrap_profiled/console.log.xz | Bin 936792 -> 937136 bytes 06-check_regression/console.log.xz | Bin 420 -> 416 bytes 07-update_baseline/console.log | 18 +++++++++--------- jenkins/manifest.sh | 11 +++++------ 7 files changed, 14 insertions(+), 15 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 updated (c3d2600cfb4 -> 1d2aa262482)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 in repository toolchain/ci/gcc. from c3d2600cfb4 tree-optimization/106186 - propagate out virtual LC PHI nod [...] adds 1cc08ceb5ba Remove dead loop-based LC SSA rewrite adds 07dd0f7ba27 tree-optimization/106198 - CFG cleanup vs LC SSA adds 069f46c71e9 c++: Prune ordinary locations adds d458c53a6f3 PR rtl-optimization/96692: ((A|B)^C)^A using andn with -mbm [...] adds 02e2e15ec4b UNSPEC_PALIGNR optimizations and clean-ups on x86. adds c73e8d45ca0 Doubleword version of and;cmp to not;test optimization on x86. adds 1d2aa262482 Provide a relation verification mechanism. No new revisions were added by this update. Summary of changes: gcc/config/i386/i386-builtin.def | 2 +- gcc/config/i386/i386-expand.cc | 8 +- gcc/config/i386/i386.cc | 13 + gcc/config/i386/i386.md | 98 +++- gcc/config/i386/sse.md | 37 +- gcc/cp/module.cc | 629 +++++++++++++----------- gcc/testsuite/g++.dg/modules/loc-prune-1.C | 2 +- gcc/testsuite/g++.dg/modules/loc-prune-4.C | 22 + gcc/testsuite/g++.dg/modules/pr98718_a.C | 2 +- gcc/testsuite/g++.dg/modules/pr98718_b.C | 2 +- gcc/testsuite/g++.dg/modules/pr99072.H | 4 +- gcc/testsuite/gcc.dg/pr106198.c | 22 + gcc/testsuite/gcc.target/i386/bmi-andn-4.c | 9 + gcc/testsuite/gcc.target/i386/ssse3-palignr-2.c | 21 + gcc/testsuite/gcc.target/i386/testnot-3.c | 9 + gcc/tree-cfgcleanup.cc | 6 +- gcc/tree-ssa-loop-manip.cc | 109 +--- gcc/value-relation.cc | 70 ++- gcc/value-relation.h | 10 +- 19 files changed, 659 insertions(+), 416 deletions(-) create mode 100644 gcc/testsuite/g++.dg/modules/loc-prune-4.C create mode 100644 gcc/testsuite/gcc.dg/pr106198.c create mode 100644 gcc/testsuite/gcc.target/i386/bmi-andn-4.c create mode 100644 gcc/testsuite/gcc.target/i386/ssse3-palignr-2.c create mode 100644 gcc/testsuite/gcc.target/i386/testnot-3.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 updated (fca3257d -> e0ec820f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 in repository toolchain/ci/base-artifacts. discards fca3257d 0: update: binutils-99298c958c5393402cd2bc2885c195838a9dd363: 7 new e0ec820f 0: update: gcc-1d2aa262482fc9b23201200ca82aa3b8659b072e: 7 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (fca3257d) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_cross_build/master-a [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1596 -> 1652 bytes 02-prepare_abe/console.log.xz | Bin 2736 -> 2728 bytes 04-build_abe-binutils/console.log.xz | Bin 30388 -> 29756 bytes 05-build_abe-stage1/console.log.xz | Bin 74156 -> 73032 bytes 06-clean_sysroot/console.log.xz | Bin 328 -> 328 bytes 07-build_abe-linux/console.log.xz | Bin 11772 -> 11776 bytes 08-build_abe-glibc/console.log.xz | Bin 237536 -> 237596 bytes 09-build_abe-stage2/console.log.xz | Bin 204124 -> 202616 bytes 10-build_abe-gdb/console.log.xz | Bin 34640 -> 34776 bytes 11-build_abe-qemu/console.log.xz | Bin 34512 -> 33824 bytes 12-check_regression/console.log.xz | Bin 416 -> 416 bytes 13-update_baseline/console.log | 16 ++++++++-------- jenkins/manifest.sh | 10 +++++----- 13 files changed, 13 insertions(+), 13 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_bmk_llvm_fx/llvm-master-aarch64-spec2k6-O2 updated (a65a3bffd31f -> 271b470f3f1a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_fx/llvm-master-aarch64-spec2k6-O2 in repository toolchain/ci/llvm-project. from a65a3bffd31f [clang-tidy] Don't treat invalid branches as identical adds f7a80c3d08d4 [clang-tidy] Properly forward clang-tidy output when runni [...] adds 2c3784cff859 [SCEV] recognize llvm.annotation intrinsic adds e98e13ac8f38 [mlir][Vector] Fold ShuffleOp(SplatOp(X), SplatOp(X)) to S [...] adds d2a35e4d39fe [AIX] Handling the label alignment of a global variable wi [...] adds 93d6fdfc232c [Driver] Ignore the clang modules validation-related flags [...] adds 8eb4dcb73747 [RISCV] Move some SHXADD matching cases into a ComplexPatt [...] adds d36e09cfe591 [RISCV] Add more SHXADD patterns. adds 1063dfc02853 [mlir][openmp] Added omp.taskloop adds 7283f48a05de [IR] Remove support for insertvalue constant expression adds b4694229aa9d [LV] Simplify setDebugLocFromInst by using early exit (NFC). adds f0089fae1d7e [AArch64] Add additional tests for D120481. adds 7fbf55c927f2 [mlir][Tensor] Move ParallelInsertSlice to the tensor dialect adds 9604601c9394 [SimplifyCFG] Remove redundant checks for hoisting (NFCI) adds 4887d047a31f [libc++][NFC] Replace enable_if with __enable_if_t in a fe [...] adds 04f6bf482b86 Revise outdated parts of the developer policy. adds 5f0a054f8954 [pseudo] Remove duplicated code in ClangPseudo.cpp adds c9fb3c6ea6cc [mlir][Tensor] Update ParallelInsertSlicOp semantics to ma [...] adds f4dd977537dc [AST] Use canonical constraint declaration for ASTContext: [...] adds 42f5b0509ded [mlir][NFC] Fix various warnings generated by GCC 9 adds cce64e7a9cba [DAG] visitTRUNCATE - move GetDemandedBits AFTER SimplifyD [...] adds f90f0e8fe7f5 [AMDGPU][GFX10][DOC][NFC] Update assembler syntax description adds bf89d24f5319 [AArch64] NFC: Move safe predicate casting to a separate f [...] adds 740633ff08ff [flang] Add TODO for derived types with final procedure adds 4905bcac00e6 [ConstantFolding] Check return value of ConstantFoldInstOp [...] adds 8e70258b18ba [AMDGPUCodeGenPrepare] Check result of ConstantFoldBinaryO [...] adds 19a1e20b8a0f [VectorCombine] Improve shuffle select shuffle-of-shuffles adds 25607d143d1d [libc++] Implement `std::ranges::merge` adds 3912928aa891 [gn build] Port 25607d143d1d adds 32a76fc292d9 [SCEVExpander] Avoid ConstantExpr::get() (NFCI) adds 93cbdaef0455 [Reassociate] Avoid ConstantExpr::get() adds 2de05afc192d [SLP] Peek into loads when hitting the RecursionMaxDepth adds 2ab260eecfab [llvm-ar][test] Add additional MRI script testing adds 4e6c30c8354f [libc] Add a separate algorithm_test. adds d7697c175db9 [flang] Avoid segfault when defining op is not a fir::Convert adds f93cd56262d1 [BPI] Avoid ConstantExpr::get() adds aa78c5298ea3 Fix MLIR Python CMake bug causing duplicate sources target. adds 644a965c1efe [LV] Vectorize cases with larger number of RT checks, exec [...] adds c06d0b4d02ea [RISCV] Add ADDI instr for computing FrameIndex address adds c146af3f469a [LoopVectorize][NFC] Reinstate TTICapture workaround for gcc-6 adds 8471c6861992 [LTO] Update remark test after 644a965c1efef6. adds 89cb8cae606b [Bitcode] Use bitcode input for test (NFC) adds abbd684c02c7 [InstCombine] Avoid ConstantExpr::get() in phi binop fold adds 10ebaf76860e [SLP] add test for load combining + shuffling; NFC adds fdf505f3f223 [mlir][OpenMP] omp.task translation to LLVM IR adds 2bfca3561466 [X86] Disable combineVectorSizedSetCCEquality for soft float. adds 5785717e18d5 [AArch64] Add support for insert/extract for nxv1i1 types. adds 2fde26dfcabe [mlir][Linalg][NFC] Make getReassociationMapForFoldingUnit [...] adds 9eb657278611 [LV] Add back CantReorderMemOps remark. adds c3839c0b46a9 CombineContractBroadcast should not create dims unused in LHS+RHS adds bc70ba814dc1 Use add_llvm_install_targets for install-llvmlibc adds b37dafd5dc83 [pseudo] Store shift and goto actions in a compact structu [...] adds 12d26ce9b0ec [flang] Make code more homogenous in CodeGen adds 47bdf53a5dba [clang-format] Break on AfterColon only if not followed by [...] adds 1ab37d996ce3 [clang-format] Update documentation adds 2a82c15f63d4 [LV] Consider runtime checks profitable if scalar cost is zero. adds 623250b51139 [X86] Regenerate fold-tied-op.ll test checks adds a4e2c1f76295 [Orc][LLJIT] Use JITLink on RISC-V adds b6178ccfe852 [OffloadPackager] Use appropriate kind for LTO bitcode adds 4276d00b1253 [InstCombine] add helper function for sub-of-min/max folds; NFC adds 8ef053273abf [InstCombine] add tests for sub of smin/smax; NFC adds 142aca7741d5 [InstCombine] fold sub of min/max of sub with common operand adds b2b4c8721db0 [InstCombine] Make use of low zero bits to determine exact [...] adds 063500afc0b8 [RISCV][NFC] Merge the isolated decleration into foreach. adds 98c6a3c0c220 [NFC][ASTImporter] remove the unnecessary condition checks [...] adds 85318d328102 [NFC] Remove unused test inputs adds 939352b6ec31 [RISCV][Clang] Teach RISCVEmitter to generate BitCast for [...] adds 5b4851ed9113 [LoongArch] Add codegen support for load/store operations adds b940fe6fe2af [LoongArch] Add codegen support for conditional branches adds 3610d5f5d4c2 [LoongArch] Add initial support for function calls adds 0c01f42fad41 [llvm-objcopy] -O binary: align sh_offset for section chan [...] adds 3e01af093f92 [mlir] Add InferIntRangeInterface to gpu.launch adds 2028fe6fbca6 [lld-macho] Handle LOH_ARM64_ADRP_LDR_GOT optimization hints adds 4996e3f68315 [test] Check for more -fsanitize=array-bounds behavior adds 66790b70ea14 [RISCV] Rename some variables for clarity. NFC adds f27672924e36 [RISCV] Replace an explicit check with an assert. adds 7a550212e8ff [clang-tidy] Fix confusable identifiers interaction with D [...] adds b094c737cd85 [flang] Avoid opaque pointer issue with character array su [...] adds b69c75d53f8d Revert "[VectorCombine] Improve shuffle select shuffle-of- [...] adds 00927334df9a [libc++] Use __is_exactly_{input, forward}_iterator adds 0d0bd17fcfbd [libc++] Fix __split_buffer::__construct_at_end definition [...] adds 4de0680fbf4e Fix use of pointer arithmetic instead of iterators. adds df5c981be35a [mlir][Linalg] Add DropUnitDims support for tensor::Parall [...] adds 774fc6349093 [LV] Consider minimum vscale assmuption for RT check cost. adds dfb77f2e99a1 [LLD][ELF] Add FORCE_LLD_DIAGNOSTICS_CRASH to force LLD to crash adds 77b13a57a930 [AArch64][SME] Add SME addha/va intrinsics adds 00cb1c33ee2e [InstCombine] add negtive tests for (%x & C) == 0 -> %x u< [...] adds dc46ae6df5f7 [lldb] Add support to load object files from thin archives adds b6ad8cbb3575 [gn build] (manually) port dfb77f2e99a1 adds b66220f25aea [InstCombine] [NFC] use C.isNegatedPowerOf2() instead of ( [...] adds 220366d5b545 [gn build] (manually) port 6b3956e123db adds b43dd2f6c4a3 [InstCombine] improve fold for icmp_eq_and to icmp_ult adds 271b470f3f1a [IndVars] Precommit test with redundant FPToSI. No new revisions were added by this update. Summary of changes: .../clang-tidy/misc/ConfusableIdentifierCheck.cpp | 70 +- .../pseudo/include/clang-pseudo/grammar/LRTable.h | 120 +++- clang-tools-extra/pseudo/lib/GLR.cpp | 16 +- clang-tools-extra/pseudo/lib/grammar/LRTable.cpp | 65 +- .../pseudo/lib/grammar/LRTableBuild.cpp | 61 +- clang-tools-extra/pseudo/tool/ClangPseudo.cpp | 48 +- clang-tools-extra/pseudo/unittests/LRTableTest.cpp | 2 +- .../test/clang-tidy/check_clang_tidy.py | 10 +- .../checkers/misc/confusable-identifiers.cpp | 98 ++- clang/docs/ClangFormat.rst | 84 ++- clang/include/clang/AST/ASTImportError.h | 1 - clang/include/clang/Basic/riscv_vector.td | 99 +-- clang/include/clang/Support/RISCVVIntrinsicUtils.h | 2 + clang/lib/AST/ASTContext.cpp | 3 + clang/lib/AST/ASTImporter.cpp | 10 - clang/lib/Driver/ToolChains/Clang.cpp | 63 +- clang/lib/Format/ContinuationIndenter.cpp | 4 +- clang/lib/Format/TokenAnnotator.cpp | 8 +- clang/lib/Format/UnwrappedLineParser.cpp | 16 +- clang/test/CodeGen/bounds-checking-fam.c | 45 +- clang/test/Driver/modules.m | 30 +- clang/test/Frontend/optimization-remark-options.c | 2 +- clang/test/Modules/Inputs/concept/A.cppm | 3 - clang/test/Modules/Inputs/concept/foo.h | 13 - clang/test/Modules/concept.cppm | 50 +- clang/tools/clang-offload-packager/CMakeLists.txt | 1 + .../ClangOffloadPackager.cpp | 9 +- clang/unittests/Format/FormatTest.cpp | 19 + clang/utils/TableGen/RISCVVEmitter.cpp | 10 + flang/lib/Lower/ConvertType.cpp | 4 + flang/lib/Optimizer/Builder/FIRBuilder.cpp | 5 +- flang/lib/Optimizer/CodeGen/CodeGen.cpp | 77 ++- flang/test/Fir/embox.fir | 2 +- flang/test/Lower/extent_triplets.f90 | 11 + libc/lib/CMakeLists.txt | 9 +- libc/test/src/string/memory_utils/CMakeLists.txt | 17 +- libcxx/docs/Status/RangesAlgorithms.csv | 10 +- libcxx/include/CMakeLists.txt | 1 + libcxx/include/__algorithm/ranges_merge.h | 142 ++++ libcxx/include/__hash_table | 16 +- libcxx/include/__iterator/iterator_traits.h | 6 + libcxx/include/__mutex_base | 12 +- libcxx/include/__split_buffer | 26 +- libcxx/include/__tree | 32 +- libcxx/include/__tuple | 6 +- libcxx/include/algorithm | 18 + libcxx/include/array | 7 +- libcxx/include/deque | 18 +- libcxx/include/exception | 4 +- libcxx/include/forward_list | 42 +- libcxx/include/list | 16 +- libcxx/include/map | 52 +- libcxx/include/module.modulemap.in | 1 + libcxx/include/regex | 7 +- libcxx/include/tuple | 16 +- libcxx/include/unordered_map | 12 +- libcxx/include/vector | 64 +- ...ges_robust_against_copying_comparators.pass.cpp | 6 +- ...ges_robust_against_copying_projections.pass.cpp | 6 +- libcxx/test/libcxx/private_headers.verify.cpp | 1 + .../alg.sorting/alg.merge/ranges_merge.pass.cpp | 613 +++++++++++++++++ .../deque/deque.cons/assign_iter_iter.pass.cpp | 34 +- .../niebloid.compile.pass.cpp | 2 +- lld/MachO/Arch/ARM64.cpp | 16 +- lld/docs/ReleaseNotes.rst | 2 + lld/test/ELF/crash-report.test | 10 + lld/test/MachO/loh-adrp-ldr-got.s | 35 + lld/test/lit.cfg.py | 3 + lld/test/lit.site.cfg.py.in | 1 + lld/tools/lld/lld.cpp | 6 + .../BSD-Archive/ObjectContainerBSDArchive.cpp | 208 +++++- .../BSD-Archive/ObjectContainerBSDArchive.h | 22 +- lldb/test/API/functionalities/archives/Makefile | 11 +- .../functionalities/archives/TestBSDArchives.py | 7 + lldb/test/API/functionalities/archives/c.c | 11 + lldb/test/API/lit.cfg.py | 4 + lldb/test/CMakeLists.txt | 1 + llvm/bindings/go/llvm/ir.go | 10 - llvm/bindings/ocaml/llvm/llvm.ml | 2 - llvm/bindings/ocaml/llvm/llvm.mli | 5 - llvm/bindings/ocaml/llvm/llvm_ocaml.c | 17 - llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst | 764 +++++++++++---------- llvm/docs/AMDGPU/gfx10_hwreg.rst | 42 +- .../AMDGPU/{gfx10_opt.rst => gfx10_opt_0d447d.rst} | 4 +- .../AMDGPU/{gfx10_opt.rst => gfx10_opt_847aed.rst} | 2 +- ...soffset_c40a5a.rst => gfx10_soffset_73dae7.rst} | 6 +- ...soffset_59fade.rst => gfx10_soffset_d01a5c.rst} | 6 +- ...x10_vdata_c61803.rst => gfx10_vdata_0aba12.rst} | 4 +- ...x10_vdata_b2a787.rst => gfx10_vdata_16d321.rst} | 4 +- ...x10_vdata_325b78.rst => gfx10_vdata_35851e.rst} | 6 +- ...x10_vdata_87fb90.rst => gfx10_vdata_890652.rst} | 4 +- ...x10_vdata_4d8ecf.rst => gfx10_vdata_a9ff5a.rst} | 6 +- ...gfx10_vdst_48d3a8.rst => gfx10_vdst_2ea017.rst} | 6 +- ...gfx10_vdst_5d50a1.rst => gfx10_vdst_322561.rst} | 6 +- ...gfx10_vdst_5d50a1.rst => gfx10_vdst_709347.rst} | 4 +- llvm/docs/AMDGPU/gfx10_vdst_719833.rst | 21 - ...gfx10_vdst_a49b76.rst => gfx10_vdst_81a6ed.rst} | 4 +- ...gfx10_vdst_d7c57e.rst => gfx10_vdst_d71f1c.rst} | 4 +- ...gfx10_vdst_f47754.rst => gfx10_vdst_dd8a32.rst} | 4 +- llvm/docs/DeveloperPolicy.rst | 38 +- llvm/docs/LangRef.rst | 16 +- llvm/docs/ReleaseNotes.rst | 2 + llvm/include/llvm-c/Core.h | 3 - llvm/include/llvm/CodeGen/AsmPrinter.h | 7 +- llvm/include/llvm/IR/Constants.h | 11 - llvm/include/llvm/IR/IntrinsicsAArch64.td | 10 + .../Vectorize/LoopVectorizationLegality.h | 7 - llvm/lib/Analysis/BranchProbabilityInfo.cpp | 6 +- llvm/lib/Analysis/ConstantFolding.cpp | 8 +- llvm/lib/Analysis/ScalarEvolution.cpp | 8 +- llvm/lib/AsmParser/LLParser.cpp | 28 +- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 3 - llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 91 ++- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 24 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 9 +- .../lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h | 2 +- llvm/lib/ExecutionEngine/Orc/LLJIT.cpp | 5 +- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 8 +- llvm/lib/IR/AsmWriter.cpp | 4 - llvm/lib/IR/Constants.cpp | 44 +- llvm/lib/IR/ConstantsContext.h | 60 +- llvm/lib/IR/Core.cpp | 12 - llvm/lib/ObjCopy/ELF/ELFObject.cpp | 7 +- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 113 ++- llvm/lib/Target/AArch64/AArch64ISelLowering.h | 8 + llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 59 +- llvm/lib/Target/AArch64/SMEInstrFormats.td | 34 + llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 4 +- llvm/lib/Target/LoongArch/LoongArchAsmPrinter.h | 4 + .../Target/LoongArch/LoongArchFloat32InstrInfo.td | 8 + .../Target/LoongArch/LoongArchFloat64InstrInfo.td | 8 + llvm/lib/Target/LoongArch/LoongArchFrameLowering.h | 6 + .../lib/Target/LoongArch/LoongArchISelLowering.cpp | 154 +++++ llvm/lib/Target/LoongArch/LoongArchISelLowering.h | 4 + llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp | 70 +- llvm/lib/Target/LoongArch/LoongArchInstrInfo.h | 10 + llvm/lib/Target/LoongArch/LoongArchInstrInfo.td | 143 +++- llvm/lib/Target/LoongArch/LoongArchMCInstLower.cpp | 24 +- .../lib/Target/LoongArch/LoongArchRegisterInfo.cpp | 24 +- llvm/lib/Target/NVPTX/NVPTXGenericToNVVM.cpp | 4 - llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 45 +- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 147 ++-- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 12 +- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 - llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 9 +- llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td | 36 +- llvm/lib/Target/RISCV/RISCVInstrInfoZb.td | 24 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 10 +- .../Transforms/InstCombine/InstCombineAddSub.cpp | 78 ++- .../Transforms/InstCombine/InstCombineCasts.cpp | 9 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 11 +- .../InstCombine/InstructionCombining.cpp | 8 +- llvm/lib/Transforms/Scalar/Reassociate.cpp | 19 +- .../Transforms/Utils/ScalarEvolutionExpander.cpp | 3 +- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 5 +- .../Vectorize/LoopVectorizationLegality.cpp | 1 - .../Vectorize/LoopVectorizationPlanner.h | 10 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 257 +++++-- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 14 +- llvm/lib/Transforms/Vectorize/VPlan.cpp | 38 +- .../ScalarEvolution/annotation-intrinsics.ll | 4 +- llvm/test/Assembler/insertextractvalue.ll | 28 - llvm/test/Assembler/insertvalue-invalid-type-1.ll | 7 - llvm/test/Assembler/unsupported-constexprs.ll | 17 +- .../Inputs/bitcode-parseconstant-delay-select.bc | Bin 0 -> 1420 bytes .../Bitcode/bitcode-parseconstant-delay-select.ll | 2 +- llvm/test/CodeGen/AArch64/sme-intrinsics-add.ll | 43 ++ .../CodeGen/AArch64/sve-extract-scalable-vector.ll | 336 +++++++++ llvm/test/CodeGen/AArch64/sve-insert-vector.ll | 668 ++++++++++++++++++ llvm/test/CodeGen/AArch64/vselect-ext.ll | 241 ++++++- llvm/test/CodeGen/LoongArch/ir-instruction/br.ll | 358 ++++++++++ llvm/test/CodeGen/LoongArch/ir-instruction/call.ll | 79 +++ .../CodeGen/LoongArch/ir-instruction/indirectbr.ll | 30 + .../CodeGen/LoongArch/ir-instruction/load-store.ll | 368 ++++++++++ llvm/test/CodeGen/PowerPC/aix-alias-alignment-2.ll | 79 +++ llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll | 74 ++ llvm/test/CodeGen/PowerPC/aix-alias.ll | 16 +- llvm/test/CodeGen/RISCV/rv64zba.ll | 67 ++ .../RISCV/rvv/access-fixed-objects-by-rvv.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll | 98 +-- llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll | 62 +- llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll | 162 ++--- llvm/test/CodeGen/RISCV/rvv/calling-conv.ll | 18 +- llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll | 24 - llvm/test/CodeGen/RISCV/rvv/ctpop-sdnode.ll | 12 - llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll | 24 - .../CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll | 16 +- .../RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll | 111 ++- .../RISCV/rvv/fixed-vectors-calling-conv.ll | 301 ++++---- .../CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll | 148 ++-- .../CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll | 36 +- .../RISCV/rvv/fixed-vectors-insert-subvector.ll | 5 +- .../CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll | 10 +- .../RISCV/rvv/fixed-vectors-mask-buildvec.ll | 24 +- .../RISCV/rvv/fixed-vectors-masked-gather.ll | 112 +-- .../RISCV/rvv/fixed-vectors-masked-scatter.ll | 122 ++-- .../RISCV/rvv/fixed-vectors-reduction-int-vp.ll | 32 +- .../RISCV/rvv/fixed-vectors-reduction-int.ll | 24 +- .../RISCV/rvv/fixed-vectors-setcc-int-vp.ll | 36 +- .../CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vmul-vp.ll | 16 +- .../test/CodeGen/RISCV/rvv/fixed-vectors-vor-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll | 8 +- .../CodeGen/RISCV/rvv/fixed-vectors-vrem-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vremu-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vrsub-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vsadd.ll | 8 +- .../test/CodeGen/RISCV/rvv/fixed-vectors-vsaddu.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vssub.ll | 8 +- .../test/CodeGen/RISCV/rvv/fixed-vectors-vssubu.ll | 8 +- .../CodeGen/RISCV/rvv/fixed-vectors-vsub-vp.ll | 16 +- .../CodeGen/RISCV/rvv/fixed-vectors-vxor-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll | 3 +- llvm/test/CodeGen/RISCV/rvv/localvar.ll | 68 +- llvm/test/CodeGen/RISCV/rvv/masked-tama.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/memory-args.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/rvv-args-by-mem.ll | 19 +- llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/setcc-int-vp.ll | 72 +- llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll | 40 +- llvm/test/CodeGen/RISCV/rvv/stepvector.ll | 7 +- llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll | 10 +- llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll | 18 +- llvm/test/CodeGen/RISCV/rvv/vaadd.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vaaddu.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vadc-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vadd-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vadd-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vadd.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vand-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vand-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vand-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vasub.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vasubu.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vdiv-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vdiv-sdnode.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vdiv-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vdivu-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vdivu-sdnode.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vdivu-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmacc-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmadc-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmadc.carry.in-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmadd-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmadd-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmax-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmax-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmaxu-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmaxu-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmin-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmin-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vminu-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vminu-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmsbc-rv32.ll | 8 +- .../test/CodeGen/RISCV/rvv/vmsbc.borrow.in-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmseq-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmsge-rv32.ll | 18 +- llvm/test/CodeGen/RISCV/rvv/vmsgeu-rv32.ll | 18 +- llvm/test/CodeGen/RISCV/rvv/vmsgt-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmsgtu-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmsle-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmsleu-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmsltu-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmsne-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vmul-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vmul-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmul.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmulh.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmulhu.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vmv.v.x-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vnmsac-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vnmsub-rv32.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vnmsub-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vor-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vor-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vor-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll | 60 +- llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vrem-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vrem-sdnode.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vrem-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vremu-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vremu-sdnode.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vremu-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vrsub-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vrsub-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vrsub.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vsadd-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vsadd-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vsaddu-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vsaddu-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vsbc-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vselect-int-rv32.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/vssub-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vssub-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vssubu-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vssubu-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vsub-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vsub-vp.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vsub.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vxor-rv32.ll | 16 +- llvm/test/CodeGen/RISCV/rvv/vxor-sdnode.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/vxor-vp.ll | 16 +- .../test/CodeGen/RISCV/srem-seteq-illegal-types.ll | 74 +- .../test/CodeGen/RISCV/urem-seteq-illegal-types.ll | 4 +- llvm/test/CodeGen/X86/fold-tied-op.ll | 119 +++- llvm/test/CodeGen/X86/nonconst-static-iv.ll | 8 - llvm/test/CodeGen/X86/pr56351.ll | 18 + llvm/test/LTO/X86/diagnostic-handler-remarks.ll | 4 +- .../Transforms/IndVarSimplify/floating-point-iv.ll | 34 + .../InstCombine/lshr-and-negC-icmpeq-zero.ll | 52 +- llvm/test/Transforms/InstCombine/sitofp.ll | 31 +- llvm/test/Transforms/InstCombine/sub-minmax.ll | 145 +++- .../AArch64/runtime-check-size-based-threshold.ll | 18 +- .../AArch64/sve-tail-folding-forced.ll | 2 +- .../AArch64/sve-tail-folding-unroll.ll | 4 +- .../LoopVectorize/AArch64/sve-tail-folding.ll | 22 +- .../Transforms/LoopVectorize/X86/gather_scatter.ll | 2 +- .../X86/pointer-runtime-checks-unprofitable.ll | 60 +- llvm/test/Transforms/LoopVectorize/X86/pr23997.ll | 2 +- llvm/test/Transforms/LoopVectorize/X86/pr35432.ll | 2 +- llvm/test/Transforms/LoopVectorize/X86/pr54634.ll | 2 +- .../Transforms/LoopVectorize/X86/runtime-limit.ll | 22 +- .../Transforms/SLPVectorizer/AArch64/loadorder.ll | 151 ++-- .../X86/load-partial-vector-shuffle.ll | 73 ++ llvm/test/tools/llvm-ar/Inputs/mri-crlf.mri | 2 + llvm/test/tools/llvm-ar/mri-crlf.test | 9 +- llvm/test/tools/llvm-ar/mri-delete.test | 188 ++++- llvm/test/tools/llvm-ar/mri-end.test | 140 ++-- llvm/test/tools/llvm-ar/mri-nonascii.test | 37 +- .../tools/llvm-objcopy/ELF/binary-no-paddr.test | 22 +- llvm/test/tools/llvm-objcopy/ELF/binary-paddr.test | 40 ++ llvm/utils/gn/secondary/libcxx/include/BUILD.gn | 1 + llvm/utils/gn/secondary/lld/test/BUILD.gn | 1 + .../gn/secondary/llvm/tools/llvm-reduce/BUILD.gn | 1 + mlir/cmake/modules/AddMLIRPython.cmake | 2 +- mlir/include/mlir/Dialect/GPU/IR/GPUDialect.h | 1 + mlir/include/mlir/Dialect/GPU/IR/GPUOps.td | 21 +- mlir/include/mlir/Dialect/Linalg/Utils/Utils.h | 9 + mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td | 180 ++++- .../mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td | 2 +- mlir/include/mlir/Dialect/SCF/IR/SCFOps.td | 109 --- mlir/include/mlir/Dialect/Tensor/IR/Tensor.h | 1 + mlir/include/mlir/Dialect/Tensor/IR/TensorOps.td | 149 ++++ mlir/include/mlir/Dialect/Vector/IR/VectorOps.td | 1 + mlir/include/mlir/IR/AffineMap.h | 6 + mlir/lib/Dialect/Affine/IR/AffineOps.cpp | 2 +- mlir/lib/Dialect/GPU/CMakeLists.txt | 2 + .../Dialect/GPU/IR/InferIntRangeInterfaceImpls.cpp | 97 +++ .../lib/Dialect/Linalg/Transforms/DropUnitDims.cpp | 75 +- mlir/lib/Dialect/Linalg/Utils/Utils.cpp | 28 + mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp | 55 +- mlir/lib/Dialect/SCF/IR/CMakeLists.txt | 1 - mlir/lib/Dialect/SCF/IR/SCF.cpp | 143 +--- .../SCF/Transforms/BufferizableOpInterfaceImpl.cpp | 246 +------ mlir/lib/Dialect/Tensor/IR/CMakeLists.txt | 1 + mlir/lib/Dialect/Tensor/IR/TensorOps.cpp | 256 +++++-- .../Transforms/BufferizableOpInterfaceImpl.cpp | 244 +++++++ mlir/lib/Dialect/Vector/IR/VectorOps.cpp | 37 +- .../Dialect/Vector/Transforms/VectorTransforms.cpp | 21 +- mlir/lib/ExecutionEngine/OptUtils.cpp | 2 +- mlir/lib/ExecutionEngine/SparseTensorUtils.cpp | 2 +- mlir/lib/IR/AffineMap.cpp | 19 +- .../Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp | 27 + mlir/test/Dialect/GPU/int-range-interface.mlir | 128 ++++ .../test/Dialect/Linalg/drop-unit-extent-dims.mlir | 20 + mlir/test/Dialect/OpenMP/invalid.mlir | 125 ++++ mlir/test/Dialect/OpenMP/ops.mlir | 142 +++- mlir/test/Dialect/SCF/canonicalize.mlir | 25 - .../SCF/foreach-thread-canonicalization.mlir | 50 +- mlir/test/Dialect/SCF/invalid.mlir | 8 +- .../one-shot-bufferize-tensor-copy-insertion.mlir | 4 +- mlir/test/Dialect/SCF/one-shot-bufferize.mlir | 6 +- mlir/test/Dialect/SCF/ops.mlir | 4 +- mlir/test/Dialect/Tensor/canonicalize.mlir | 27 + mlir/test/Dialect/Vector/canonicalize.mlir | 14 + mlir/test/Dialect/Vector/invalid.mlir | 2 +- .../Dialect/Vector/vector-reduce-to-contract.mlir | 35 + mlir/test/Target/LLVMIR/openmp-llvm.mlir | 88 +++ utils/bazel/llvm-project-overlay/mlir/BUILD.bazel | 4 + 388 files changed, 10122 insertions(+), 4414 deletions(-) delete mode 100644 clang/test/Modules/Inputs/concept/A.cppm delete mode 100644 clang/test/Modules/Inputs/concept/foo.h create mode 100644 flang/test/Lower/extent_triplets.f90 create mode 100644 libcxx/include/__algorithm/ranges_merge.h create mode 100644 libcxx/test/std/algorithms/alg.sorting/alg.merge/ranges_merge.pass.cpp create mode 100644 lld/test/ELF/crash-report.test create mode 100644 lld/test/MachO/loh-adrp-ldr-got.s create mode 100644 lldb/test/API/functionalities/archives/c.c copy llvm/docs/AMDGPU/{gfx10_opt.rst => gfx10_opt_0d447d.rst} (83%) rename llvm/docs/AMDGPU/{gfx10_opt.rst => gfx10_opt_847aed.rst} (91%) rename llvm/docs/AMDGPU/{gfx10_soffset_c40a5a.rst => gfx10_soffset_73dae7.rst} (72%) rename llvm/docs/AMDGPU/{gfx10_soffset_59fade.rst => gfx10_soffset_d01a5c.rst} (61%) rename llvm/docs/AMDGPU/{gfx10_vdata_c61803.rst => gfx10_vdata_0aba12.rst} (80%) rename llvm/docs/AMDGPU/{gfx10_vdata_b2a787.rst => gfx10_vdata_16d321.rst} (80%) rename llvm/docs/AMDGPU/{gfx10_vdata_325b78.rst => gfx10_vdata_35851e.rst} (81%) rename llvm/docs/AMDGPU/{gfx10_vdata_87fb90.rst => gfx10_vdata_890652.rst} (80%) rename llvm/docs/AMDGPU/{gfx10_vdata_4d8ecf.rst => gfx10_vdata_a9ff5a.rst} (81%) rename llvm/docs/AMDGPU/{gfx10_vdst_48d3a8.rst => gfx10_vdst_2ea017.rst} (76%) copy llvm/docs/AMDGPU/{gfx10_vdst_5d50a1.rst => gfx10_vdst_322561.rst} (71%) rename llvm/docs/AMDGPU/{gfx10_vdst_5d50a1.rst => gfx10_vdst_709347.rst} (76%) delete mode 100644 llvm/docs/AMDGPU/gfx10_vdst_719833.rst rename llvm/docs/AMDGPU/{gfx10_vdst_a49b76.rst => gfx10_vdst_81a6ed.rst} (75%) rename llvm/docs/AMDGPU/{gfx10_vdst_d7c57e.rst => gfx10_vdst_d71f1c.rst} (75%) rename llvm/docs/AMDGPU/{gfx10_vdst_f47754.rst => gfx10_vdst_dd8a32.rst} (75%) delete mode 100644 llvm/test/Assembler/insertvalue-invalid-type-1.ll create mode 100644 llvm/test/Bitcode/Inputs/bitcode-parseconstant-delay-select.bc create mode 100644 llvm/test/CodeGen/AArch64/sme-intrinsics-add.ll create mode 100644 llvm/test/CodeGen/LoongArch/ir-instruction/br.ll create mode 100644 llvm/test/CodeGen/LoongArch/ir-instruction/call.ll create mode 100644 llvm/test/CodeGen/LoongArch/ir-instruction/indirectbr.ll create mode 100644 llvm/test/CodeGen/LoongArch/ir-instruction/load-store.ll create mode 100644 llvm/test/CodeGen/PowerPC/aix-alias-alignment-2.ll create mode 100644 llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll delete mode 100644 llvm/test/CodeGen/X86/nonconst-static-iv.ll create mode 100644 llvm/test/CodeGen/X86/pr56351.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/load-partial-vector-shuffle.ll create mode 100644 mlir/lib/Dialect/GPU/IR/InferIntRangeInterfaceImpls.cpp create mode 100644 mlir/test/Dialect/GPU/int-range-interface.mlir -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 10 months

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

Tcwg-commits July 2022