Tcwg-commits June 2022

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14714 discussions

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gcc_check/master-arm updated (f40bb390bb -> d0e0f9c87a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_check/master-arm in repository toolchain/ci/binutils-gdb. from f40bb390bb PowerPC64: align plt_branch stubs adds d0e0f9c87a ld/x86: skip p_align-1 tests with unsuitable compiler No new revisions were added by this update. Summary of changes: ld/testsuite/ld-elf/linux-x86.exp | 82 ++++++++++++++++++++++----------------- 1 file changed, 46 insertions(+), 36 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_check/master-arm updated (d3fe19ab -> 0a373329)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_check/master-arm in repository toolchain/ci/base-artifacts. discards d3fe19ab 0: update: binutils-gcc: 1 new 0a373329 0: update: binutils-gcc: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (d3fe19ab) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_check/master-arm (0a373329) You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1520 -> 1480 bytes 02-prepare_abe/console.log.xz | Bin 2696 -> 2724 bytes 03-build_abe-binutils/console.log.xz | Bin 51088 -> 51700 bytes 04-build_abe-gcc/console.log.xz | Bin 231524 -> 231240 bytes 05-build_abe-dejagnu/console.log.xz | Bin 3836 -> 3828 bytes 06-build_abe-check_gcc/console.log.xz | Bin 2796 -> 2696 bytes 07-check_regression/console.log.xz | Bin 3600 -> 3908 bytes 07-check_regression/extra-bisect-params | 2 +- 07-check_regression/fails.sum | 10 +- 07-check_regression/results.compare | 15 + 07-check_regression/results.compare2 | 55 +- 07-check_regression/results.regressions | 15 + 08-update_baseline/console.log | 626 ++--- 08-update_baseline/extra-bisect-params | 2 +- 08-update_baseline/fails.sum | 10 +- 08-update_baseline/results.compare | 15 + 08-update_baseline/results.compare2 | 55 +- 08-update_baseline/results.regressions | 15 + jenkins/manifest.sh | 12 +- sumfiles/g++.log.xz | Bin 2794852 -> 2790724 bytes sumfiles/g++.sum | 44 +- sumfiles/gcc.log.xz | Bin 2350332 -> 2352468 bytes sumfiles/gcc.sum | 4028 +++++++++++++++---------------- sumfiles/gfortran.log.xz | Bin 908016 -> 900112 bytes sumfiles/gfortran.sum | 56 +- sumfiles/libatomic.log.xz | Bin 2160 -> 2156 bytes sumfiles/libatomic.sum | 2 +- sumfiles/libgomp.log.xz | Bin 201876 -> 201608 bytes sumfiles/libgomp.sum | 2 +- sumfiles/libitm.log.xz | Bin 2544 -> 2544 bytes sumfiles/libitm.sum | 2 +- sumfiles/libstdc++.log.xz | Bin 460796 -> 458232 bytes sumfiles/libstdc++.sum | 2 +- 33 files changed, 2551 insertions(+), 2417 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 5 months

[binutils-gdb] branch binutils-2_38-branch updated (04d55a034ca -> b8a2baa80b1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch binutils-2_38-branch in repository binutils-gdb. from 04d55a034ca Automatic date update in version.in new 7f9a495a167 libctf: fix linking together multiple objects derived from [...] new b8a2baa80b1 libctf: tests: prune warnings from compiler output The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: libctf/ctf-dedup.c | 2 + libctf/ctf-impl.h | 4 + libctf/ctf-link.c | 161 ++++++++++++++++----- libctf/testsuite/config/default.exp | 7 + libctf/testsuite/lib/ctf-lib.exp | 4 +- .../libctf-regression/libctf-repeat-cu-lib.c | 9 ++ .../libctf-regression/libctf-repeat-cu-main.c | 5 + .../testsuite/libctf-regression/libctf-repeat-cu.d | 7 + .../libctf-regression/libctf-repeat-cu.exp | 118 +++++++++++++++ 9 files changed, 282 insertions(+), 35 deletions(-) create mode 100644 libctf/testsuite/libctf-regression/libctf-repeat-cu-lib.c create mode 100644 libctf/testsuite/libctf-regression/libctf-repeat-cu-main.c create mode 100644 libctf/testsuite/libctf-regression/libctf-repeat-cu.d create mode 100644 libctf/testsuite/libctf-regression/libctf-repeat-cu.exp -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 5 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_bmk_llvm_sq/llvm-master-aarch64-cpu2017-Os updated (88c4a4a6beb5 -> fa596c692115)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_sq/llvm-master-aarch64-cpu2017-Os in repository toolchain/ci/llvm-project. from 88c4a4a6beb5 [flang] Update the release notes adds bdfe556dd837 [clang][dataflow] Implement functionality for flow conditi [...] adds 869385b11c32 [flang][driver] Add support for `-O{0|1|2|3}` adds 7de277d684fd [llvm-ar] Improve MRI script CREATE command handling adds c06f01ffee86 [mlir][bufferization] Add `memory_space` op attribute adds 5830da1f8625 [AArch64] Define __FP_FAST_FMA[F] adds ba9d886db4fb [mlir][bufferization][NFC] Bufferize with PostOrder traversal adds 0b998053db7c [X86] combineConcatVectorOps - IsConcatFree must check ext [...] adds a83aa33d1bf9 [IR] Move vector.insert/vector.extract out of experimental [...] adds 94fbb147c8ce [STACKMAPS] Document+test UINT64_MAX stack size. adds 480f3e022839 [AMDGPU][GFX9][DOC][NFC] Update assembler syntax description adds 19efb84c7a03 [mlir][shape][bufferize][NFC] Bufferize block terminators [...] adds 4588b6fd2662 Fix clang docs build; NFC adds 8871c3c56269 [AMDGPU] Regenerate MIR checks. NFC. adds 7ebf70d85d63 [mlir][SCF][bufferize][NFC] Bufferize parallel_insert_slic [...] adds 8e691e1f245a [mlir][SCF][bufferize] Bufferize scf.if/execute_region ter [...] adds 3ff93f838ebd [mlir][SCF][bufferize][NFC] Bufferize scf.for terminator s [...] adds 0d0a94a792c0 [mlir][bufferization][NFC] Fix typo in AllocTensorOp builders adds 5d50f51c970f [mlir][bufferization][NFC] Add error handling to getBuffer adds a0f843fdafa7 [SCF] Add thread_dim_mapping attribute to scf.foreach_thread adds b611376e7eb5 [clang][dataflow] Singleton pointer values for null pointers. adds 656b8d6c0193 [flang][NFC] Add array lowering tests adds 92df8c273669 [libc++] Improve Lit's buildhost=XXXX feature on a few platforms adds 633d1d0df766 [libc++] Use bounded iterators in std::span when the debug [...] adds e84674f7acea [gn build] Port 633d1d0df766 adds 97ed2fbc5f64 MIR: Fix parse error on empty CustomRegMask adds cfb4c1a735e9 [IndVars] Add test for PR56242 (NFC) adds 69ae441e4ce7 ARM: don't try to load function pointer before long call. adds bd90155df4a4 [flang][NFC] Add IO lowering tests adds 70a5c525349b [ARM][Thumb] Command-line option to ensure AAPCS compliant [...] adds 1466d65d9bbf [SPARC] Don't do leaf optimization on procedures with inli [...] adds f39c2a114283 [mlir][llvm] Add vector insert/extract intrinsics adds d6bfedd8ba73 [libc++] Remove dummy command in Dockerfile adds ca47ab128bf3 [Clang] Remove unused function declaration after 77475ffd2 [...] adds ac65403a21be [libc++][NFC] Remove trailing whitespace adds f5d781d6273c [X86] Support `_Float16` on SSE2 and up adds 45b995cda461 [mlir][bufferize][NFC] Change signature of allocateTensorF [...] adds 13fb97d68821 tsan: add missing guard for DumpProcessMap call adds c0b0b6a00a2c [mlir][bufferize] Infer memory space in all bufferization [...] adds 771c46ad291c [GlobalOpt] Add tests for memset with non-zero value (NFC) adds 8fa2e67979e5 [mlir][complex] complex.arg op to calculate the angle of c [...] adds f65c88c42fdd [GlobalOpt] Fix memset handling in global ctor evaluation [...] adds f164814f2f18 [mlir][SCF][bufferize] Small simplification and more comments adds 48eb2bc608e2 [flang][driver] Use `-O{0|1|2|3}` to define LLVM backend p [...] adds b4f2d7cde54c [lldb] [llgs] Support "t" vCont action adds 8322fe200d60 Adding support for target in_reduction adds aa89bb3435e0 [Driver][test] Add libclang_rt.profile{{.*}}.a tests for NetBSD adds b5818e4eb439 [AMDGPU] Cluster stores as well as loads for GFX11 adds e7d1cc923ee3 [libc++][doc] Fixes a broken table entry. adds 92d31a7cdffa Silence some format specifier warnings adds 92fd2eb74f5b [Clang][OpenMP] Claim nowait clause on taskwait adds 9878e17624d8 Silence an "illegal conversion" diagnostic adds 6a1e5f5a7111 [llvm-ar] Fix MRI ADDLIB command when used with thin archives adds fe80829289bf [lldb] [llgs] Skip new vCont test on Windows adds 3a1a404ae2d3 [memprof] Return an error for unsupported symbolization. adds 856056d1b0b3 [mlir][LLVMIR] Add support for va_start/copy/end intrinsics adds fc7f7260a609 [mlir][LLVMIR] Memorize compatible LLVM types adds a2c1603206a4 [libc++] Add a few missing min/max macro push/pop adds becbbb7e3c81 Round up zero-sized symbols to 1 byte in `.debug_aranges` [...] adds 9bdb7e573427 [lldb] Add a log dump command adds 62b5aa984e84 llvm-reduce: Check shouldKeep before trying to reduce operands adds 049e107139a3 [NFC][SVE] Add more tests of vector compares and selects t [...] adds c4302e4fc201 [BOLT][NFC] Use llvm::less_first adds 0d477f63b0ea [BOLT][NFC] Add aliases for ICP flags adds 535845708949 [libc][docs] Added fmod performance results. adds c7243f21d3f1 [OpenMP] Only strip runtime attributes if needed adds ee0dd2ec112b [Docs] Update clang & llvm release notes for HLSL adds eb5af0acf054 [Symbolize] Add log markup --filter to llvm-symbolizer. adds 03859994b373 [gn build] Port eb5af0acf054 adds 057e33ef36d0 [mlir][sparse]Add more integration tests for sparse_tensor.unary adds d58b5a06147e [BOLT] Restrict icp-inline to callsites adds 7598a42e2abc [Symbolize] Fix llvm-symbolizer --filter-markup test on Windows. adds d3ff32720dbe [Symbolize] Fix MarkupFilter tests for Windows. adds 15d1cb45204f [mlir][sparse]more integration test cases for sparse_tenso [...] adds aab7e2fa05c0 [MLIR][Parser] Fix AffineParser colliding bare identifiers [...] adds 4db52450c1a4 [mlir][sparse] remove redundant whitespace adds fa34210fa69f [clang][dataflow] Do not allow substitution of true/false [...] adds ae90bc846758 [clang][dataflow] Add `buildAndSubstituteFlowCondition` to [...] adds 6678f8e505b1 [ubsan] Using metadata instead of prologue data for functi [...] adds e2e9e708e5c2 [Coroutine] Remove the '!func_sanitize' metadata for split [...] adds 6e2b3cc6caac Fix sphinx docs build adds ef5510d81b64 [NFC][lldb] Correct Module::FindFunctions documentation adds 11b414463dc2 [test] Add workaround for flaky error we see on Windows bots adds cb471241797b [mlir][bufferize] Improve to_tensor/to_memref folding adds 8f7cca90af6e Revert "[X86] Support `_Float16` on SSE2 and up" adds aadc9d26a361 [RISCV] Cost model for scalable reductions adds 0533b6e2f605 [RISCV] Remove a use of getMinVLen in favor of getRealMinVLen adds 80baa56c467a [libc++][lit][AIX] Port tests for money format to AIX adds 339e824bcae0 [libc++][lit][AIX] Port tests for getting time to AIX adds d2dad6287cb3 Add wait for child processe(s) to exit. (amended+clang-formatted) adds 20dd3297b1c0 [LV] Allow scalable vectorization with vscale = 1 adds 9afa5b8da228 [RISCV] Add tests for (load (add X, [2048,4094])). NFC adds 87077c7eb53c [RISCV] Remove repeated calls to getSExtValue. NFC adds 1bdbf1374620 [Sanitizer][Darwin] atos does not show line numbers for globals adds cdfa15da94f0 Revert "[clang] Introduce -fstrict-flex-arrays=<n> for str [...] adds 62a71cc5ef3f [Sanitizer][Darwin] Mark test UNSUPPORTED instead of XFAIL adds df18167ac56d [docs] Restore missing blank line adds dacfa24f75c3 Delete 'llvm.asan.globals' for global metadata. adds 6824eee94203 [asan] Add missing dependency on Demangle adds c1b07d617705 Have CommandObjectParsed check for "commands that take no [...] adds 85eaecbe8e54 [pseudo] Check follow-sets instead of tying reduce actions [...] adds 6ec465ab8ff2 [libc] add printf oct conversion adds 0103d4da740c [Clang][OpenMP] Don't overload "extension" in status doc adds 53217ecb882c [lld][WebAssembly] Don't apply data relocations at static [...] adds 7b2355277950 Fix-forward ASan on Windows. adds 92bdc5c3e55f [mlir][ods] Add convertFromStorage field to parameters adds ca479dac514d Mark ASan global-location-nodebug test as unspported on win. adds 14d3021c10d0 [lit][test] relaxed GTEST_TOTAL_SHARDS checking for some g [...] adds a630ea3003de Reland [Metadata] Add a resize capability to MDNodes and a [...] adds e06a88cbe9cb [lldb] Use assertState in TestIgnoredExceptions adds efd90ffbfc42 [test] Add -fsanitize=array-bounds test for pseudo flexibl [...] adds 84b2e04aea1f [docs] Remove outdated status update for FreeBSD adds 261075590b2b llvm-reduce: Handle reducing FP values to nan adds 9f94d63a6a7e Add missing (void) for function declarations in C adds ea1b86127814 [RISCV] Fix misleading formatting and remove a dead getNod [...] adds de4a57cb21a1 [libc++] Re-add transitive includes that had been removed [...] adds f1e27716cf21 [LiveInterval] Simplify with partition_point. NFC adds 17a36c7c40e9 [RISCV] Zero extend immediate for vget/vset builtins to ma [...] adds 1919adb19b4a [RISCV] Fix the problem of parsing long version numbers adds 1178992c72b0 [RISCV] Optimize 2x SELECT for floating-point types adds f1dcc6af30d9 [lldb] [test] Mark test_vCont_supports_t llgs-only adds b941857b40ed [LoopInterchange] New cost model for loop interchange adds fa596c692115 [mlir][Vector] Fix reordering of floating point adds durin [...] No new revisions were added by this update. Summary of changes: bolt/lib/Core/BinaryFunctionProfile.cpp | 4 + bolt/lib/Core/DebugData.cpp | 15 +- bolt/lib/Passes/IndirectCallPromotion.cpp | 40 +- bolt/lib/Passes/LongJmp.cpp | 6 +- clang-tools-extra/clangd/CompileCommands.cpp | 2 +- .../pseudo/include/clang-pseudo/grammar/LRTable.h | 70 +- clang-tools-extra/pseudo/lib/GLR.cpp | 25 +- clang-tools-extra/pseudo/lib/grammar/LRTable.cpp | 37 +- .../pseudo/lib/grammar/LRTableBuild.cpp | 71 +- clang-tools-extra/pseudo/test/lr-build-basic.test | 10 +- .../pseudo/test/lr-build-conflicts.test | 18 +- clang-tools-extra/pseudo/unittests/GLRTest.cpp | 98 +- clang-tools-extra/pseudo/unittests/LRTableTest.cpp | 74 +- clang/docs/ClangCommandLineReference.rst | 6 - clang/docs/LanguageExtensions.rst | 1 + clang/docs/OpenMPSupport.rst | 198 +- clang/docs/ReleaseNotes.rst | 9 +- clang/include/clang/AST/Expr.h | 10 - .../FlowSensitive/DataflowAnalysisContext.h | 51 + .../Analysis/FlowSensitive/DataflowEnvironment.h | 14 + clang/include/clang/Basic/LangOptions.def | 1 - clang/include/clang/Basic/riscv_vector.td | 10 +- clang/include/clang/Driver/Options.td | 26 +- .../StaticAnalyzer/Core/PathSensitive/MemRegion.h | 1 - clang/lib/AST/Expr.cpp | 85 - clang/lib/AST/ExprConstant.cpp | 7 - .../FlowSensitive/DataflowAnalysisContext.cpp | 91 + .../Analysis/FlowSensitive/DataflowEnvironment.cpp | 4 + clang/lib/Analysis/FlowSensitive/Transfer.cpp | 10 + clang/lib/Basic/Targets/AArch64.cpp | 4 + clang/lib/CodeGen/BackendUtil.cpp | 1 - clang/lib/CodeGen/CGCall.cpp | 7 +- clang/lib/CodeGen/CGExpr.cpp | 51 +- clang/lib/CodeGen/CGExprScalar.cpp | 8 +- clang/lib/CodeGen/CGOpenMPRuntime.cpp | 3 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 102 +- clang/lib/CodeGen/CodeGenFunction.cpp | 36 +- clang/lib/CodeGen/CodeGenFunction.h | 10 +- clang/lib/CodeGen/CodeGenModule.cpp | 16 + clang/lib/CodeGen/CodeGenModule.h | 5 + clang/lib/CodeGen/SanitizerMetadata.cpp | 46 - clang/lib/CodeGen/SanitizerMetadata.h | 6 - clang/lib/Driver/SanitizerArgs.cpp | 13 + clang/lib/Driver/ToolChains/Arch/ARM.cpp | 9 + clang/lib/Driver/ToolChains/Clang.cpp | 2 - clang/lib/Driver/ToolChains/Flang.cpp | 10 + clang/lib/Sema/SemaChecking.cpp | 54 +- clang/lib/Sema/SemaOpenMP.cpp | 3 +- clang/lib/StaticAnalyzer/Core/MemRegion.cpp | 3 - .../CodeGen/RISCV/rvv-intrinsics-overloaded/vget.c | 120 +- .../RISCV/rvv-intrinsics-overloaded/vlmul.c | 480 +-- .../CodeGen/RISCV/rvv-intrinsics-overloaded/vset.c | 120 +- .../CodeGen/RISCV/rvv-intrinsics/vget-vset-ice.cpp | 4 +- clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c | 533 +-- clang/test/CodeGen/RISCV/rvv-intrinsics/vlmul.c | 540 +-- clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c | 533 +-- ...4-sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.c | 12 +- ...sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp | 10 +- .../aarch64-sve-intrinsics/acle_sve_dupq-bfloat.c | 4 +- .../CodeGen/aarch64-sve-intrinsics/acle_sve_dupq.c | 60 +- clang/test/CodeGen/aarch64-sve-vls-arith-ops.c | 832 ++--- clang/test/CodeGen/aarch64-sve-vls-bitwise-ops.c | 198 +- clang/test/CodeGen/aarch64-sve-vls-compare-ops.c | 432 +-- clang/test/CodeGen/aarch64-sve-vls-shift-ops.c | 224 +- clang/test/CodeGen/aarch64-sve-vls-subscript-ops.c | 18 +- .../acle_neon_sve_bridge_dup_neonq.c | 50 +- .../acle_neon_sve_bridge_get_neonq.c | 48 +- .../acle_neon_sve_bridge_set_neonq.c | 48 +- clang/test/CodeGen/asan-globals.cpp | 76 +- .../CodeGen/attr-arm-sve-vector-bits-bitcast.c | 48 +- clang/test/CodeGen/attr-arm-sve-vector-bits-call.c | 2 +- clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c | 10 +- .../CodeGen/attr-arm-sve-vector-bits-codegen.c | 26 +- .../CodeGen/attr-arm-sve-vector-bits-globals.c | 24 +- clang/test/CodeGen/bounds-checking-fam.c | 34 + clang/test/CodeGen/bounds-checking-fma.c | 42 - clang/test/CodeGen/bounds-checking.c | 5 +- clang/test/CodeGen/hwasan-globals.cpp | 25 +- clang/test/CodeGen/memtag-globals.cpp | 23 - clang/test/CodeGen/object-size-flex-array.c | 106 - clang/test/CodeGen/sanitize-init-order.cpp | 12 - clang/test/CodeGen/ubsan-function.cpp | 5 +- clang/test/CodeGenCXX/catch-undef-behavior.cpp | 37 +- clang/test/CodeGenCXX/ubsan-function-noexcept.cpp | 6 +- clang/test/CodeGenObjC/ubsan-array-bounds.m | 43 + clang/test/Driver/coverage-ld.c | 9 + clang/test/Driver/fsanitize.c | 3 + clang/test/Driver/instrprof-ld.c | 19 + clang/test/OpenMP/target_in_reduction_codegen.cpp | 668 ++++ clang/test/Preprocessor/init-aarch64.c | 14 +- clang/test/Sema/array-bounds-ptr-arith.c | 39 +- .../SemaCXX/array-bounds-strict-flex-arrays.cpp | 19 - .../FlowSensitive/DataflowAnalysisContextTest.cpp | 196 + .../Analysis/FlowSensitive/TransferTest.cpp | 87 + compiler-rt/lib/tsan/rtl/tsan_rtl.cpp | 2 + .../test/asan/TestCases/Posix/coverage-fork.cpp | 5 + .../asan/TestCases/Windows/recalloc_sanity.cpp | 3 + compiler-rt/test/asan/TestCases/debug_locate.cpp | 4 +- .../test/asan/TestCases/describe_address.cpp | 2 +- .../test/asan/TestCases/global-demangle.cpp | 4 +- .../asan/TestCases/global-location-nodebug.cpp | 9 +- .../test/asan/TestCases/global-location.cpp | 6 +- .../sanitizer_common/TestCases/symbolize_stack.cpp | 2 +- flang/include/flang/Frontend/CodeGenOptions.def | 22 + flang/include/flang/Frontend/CodeGenOptions.h | 52 + flang/include/flang/Frontend/CompilerInvocation.h | 7 + flang/include/flang/Frontend/FrontendActions.h | 5 + flang/lib/Frontend/CMakeLists.txt | 1 + flang/lib/Frontend/CodeGenOptions.cpp | 23 + flang/lib/Frontend/CompilerInvocation.cpp | 15 + flang/lib/Frontend/FrontendActions.cpp | 101 +- flang/test/Driver/default-backend-pipelines.f90 | 25 + .../test/Driver/default-optimization-pipelines.f90 | 27 + flang/test/Driver/driver-help.f90 | 2 + flang/test/Driver/flang_f_opts.f90 | 14 + flang/test/Lower/array-derived-assignments.f90 | 104 + flang/test/Lower/array-derived.f90 | 141 + .../Lower/array-elemental-calls-char-byval.f90 | 198 + flang/test/Lower/array-elemental-calls-char.f90 | 267 ++ flang/test/Lower/array-elemental-subroutines.f90 | 64 + flang/test/Lower/array-expression-assumed-size.f90 | 303 ++ flang/test/Lower/array-expression-slice-1.f90 | 413 ++ flang/test/Lower/array-temp.f90 | 413 ++ flang/test/Lower/io-implied-do-fixes.f90 | 49 + flang/test/Lower/io-item-list.f90 | 2 +- flang/test/Lower/io-statement-1.f90 | 23 +- flang/test/Lower/io-statement-big-unit-checks.f90 | 315 ++ flang/test/Lower/io-statement-clean-ups.f90 | 6 +- libc/docs/math.rst | 10 +- libc/src/stdio/printf_core/CMakeLists.txt | 1 + libc/src/stdio/printf_core/converter.cpp | 2 +- libc/src/stdio/printf_core/converter_atlas.h | 1 + libc/src/stdio/printf_core/oct_converter.h | 111 + libc/test/src/stdio/printf_core/converter_test.cpp | 46 +- libc/test/src/stdio/sprintf_test.cpp | 121 + .../caches/Generic-no-transitive-includes.cmake | 2 + libcxx/docs/ReleaseNotes.rst | 22 +- libcxx/docs/Status/RangesIssues.csv | 2 +- libcxx/include/CMakeLists.txt | 1 + libcxx/include/__algorithm/ranges_minmax.h | 5 + libcxx/include/__config | 2 - libcxx/include/__iterator/bounded_iter.h | 229 ++ libcxx/include/__ranges/drop_view.h | 5 + libcxx/include/algorithm | 6 + libcxx/include/any | 4 + libcxx/include/array | 6 + libcxx/include/atomic | 4 + libcxx/include/bit | 4 + libcxx/include/charconv | 4 + libcxx/include/coroutine | 4 + libcxx/include/deque | 6 + libcxx/include/experimental/simd | 5 + libcxx/include/experimental/unordered_map | 8 + libcxx/include/ext/hash_map | 4 + libcxx/include/ext/hash_set | 4 + libcxx/include/forward_list | 6 + libcxx/include/functional | 4 + libcxx/include/future | 4 + libcxx/include/iterator | 8 + libcxx/include/list | 6 + libcxx/include/locale | 4 + libcxx/include/map | 6 + libcxx/include/memory | 5 + libcxx/include/module.modulemap.in | 1 + libcxx/include/mutex | 4 + libcxx/include/numeric | 5 + libcxx/include/optional | 15 + libcxx/include/ostream | 4 + libcxx/include/queue | 4 + libcxx/include/random | 4 + libcxx/include/regex | 5 + libcxx/include/set | 5 + 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.../AMDGPU/GlobalISel/legalize-atomicrmw-umax.mir | 16 +- .../AMDGPU/GlobalISel/legalize-atomicrmw-umin.mir | 16 +- .../GlobalISel/legalize-atomicrmw-xchg-flat.mir | 8 +- .../AMDGPU/GlobalISel/legalize-atomicrmw-xchg.mir | 16 +- .../AMDGPU/GlobalISel/legalize-atomicrmw-xor.mir | 16 +- .../CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir | 220 +- .../AMDGPU/GlobalISel/legalize-bitreverse.mir | 32 +- .../AMDGPU/GlobalISel/legalize-block-addr.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir | 664 ++-- .../CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir | 536 +-- .../GlobalISel/legalize-build-vector-trunc.mir | 4 +- .../AMDGPU/GlobalISel/legalize-build-vector.mir | 124 +- .../GlobalISel/legalize-build-vector.s16.mir | 56 +- .../AMDGPU/GlobalISel/legalize-concat-vectors.mir | 52 +- .../AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir | 40 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir | 40 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir | 56 +- .../AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir | 40 +- .../CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir | 40 +- .../GlobalISel/legalize-extract-vector-elt.mir | 212 +- .../CodeGen/AMDGPU/GlobalISel/legalize-extract.mir | 228 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir | 96 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir | 120 +- .../AMDGPU/GlobalISel/legalize-fcanonicalize.mir | 96 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fceil.mir | 96 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir | 558 +-- .../AMDGPU/GlobalISel/legalize-fconstant.mir | 8 +- .../AMDGPU/GlobalISel/legalize-fcopysign.mir | 1352 +++---- .../CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir | 108 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir | 360 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir | 72 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fexp2.mir | 248 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir | 120 +- .../CodeGen/AMDGPU/GlobalISel/legalize-flog.mir | 132 +- .../CodeGen/AMDGPU/GlobalISel/legalize-flog10.mir | 132 +- .../CodeGen/AMDGPU/GlobalISel/legalize-flog2.mir | 38 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fma.mir | 120 +- .../AMDGPU/GlobalISel/legalize-fmad.s16.mir | 1822 ++++----- .../AMDGPU/GlobalISel/legalize-fmad.s32.mir | 878 +++-- .../AMDGPU/GlobalISel/legalize-fmad.s64.mir | 80 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir | 216 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir | 216 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir | 120 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir | 96 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir | 214 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fpow.mir | 456 +-- .../CodeGen/AMDGPU/GlobalISel/legalize-fpowi.mir | 82 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir | 1066 +++--- .../CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir | 926 ++--- .../CodeGen/AMDGPU/GlobalISel/legalize-fptrunc.mir | 786 ++-- .../CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir | 12 +- .../CodeGen/AMDGPU/GlobalISel/legalize-frint.mir | 250 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir | 108 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir | 108 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir | 108 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir | 96 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir | 132 +- .../CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir | 1136 +++--- .../GlobalISel/legalize-implicit-def-s1025.mir | 848 ++--- .../AMDGPU/GlobalISel/legalize-implicit-def.mir | 4 +- .../GlobalISel/legalize-insert-vector-elt.mir | 56 +- .../CodeGen/AMDGPU/GlobalISel/legalize-insert.mir | 304 +- .../legalize-intrinsic-amdgcn-fdiv-fast.mir | 56 +- .../AMDGPU/GlobalISel/legalize-intrinsic-round.mir | 108 +- .../AMDGPU/GlobalISel/legalize-intrinsic-trunc.mir | 462 ++- .../AMDGPU/GlobalISel/legalize-inttoptr.mir | 48 +- .../legalize-llvm.amdgcn.s.buffer.load.mir | 32 +- .../GlobalISel/legalize-load-constant-32bit.mir | 8 +- .../AMDGPU/GlobalISel/legalize-load-constant.mir | 1368 +++++-- .../AMDGPU/GlobalISel/legalize-load-flat.mir | 1176 ++++-- .../AMDGPU/GlobalISel/legalize-load-global.mir | 3240 ++++++++++++---- .../AMDGPU/GlobalISel/legalize-load-local.mir | 3680 +++++++++++++----- .../GlobalISel/legalize-load-memory-metadata.mir | 16 +- .../AMDGPU/GlobalISel/legalize-load-private.mir | 2232 ++++++++--- .../CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir | 360 +- .../CodeGen/AMDGPU/GlobalISel/legalize-memcpy.mir | 4 +- .../AMDGPU/GlobalISel/legalize-memcpyinline.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/legalize-memmove.mir | 4 +- .../CodeGen/AMDGPU/GlobalISel/legalize-memset.mir | 4 +- .../AMDGPU/GlobalISel/legalize-merge-values.mir | 32 +- .../CodeGen/AMDGPU/GlobalISel/legalize-mul.mir | 176 +- .../test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir | 76 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ptr-add.mir | 76 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ptrmask.mir | 48 +- .../AMDGPU/GlobalISel/legalize-ptrtoint.mir | 48 +- .../AMDGPU/GlobalISel/legalize-rotl-rotr.mir | 533 +-- .../CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir | 16 +- .../CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir | 32 +- .../CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir | 132 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir | 44 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir | 144 +- .../CodeGen/AMDGPU/GlobalISel/legalize-select.mir | 180 +- .../AMDGPU/GlobalISel/legalize-sext-inreg.mir | 336 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sext.mir | 132 +- .../legalize-sextload-constant-32bit.mir | 24 +- .../AMDGPU/GlobalISel/legalize-sextload-flat.mir | 48 +- .../AMDGPU/GlobalISel/legalize-sextload-global.mir | 152 +- .../AMDGPU/GlobalISel/legalize-sextload-local.mir | 24 +- .../GlobalISel/legalize-sextload-private.mir | 24 +- .../CodeGen/AMDGPU/GlobalISel/legalize-shl.mir | 372 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sitofp.mir | 764 ++-- .../CodeGen/AMDGPU/GlobalISel/legalize-smax.mir | 120 +- .../CodeGen/AMDGPU/GlobalISel/legalize-smin.mir | 120 +- .../CodeGen/AMDGPU/GlobalISel/legalize-smulh.mir | 584 +-- .../CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir | 698 ++-- .../CodeGen/AMDGPU/GlobalISel/legalize-srem.mir | 144 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir | 132 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir | 16 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir | 32 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir | 132 +- .../AMDGPU/GlobalISel/legalize-store-global.mir | 1904 +++++++--- .../CodeGen/AMDGPU/GlobalISel/legalize-store.mir | 272 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sub.mir | 120 +- .../CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir | 80 +- .../CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir | 16 +- .../CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir | 32 +- .../CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir | 132 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir | 64 +- .../CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir | 144 +- .../CodeGen/AMDGPU/GlobalISel/legalize-uitofp.mir | 666 ++-- .../CodeGen/AMDGPU/GlobalISel/legalize-umax.mir | 120 +- .../CodeGen/AMDGPU/GlobalISel/legalize-umin.mir | 120 +- .../CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir | 80 +- .../CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir | 80 +- .../AMDGPU/GlobalISel/legalize-unmerge-values.mir | 124 +- .../CodeGen/AMDGPU/GlobalISel/legalize-urem.mir | 144 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir | 132 +- .../CodeGen/AMDGPU/GlobalISel/legalize-usube.mir | 16 +- .../CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir | 32 +- .../CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir | 132 +- .../GlobalISel/legalize-vector-args-gfx7.mir | 20 +- .../GlobalISel/legalize-vector-args-gfx8-plus.mir | 40 +- .../CodeGen/AMDGPU/GlobalISel/legalize-xor.mir | 76 +- .../CodeGen/AMDGPU/GlobalISel/legalize-zext.mir | 132 +- .../legalize-zextload-constant-32bit.mir | 24 +- .../AMDGPU/GlobalISel/legalize-zextload-flat.mir | 48 +- .../AMDGPU/GlobalISel/legalize-zextload-global.mir | 152 +- .../AMDGPU/GlobalISel/legalize-zextload-local.mir | 24 +- .../GlobalISel/legalize-zextload-private.mir | 24 +- .../AMDGPU/GlobalISel/llvm.amdgcn.softwqm.ll | 70 +- .../CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.ll | 70 +- .../CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wwm.ll | 140 +- .../GlobalISel/postlegalizer-combiner-divrem.mir | 148 +- .../GlobalISel/postlegalizercombiner-and.mir | 143 +- .../GlobalISel/prelegalizer-combiner-divrem.mir | 344 +- .../regbankcombiner-clamp-minmax-const.mir | 4 +- .../AMDGPU/GlobalISel/regbankcombiner-smed3.mir | 62 +- .../AMDGPU/GlobalISel/regbankcombiner-umed3.mir | 62 +- .../AMDGPU/GlobalISel/regbankselect-add.s16.mir | 66 +- .../AMDGPU/GlobalISel/regbankselect-add.s32.mir | 36 +- .../AMDGPU/GlobalISel/regbankselect-add.v2s16.mir | 58 +- .../GlobalISel/regbankselect-amdgcn-exp-compr.mir | 20 +- .../AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir | 32 +- .../GlobalISel/regbankselect-amdgcn.ballot.i64.mir | 33 +- .../GlobalISel/regbankselect-amdgcn.class.mir | 40 +- .../GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir | 40 +- .../GlobalISel/regbankselect-amdgcn.div.fmas.mir | 90 +- .../GlobalISel/regbankselect-amdgcn.div.scale.mir | 40 +- .../GlobalISel/regbankselect-amdgcn.ds.append.mir | 12 +- .../regbankselect-amdgcn.ds.bpermute.mir | 11 +- .../GlobalISel/regbankselect-amdgcn.ds.consume.mir | 12 +- .../regbankselect-amdgcn.ds.gws.init.mir | 36 +- .../regbankselect-amdgcn.ds.gws.sema.v.mir | 12 +- .../regbankselect-amdgcn.ds.ordered.add.mir | 40 +- .../regbankselect-amdgcn.ds.ordered.swap.mir | 40 +- .../GlobalISel/regbankselect-amdgcn.ds.permute.mir | 11 +- .../GlobalISel/regbankselect-amdgcn.ds.swizzle.mir | 7 +- .../GlobalISel/regbankselect-amdgcn.else.32.mir | 6 +- .../GlobalISel/regbankselect-amdgcn.else.64.mir | 6 +- .../GlobalISel/regbankselect-amdgcn.fcmp.mir | 40 +- .../regbankselect-amdgcn.fmul.legacy.mir | 40 +- .../GlobalISel/regbankselect-amdgcn.icmp.mir | 40 +- .../GlobalISel/regbankselect-amdgcn.interp.mov.mir | 16 +- .../regbankselect-amdgcn.interp.p1.f16.mir | 20 +- .../GlobalISel/regbankselect-amdgcn.interp.p1.mir | 36 +- .../regbankselect-amdgcn.interp.p2.f16.mir | 28 +- .../GlobalISel/regbankselect-amdgcn.interp.p2.mir | 28 +- .../GlobalISel/regbankselect-amdgcn.kill.mir | 32 +- .../regbankselect-amdgcn.lds.direct.load.mir | 12 +- .../regbankselect-amdgcn.lds.param.load.mir | 12 +- .../GlobalISel/regbankselect-amdgcn.live.mask.mir | 2 +- .../GlobalISel/regbankselect-amdgcn.mfma.mir | 560 +-- .../GlobalISel/regbankselect-amdgcn.ps.live.mir | 2 +- .../regbankselect-amdgcn.readfirstlane.mir | 14 +- .../GlobalISel/regbankselect-amdgcn.readlane.mir | 92 +- .../GlobalISel/regbankselect-amdgcn.s.sendmsg.mir | 14 +- .../regbankselect-amdgcn.s.sendmsghalt.mir | 14 +- .../GlobalISel/regbankselect-amdgcn.wqm.demote.mir | 32 +- .../AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir | 14 +- .../GlobalISel/regbankselect-amdgcn.wqm.vote.mir | 34 +- .../GlobalISel/regbankselect-amdgcn.writelane.mir | 60 +- .../AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir | 14 +- .../GlobalISel/regbankselect-amdgpu-ffbh-u32.mir | 12 +- .../GlobalISel/regbankselect-amdgpu-ffbl-b32.mir | 12 +- .../AMDGPU/GlobalISel/regbankselect-and-s1.mir | 188 +- .../AMDGPU/GlobalISel/regbankselect-and.mir | 448 ++- .../AMDGPU/GlobalISel/regbankselect-anyext.mir | 152 +- .../AMDGPU/GlobalISel/regbankselect-ashr.mir | 174 +- .../GlobalISel/regbankselect-atomic-cmpxchg.mir | 48 +- .../GlobalISel/regbankselect-atomicrmw-add.mir | 36 +- .../GlobalISel/regbankselect-atomicrmw-and.mir | 36 +- .../GlobalISel/regbankselect-atomicrmw-fadd.mir | 12 +- .../GlobalISel/regbankselect-atomicrmw-max.mir | 36 +- .../GlobalISel/regbankselect-atomicrmw-min.mir | 36 +- .../GlobalISel/regbankselect-atomicrmw-or.mir | 36 +- .../GlobalISel/regbankselect-atomicrmw-sub.mir | 36 +- .../GlobalISel/regbankselect-atomicrmw-umax.mir | 36 +- .../GlobalISel/regbankselect-atomicrmw-umin.mir | 36 +- .../GlobalISel/regbankselect-atomicrmw-xchg.mir | 36 +- .../GlobalISel/regbankselect-atomicrmw-xor.mir | 36 +- .../AMDGPU/GlobalISel/regbankselect-bitcast.mir | 12 +- .../AMDGPU/GlobalISel/regbankselect-bitreverse.mir | 30 +- .../AMDGPU/GlobalISel/regbankselect-block-addr.mir | 2 +- .../AMDGPU/GlobalISel/regbankselect-brcond.mir | 129 +- .../AMDGPU/GlobalISel/regbankselect-bswap.mir | 14 +- .../regbankselect-build-vector-trunc.mir | 62 +- .../regbankselect-build-vector-trunc.v2s16.mir | 62 +- .../GlobalISel/regbankselect-build-vector.mir | 175 +- .../GlobalISel/regbankselect-concat-vector.mir | 98 +- .../AMDGPU/GlobalISel/regbankselect-constant.mir | 12 +- .../AMDGPU/GlobalISel/regbankselect-copy.mir | 82 +- .../GlobalISel/regbankselect-ctlz-zero-undef.mir | 42 +- .../AMDGPU/GlobalISel/regbankselect-ctpop.mir | 38 +- .../GlobalISel/regbankselect-cttz-zero-undef.mir | 42 +- .../AMDGPU/GlobalISel/regbankselect-default.mir | 2 +- .../GlobalISel/regbankselect-dyn-stackalloc.mir | 360 +- .../regbankselect-extract-vector-elt.mir | 1948 +++++----- .../AMDGPU/GlobalISel/regbankselect-extract.mir | 32 +- .../AMDGPU/GlobalISel/regbankselect-fabs.mir | 16 +- .../AMDGPU/GlobalISel/regbankselect-fadd.mir | 40 +- .../GlobalISel/regbankselect-fcanonicalize.mir | 18 +- .../AMDGPU/GlobalISel/regbankselect-fceil.mir | 14 +- .../AMDGPU/GlobalISel/regbankselect-fcmp.mir | 36 +- .../AMDGPU/GlobalISel/regbankselect-fexp2.mir | 14 +- .../AMDGPU/GlobalISel/regbankselect-flog2.mir | 14 +- .../AMDGPU/GlobalISel/regbankselect-fma.mir | 104 +- .../AMDGPU/GlobalISel/regbankselect-fmul.mir | 40 +- .../AMDGPU/GlobalISel/regbankselect-fneg.mir | 16 +- .../AMDGPU/GlobalISel/regbankselect-fpext.mir | 14 +- .../AMDGPU/GlobalISel/regbankselect-fptosi.mir | 14 +- .../AMDGPU/GlobalISel/regbankselect-fptoui.mir | 14 +- .../AMDGPU/GlobalISel/regbankselect-fptrunc.mir | 14 +- .../AMDGPU/GlobalISel/regbankselect-freeze.mir | 280 +- .../AMDGPU/GlobalISel/regbankselect-frint.mir | 14 +- .../AMDGPU/GlobalISel/regbankselect-fshr.mir | 104 +- .../AMDGPU/GlobalISel/regbankselect-fsqrt.mir | 18 +- .../AMDGPU/GlobalISel/regbankselect-fsub.mir | 40 +- .../AMDGPU/GlobalISel/regbankselect-icmp.mir | 364 +- .../AMDGPU/GlobalISel/regbankselect-icmp.s16.mir | 56 +- .../GlobalISel/regbankselect-insert-vector-elt.mir | 938 ++--- .../AMDGPU/GlobalISel/regbankselect-insert.mir | 96 +- .../GlobalISel/regbankselect-intrinsic-trunc.mir | 14 +- .../AMDGPU/GlobalISel/regbankselect-inttoptr.mir | 12 +- .../AMDGPU/GlobalISel/regbankselect-load.mir | 152 +- .../AMDGPU/GlobalISel/regbankselect-lshr.mir | 178 +- .../AMDGPU/GlobalISel/regbankselect-mad_64_32.mir | 104 +- .../GlobalISel/regbankselect-merge-values.mir | 62 +- .../AMDGPU/GlobalISel/regbankselect-mul.mir | 36 +- .../CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir | 576 +-- .../AMDGPU/GlobalISel/regbankselect-phi-s1.mir | 2036 +++++----- .../AMDGPU/GlobalISel/regbankselect-phi.mir | 3328 +++++++++-------- .../AMDGPU/GlobalISel/regbankselect-ptr-add.mir | 44 +- .../AMDGPU/GlobalISel/regbankselect-ptrmask.mir | 44 +- .../AMDGPU/GlobalISel/regbankselect-ptrtoint.mir | 12 +- .../GlobalISel/regbankselect-reg-sequence.mir | 40 +- .../AMDGPU/GlobalISel/regbankselect-sadde.mir | 176 +- .../AMDGPU/GlobalISel/regbankselect-sbfx.mir | 266 +- .../AMDGPU/GlobalISel/regbankselect-select.mir | 2016 +++++----- .../AMDGPU/GlobalISel/regbankselect-sext-inreg.mir | 138 +- .../AMDGPU/GlobalISel/regbankselect-sext.mir | 178 +- .../AMDGPU/GlobalISel/regbankselect-sextload.mir | 48 +- .../AMDGPU/GlobalISel/regbankselect-shl.mir | 170 +- .../GlobalISel/regbankselect-shuffle-vector.mir | 36 +- .../AMDGPU/GlobalISel/regbankselect-sitofp.mir | 14 +- .../AMDGPU/GlobalISel/regbankselect-smax.mir | 158 +- .../AMDGPU/GlobalISel/regbankselect-smin.mir | 162 +- .../AMDGPU/GlobalISel/regbankselect-smulh.mir | 76 +- .../regbankselect-split-scalar-load-metadata.mir | 8 +- .../AMDGPU/GlobalISel/regbankselect-ssube.mir | 176 +- .../AMDGPU/GlobalISel/regbankselect-sub.mir | 36 +- .../AMDGPU/GlobalISel/regbankselect-trunc.mir | 36 +- .../AMDGPU/GlobalISel/regbankselect-uadde.mir | 176 +- .../AMDGPU/GlobalISel/regbankselect-uaddo.mir | 38 +- .../AMDGPU/GlobalISel/regbankselect-ubfx.mir | 264 +- .../AMDGPU/GlobalISel/regbankselect-uitofp.mir | 14 +- .../AMDGPU/GlobalISel/regbankselect-umax.mir | 166 +- .../AMDGPU/GlobalISel/regbankselect-umin.mir | 166 +- .../AMDGPU/GlobalISel/regbankselect-umulh.mir | 76 +- .../regbankselect-uniform-load-noclobber.mir | 172 +- .../GlobalISel/regbankselect-unmerge-values.mir | 30 +- .../AMDGPU/GlobalISel/regbankselect-usube.mir | 176 +- .../AMDGPU/GlobalISel/regbankselect-usubo.mir | 38 +- .../regbankselect-widen-scalar-loads.mir | 558 +-- .../AMDGPU/GlobalISel/regbankselect-xor.mir | 594 +-- .../AMDGPU/GlobalISel/regbankselect-zext.mir | 172 +- .../AMDGPU/GlobalISel/regbankselect-zextload.mir | 48 +- .../CodeGen/AMDGPU/GlobalISel/regbankselect.mir | 66 +- llvm/test/CodeGen/AMDGPU/agpr-copy-propagation.mir | 32 +- llvm/test/CodeGen/AMDGPU/bundle-latency.mir | 20 +- llvm/test/CodeGen/AMDGPU/call-waw-waitcnt.mir | 29 +- llvm/test/CodeGen/AMDGPU/change-scc-to-vcc.mir | 52 +- llvm/test/CodeGen/AMDGPU/cluster_stores.ll | 119 + .../coalesce-identity-copies-undef-subregs.mir | 313 +- .../CodeGen/AMDGPU/coalescer-remat-dead-use.mir | 44 +- ...alescer-removepartial-extend-undef-subrange.mir | 57 +- .../AMDGPU/coalescer-subranges-prune-kill-copy.mir | 24 +- .../coalescing-subreg-was-undef-but-became-def.mir | 22 +- .../AMDGPU/coalescing_makes_lanes_undef.mir | 32 +- llvm/test/CodeGen/AMDGPU/collapse-endcf-broken.mir | 32 +- llvm/test/CodeGen/AMDGPU/collapse-endcf2.mir | 98 +- llvm/test/CodeGen/AMDGPU/commute-vop3.mir | 46 +- .../test/CodeGen/AMDGPU/copy-overlap-vgpr-kill.mir | 46 +- llvm/test/CodeGen/AMDGPU/copy_phys_vgpr64.mir | 476 ++- .../CodeGen/AMDGPU/couldnt-join-subrange-3.mir | 93 +- .../CodeGen/AMDGPU/early-tailduplicator-nophis.mir | 33 +- .../AMDGPU/extend-phi-subrange-not-in-parent.mir | 64 +- .../CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll | 30 +- llvm/test/CodeGen/AMDGPU/fast-ra-kills-vcc.mir | 24 +- llvm/test/CodeGen/AMDGPU/fast-regalloc-bundles.mir | 10 +- .../AMDGPU/fastregalloc-illegal-subreg-physreg.mir | 7 +- .../AMDGPU/fastregalloc-self-loop-heuristic.mir | 138 +- llvm/test/CodeGen/AMDGPU/flat-scratch-fold-fi.mir | 18 +- llvm/test/CodeGen/AMDGPU/fold-cndmask-wave32.mir | 5 +- llvm/test/CodeGen/AMDGPU/fold-fi-mubuf.mir | 86 +- .../test/CodeGen/AMDGPU/fold-fi-operand-shrink.mir | 70 +- .../fold-immediate-operand-shrink-with-carry.mir | 42 +- .../AMDGPU/fold-immediate-operand-shrink.mir | 325 +- .../AMDGPU/fold-operands-remove-m0-redef.mir | 197 +- llvm/test/CodeGen/AMDGPU/fold_16bit_imm.mir | 20 +- .../AMDGPU/greedy-alloc-fail-sgpr1024-spill.mir | 196 +- .../CodeGen/AMDGPU/greedy-global-heuristic.mir | 214 +- llvm/test/CodeGen/AMDGPU/gws-hazards.mir | 92 +- .../AMDGPU/hazard-recognizer-meta-insts.mir | 20 +- llvm/test/CodeGen/AMDGPU/i1-copies-rpo.mir | 38 +- .../AMDGPU/i1_copy_phi_with_phi_incoming_value.mir | 118 +- .../CodeGen/AMDGPU/indirect-addressing-term.ll | 188 +- .../CodeGen/AMDGPU/insert-skips-flat-vmem-ds.mir | 60 +- llvm/test/CodeGen/AMDGPU/insert-skips-gws.mir | 40 +- llvm/test/CodeGen/AMDGPU/licm-regpressure.mir | 132 +- llvm/test/CodeGen/AMDGPU/loop_header_nopred.mir | 58 +- .../lower-control-flow-other-terminators.mir | 215 +- ...er-i1-copies-implicit-def-unstructured-loop.mir | 162 +- llvm/test/CodeGen/AMDGPU/lower-term-opcodes.mir | 90 +- .../AMDGPU/machine-cse-commute-target-flags.mir | 37 +- .../test/CodeGen/AMDGPU/move-load-addr-to-valu.mir | 420 ++- ...optimize-exec-copies-extra-insts-after-copy.mir | 35 +- .../AMDGPU/optimize-exec-masking-pre-ra.mir | 106 +- ...optimize-exec-masking-strip-terminator-bits.mir | 31 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2 years, 5 months

[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_llvm_sq/llvm-master-aarch64-cpu2017-Os updated (dbb0f06cc0 -> cfdc4df66c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_sq/llvm-master-aarch64-cpu2017-Os in repository toolchain/ci/glibc. from dbb0f06cc0 Makerules: Remove no-op -Wl,-d when linking libc_pic.os adds 227afaa672 x86: Align entry for memrchr to 64-bytes. adds afc6e4328f x86: Put wcs{n}len-sse4.1 in the sse4.1 text section adds d1e931125b x86: Remove unused file wmemcmp-sse4 adds d912127bde x86: Rename strstr_sse2 to strstr_generic as it uses string/ [...] adds 4fc321dc58 x86: Fix backwards Prefer_No_VZEROUPPER check in ifunc-evex.h adds f56c497d2b x86: Move CPU_FEATURE{S}_{USABLE|ARCH}_P to isa-level.h adds cfdc4df66c x86-64: Only define used SSE/AVX/AVX512 run-time resolvers No new revisions were added by this update. Summary of changes: sysdeps/x86/isa-ifunc-macros.h | 11 ----- sysdeps/x86/isa-level.h | 54 ++++++++++++++-------- sysdeps/x86_64/dl-machine.h | 12 +++-- sysdeps/x86_64/dl-trampoline.S | 59 +++++++++++++----------- sysdeps/x86_64/multiarch/ifunc-evex.h | 4 +- sysdeps/x86_64/multiarch/ifunc-impl-list.c | 2 +- sysdeps/x86_64/multiarch/memrchr-avx2.S | 2 +- sysdeps/x86_64/multiarch/strlen-vec.S | 6 ++- sysdeps/x86_64/multiarch/strstr-sse2-unaligned.S | 2 +- sysdeps/x86_64/multiarch/strstr.c | 8 ++-- sysdeps/x86_64/multiarch/wcslen-sse4_1.S | 1 + sysdeps/x86_64/multiarch/wcsnlen-sse4_1.S | 1 + sysdeps/x86_64/multiarch/wmemcmp-sse4.S | 4 -- 13 files changed, 92 insertions(+), 74 deletions(-) delete mode 100644 sysdeps/x86_64/multiarch/wmemcmp-sse4.S -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 5 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_llvm_sq/llvm-master-aarch64-cpu2017-Os updated (153689603fd -> f9764ea128c)

by git＠git.linaro.org

2 years, 5 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk_llvm_sq/llvm-master-aarch64-cpu2017-Os updated (4f6c04da69 -> f40bb390bb)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_sq/llvm-master-aarch64-cpu2017-Os in repository toolchain/ci/binutils-gdb. from 4f6c04da69 bfd: prune config.bfd's setting of targ_archs adds ed1c7ad8e3 Disable execstack and rwx segments warnings for MIPS targets. adds a08bdb159b [gdb/build] Fix gdbserver build with -fsanitize=thread adds 65067f1c2c [gdb/symtab] Fix parsing of .debug_str_offsets header adds 2043638bf9 [gdb/testsuite] Skip gdb.fortran/namelist.exp for gfortran 4.8 adds cdcec216b4 [gdb/testsuite] Workaround unnecessary .s file with gfortran 4.8 adds 7d476bd555 [gdb/testsuite] Enable some test-cases for x86_64 -m32 adds 772f8196d6 [gdb/testsuite] Fix gdb.reverse/i387-env-reverse.exp for -pie adds 2135495484 [gdb/testsuite] Handle older python in gdb.python/py-send-packet.py adds a3f1431a50 Stop bogus warnings about DWARF indexed string offsets being [...] adds 8c9ae6df3c gdb/arm: Unwind Non-Secure callbacks from Secure adds 2a4fc266db Have gold's File_read::do_read() function check the start parameter adds e98e7d9a70 Fix NULL pointer indirection when parsing corrupt DWARF data. adds e3e5ae0493 Replace a run-time assertion failure with a warning message [...] adds 171fba11ab Make GDBserver abort on internal error in development mode adds 95127faf50 [gdb/build] Fix build breaker with --enable-shared adds e1692475fd gdb/testsuite: update bug numbers from Gnats to bugzilla adds f0cb8284cf Automatic date update in version.in adds 8bddb52eb9 Re: Disable execstack and rwx segments warnings for MIPS targets. adds 39590abd65 RISC-V: Add new CSR feature gate handling (RV32,H) adds 6af47b081e RISC-V: Add 'Smstateen' extension and its CSRs adds 713f370809 RISC-V: Add 'Sscofpmf' extension with its CSRs adds 766077c173 RISC-V: Add 'Sstc' extension and its CSRs adds 7c24bdc583 PR29293, elfnn-aarch64.c: def_protected member unintialized adds e3940312c1 gdb:csky add pseudo regs for float and vector regs adds 04cb922ade PowerPC64: Tidy stub type changes adds 0f0d9373a3 PowerPC64: plt_stub_pad adds f40bb390bb PowerPC64: align plt_branch stubs No new revisions were added by this update. Summary of changes: bfd/elf64-ppc.c | 111 +++++----- bfd/elfnn-aarch64.c | 1 + bfd/elfxx-riscv.c | 3 + bfd/version.h | 2 +- binutils/ChangeLog | 19 ++ binutils/dwarf.c | 107 +++------- binutils/testsuite/binutils-all/pr26112.r | 6 +- configure | 10 +- configure.ac | 10 +- gas/config/tc-riscv.c | 47 +++- gas/testsuite/gas/riscv/csr-dw-regnums.d | 54 +++++ gas/testsuite/gas/riscv/csr-dw-regnums.s | 57 +++++ gas/testsuite/gas/riscv/csr-version-1p10.d | 108 ++++++++++ gas/testsuite/gas/riscv/csr-version-1p10.l | 207 ++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p11.d | 108 ++++++++++ gas/testsuite/gas/riscv/csr-version-1p11.l | 207 ++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p12.d | 108 ++++++++++ gas/testsuite/gas/riscv/csr-version-1p12.l | 207 ++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p9p1.d | 108 ++++++++++ gas/testsuite/gas/riscv/csr-version-1p9p1.l | 207 ++++++++++++++++++ gas/testsuite/gas/riscv/csr.s | 60 ++++++ gdb/arm-tdep.c | 114 +++++++--- gdb/csky-tdep.c | 261 +++++++++++++++++++++++ gdb/csky-tdep.h | 7 + gdb/dwarf2/read.c | 64 +++++- gdb/testsuite/gdb.base/annota1.exp | 8 +- gdb/testsuite/gdb.base/macscp.exp | 14 +- gdb/testsuite/gdb.fortran/namelist.exp | 6 +- gdb/testsuite/gdb.python/py-send-packet.py | 8 +- gdb/testsuite/gdb.reverse/i386-precsave.exp | 2 +- gdb/testsuite/gdb.reverse/i386-reverse.exp | 2 +- gdb/testsuite/gdb.reverse/i387-env-reverse.exp | 121 +++++------ gdb/testsuite/gdb.reverse/i387-stack-reverse.exp | 214 +++++++++---------- gdb/testsuite/lib/gdb.exp | 16 +- gdbserver/utils.cc | 20 +- gdbsupport/config.in | 3 + gdbsupport/configure | 13 ++ gdbsupport/configure.ac | 10 + gold/ChangeLog | 6 + gold/fileread.cc | 6 + include/opcode/riscv-opc.h | 114 ++++++++++ ld/ChangeLog | 8 + ld/configure | 14 +- ld/configure.ac | 14 +- ld/configure.tgt | 41 +++- ld/testsuite/ld-elf/elf.exp | 4 +- ld/testsuite/ld-powerpc/elfv2exe.d | 11 +- ld/testsuite/ld-powerpc/notoc.d | 49 +++-- ld/testsuite/ld-powerpc/notoc.wf | 12 +- ld/testsuite/ld-powerpc/notoc3.d | 15 +- ld/testsuite/ld-powerpc/pr23937.d | 4 +- 51 files changed, 2472 insertions(+), 456 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_llvm_sq/llvm-master-aarch64-cpu2017-Os updated (947f84ef -> a309b620)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_sq/llvm-master-aarch64-cpu2017-Os in repository toolchain/ci/base-artifacts. discards 947f84ef 0: update: binutils-gcc-linux-glibc-llvm: 1 new a309b620 0: update: binutils-gcc-linux-glibc-llvm: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (947f84ef) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk_llvm_sq/llvm-master- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1608 -> 1864 bytes 02-prepare_abe/console.log.xz | Bin 2720 -> 2736 bytes 03-build_abe-binutils/console.log.xz | Bin 31272 -> 31432 bytes 04-build_abe-stage1/console.log.xz | Bin 74980 -> 74808 bytes 05-clean_sysroot/console.log.xz | Bin 332 -> 332 bytes 06-build_abe-linux/console.log.xz | Bin 9220 -> 9152 bytes 07-build_abe-glibc/console.log.xz | Bin 240752 -> 240820 bytes 08-build_abe-stage2/console.log.xz | Bin 182448 -> 181804 bytes 09-build_llvm-true/console.log.xz | Bin 62104 -> 62280 bytes 10-benchmark/benchmark-build.log | 76 +- 10-benchmark/benchmark.log | 74 +- 10-benchmark/console.log.xz | Bin 3716 -> 3712 bytes 11-check_regression/console.log.xz | Bin 4124 -> 4124 bytes 11-check_regression/csv-results-0/md5sum.csv | 74450 +++--- 11-check_regression/csv-results-0/perf.csv | 1533 +- 11-check_regression/csv-results-0/results.csv | 8856 +- 11-check_regression/csv-results-0/size.csv | 279565 ++++++++++++----------- 11-check_regression/csv-results-0/vect.csv | 20 +- 11-check_regression/csv-results-1/md5sum.csv | 74450 +++--- 11-check_regression/csv-results-1/perf.csv | 1537 +- 11-check_regression/csv-results-1/results.csv | 3879 +- 11-check_regression/csv-results-1/size.csv | 279186 +++++++++++----------- 11-check_regression/csv-results-1/vect.csv | 20 +- 11-check_regression/results-brief.csv | 26 +- 11-check_regression/results-full.csv | 1621 +- 11-check_regression/results-internal.csv | 98 +- 11-check_regression/results.log | 1666 +- 12-update_baseline/console.log | 3570 +- 12-update_baseline/csv-results-0/md5sum.csv | 74450 +++--- 12-update_baseline/csv-results-0/perf.csv | 1533 +- 12-update_baseline/csv-results-0/results.csv | 8856 +- 12-update_baseline/csv-results-0/size.csv | 279565 ++++++++++++----------- 12-update_baseline/csv-results-0/vect.csv | 20 +- 12-update_baseline/csv-results-1/md5sum.csv | 74450 +++--- 12-update_baseline/csv-results-1/perf.csv | 1537 +- 12-update_baseline/csv-results-1/results.csv | 3879 +- 12-update_baseline/csv-results-1/size.csv | 279186 +++++++++++----------- 12-update_baseline/csv-results-1/vect.csv | 20 +- 12-update_baseline/results-brief.csv | 26 +- 12-update_baseline/results-full.csv | 1621 +- 12-update_baseline/results-internal.csv | 98 +- 12-update_baseline/results.log | 1662 +- jenkins/manifest.sh | 22 +- results | 2 +- results_id | 2 +- 45 files changed, 728775 insertions(+), 728781 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 5 months

[gcc] branch master updated (835b19936bf -> 133d0d422eb)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 835b19936bf libstdc++: Do not optimize away storing pathname if it's needed new 198781144f3 libstdc++: Improve directory iterator abstractions for openat new 07f49e855b5 Use mark_block_for_update properly in insert_updated_phi_nodes_for new 8354d0abeb7 Speedup loop splitting SSA update new 133d0d422eb fortran, libgfortran: Avoid using libquadmath for glibc 2.26+ The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/fortran/gfortran.h | 3 + gcc/fortran/trans-intrinsic.cc | 15 +- gcc/fortran/trans-types.cc | 12 + gcc/fortran/trans-types.h | 4 + gcc/tree-into-ssa.cc | 16 +- gcc/tree-ssa-loop-split.cc | 5 +- libgfortran/Makefile.am | 4 +- libgfortran/Makefile.in | 5 +- libgfortran/acinclude.m4 | 68 +- libgfortran/caf/single.c | 7 +- libgfortran/config.h.in | 197 +- libgfortran/configure | 3403 ++++++++++++++++++++++++++++-- libgfortran/configure.ac | 83 +- libgfortran/generated/bessel_r16.c | 4 + libgfortran/generated/bessel_r17.c | 2 + libgfortran/generated/norm2_r16.c | 4 + libgfortran/generated/norm2_r17.c | 2 + libgfortran/ieee/issignaling_fallback.h | 8 +- libgfortran/intrinsics/cshift0.c | 4 +- libgfortran/intrinsics/erfc_scaled.c | 25 +- libgfortran/intrinsics/pack_generic.c | 4 +- libgfortran/intrinsics/spread_generic.c | 8 +- libgfortran/intrinsics/trigd.c | 18 + libgfortran/intrinsics/unpack_generic.c | 8 +- libgfortran/io/read.c | 13 + libgfortran/io/transfer128.c | 4 +- libgfortran/io/write_float.def | 54 +- libgfortran/kinds-override.h | 14 +- libgfortran/libgfortran.h | 8 +- libgfortran/m4/mtype.m4 | 6 + libgfortran/mk-kinds-h.sh | 18 +- libgfortran/runtime/in_pack_generic.c | 4 +- libgfortran/runtime/in_unpack_generic.c | 4 +- libstdc++-v3/src/c++17/fs_dir.cc | 29 +- libstdc++-v3/src/filesystem/dir-common.h | 66 +- libstdc++-v3/src/filesystem/dir.cc | 21 +- 36 files changed, 3810 insertions(+), 340 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 5 months

[gcc] branch releases/gcc-12 updated (81c832f9d55 -> 8e230a3c026)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch releases/gcc-12 in repository gcc. from 81c832f9d55 libgomp: fix typo in mold linker detection new 8e230a3c026 loongarch: exclude LARCH_PROLOGUE_TEMP from SIBCALL_REGS [P [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/loongarch/loongarch.cc | 2 +- gcc/config/loongarch/loongarch.h | 2 +- .../{nios2/nios2.exp => loongarch/loongarch.exp} | 4 +- gcc/testsuite/g++.target/loongarch/pr106096.C | 75 ++++++++++++++++++++++ 4 files changed, 79 insertions(+), 4 deletions(-) copy gcc/testsuite/g++.target/{nios2/nios2.exp => loongarch/loongarch.exp} (91%) create mode 100644 gcc/testsuite/g++.target/loongarch/pr106096.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 5 months

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