Tcwg-commits June 2022

tcwg-commits@lists.linaro.org

4 participants
14714 discussions

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/release-aarch64-bootstrap_ubsan updated (07bc6edb1 -> 3c6a54b7c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/release-aarch64-bootstrap_ubsan in repository toolchain/ci/base-artifacts. discards 07bc6edb1 0: update: binutils-gcc: 2 new 3c6a54b7c 0: update: binutils-gcc: 2 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (07bc6edb1) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_bootstrap/release-aa [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1568 -> 1556 bytes 02-prepare_abe/console.log.xz | Bin 2748 -> 2732 bytes 04-build_abe-binutils/console.log.xz | Bin 39280 -> 39236 bytes 05-build_abe-bootstrap_ubsan/console.log.xz | Bin 309648 -> 312388 bytes 06-check_regression/console.log.xz | Bin 416 -> 416 bytes 07-update_baseline/console.log | 16 ++++++++-------- jenkins/manifest.sh | 14 +++++++------- 7 files changed, 15 insertions(+), 15 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-arm updated (6d940eff47 -> 028f2361d0)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-arm in repository toolchain/ci/qemu. from 6d940eff47 Merge tag 'pull-tpm-2022-06-07-1' of https://github.com/stef [...] adds ec6600be0d vfio/common: remove spurious warning on vfio_listener_region_del adds 05911658cb Merge tag 'vfio-updates-20220608.0' of https://gitlab.com/al [...] adds d507bc3b05 target/arm: Declare support for FEAT_RASv1p1 adds 7ac610206a target/arm: Implement FEAT_DoubleFault adds 9323e79f10 Fix 'writeable' typos adds d2008b3355 xlnx_dp: fix the wrong register size adds 759ae1b47e xlnx_dp: Introduce a vblank signal adds 39f40d02f6 xlnx_dp: Fix the interrupt disable logic adds b3f5cc3fda xlnx-zynqmp: fix the irq mapping for the display port and its dma adds d8cca960a9 target/arm: Move stage_1_mmu_idx decl to internals.h adds 8ae0886002 target/arm: Move get_phys_addr to ptw.c adds f2d2f5ceb8 target/arm: Move get_phys_addr_v5 to ptw.c adds 53c038efb7 target/arm: Move get_phys_addr_v6 to ptw.c adds 9a12fb366d target/arm: Move get_phys_addr_pmsav5 to ptw.c adds 7d2e08c960 target/arm: Move get_phys_addr_pmsav7_default to ptw.c adds 1f2e87e5ab target/arm: Move get_phys_addr_pmsav7 to ptw.c adds 730d5c31d8 target/arm: Move get_phys_addr_pmsav8 to ptw.c adds fedbaa0503 target/arm: Move pmsav8_mpu_lookup to ptw.c adds c8e436c9f7 target/arm: Move pmsav7_use_background_region to ptw.c adds 2c1f429df3 target/arm: Move v8m_security_lookup to ptw.c adds 47ff5ba9d0 target/arm: Move m_is_{ppb,system}_region to ptw.c adds 4c74ab157b target/arm: Move get_level1_table_address to ptw.c adds 966f4bb7d8 target/arm: Move combine_cacheattrs and subroutines to ptw.c adds 3283222acd target/arm: Move get_phys_addr_lpae to ptw.c adds 11552bb0d9 target/arm: Move arm_{ldl,ldq}_ptw to ptw.c adds cd6bc4d517 target/arm: Move {arm_s1_, }regime_using_lpae_format to tlb_ [...] adds 1c73d84807 target/arm: Move arm_pamax, pamax_map into ptw.c adds f8526edc2f target/arm: Move get_S1prot, get_S2prot to ptw.c adds c5168785d2 target/arm: Move check_s2_mmu_setup to ptw.c adds 2f0ec92e94 target/arm: Move aa32_va_parameters to ptw.c adds 4845d3be12 target/arm: Move ap_to_tw_prot etc to ptw.c adds 0c23d56fc1 target/arm: Move regime_is_user to ptw.c adds 3b318aaeef target/arm: Move regime_ttbr to ptw.c adds 8db1a3a0bb target/arm: Move regime_translation_disabled to ptw.c adds 23971205cf target/arm: Move arm_cpu_get_phys_page_attrs_debug to ptw.c adds 1d26125536 target/arm: Move stage_1_mmu_idx, arm_stage1_mmu_idx to ptw.c adds 5e79887ba6 target/arm: Pass CPUARMState to arm_ld[lq]_ptw adds f45ce4c35f target/arm: Rename TBFLAG_A64 ZCR_LEN to VL adds 8b599e5c02 linux-user/aarch64: Introduce sve_vq adds 61a8c23a3b target/arm: Remove route_to_el2 check from sve_exception_el adds 397d922c62 target/arm: Remove fp checks from sve_exception_el adds 19668718ad target/arm: Add el_is_in_host adds c6225bebc2 target/arm: Use el_is_in_host for sve_zcr_len_for_el adds aa4451b60e target/arm: Use el_is_in_host for sve_exception_el adds 7d38cb92aa target/arm: Hoist arm_is_el2_enabled check in sve_exception_el adds 87252bdecd target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset adds 9b5f422559 target/arm: Merge aarch64_sve_zcr_get_valid_len into caller adds 886902ece7 target/arm: Use uint32_t instead of bitmap for sve vq's adds 5ef3cc5636 target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el adds d1ce862602 target/arm: Split out load/store primitives to sve_ldst_internal.h adds 0b68112b39 target/arm: Export sve contiguous ldst support functions adds 820e0bb9ce target/arm: Move expand_pred_b to vec_internal.h adds 05dd14bdfa target/arm: Use expand_pred_b in mve_helper.c adds a613cf2d4a target/arm: Move expand_pred_h to vec_internal.h adds 72db2aa353 target/arm: Export bfdotadd from vec_helper.c adds f305bf9436 target/arm: Add isar_feature_aa64_sme adds 414c54d515 target/arm: Add ID_AA64SMFR0_EL1 adds 028f2361d0 Merge tag 'pull-target-arm-20220609' of https://git.linaro.o [...] No new revisions were added by this update. Summary of changes: accel/hvf/hvf-accel-ops.c | 4 +- accel/kvm/kvm-all.c | 4 +- accel/tcg/user-exec.c | 6 +- docs/interop/vhost-user.rst | 2 +- docs/specs/vmgenid.txt | 4 +- docs/system/arm/emulation.rst | 2 + hw/acpi/ghes.c | 2 +- hw/arm/xlnx-zynqmp.c | 4 +- hw/display/xlnx_dp.c | 49 +- hw/intc/arm_gicv3_cpuif.c | 2 +- hw/intc/arm_gicv3_dist.c | 2 +- hw/intc/arm_gicv3_redist.c | 4 +- hw/intc/riscv_aclint.c | 2 +- hw/intc/riscv_aplic.c | 2 +- hw/pci/shpc.c | 2 +- hw/scsi/mfi.h | 2 +- hw/sparc64/sun4u_iommu.c | 2 +- hw/timer/sse-timer.c | 2 +- hw/vfio/common.c | 10 +- hw/vfio/trace-events | 2 +- include/hw/display/xlnx_dp.h | 12 +- linux-user/aarch64/signal.c | 4 +- linux-user/aarch64/target_prctl.h | 18 +- python/qemu/machine/machine.py | 2 +- target/arm/arch_dump.c | 2 +- target/arm/cpu.c | 5 +- target/arm/cpu.h | 66 +- target/arm/cpu64.c | 120 +- target/arm/gdbstub.c | 2 +- target/arm/gdbstub64.c | 2 +- target/arm/helper.c | 3042 ++++--------------------------------- target/arm/hvf/hvf.c | 4 +- target/arm/internals.h | 45 +- target/arm/kvm64.c | 47 +- target/arm/kvm_arm.h | 7 +- target/arm/meson.build | 1 + target/arm/mve_helper.c | 6 +- target/arm/ptw.c | 2540 +++++++++++++++++++++++++++++++ target/arm/sve_helper.c | 232 +-- target/arm/sve_ldst_internal.h | 221 +++ target/arm/tlb_helper.c | 26 + target/arm/translate-a64.c | 2 +- target/arm/translate-a64.h | 2 +- target/arm/translate-sve.c | 2 +- target/arm/translate.h | 2 +- target/arm/vec_helper.c | 28 +- target/arm/vec_internal.h | 28 +- target/i386/cpu-sysemu.c | 2 +- target/i386/hvf/vmcs.h | 2 +- target/i386/hvf/vmx.h | 2 +- target/s390x/ioinst.c | 2 +- tests/tcg/x86_64/system/boot.S | 2 +- 52 files changed, 3399 insertions(+), 3188 deletions(-) create mode 100644 target/arm/ptw.c create mode 100644 target/arm/sve_ldst_internal.h -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/gdb] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-arm updated (8f4141b0ae -> 1c76a0e2a6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-arm in repository toolchain/ci/gdb. from 8f4141b0ae gdb: add Yvan Roux to gdb/MAINTAINERS adds 61ee7510b3 gdb/testsuite: use test_compiler_info in gcc_major_version adds 1562f64fec gdb/testsuite: remove get_compiler_info calls from gdb.exp a [...] adds 08b326ee0a gdb/testsuite: make 'c' default language for get/test compiler info adds 0e471fde07 gdb/testsuite: handle errors better in test_compiler_info adds 575a212a78 gdb/testsuite: solve problems with compiler_info caching adds 148ca9dd5c gdb/arm: Terminate unwinding when LR is 0xffffffff adds 8db775b211 Fix ARM_CC_FOR_TARGET handling adds 1ef3351b7b gdb/arm: Simplify logic for updating addresses adds 2d9cf99d9a gdb/arm: Document and fix exception stack offsets adds 396d2e56be gdb/aarch64: fix 32-bit arm compatibility adds 1c76a0e2a6 Minor fix to Python breakpoint event documentation No new revisions were added by this update. Summary of changes: gdb/aarch64-linux-nat.c | 114 ++++++++++++++++++++++++++++++++++++++------ gdb/arm-tdep.c | 85 +++++++++++++++++++++++++++++---- gdb/doc/python.texi | 6 +-- gdb/testsuite/lib/dwarf.exp | 8 ---- gdb/testsuite/lib/gdb.exp | 91 +++++++++++++++++------------------ 5 files changed, 225 insertions(+), 79 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-arm updated (2fc6e3d55f6 -> 699e9a0f671)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-arm in repository toolchain/ci/gcc. from 2fc6e3d55f6 This patch replaces shift and ior insns with one rotate and [...] adds 269edf4e5e6 Update {skylake,icelake,alderlake}_cost to add a bit prefer [...] adds 17f52a1c725 openmp: Add support for HBW or large capacity or interleave [...] adds 2dc19a1b590 doc: Fix up -Waddress documentation adds 209de00fdb9 OpenMP: Handle ancestor:1 with discover_declare_target adds 97b81fb0363 c++: Better module initializer code adds 702a11ade2e RISC-V: Use a tab rather than space with FSFLAGS adds 4c334e0e4ff c++: Fix up ICE on __builtin_shufflevector constexpr evalua [...] adds 699e9a0f671 openmp: Fix up include of the generic allocator.c No new revisions were added by this update. Summary of changes: gcc/config/i386/x86-tune-costs.h | 26 +- gcc/config/riscv/riscv.md | 4 +- gcc/cp/constexpr.cc | 13 +- gcc/cp/cp-tree.h | 3 +- gcc/cp/decl2.cc | 32 +- gcc/cp/module.cc | 23 +- gcc/doc/invoke.texi | 4 +- gcc/omp-offload.cc | 21 +- .../c-c++-common/gomp/reverse-offload-1.c | 93 ++++++ gcc/testsuite/g++.dg/modules/init-2_a.C | 2 + gcc/testsuite/g++.dg/modules/init-2_b.C | 2 + gcc/testsuite/g++.dg/pr105871.C | 12 + gcc/testsuite/g++.target/i386/pr105638.C | 3 +- gcc/testsuite/gcc.target/i386/pr105493.c | 51 +++ gcc/testsuite/gcc.target/i386/pr91446.c | 2 +- gcc/testsuite/gcc.target/i386/pr99881.c | 2 +- libgomp/allocator.c | 365 ++++++++++++++++++++- libgomp/config/linux/allocator.c | 36 ++ 18 files changed, 621 insertions(+), 73 deletions(-) create mode 100644 gcc/testsuite/c-c++-common/gomp/reverse-offload-1.c create mode 100644 gcc/testsuite/g++.dg/pr105871.C create mode 100644 gcc/testsuite/gcc.target/i386/pr105493.c create mode 100644 libgomp/config/linux/allocator.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-arm updated (8f4141b0ae -> 1c76a0e2a6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-arm in repository toolchain/ci/binutils-gdb. from 8f4141b0ae gdb: add Yvan Roux to gdb/MAINTAINERS adds 61ee7510b3 gdb/testsuite: use test_compiler_info in gcc_major_version adds 1562f64fec gdb/testsuite: remove get_compiler_info calls from gdb.exp a [...] adds 08b326ee0a gdb/testsuite: make 'c' default language for get/test compiler info adds 0e471fde07 gdb/testsuite: handle errors better in test_compiler_info adds 575a212a78 gdb/testsuite: solve problems with compiler_info caching adds 148ca9dd5c gdb/arm: Terminate unwinding when LR is 0xffffffff adds 8db775b211 Fix ARM_CC_FOR_TARGET handling adds 1ef3351b7b gdb/arm: Simplify logic for updating addresses adds 2d9cf99d9a gdb/arm: Document and fix exception stack offsets adds 396d2e56be gdb/aarch64: fix 32-bit arm compatibility adds 1c76a0e2a6 Minor fix to Python breakpoint event documentation No new revisions were added by this update. Summary of changes: gdb/aarch64-linux-nat.c | 114 ++++++++++++++++++++++++++++++++++++++------ gdb/arm-tdep.c | 85 +++++++++++++++++++++++++++++---- gdb/doc/python.texi | 6 +-- gdb/testsuite/lib/dwarf.exp | 8 ---- gdb/testsuite/lib/gdb.exp | 91 +++++++++++++++++------------------ 5 files changed, 225 insertions(+), 79 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-arm updated (cf4227f9c -> b7633bac2)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_check_gcc/master-arm in repository toolchain/ci/base-artifacts. discards cf4227f9c 0: update: binutils-linux-glibc-gdb-qemu: 1 new b7633bac2 0: update: binutils-gcc-linux-glibc-gdb-qemu: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (cf4227f9c) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_cross_check_gcc/mast [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1536 -> 1576 bytes 02-prepare_abe/console.log.xz | Bin 2732 -> 2724 bytes 03-build_abe-binutils/console.log.xz | Bin 29972 -> 30176 bytes 04-build_abe-stage1/console.log.xz | Bin 91200 -> 90324 bytes 05-clean_sysroot/console.log.xz | Bin 332 -> 332 bytes 06-build_abe-linux/console.log.xz | Bin 8772 -> 8788 bytes 07-build_abe-glibc/console.log.xz | Bin 232896 -> 233032 bytes 08-build_abe-stage2/console.log.xz | Bin 225524 -> 223516 bytes 09-build_abe-gdb/console.log.xz | Bin 37268 -> 37380 bytes 10-build_abe-qemu/console.log.xz | Bin 31820 -> 32548 bytes 11-build_abe-dejagnu/console.log.xz | Bin 3848 -> 3852 bytes 12-build_abe-check_gcc/console.log.xz | Bin 2628 -> 2616 bytes 13-check_regression/console.log.xz | Bin 2828 -> 3216 bytes 13-check_regression/extra-bisect-params | 1 - 13-check_regression/fails.sum | 6 - 13-check_regression/results.compare | 35 +- 13-check_regression/results.compare2 | 85 +- 13-check_regression/results.regressions | 26 - 14-update_baseline/console.log | 421 ++--- 14-update_baseline/extra-bisect-params | 1 - 14-update_baseline/fails.sum | 6 - 14-update_baseline/results.compare | 35 +- 14-update_baseline/results.compare2 | 85 +- 14-update_baseline/results.regressions | 26 - jenkins/manifest.sh | 23 +- sumfiles/g++.log.xz | Bin 2660228 -> 2640844 bytes sumfiles/g++.sum | 174 +- sumfiles/gcc.log.xz | Bin 2218824 -> 2171752 bytes sumfiles/gcc.sum | 2617 ++++++++++++++++--------------- sumfiles/gfortran.log.xz | Bin 878992 -> 884188 bytes sumfiles/gfortran.sum | 46 +- sumfiles/libatomic.log.xz | Bin 2264 -> 2260 bytes sumfiles/libatomic.sum | 4 +- sumfiles/libgomp.log.xz | Bin 198764 -> 198712 bytes sumfiles/libgomp.sum | 16 +- sumfiles/libitm.log.xz | Bin 2664 -> 2668 bytes sumfiles/libitm.sum | 6 +- sumfiles/libstdc++.log.xz | Bin 424944 -> 422324 bytes sumfiles/libstdc++.sum | 14 +- 39 files changed, 1894 insertions(+), 1733 deletions(-) delete mode 100644 13-check_regression/extra-bisect-params delete mode 100644 13-check_regression/fails.sum delete mode 100644 13-check_regression/results.regressions delete mode 100644 14-update_baseline/extra-bisect-params delete mode 100644 14-update_baseline/fails.sum delete mode 100644 14-update_baseline/results.regressions -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu_native_build/master-arm updated (17f52a1c725 -> 4c334e0e4ff)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_native_build/master-arm in repository toolchain/ci/gcc. from 17f52a1c725 openmp: Add support for HBW or large capacity or interleave [...] adds 2dc19a1b590 doc: Fix up -Waddress documentation adds 209de00fdb9 OpenMP: Handle ancestor:1 with discover_declare_target adds 97b81fb0363 c++: Better module initializer code adds 702a11ade2e RISC-V: Use a tab rather than space with FSFLAGS adds 4c334e0e4ff c++: Fix up ICE on __builtin_shufflevector constexpr evalua [...] No new revisions were added by this update. Summary of changes: gcc/config/riscv/riscv.md | 4 +- gcc/cp/constexpr.cc | 13 ++- gcc/cp/cp-tree.h | 3 +- gcc/cp/decl2.cc | 32 ++++---- gcc/cp/module.cc | 23 +++--- gcc/doc/invoke.texi | 4 +- gcc/omp-offload.cc | 21 ++--- .../c-c++-common/gomp/reverse-offload-1.c | 93 ++++++++++++++++++++++ gcc/testsuite/g++.dg/modules/init-2_a.C | 2 + gcc/testsuite/g++.dg/modules/init-2_b.C | 2 + gcc/testsuite/g++.dg/pr105871.C | 12 +++ 11 files changed, 164 insertions(+), 45 deletions(-) create mode 100644 gcc/testsuite/c-c++-common/gomp/reverse-offload-1.c create mode 100644 gcc/testsuite/g++.dg/pr105871.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_native_build/master-arm updated (e4f091265 -> fcc38d304)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_native_build/master-arm in repository toolchain/ci/base-artifacts. from e4f091265 1: reset: gcc-17f52a1c725948befcc3dd3c90d1abad77b6f6fe: 1 new fcc38d304 2: update: gcc-4c334e0e4ff05d3a7ca9ebb832428c446cd0ae8d: 1 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1588 -> 1480 bytes 02-prepare_abe/console.log.xz | Bin 2716 -> 2720 bytes 04-build_abe-binutils/console.log.xz | Bin 51168 -> 49976 bytes 05-build_abe-gcc/console.log.xz | Bin 125292 -> 126904 bytes 10-check_regression/console.log.xz | Bin 1200 -> 416 bytes 10-check_regression/jira-body.txt | 2 -- 10-check_regression/mail-body.txt | 34 -------------------------- 10-check_regression/mail-subject.txt | 1 - 10-check_regression/results.regressions | 8 ------ 10-check_regression/trigger-bisect | 2 -- 11-update_baseline/console.log | 42 +++++++++++++++++++++++++++++--- jenkins/manifest.sh | 10 ++++---- mail/jira-body.txt | 5 ---- mail/mail-body.txt | 37 ---------------------------- mail/mail-subject.txt | 1 - reset-baseline | 0 results | 8 ------ 17 files changed, 43 insertions(+), 107 deletions(-) delete mode 100644 10-check_regression/jira-body.txt delete mode 100644 10-check_regression/mail-body.txt delete mode 100644 10-check_regression/mail-subject.txt delete mode 100644 10-check_regression/results.regressions delete mode 100644 10-check_regression/trigger-bisect delete mode 100644 mail/jira-body.txt delete mode 100644 mail/mail-body.txt delete mode 100644 mail/mail-subject.txt delete mode 100644 reset-baseline -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[glibc] branch master updated (ace9e3edbc -> cffb9414c5)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository glibc. from ace9e3edbc nss: handle stat failure in check_reload_and_get (BZ #28752) new 4654e7fd5a x86: Add copyright to strpbrk-c.c new 0f91811333 x86: Align varshift table to 32-bytes new 73bae395cf x86: Improve svml_s_atanhf16_core_avx512.S new 65897e9916 x86: Improve svml_s_atanhf8_core_avx2.S new fe1915d4f6 x86: Improve svml_s_atanhf4_core_sse4.S new e560b3c2d2 x86: Optimize svml_s_tanhf16_core_avx512.S new 3a49ce8799 x86: Add data file that can be shared by tanhf-avx2 and tanhf-sse4 new bcc41f66a4 x86: Optimize svml_s_tanhf8_core_avx2.S new cffb9414c5 x86: Optimize svml_s_tanhf4_core_sse4.S The 9 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../fpu/multiarch/svml_s_atanhf16_core_avx512.S | 474 +++++------ .../fpu/multiarch/svml_s_atanhf4_core_sse4.S | 378 ++++----- .../fpu/multiarch/svml_s_atanhf8_core_avx2.S | 405 +++++---- .../fpu/multiarch/svml_s_tanhf16_core_avx512.S | 527 ++++++------ .../x86_64/fpu/multiarch/svml_s_tanhf4_core_sse4.S | 865 ++++--------------- .../x86_64/fpu/multiarch/svml_s_tanhf8_core_avx2.S | 912 ++++----------------- sysdeps/x86_64/fpu/multiarch/svml_s_tanhf_rodata.S | 621 ++++++++++++++ sysdeps/x86_64/multiarch/strpbrk-c.c | 18 + sysdeps/x86_64/multiarch/varshift.c | 5 +- sysdeps/x86_64/multiarch/varshift.h | 3 +- 10 files changed, 1855 insertions(+), 2353 deletions(-) create mode 100644 sysdeps/x86_64/fpu/multiarch/svml_s_tanhf_rodata.S -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_gnu_tx1/gnu-master-aarch64-spec2k6-O2_LTO updated (999835533b -> ace9e3edbc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_gnu_tx1/gnu-master-aarch64-spec2k6-O2_LTO in repository toolchain/ci/glibc. from 999835533b socket: Fix mistyped define statement in socket/sys/socket.h [...] adds 8521001731 scripts/glibcelf.py: Add PT_AARCH64_MEMTAG_MTE constant adds 5082a287d5 x86_64: Add strstr function with 512-bit EVEX adds 9f298bfe1f AArch64: Add SVE memcpy adds eea282d9c6 AArch64: Sort makefile entries adds 0218463dd8 powerpc: Fix VSX register number on __strncpy_power9 [BZ #29197] adds 8a780a6b91 x86: Create header for VEC classes in x86 strings library adds dd5c483b25 x86: Add COND_VZEROUPPER that can replace vzeroupper if no `ret` adds d0370d992e Benchtests: Improve memrchr benchmarks adds 731feee386 x86: Optimize memrchr-sse2.S adds b4209615a0 x86: Optimize memrchr-evex.S adds af5306a735 x86: Optimize memrchr-avx2.S adds 6dcbb7d95d x86: Shrink code size of memchr-avx2.S adds 56da3fe1dd x86: Shrink code size of memchr-evex.S adds c28db9cb29 x86: ZERO_UPPER_VEC_REGISTERS_RETURN_XTEST expect no transactions adds c7d36dcecc nptl: Fix __libc_cleanup_pop_restore asynchronous restore (B [...] adds c2f39be490 elf: add missing newlines in lateglobal test adds aa13fd1618 nptl_db: disable DT_RELR on libthread_db.so adds 2c9af8421d x86: Fix page cross case in rawmemchr-avx2 [BZ #29234] adds 3fdf0a205b nss: add assert to DB_LOOKUP_FCT (BZ #28752) adds ace9e3edbc nss: handle stat failure in check_reload_and_get (BZ #28752) No new revisions were added by this update. Summary of changes: benchtests/bench-memchr.c | 110 +++-- elf/lateglobal.c | 6 +- nptl/libc-cleanup.c | 3 +- nptl_db/Makefile | 6 + nss/XXX-lookup.c | 5 + nss/nss_database.c | 39 +- scripts/glibcelf.py | 4 + string/test-rawmemchr.c | 57 ++- sysdeps/aarch64/multiarch/Makefile | 24 +- sysdeps/aarch64/multiarch/ifunc-impl-list.c | 4 +- sysdeps/aarch64/multiarch/memcpy.c | 51 ++- sysdeps/aarch64/multiarch/memcpy_sve.S | 218 +++++++++ sysdeps/aarch64/multiarch/memmove.c | 51 ++- sysdeps/powerpc/powerpc64/le/power9/strncpy.S | 4 +- sysdeps/pthread/Makefile | 1 + sysdeps/pthread/tst-cancel30.c | 82 ++++ sysdeps/x86_64/memrchr.S | 613 ++++++++++++-------------- sysdeps/x86_64/multiarch/Makefile | 2 + sysdeps/x86_64/multiarch/avx-rtm-vecs.h | 35 ++ sysdeps/x86_64/multiarch/avx-vecs.h | 47 ++ sysdeps/x86_64/multiarch/evex-vecs-common.h | 39 ++ sysdeps/x86_64/multiarch/evex256-vecs.h | 35 ++ sysdeps/x86_64/multiarch/evex512-vecs.h | 35 ++ sysdeps/x86_64/multiarch/ifunc-impl-list.c | 6 + sysdeps/x86_64/multiarch/memchr-avx2-rtm.S | 1 + sysdeps/x86_64/multiarch/memchr-avx2.S | 109 ++--- sysdeps/x86_64/multiarch/memchr-evex.S | 46 +- sysdeps/x86_64/multiarch/memrchr-avx2-rtm.S | 1 + sysdeps/x86_64/multiarch/memrchr-avx2.S | 534 +++++++++++----------- sysdeps/x86_64/multiarch/memrchr-evex.S | 539 +++++++++++----------- sysdeps/x86_64/multiarch/sse2-vecs.h | 47 ++ sysdeps/x86_64/multiarch/strstr-avx512.c | 214 +++++++++ sysdeps/x86_64/multiarch/strstr.c | 24 +- sysdeps/x86_64/multiarch/vec-macros.h | 90 ++++ sysdeps/x86_64/sysdep.h | 24 +- 35 files changed, 2044 insertions(+), 1062 deletions(-) create mode 100644 sysdeps/aarch64/multiarch/memcpy_sve.S create mode 100644 sysdeps/pthread/tst-cancel30.c create mode 100644 sysdeps/x86_64/multiarch/avx-rtm-vecs.h create mode 100644 sysdeps/x86_64/multiarch/avx-vecs.h create mode 100644 sysdeps/x86_64/multiarch/evex-vecs-common.h create mode 100644 sysdeps/x86_64/multiarch/evex256-vecs.h create mode 100644 sysdeps/x86_64/multiarch/evex512-vecs.h create mode 100644 sysdeps/x86_64/multiarch/sse2-vecs.h create mode 100644 sysdeps/x86_64/multiarch/strstr-avx512.c create mode 100644 sysdeps/x86_64/multiarch/vec-macros.h -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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Tcwg-commits June 2022