Tcwg-commits June 2022

tcwg-commits@lists.linaro.org

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14714 discussions

[gcc] branch master updated (671970a5621 -> 1459b55d24c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 671970a5621 libstdc++: Make std::lcm and std::gcd detect overflow [PR105844] new 1459b55d24c libgomp nvptx plugin: Remove '--with-cuda-driver=[...]' etc [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: libgomp/Makefile.in | 50 ++++----- libgomp/configure | 143 +------------------------- libgomp/plugin/Makefrag.am | 25 ++--- libgomp/plugin/configfrag.ac | 90 +--------------- libgomp/testsuite/Makefile.in | 5 - libgomp/testsuite/lib/libgomp.exp | 13 --- libgomp/testsuite/libgomp-test-support.exp.in | 3 - 7 files changed, 37 insertions(+), 292 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allnoconfig updated (ca127b3fc2 -> b3cd3b5a66)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allnoconfig in repository toolchain/ci/qemu. from ca127b3fc2 Merge tag 'nvme-next-pull-request' of git://git.infradead.or [...] adds 9f9dcb96a4 target/i386/tcg: Fix masking of real-mode addresses with A20 bit adds d8f3a60931 build: add a "make modules" target adds b0f3184e82 target/i386: Fix wrong count setting adds 24ce7aa77d modules: introduces module_kconfig directive adds 05d6814c3e modules: generates per-target modinfo adds c4b8ffcbb8 replay: fix event queue flush for qemu shutdown adds 75bbe5e5ec replay: notify vCPU when BH is scheduled adds 60618e2d77 replay: rewrite async event handling adds 3e21408b05 replay: simplify async event processing adds 04d0583a4f docs: convert docs/devel/replay page to rst adds 43185f7bd4 docs: move replay docs to docs/system/replay.rst adds c9d27a0f9f tests/avocado: update replay_linux test adds 3cd1dce33d tests/avocado: add replay Linux tests for virtio machine adds 9b59af628c tests/avocado: add replay Linux test for Aarch64 machines adds d426ff938b tests/Makefile.include: Fix 'make check-help' output adds efb3934adf x86: cpu: make sure number of addressable IDs for processor [...] adds d7caf13b5f x86: cpu: fixup number of addressable IDs for logical proces [...] adds e7874a50ff python: update for mypy 0.950 adds caa0f7cbaf tests: add "TESTS_PYTHON" variable to Makefile adds aa19dd33ce tests: use python3 as the python executable name adds a547c82701 tests: silence pip upgrade warnings during venv creation adds 5a6f1199cb tests: add quiet-venv-pip macro adds 0e7647aa8a tests: install "qemu" namespace package into venv adds f4c66f1705 tests: use tests/venv to run basevm.py-based scripts adds e184036a0e tests: add python3-venv to debian10.docker adds 1d8cf47e5b tests: run 'device-crash-test' from tests/venv adds d4bb4432ab regenerate meson-buildoptions.sh adds 7632a38e7c configure: remove reference to removed option adds ca5765c852 meson: qga: do not use deprecated meson.build_root() adds 57c9363c45 Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu [...] adds 64baad62cd target/loongarch: Add README adds 228021f05e target/loongarch: Add core definition adds f8da88d78f target/loongarch: Add main translation routines adds 143d6785ef target/loongarch: Add fixed point arithmetic instruction tra [...] adds 63cfcd47d7 target/loongarch: Add fixed point shift instruction translation adds ad08cb3f97 target/loongarch: Add fixed point bit instruction translation adds bb79174d4e target/loongarch: Add fixed point load/store instruction tra [...] adds 94b02d57b0 target/loongarch: Add fixed point atomic instruction translation adds 8708a04a61 target/loongarch: Add fixed point extra instruction translation adds d578ca6cbb target/loongarch: Add floating point arithmetic instruction [...] adds 9b7410763a target/loongarch: Add floating point comparison instruction [...] adds 7c1f88703d target/loongarch: Add floating point conversion instruction [...] adds b7dabd5624 target/loongarch: Add floating point move instruction translation adds e616bdfd01 target/loongarch: Add floating point load/store instruction [...] adds ee86bd58b8 target/loongarch: Add branch instruction translation adds aae1746c72 target/loongarch: Add disassembler adds 14f2b0b741 target/loongarch: Add target build suport adds d88b51dc26 target/loongarch: Add system emulation introduction adds 398cecb9c3 target/loongarch: Add CSRs definition adds 67ebd42a48 target/loongarch: Add basic vmstate description of CPU. adds 425876f5d8 target/loongarch: Implement qmp_query_cpu_definitions() adds 7e1c521e2a target/loongarch: Add MMU support for LoongArch CPU. adds f757a2cd69 target/loongarch: Add LoongArch interrupt and exception handle adds dd615fa48d target/loongarch: Add constant timer support adds 5b1dedfe84 target/loongarch: Add LoongArch CSR instruction adds f84a2aacf5 target/loongarch: Add LoongArch IOCSR instruction adds fcbbeb8ecd target/loongarch: Add TLB instruction support adds d2cba6f7ce target/loongarch: Add other core instructions support adds f9bf50745f target/loongarch: Add timer related instructions support. adds a8a506c390 hw/loongarch: Add support loongson3 virt machine type. adds f6783e3438 hw/loongarch: Add LoongArch ipi interrupt support(IPI) adds 0f4fcf1845 hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC) adds 249ad85a4b hw/intc: Add LoongArch ls7a msi interrupt controller support [...] adds cbff2db1e9 hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) adds 69d9c74fa9 hw/loongarch: Add irq hierarchy for the system adds 256309e188 Enable common virtio pci support for LoongArch adds dc93b8df8a hw/loongarch: Add some devices support for 3A5000. adds c117f68a46 hw/loongarch: Add LoongArch ls7a rtc device support adds 6a6f26f481 hw/loongarch: Add LoongArch load elf function. adds 9e6602d657 hw/loongarch: Add LoongArch virt power manager support. adds ca61e75071 target/loongarch: Add gdb support. adds c429333398 tests/tcg/loongarch64: Add hello/memory test in loongarch64 system adds 34bb43b074 target/loongarch: 'make check-tcg' support adds 9b1f588549 Merge tag 'pull-la-20220606' of https://gitlab.com/rth7680/q [...] adds 4d84bb6c8b hw/tpm/tpm_tis_common.c: Assert that locty is in range adds e37a0ef460 tpm_crb: mark command buffer as dirty on request completion adds 6d940eff47 Merge tag 'pull-tpm-2022-06-07-1' of https://github.com/stef [...] adds ec6600be0d vfio/common: remove spurious warning on vfio_listener_region_del adds 05911658cb Merge tag 'vfio-updates-20220608.0' of https://gitlab.com/al [...] adds d507bc3b05 target/arm: Declare support for FEAT_RASv1p1 adds 7ac610206a target/arm: Implement FEAT_DoubleFault adds 9323e79f10 Fix 'writeable' typos adds d2008b3355 xlnx_dp: fix the wrong register size adds 759ae1b47e xlnx_dp: Introduce a vblank signal adds 39f40d02f6 xlnx_dp: Fix the interrupt disable logic adds b3f5cc3fda xlnx-zynqmp: fix the irq mapping for the display port and its dma adds d8cca960a9 target/arm: Move stage_1_mmu_idx decl to internals.h adds 8ae0886002 target/arm: Move get_phys_addr to ptw.c adds f2d2f5ceb8 target/arm: Move get_phys_addr_v5 to ptw.c adds 53c038efb7 target/arm: Move get_phys_addr_v6 to ptw.c adds 9a12fb366d target/arm: Move get_phys_addr_pmsav5 to ptw.c adds 7d2e08c960 target/arm: Move get_phys_addr_pmsav7_default to ptw.c adds 1f2e87e5ab target/arm: Move get_phys_addr_pmsav7 to ptw.c adds 730d5c31d8 target/arm: Move get_phys_addr_pmsav8 to ptw.c adds fedbaa0503 target/arm: Move pmsav8_mpu_lookup to ptw.c adds c8e436c9f7 target/arm: Move pmsav7_use_background_region to ptw.c adds 2c1f429df3 target/arm: Move v8m_security_lookup to ptw.c adds 47ff5ba9d0 target/arm: Move m_is_{ppb,system}_region to ptw.c adds 4c74ab157b target/arm: Move get_level1_table_address to ptw.c adds 966f4bb7d8 target/arm: Move combine_cacheattrs and subroutines to ptw.c adds 3283222acd target/arm: Move get_phys_addr_lpae to ptw.c adds 11552bb0d9 target/arm: Move arm_{ldl,ldq}_ptw to ptw.c adds cd6bc4d517 target/arm: Move {arm_s1_, }regime_using_lpae_format to tlb_ [...] adds 1c73d84807 target/arm: Move arm_pamax, pamax_map into ptw.c adds f8526edc2f target/arm: Move get_S1prot, get_S2prot to ptw.c adds c5168785d2 target/arm: Move check_s2_mmu_setup to ptw.c adds 2f0ec92e94 target/arm: Move aa32_va_parameters to ptw.c adds 4845d3be12 target/arm: Move ap_to_tw_prot etc to ptw.c adds 0c23d56fc1 target/arm: Move regime_is_user to ptw.c adds 3b318aaeef target/arm: Move regime_ttbr to ptw.c adds 8db1a3a0bb target/arm: Move regime_translation_disabled to ptw.c adds 23971205cf target/arm: Move arm_cpu_get_phys_page_attrs_debug to ptw.c adds 1d26125536 target/arm: Move stage_1_mmu_idx, arm_stage1_mmu_idx to ptw.c adds 5e79887ba6 target/arm: Pass CPUARMState to arm_ld[lq]_ptw adds f45ce4c35f target/arm: Rename TBFLAG_A64 ZCR_LEN to VL adds 8b599e5c02 linux-user/aarch64: Introduce sve_vq adds 61a8c23a3b target/arm: Remove route_to_el2 check from sve_exception_el adds 397d922c62 target/arm: Remove fp checks from sve_exception_el adds 19668718ad target/arm: Add el_is_in_host adds c6225bebc2 target/arm: Use el_is_in_host for sve_zcr_len_for_el adds aa4451b60e target/arm: Use el_is_in_host for sve_exception_el adds 7d38cb92aa target/arm: Hoist arm_is_el2_enabled check in sve_exception_el adds 87252bdecd target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset adds 9b5f422559 target/arm: Merge aarch64_sve_zcr_get_valid_len into caller adds 886902ece7 target/arm: Use uint32_t instead of bitmap for sve vq's adds 5ef3cc5636 target/arm: Rename sve_zcr_len_for_el to sve_vqm1_for_el adds d1ce862602 target/arm: Split out load/store primitives to sve_ldst_internal.h adds 0b68112b39 target/arm: Export sve contiguous ldst support functions adds 820e0bb9ce target/arm: Move expand_pred_b to vec_internal.h adds 05dd14bdfa target/arm: Use expand_pred_b in mve_helper.c adds a613cf2d4a target/arm: Move expand_pred_h to vec_internal.h adds 72db2aa353 target/arm: Export bfdotadd from vec_helper.c adds f305bf9436 target/arm: Add isar_feature_aa64_sme adds 414c54d515 target/arm: Add ID_AA64SMFR0_EL1 adds 028f2361d0 Merge tag 'pull-target-arm-20220609' of https://git.linaro.o [...] adds 7851b21a81 hw/ide/piix: Remove redundant "piix3-ide-xen" device class adds 3690241746 hw/ide/piix: Add some documentation to pci_piix3_xen_ide_unplug() adds 6a8a8b62bd include/hw/ide: Unexport pci_piix3_xen_ide_unplug() adds 9cc1bf1ebc Merge tag 'pull-xen-20220609' of https://xenbits.xen.org/git [...] adds efe1592c43 MAINTAINERS: Cover hw/core/uboot_image.h within Generic Load [...] adds de799beba7 target/riscv: add support for zmmul extension v0.1 adds f9a461b2d3 hw/riscv: virt: Generate fw_cfg DT node correctly adds 40244040a7 hw/intc: sifive_plic: Avoid overflowing the addr_config buffer adds af9751316e hw/core/loader: return image sizes as ssize_t adds 8f42415fc1 target/riscv: Wake on VS-level external interrupts adds d1d8541217 target/riscv/debug.c: keep experimental rv128 support working adds 8a085fb2ad target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed adds 25eae0486d target/riscv: rvv: Prune redundant access_type parameter passed adds c7b8a4213b target/riscv: rvv: Rename ambiguous esz adds 41d3d7f76a target/riscv: rvv: Early exit when vstart >= vl adds f1eed927fb target/riscv: rvv: Add tail agnostic for vv instructions adds 752614cab8 target/riscv: rvv: Add tail agnostic for vector load / store [...] adds 5c19fc156e target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions adds 7b1bff41c1 target/riscv: rvv: Add tail agnostic for vector integer shif [...] adds 38581e5c9a target/riscv: rvv: Add tail agnostic for vector integer comp [...] adds 89a32de2d5 target/riscv: rvv: Add tail agnostic for vector integer merg [...] adds 09106eed30 target/riscv: rvv: Add tail agnostic for vector fix-point ar [...] adds 5eacf7d8a0 target/riscv: rvv: Add tail agnostic for vector floating-poi [...] adds df4f52a758 target/riscv: rvv: Add tail agnostic for vector reduction in [...] adds acc6ffd482 target/riscv: rvv: Add tail agnostic for vector mask instructions adds 803963f7cb target/riscv: rvv: Add tail agnostic for vector permutation [...] adds b8312675d6 target/riscv: rvv: Add option 'rvv_ta_all_1s' to enable opti [...] adds 26b2bc5859 target/riscv: Don't expose the CPU properties on names CPUs adds 07314158f6 target/riscv: trans_rvv: Avoid assert for RV32 and e64 adds b3cd3b5a66 Merge tag 'pull-riscv-to-apply-20220610' of github.com:alist [...] No new revisions were added by this update. Summary of changes: .gitlab-ci.d/buildtest.yml | 8 +- MAINTAINERS | 25 + accel/hvf/hvf-accel-ops.c | 4 +- accel/kvm/kvm-all.c | 4 +- accel/tcg/tcg-accel-ops-icount.c | 5 +- accel/tcg/user-exec.c | 6 +- configs/devices/loongarch64-softmmu/default.mak | 3 + configs/targets/loongarch64-softmmu.mak | 4 + configure | 2 +- docs/devel/index-tcg.rst | 1 + docs/devel/replay.rst | 306 ++ docs/devel/replay.txt | 46 - docs/interop/vhost-user.rst | 2 +- docs/replay.txt | 410 --- docs/specs/vmgenid.txt | 4 +- docs/system/arm/emulation.rst | 2 + docs/system/index.rst | 1 + docs/system/loongarch/loongson3.rst | 41 + docs/system/replay.rst | 237 ++ gdb-xml/loongarch-base64.xml | 44 + gdb-xml/loongarch-fpu64.xml | 57 + hw/Kconfig | 1 + hw/acpi/ghes.c | 2 +- hw/arm/armv7m.c | 2 +- hw/arm/boot.c | 8 +- hw/arm/xlnx-zynqmp.c | 4 +- hw/core/generic-loader.c | 2 +- hw/core/loader.c | 81 +- hw/display/qxl.c | 1 + hw/display/vhost-user-gpu-pci.c | 1 + hw/display/vhost-user-gpu.c | 1 + hw/display/vhost-user-vga.c | 1 + hw/display/virtio-gpu-base.c | 1 + hw/display/virtio-gpu-gl.c | 1 + hw/display/virtio-gpu-pci-gl.c | 1 + hw/display/virtio-gpu-pci.c | 1 + hw/display/virtio-gpu.c | 1 + hw/display/virtio-vga-gl.c | 1 + hw/display/virtio-vga.c | 1 + hw/display/xlnx_dp.c | 49 +- hw/i386/pc_piix.c | 3 +- hw/i386/x86.c | 2 +- hw/i386/xen/xen_platform.c | 48 +- hw/ide/piix.c | 42 - hw/intc/Kconfig | 15 + hw/intc/arm_gicv3_cpuif.c | 2 +- hw/intc/arm_gicv3_dist.c | 2 +- hw/intc/arm_gicv3_redist.c | 4 +- hw/intc/loongarch_extioi.c | 312 ++ hw/intc/loongarch_ipi.c | 242 ++ hw/intc/loongarch_pch_msi.c | 73 + hw/intc/loongarch_pch_pic.c | 431 +++ hw/intc/meson.build | 4 + hw/intc/riscv_aclint.c | 2 +- hw/intc/riscv_aplic.c | 2 +- hw/intc/sifive_plic.c | 19 +- hw/intc/trace-events | 22 + hw/loongarch/Kconfig | 16 + hw/loongarch/loongson3.c | 382 +++ hw/loongarch/meson.build | 4 + hw/meson.build | 1 + hw/pci/shpc.c | 2 +- hw/riscv/boot.c | 5 +- hw/riscv/virt.c | 28 +- hw/rtc/Kconfig | 3 + hw/rtc/ls7a_rtc.c | 528 ++++ hw/rtc/meson.build | 1 + hw/s390x/virtio-ccw-gpu.c | 1 + hw/scsi/mfi.h | 2 +- hw/sparc64/sun4u_iommu.c | 2 +- hw/timer/sse-timer.c | 2 +- hw/tpm/tpm_crb.c | 1 + hw/tpm/tpm_tis_common.c | 7 +- hw/usb/ccid-card-emulated.c | 1 + hw/usb/ccid-card-passthru.c | 1 + hw/usb/host-libusb.c | 1 + hw/usb/redirect.c | 1 + hw/vfio/common.c | 10 +- hw/vfio/trace-events | 2 +- include/disas/dis-asm.h | 2 + include/exec/poison.h | 2 + include/hw/display/xlnx_dp.h | 12 +- include/hw/ide.h | 3 - include/hw/intc/loongarch_extioi.h | 62 + include/hw/intc/loongarch_ipi.h | 52 + include/hw/intc/loongarch_pch_msi.h | 20 + include/hw/intc/loongarch_pch_pic.h | 69 + include/hw/loader.h | 55 +- include/hw/loongarch/virt.h | 33 + include/hw/pci-host/ls7a.h | 44 + include/qemu/module.h | 10 + include/sysemu/arch_init.h | 1 + include/sysemu/cpu-timers.h | 1 + include/sysemu/replay.h | 9 +- linux-user/aarch64/signal.c | 4 +- linux-user/aarch64/target_prctl.h | 18 +- meson.build | 29 +- python/qemu/machine/machine.py | 2 +- python/qemu/qmp/util.py | 4 +- python/setup.cfg | 1 + qapi/machine-target.json | 6 +- qapi/machine.json | 2 +- qga/meson.build | 2 +- replay/replay-events.c | 56 +- replay/replay-internal.h | 37 +- replay/replay-snapshot.c | 2 - replay/replay.c | 78 +- scripts/device-crash-test | 16 +- scripts/meson-buildoptions.sh | 4 +- scripts/modinfo-generate.py | 49 +- softmmu/icount.c | 12 +- softmmu/qdev-monitor.c | 3 +- stubs/icount.c | 4 + target/Kconfig | 1 + target/arm/arch_dump.c | 2 +- target/arm/cpu.c | 5 +- target/arm/cpu.h | 66 +- target/arm/cpu64.c | 120 +- target/arm/gdbstub.c | 2 +- target/arm/gdbstub64.c | 2 +- target/arm/helper.c | 3042 ++------------------ target/arm/hvf/hvf.c | 4 +- target/arm/internals.h | 45 +- target/arm/kvm64.c | 47 +- target/arm/kvm_arm.h | 7 +- target/arm/meson.build | 1 + target/arm/mve_helper.c | 6 +- target/arm/ptw.c | 2540 ++++++++++++++++ target/arm/sve_helper.c | 232 +- target/arm/sve_ldst_internal.h | 221 ++ target/arm/tlb_helper.c | 26 + target/arm/translate-a64.c | 2 +- target/arm/translate-a64.h | 2 +- target/arm/translate-sve.c | 2 +- target/arm/translate.h | 2 +- target/arm/vec_helper.c | 28 +- target/arm/vec_internal.h | 28 +- target/i386/cpu-sysemu.c | 2 +- target/i386/cpu.c | 22 +- target/i386/hvf/vmcs.h | 2 +- target/i386/hvf/vmx.h | 2 +- target/i386/tcg/sysemu/excp_helper.c | 4 +- target/loongarch/Kconfig | 2 + target/loongarch/README | 64 + target/loongarch/constant_timer.c | 64 + target/loongarch/cpu-csr.h | 208 ++ target/loongarch/cpu-param.h | 18 + target/loongarch/cpu.c | 704 +++++ target/loongarch/cpu.h | 391 +++ target/loongarch/csr_helper.c | 87 + target/loongarch/disas.c | 757 +++++ target/loongarch/fpu_helper.c | 862 ++++++ target/loongarch/gdbstub.c | 81 + target/loongarch/helper.h | 130 + target/loongarch/insn_trans/trans_arith.c.inc | 304 ++ target/loongarch/insn_trans/trans_atomic.c.inc | 113 + target/loongarch/insn_trans/trans_bit.c.inc | 212 ++ target/loongarch/insn_trans/trans_branch.c.inc | 83 + target/loongarch/insn_trans/trans_extra.c.inc | 101 + target/loongarch/insn_trans/trans_farith.c.inc | 105 + target/loongarch/insn_trans/trans_fcmp.c.inc | 56 + target/loongarch/insn_trans/trans_fcnv.c.inc | 33 + target/loongarch/insn_trans/trans_fmemory.c.inc | 153 + target/loongarch/insn_trans/trans_fmov.c.inc | 157 + target/loongarch/insn_trans/trans_memory.c.inc | 229 ++ target/loongarch/insn_trans/trans_privileged.c.inc | 466 +++ target/loongarch/insn_trans/trans_shift.c.inc | 106 + target/loongarch/insns.decode | 486 ++++ target/loongarch/internals.h | 56 + target/loongarch/iocsr_helper.c | 67 + target/loongarch/machine.c | 102 + target/loongarch/meson.build | 30 + target/loongarch/op_helper.c | 133 + target/loongarch/tlb_helper.c | 763 +++++ target/loongarch/translate.c | 281 ++ target/loongarch/translate.h | 45 + target/meson.build | 1 + target/riscv/cpu.c | 68 +- target/riscv/cpu.h | 4 + target/riscv/cpu_helper.c | 4 +- target/riscv/debug.c | 2 + target/riscv/insn_trans/trans_rvm.c.inc | 18 +- target/riscv/insn_trans/trans_rvv.c.inc | 106 +- target/riscv/internals.h | 6 +- target/riscv/translate.c | 4 + target/riscv/vector_helper.c | 1588 ++++++---- target/s390x/ioinst.c | 2 +- tests/Makefile.include | 48 +- tests/avocado/avocado_qemu/__init__.py | 11 +- tests/avocado/replay_linux.py | 85 +- tests/avocado/virtio_check_params.py | 1 - tests/avocado/virtio_version.py | 1 - tests/docker/dockerfiles/debian10.docker | 1 + tests/requirements.txt | 1 + tests/tcg/loongarch64/Makefile.softmmu-target | 33 + tests/tcg/loongarch64/system/boot.S | 56 + tests/tcg/loongarch64/system/kernel.ld | 30 + tests/tcg/loongarch64/system/regdef.h | 86 + tests/tcg/x86_64/system/boot.S | 2 +- tests/vm/Makefile.include | 13 +- tests/vm/basevm.py | 6 +- util/async.c | 8 + 202 files changed, 15751 insertions(+), 4650 deletions(-) create mode 100644 configs/devices/loongarch64-softmmu/default.mak create mode 100644 configs/targets/loongarch64-softmmu.mak create mode 100644 docs/devel/replay.rst delete mode 100644 docs/devel/replay.txt delete mode 100644 docs/replay.txt create mode 100644 docs/system/loongarch/loongson3.rst create mode 100644 docs/system/replay.rst create mode 100644 gdb-xml/loongarch-base64.xml create mode 100644 gdb-xml/loongarch-fpu64.xml create mode 100644 hw/intc/loongarch_extioi.c create mode 100644 hw/intc/loongarch_ipi.c create mode 100644 hw/intc/loongarch_pch_msi.c create mode 100644 hw/intc/loongarch_pch_pic.c create mode 100644 hw/loongarch/Kconfig create mode 100644 hw/loongarch/loongson3.c create mode 100644 hw/loongarch/meson.build create mode 100644 hw/rtc/ls7a_rtc.c create mode 100644 include/hw/intc/loongarch_extioi.h create mode 100644 include/hw/intc/loongarch_ipi.h create mode 100644 include/hw/intc/loongarch_pch_msi.h create mode 100644 include/hw/intc/loongarch_pch_pic.h create mode 100644 include/hw/loongarch/virt.h create mode 100644 include/hw/pci-host/ls7a.h create mode 100644 target/arm/ptw.c create mode 100644 target/arm/sve_ldst_internal.h create mode 100644 target/loongarch/Kconfig create mode 100644 target/loongarch/README create mode 100644 target/loongarch/constant_timer.c create mode 100644 target/loongarch/cpu-csr.h create mode 100644 target/loongarch/cpu-param.h create mode 100644 target/loongarch/cpu.c create mode 100644 target/loongarch/cpu.h create mode 100644 target/loongarch/csr_helper.c create mode 100644 target/loongarch/disas.c create mode 100644 target/loongarch/fpu_helper.c create mode 100644 target/loongarch/gdbstub.c create mode 100644 target/loongarch/helper.h create mode 100644 target/loongarch/insn_trans/trans_arith.c.inc create mode 100644 target/loongarch/insn_trans/trans_atomic.c.inc create mode 100644 target/loongarch/insn_trans/trans_bit.c.inc create mode 100644 target/loongarch/insn_trans/trans_branch.c.inc create mode 100644 target/loongarch/insn_trans/trans_extra.c.inc create mode 100644 target/loongarch/insn_trans/trans_farith.c.inc create mode 100644 target/loongarch/insn_trans/trans_fcmp.c.inc create mode 100644 target/loongarch/insn_trans/trans_fcnv.c.inc create mode 100644 target/loongarch/insn_trans/trans_fmemory.c.inc create mode 100644 target/loongarch/insn_trans/trans_fmov.c.inc create mode 100644 target/loongarch/insn_trans/trans_memory.c.inc create mode 100644 target/loongarch/insn_trans/trans_privileged.c.inc create mode 100644 target/loongarch/insn_trans/trans_shift.c.inc create mode 100644 target/loongarch/insns.decode create mode 100644 target/loongarch/internals.h create mode 100644 target/loongarch/iocsr_helper.c create mode 100644 target/loongarch/machine.c create mode 100644 target/loongarch/meson.build create mode 100644 target/loongarch/op_helper.c create mode 100644 target/loongarch/tlb_helper.c create mode 100644 target/loongarch/translate.c create mode 100644 target/loongarch/translate.h create mode 100644 tests/tcg/loongarch64/Makefile.softmmu-target create mode 100644 tests/tcg/loongarch64/system/boot.S create mode 100644 tests/tcg/loongarch64/system/kernel.ld create mode 100644 tests/tcg/loongarch64/system/regdef.h -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allnoconfig updated (d4a7d2397d6 -> 37499ac6dca)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allnoconfig in repository toolchain/ci/gcc. from d4a7d2397d6 Daily bump. adds 261440b7372 Daily bump. adds 1908e200078 Daily bump. adds c45a9752f15 Fix insn does not satisfy its constraints: sse2_lshrv1ti3 adds 64f5d58d815 libstdc++: Only include <ext/atomicity.h> for COW string adds 6666ca1ab44 libstdc++: Fix narrowing conversions for 16-bit size_t [PR105681] adds d47c4f0f1da libstdc++: Mark non-exported function always_inline [PR105671] adds 777a80af43e gcc: xtensa: fix PR target/105879 adds e057d454db4 c++: redeclared hidden friend take 2 [PR105852] adds 669fc7629eb Daily bump. adds 94f9c03b99f Update gcc sv.po adds 37499ac6dca Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 17 + gcc/DATESTAMP | 2 +- gcc/config/i386/sse.md | 6 +- gcc/config/xtensa/xtensa.md | 13 +- gcc/cp/ChangeLog | 10 + gcc/cp/cp-tree.h | 1 + gcc/cp/decl.cc | 16 +- gcc/cp/pt.cc | 29 +- gcc/po/ChangeLog | 4 + gcc/po/sv.po | 1530 ++++---------------- gcc/testsuite/ChangeLog | 7 + gcc/testsuite/g++.dg/modules/tpl-friend-2_a.C | 2 +- gcc/testsuite/g++.dg/template/friend74.C | 8 + libstdc++-v3/ChangeLog | 30 + libstdc++-v3/include/bits/basic_string.h | 1 - libstdc++-v3/include/bits/cow_string.h | 2 + .../resize_policy/hash_prime_size_policy_imp.hpp | 18 +- libstdc++-v3/include/ext/random | 2 + libstdc++-v3/include/std/sstream | 1 + 19 files changed, 446 insertions(+), 1253 deletions(-) create mode 100644 gcc/testsuite/g++.dg/template/friend74.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allnoconfig updated (c86fbb1d88 -> fe36d34f25)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allnoconfig in repository toolchain/ci/binutils-gdb. from c86fbb1d88 Automatic date update in version.in adds d61f79dc47 Automatic date update in version.in adds 884e81eeb2 Automatic date update in version.in adds 0dae8bed68 Automatic date update in version.in adds fe36d34f25 Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allnoconfig updated (39c1e19ad -> e6ce34215)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allnoconfig in repository toolchain/ci/base-artifacts. discards 39c1e19ad 0: update: binutils-gcc-linux-qemu: all new e6ce34215 0: update: binutils-gcc-linux-qemu: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (39c1e19ad) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1552 -> 1556 bytes 02-prepare_abe/console.log.xz | Bin 2732 -> 2736 bytes 03-build_abe-binutils/console.log.xz | Bin 29916 -> 30060 bytes 04-build_abe-stage1/console.log.xz | Bin 85504 -> 86068 bytes 05-build_abe-qemu/console.log.xz | Bin 31928 -> 32060 bytes 06-build_linux/console.log.xz | Bin 3596 -> 3560 bytes 07-boot_linux/console.log.xz | Bin 496 -> 496 bytes 08-check_regression/console.log.xz | Bin 412 -> 412 bytes 09-update_baseline/console.log | 10 +++++----- jenkins/manifest.sh | 18 +++++++++--------- 10 files changed, 14 insertions(+), 14 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap updated (6a72edd8e2 -> 80c0a3bf1b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap in repository toolchain/ci/binutils-gdb. from 6a72edd8e2 [gdb/testsuite] Fix XPASS with gcc-12 in gdb.base/vla-struct [...] adds 3abc1d8fe0 Document the ARM_CC_FOR_TARGET testsuite variable adds 80c0a3bf1b gdb/testsuite: remove definition of true/false from gdb_comp [...] No new revisions were added by this update. Summary of changes: gdb/testsuite/README | 30 ++++++++++++++++++++++++++++++ gdb/testsuite/gdb.base/all-bin.exp | 4 ++++ gdb/testsuite/gdb.base/eval-skip.exp | 3 +++ gdb/testsuite/gdb.base/exprs.exp | 4 ++++ gdb/testsuite/gdb.base/miscexprs.exp | 3 +++ gdb/testsuite/gdb.base/pointers.exp | 4 ++++ gdb/testsuite/gdb.base/relational.exp | 4 ++++ gdb/testsuite/lib/gdb.exp | 5 ----- 8 files changed, 52 insertions(+), 5 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap updated (ef78c2755 -> d6a7df1f8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap in repository toolchain/ci/base-artifacts. discards ef78c2755 0: update: binutils-gcc: 2 new d6a7df1f8 0: update: binutils-gcc: 2 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (ef78c2755) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_bootstrap/master-aar [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1688 -> 1536 bytes 02-prepare_abe/console.log.xz | Bin 2732 -> 2700 bytes 04-build_abe-binutils/console.log.xz | Bin 38444 -> 38524 bytes 05-build_abe-bootstrap/console.log.xz | Bin 270196 -> 269764 bytes 06-check_regression/console.log.xz | Bin 416 -> 416 bytes 07-update_baseline/console.log | 36 ---------------------------------- jenkins/manifest.sh | 8 ++++---- 7 files changed, 4 insertions(+), 40 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_profiled_lto_lean updated (02b4e2de320 -> e3bba42fb5d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_profiled_lto_lean in repository toolchain/ci/gcc. from 02b4e2de320 Daily bump. adds 2fc6e3d55f6 This patch replaces shift and ior insns with one rotate and [...] adds 269edf4e5e6 Update {skylake,icelake,alderlake}_cost to add a bit prefer [...] adds 17f52a1c725 openmp: Add support for HBW or large capacity or interleave [...] adds 2dc19a1b590 doc: Fix up -Waddress documentation adds 209de00fdb9 OpenMP: Handle ancestor:1 with discover_declare_target adds 97b81fb0363 c++: Better module initializer code adds 702a11ade2e RISC-V: Use a tab rather than space with FSFLAGS adds 4c334e0e4ff c++: Fix up ICE on __builtin_shufflevector constexpr evalua [...] adds 699e9a0f671 openmp: Fix up include of the generic allocator.c adds a05aac0a130 rs6000: Delete FP_ISA3 adds 64584863452 Update gcc sv.po adds 2fcc69d8ce4 xtensa: Implement bswaphi2 insn pattern adds 9777d446e21 xtensa: Make one_cmplsi2 optimizer-friendly adds e44e7face13 xtensa: Optimize '(~x & y)' to '((x & y) ^ y)' adds 29dc90a580b xtensa: Add clrsbsi2 insn pattern adds e3bba42fb5d Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 65 + gcc/DATESTAMP | 2 +- gcc/config/i386/x86-tune-costs.h | 26 +- gcc/config/riscv/riscv.md | 4 +- gcc/config/rs6000/rs6000.md | 43 +- gcc/config/xtensa/xtensa.md | 68 +- gcc/cp/ChangeLog | 23 + gcc/cp/constexpr.cc | 13 +- gcc/cp/cp-tree.h | 3 +- gcc/cp/decl2.cc | 32 +- gcc/cp/module.cc | 23 +- gcc/doc/invoke.texi | 4 +- gcc/omp-offload.cc | 21 +- gcc/po/ChangeLog | 4 + gcc/po/sv.po | 1530 ++++---------------- gcc/testsuite/ChangeLog | 35 + .../c-c++-common/gomp/reverse-offload-1.c | 93 ++ gcc/testsuite/g++.dg/modules/init-2_a.C | 2 + gcc/testsuite/g++.dg/modules/init-2_b.C | 2 + gcc/testsuite/g++.dg/pr105871.C | 12 + gcc/testsuite/g++.target/i386/pr105638.C | 3 +- gcc/testsuite/gcc.target/i386/pr105493.c | 51 + gcc/testsuite/gcc.target/i386/pr91446.c | 2 +- gcc/testsuite/gcc.target/i386/pr99881.c | 2 +- gcc/testsuite/gcc.target/powerpc/pr93453-1.c | 14 + gcc/testsuite/gcc.target/xtensa/check_zero_byte.c | 9 + gcc/testsuite/gcc.target/xtensa/one_cmpl_abs.c | 9 + libgcc/ChangeLog | 5 + libgcc/config/xtensa/lib1funcs.S | 23 + libgcc/config/xtensa/t-xtensa | 2 +- libgomp/ChangeLog | 19 + libgomp/allocator.c | 365 ++++- libgomp/config/linux/allocator.c | 36 + 33 files changed, 1210 insertions(+), 1335 deletions(-) create mode 100644 gcc/testsuite/c-c++-common/gomp/reverse-offload-1.c create mode 100644 gcc/testsuite/g++.dg/pr105871.C create mode 100644 gcc/testsuite/gcc.target/i386/pr105493.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr93453-1.c create mode 100644 gcc/testsuite/gcc.target/xtensa/check_zero_byte.c create mode 100644 gcc/testsuite/gcc.target/xtensa/one_cmpl_abs.c create mode 100644 libgomp/config/linux/allocator.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_profiled_lto_lean updated (d21691eaa7 -> f460ede603)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_profiled_lto_lean in repository toolchain/ci/binutils-gdb. from d21691eaa7 Automatic date update in version.in adds 417d2514ef gdb/testsuite: resolve duplicate test name in gnu_vector.exp adds b1054b67df gdb/testsuite: resolve duplicate test names in gdb.threads/tls.exp adds 8f4141b0ae gdb: add Yvan Roux to gdb/MAINTAINERS adds 61ee7510b3 gdb/testsuite: use test_compiler_info in gcc_major_version adds 1562f64fec gdb/testsuite: remove get_compiler_info calls from gdb.exp a [...] adds 08b326ee0a gdb/testsuite: make 'c' default language for get/test compiler info adds 0e471fde07 gdb/testsuite: handle errors better in test_compiler_info adds 575a212a78 gdb/testsuite: solve problems with compiler_info caching adds 148ca9dd5c gdb/arm: Terminate unwinding when LR is 0xffffffff adds 8db775b211 Fix ARM_CC_FOR_TARGET handling adds 1ef3351b7b gdb/arm: Simplify logic for updating addresses adds 2d9cf99d9a gdb/arm: Document and fix exception stack offsets adds 396d2e56be gdb/aarch64: fix 32-bit arm compatibility adds 1c76a0e2a6 Minor fix to Python breakpoint event documentation adds f460ede603 Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- gdb/MAINTAINERS | 1 + gdb/aarch64-linux-nat.c | 114 +++++++++++++++++++++++++++++----- gdb/arm-tdep.c | 85 ++++++++++++++++++++++--- gdb/doc/python.texi | 6 +- gdb/testsuite/gdb.base/gnu_vector.exp | 20 +++--- gdb/testsuite/gdb.threads/tls.exp | 5 +- gdb/testsuite/lib/dwarf.exp | 8 --- gdb/testsuite/lib/gdb.exp | 91 ++++++++++++++------------- 9 files changed, 242 insertions(+), 90 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_profiled_lto_lean updated (2ade40b2e -> 59651bb3f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_profiled_lto_lean in repository toolchain/ci/base-artifacts. discards 2ade40b2e 0: update: binutils-gcc: 2 new 59651bb3f 0: update: binutils-gcc: 2 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (2ade40b2e) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_bootstrap/master-aar [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1524 -> 1588 bytes 02-prepare_abe/console.log.xz | Bin 2704 -> 2728 bytes 04-build_abe-binutils/console.log.xz | Bin 38100 -> 37768 bytes .../console.log.xz | Bin 520632 -> 520176 bytes 06-check_regression/console.log.xz | Bin 416 -> 416 bytes 07-update_baseline/console.log | 22 ++++++++++++++------- jenkins/manifest.sh | 14 ++++++------- 7 files changed, 22 insertions(+), 14 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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Tcwg-commits June 2022