Tcwg-commits June 2022

tcwg-commits@lists.linaro.org

4 participants
14714 discussions

[gcc] branch releases/gcc-11 updated (27803acc33b -> 3f1637f8b17)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch releases/gcc-11 in repository gcc. from 27803acc33b Daily bump. new 3f1637f8b17 ipa-icf: skip variables with body_removed The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ipa-icf.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-allmodconfig updated (a28498b1f9 -> 2b049d2c8d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-allmodconfig in repository toolchain/ci/qemu. from a28498b1f9 Merge tag 'for_upstream' of git://git.kernel.org/pub/scm/vir [...] adds 77d3522b3f bsd-user: Implement open, openat and close adds a2ba6c7b80 bsd-user: Implement fdatasync, fsync and close_from adds 65c6c4c893 bsd-user: Implement revoke, access, eaccess and faccessat adds 390f547ea8 bsd-user: Implement chdir and fchdir adds ab5fd2d969 bsd-user: Implement rename and renameat adds 2d3b7e01d6 bsd-user: Implement link, linkat, unlink and unlinkat adds 1ffbd5e7fe bsd-user: Implement mkdir and mkdirat adds 6af8f76a9f bsd-user: Implement rmdir and undocumented __getcwd adds a15699acaf bsd-user: Implement dup and dup2 adds 4b795b147b bsd-user: Implement trunctate and ftruncate adds d35020ed00 bsd-user: Implement acct and sync adds c8b2d41376 Merge tag 'bsd-user-syscall-2022q2-pull-request' of ssh://gi [...] adds 61f302615a target/ppc: Implemented vector divide instructions adds 1700f2bf97 target/ppc: Implemented vector divide quadword adds 9a1f0866a3 target/ppc: Implemented vector divide extended word adds 4724bbd284 host-utils: Implemented unsigned 256-by-128 division adds 62c9947fb7 host-utils: Implemented signed 256-by-128 division adds a173ba88be target/ppc: Implemented remaining vector divide extended adds 5adb27cd8f target/ppc: Implemented vector module word/doubleword adds b80bec3a07 target/ppc: Implemented vector module quadword adds 453eb94c76 ppc: fix boot with sam460ex adds 8f7d41e0c9 target/ppc: fix vbpermd in big endian hosts adds 151308677c pnv/xive2: Access direct mapped thread contexts from all chips adds 78d6b5d33a ppc/pnv: fix extra indent spaces with DEFINE_PROP* adds feeef6b6dd target/ppc: avoid int32 multiply overflow in int_helper.c adds 5980167e07 target/ppc: fix unreachable code in fpu_helper.c adds 609b1c8669 target/ppc: cpu_init: Clean up stop state on cpu reset adds 5cdcfd861e Merge tag 'pull-ppc-20220621' of https://gitlab.com/danielhb [...] adds 4d5738222f tcg/ppc: implement rem[u]_i{32,64} with mod[su][wd] adds adb5974dcc target/avr: Drop avr_cpu_memory_rw_debug() adds a82fd5a4ec accel/tcg: Init TCG cflags in vCPU thread handler adds 18b8c47f8e accel/tcg: Reorganize tcg_accel_ops_init() adds 3f42906c9a qemu-timer: Skip empty timer lists before locking in qemu_cl [...] adds 418ade7849 softmmu: Always initialize xlat in address_space_translate_f [...] adds 7971375287 util: Merge cacheflush.c and cacheinfo.c adds bdd50dc7d0 util/cacheflush: Merge aarch64 ctr_el0 usage adds c79a8e840c util/cacheflush: Optimize flushing when ppc host has coheren [...] adds f200ff158d Merge tag 'pull-tcg-20220621' of https://gitlab.com/rth7680/ [...] adds f4c155dddb aspeed: Remove fake RTC device on ast2500-evb adds 341e21fa13 test/avocado/machine_aspeed.py: Move OpenBMC tests adds f7bc7da072 test/avocado/machine_aspeed.py: Add tests using buildroot images adds 7a7308eae0 test/avocado/machine_aspeed.py: Add I2C tests to ast2500-evb adds 61cf757d15 test/avocado/machine_aspeed.py: Add I2C tests to ast2600-evb adds 3302184f7f test/avocado/machine_aspeed.py: Add an I2C RTC test adds 4a71d6d32e hw/registerfields: Add shared fields macros adds 3be3d6ccf2 aspeed: i2c: Migrate to registerfields API adds 2260fc6ff3 aspeed: i2c: Use reg array instead of individual vars adds ba2cccd64e aspeed: i2c: Add new mode support adds 0efec47b5f aspeed: i2c: Add PKT_DONE IRQ to trace adds e532cd0485 aspeed: i2c: Move regs and helpers to header file adds b35802ce31 aspeed/i2c: Add ast1030 controller models adds 4c70ab168d aspeed: Add I2C buses to AST1030 model adds b03ec4ff06 hw/i2c/aspeed: rework raise interrupt trace event adds d72a712ce0 hw/i2c/aspeed: add DEV_ADDR in old register mode adds 33e30f11c7 aspeed/i2c: Enable SLAVE_ADDR_RX_MATCH always adds 87893cb5f5 aspeed/hace: Add missing newlines to unimp messages adds 92a45bde8c hw: m25p80: fixing individual test failure when tests are ru [...] adds 2b049d2c8d Merge tag 'pull-aspeed-20220622' of https://github.com/legoa [...] No new revisions were added by this update. Summary of changes: accel/tcg/tcg-accel-ops-mttcg.c | 5 +- accel/tcg/tcg-accel-ops-rr.c | 7 +- accel/tcg/tcg-accel-ops.c | 15 +- bsd-user/bsd-file.h | 359 ++++++++++++++++ bsd-user/freebsd/os-syscall.c | 116 +++++ bsd-user/syscall_defs.h | 4 + hw/arm/aspeed.c | 17 +- hw/arm/aspeed_ast10x0.c | 18 + hw/i2c/aspeed_i2c.c | 820 ++++++++++++++++++++++-------------- hw/i2c/trace-events | 2 +- hw/intc/pnv_xive2.c | 18 +- hw/misc/aspeed_hace.c | 4 +- hw/pci-host/pnv_phb3.c | 8 +- hw/pci-host/pnv_phb4.c | 10 +- hw/pci-host/pnv_phb4_pec.c | 10 +- hw/ppc/ppc440_uc.c | 8 + include/hw/i2c/aspeed_i2c.h | 289 ++++++++++++- include/hw/registerfields.h | 70 +++ include/qemu/host-utils.h | 3 + include/qemu/int128.h | 38 ++ softmmu/physmem.c | 13 +- target/avr/cpu.c | 1 - target/avr/cpu.h | 2 - target/avr/helper.c | 6 - target/ppc/cpu_init.c | 3 + target/ppc/fpu_helper.c | 2 +- target/ppc/helper.h | 8 + target/ppc/insn32.decode | 23 + target/ppc/int_helper.c | 116 ++++- target/ppc/translate/vmx-impl.c.inc | 151 +++++++ tcg/ppc/tcg-target.c.inc | 22 + tcg/ppc/tcg-target.h | 4 +- tests/avocado/boot_linux_console.py | 43 -- tests/avocado/machine_aspeed.py | 136 ++++++ tests/qtest/aspeed_smc-test.c | 74 +++- util/cacheflush.c | 247 ++++++++++- util/cacheinfo.c | 200 --------- util/host-utils.c | 180 ++++++++ util/meson.build | 2 +- util/qemu-timer.c | 3 + 40 files changed, 2412 insertions(+), 645 deletions(-) delete mode 100644 util/cacheinfo.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-allmodconfig updated (c12386ae247c -> f28c006a5895)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-allmodconfig in repository toolchain/ci/llvm-project. from c12386ae247c [MC][AArch64] Enable '+v8a' when nothing specified for MCS [...] adds ec42d3c069c7 [AVR] Add more devices adds aa586b6f5f55 [clang][AVR] Implement standard calling convention for AVR [...] adds f28c006a5895 Bump version to 14.0.6 No new revisions were added by this update. Summary of changes: clang/lib/Basic/Targets/AVR.cpp | 543 +++++++++++---------- clang/lib/Driver/ToolChains/AVR.cpp | 17 + clang/test/Misc/target-invalid-cpu-note.c | 2 +- libcxx/CMakeLists.txt | 2 +- libcxxabi/CMakeLists.txt | 2 +- libunwind/CMakeLists.txt | 2 +- llvm/CMakeLists.txt | 2 +- llvm/lib/Target/AVR/AVRDevices.td | 16 + llvm/utils/gn/secondary/llvm/version.gni | 2 +- llvm/utils/lit/lit/__init__.py | 2 +- llvm/utils/release/build_llvm_package.bat | 4 +- .../llvm/include/llvm/Config/llvm-config.h | 2 +- 12 files changed, 322 insertions(+), 274 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-allmodconfig updated (5cc2bdc75b -> eed56ee299)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-allmodconfig in repository toolchain/ci/binutils-gdb. from 5cc2bdc75b Automatic date update in version.in adds f0b5a0b568 Automatic date update in version.in adds 6b2a26c63b Automatic date update in version.in adds 8e001ed8f2 Automatic date update in version.in adds eed56ee299 Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-allmodconfig updated (a2a09602 -> fa3f5b6f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-stable-allmodconfig in repository toolchain/ci/base-artifacts. discards a2a09602 2: update: binutils-llvm-linux-qemu: 22465 new fa3f5b6f 2: update: binutils-llvm-linux-qemu: 22465 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (a2a09602) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-arm- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1580 -> 1564 bytes 02-prepare_abe/console.log.xz | Bin 2732 -> 2732 bytes 03-build_abe-binutils/console.log.xz | Bin 30004 -> 30048 bytes 04-build_kernel_llvm/console.log.xz | Bin 60936 -> 61848 bytes 05-build_abe-qemu/console.log.xz | Bin 32460 -> 32704 bytes 06-build_linux/console.log.xz | Bin 5104 -> 5260 bytes 08-check_regression/console.log.xz | Bin 480 -> 484 bytes 09-update_baseline/console.log | 130 +++++++++++++++++------------------ jenkins/manifest.sh | 16 ++--- 9 files changed, 73 insertions(+), 73 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years

[toolchain/ci/gdb] branch linaro-local/ci/tcwg_gnu_native_check_binutils/master-arm updated (4491a7c1aa -> 570e911f4e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_native_check_binutils/master-arm in repository toolchain/ci/gdb. from 4491a7c1aa readelf: replace xmalloc with malloc in slurp_relr_relocs adds b215cdf529 RISC-V: Fix inconsistent error message (range) adds dd8cc00cac RISC-V: Prepare i18n for required ISA extensions adds 1176bc3876 RISC-V: Add 'H' to canonical extension ordering adds c625f4ed05 RISC-V: Use single h extension to control hypervisor CSRs an [...] adds afc41ffb99 RISC-V: Reorder the prefixed extensions which are out of order. adds f18acc9c4e Binutils support for split-dwarf and dwarf-5 adds 90b7a5df15 aarch64: Disallow copy relocations on protected data adds 3af607d998 Use unique_xmalloc_ptr in interp adds ee04bfc01e Move mi_interpreter to mi-interp.h adds b2a696a881 Use std::string for interpreter_p adds 325600eb11 Automatic date update in version.in adds 4fb55bf6a9 aarch64: Define elf_backend_extern_protected_data to 0 [PR 18705] adds 83c325007c aarch64: Allow PC-relative relocations against protected STT [...] new ecc741e64e Re: PowerPC64: stub debug dump new 570e911f4e PowerPC64: fix assertion in ppc_build_one_stub with -Os code The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: bfd/elf64-ppc.c | 103 +++++++++++++-------- bfd/elfnn-aarch64.c | 32 ++++++- bfd/elfxx-riscv.c | 68 ++++---------- bfd/version.h | 2 +- binutils/ChangeLog | 13 ++- binutils/dwarf.c | 57 +++++++++--- binutils/dwarf.h | 1 + gas/config/tc-riscv.c | 12 ++- gas/testsuite/gas/riscv/csr-version-1p10.d | 100 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p10.l | 100 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p11.d | 100 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p11.l | 100 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p12.l | 50 ++++++++++ gas/testsuite/gas/riscv/csr-version-1p9p1.d | 100 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p9p1.l | 100 ++++++++++---------- gas/testsuite/gas/riscv/h-ext-32.d | 2 +- gas/testsuite/gas/riscv/h-ext-64.d | 2 +- gas/testsuite/gas/riscv/march-fail-order-x-z.d | 3 - gas/testsuite/gas/riscv/march-fail-order-x-z.l | 2 - gas/testsuite/gas/riscv/march-fail-order-x.d | 3 - gas/testsuite/gas/riscv/march-fail-order-x.l | 2 - gas/testsuite/gas/riscv/march-fail-order-z.d | 3 - gas/testsuite/gas/riscv/march-fail-order-z.l | 2 - .../gas/riscv/march-fail-single-prefix-h.d | 3 - gas/testsuite/gas/riscv/march-fail-unknown-h.d | 3 - gdb/interps.c | 15 +-- gdb/interps.h | 10 +- gdb/main.c | 24 ++--- gdb/main.h | 2 +- gdb/mi/mi-common.h | 50 ---------- gdb/mi/mi-interp.h | 50 ++++++++++ gdb/mi/mi-main.c | 2 +- gdb/tui/tui-interp.c | 9 +- include/opcode/riscv-opc.h | 50 +++++----- include/opcode/riscv.h | 1 + ld/testsuite/ld-aarch64/aarch64-elf.exp | 10 ++ ld/testsuite/ld-aarch64/copy-reloc-protected.d | 2 + ld/testsuite/ld-aarch64/pcrel-protected.s | 11 +++ ld/testsuite/ld-aarch64/pcrel_pic_protected.d | 7 ++ ld/testsuite/ld-aarch64/protected-data.d | 2 +- ld/testsuite/ld-aarch64/protected.s | 8 ++ opcodes/riscv-opc.c | 38 ++++---- 42 files changed, 686 insertions(+), 568 deletions(-) delete mode 100644 gas/testsuite/gas/riscv/march-fail-order-x-z.d delete mode 100644 gas/testsuite/gas/riscv/march-fail-order-x-z.l delete mode 100644 gas/testsuite/gas/riscv/march-fail-order-x.d delete mode 100644 gas/testsuite/gas/riscv/march-fail-order-x.l delete mode 100644 gas/testsuite/gas/riscv/march-fail-order-z.d delete mode 100644 gas/testsuite/gas/riscv/march-fail-order-z.l delete mode 100644 gas/testsuite/gas/riscv/march-fail-single-prefix-h.d delete mode 100644 gas/testsuite/gas/riscv/march-fail-unknown-h.d create mode 100644 ld/testsuite/ld-aarch64/copy-reloc-protected.d create mode 100644 ld/testsuite/ld-aarch64/pcrel-protected.s create mode 100644 ld/testsuite/ld-aarch64/pcrel_pic_protected.d create mode 100644 ld/testsuite/ld-aarch64/protected.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years

[toolchain/ci/glibc] branch linaro-local/ci/tcwg_gnu_native_check_binutils/master-arm updated (2249ec60a9 -> 3079f652d7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_native_check_binutils/master-arm in repository toolchain/ci/glibc. from 2249ec60a9 s390: use LC_ALL=C for readelf call adds dc30acf20b debug: make __read_chk a cancellation point (bug 29274) adds dd06af4f81 stdlib: Remove trailing whitespace from Makefile adds 464d189b96 stdlib: Remove attr_write from mbstows if dst is NULL [BZ: 29265] adds 703f434108 x86: Add defines / utilities for making ISA specific x86 builds adds 3edda6a0f0 x86: Add support for compiling {raw|w}memchr with high ISA level adds 3079f652d7 x86: Replace all sse instructions with vex equivilent in avx+ files No new revisions were added by this update. Summary of changes: debug/Makefile | 7 + debug/read_chk.c | 10 - .../tst-read-chk-cancel.c | 33 +- stdlib/Makefile | 5 +- stdlib/bits/stdlib.h | 16 +- stdlib/testmb.c | 7 + sysdeps/x86/init-arch.h | 4 +- sysdeps/x86/isa-ifunc-macros.h | 70 ++++ sysdeps/x86/isa-level.c | 17 +- sysdeps/x86/isa-level.h | 102 ++++++ .../x86_64/fpu/multiarch/svml_d_acos4_core_avx2.S | 4 +- .../fpu/multiarch/svml_d_acos8_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_d_acosh4_core_avx2.S | 4 +- .../fpu/multiarch/svml_d_acosh8_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_d_asin4_core_avx2.S | 4 +- .../fpu/multiarch/svml_d_asin8_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_d_asinh4_core_avx2.S | 4 +- .../fpu/multiarch/svml_d_asinh8_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_d_atan24_core_avx2.S | 6 +- .../fpu/multiarch/svml_d_atan28_core_avx512.S | 6 +- .../x86_64/fpu/multiarch/svml_d_atanh4_core_avx2.S | 4 +- .../fpu/multiarch/svml_d_atanh8_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_d_cbrt4_core_avx2.S | 4 +- .../x86_64/fpu/multiarch/svml_d_cosh4_core_avx2.S | 4 +- .../fpu/multiarch/svml_d_cosh8_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_d_erfc4_core_avx2.S | 4 +- .../fpu/multiarch/svml_d_erfc8_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_d_exp104_core_avx2.S | 4 +- .../fpu/multiarch/svml_d_exp108_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_d_exp24_core_avx2.S | 4 +- .../fpu/multiarch/svml_d_exp28_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_d_expm14_core_avx2.S | 4 +- .../fpu/multiarch/svml_d_expm18_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_d_hypot4_core_avx2.S | 6 +- .../fpu/multiarch/svml_d_hypot8_core_avx512.S | 6 +- .../x86_64/fpu/multiarch/svml_d_log104_core_avx2.S | 4 +- .../fpu/multiarch/svml_d_log108_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_d_log1p4_core_avx2.S | 4 +- .../fpu/multiarch/svml_d_log1p8_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_d_log24_core_avx2.S | 4 +- .../fpu/multiarch/svml_d_log28_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_d_sinh4_core_avx2.S | 4 +- .../fpu/multiarch/svml_d_sinh8_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_d_tan4_core_avx2.S | 4 +- .../x86_64/fpu/multiarch/svml_d_tan8_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_d_tanh4_core_avx2.S | 6 +- .../fpu/multiarch/svml_d_tanh8_core_avx512.S | 4 +- .../fpu/multiarch/svml_s_acosf16_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_s_acosf8_core_avx2.S | 4 +- .../fpu/multiarch/svml_s_acoshf16_core_avx512.S | 4 +- .../fpu/multiarch/svml_s_acoshf8_core_avx2.S | 4 +- .../fpu/multiarch/svml_s_asinf16_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_s_asinf8_core_avx2.S | 4 +- .../fpu/multiarch/svml_s_asinhf16_core_avx512.S | 4 +- .../fpu/multiarch/svml_s_asinhf8_core_avx2.S | 4 +- .../fpu/multiarch/svml_s_atan2f16_core_avx512.S | 6 +- .../fpu/multiarch/svml_s_atan2f8_core_avx2.S | 6 +- .../fpu/multiarch/svml_s_atanhf16_core_avx512.S | 4 +- .../fpu/multiarch/svml_s_atanhf8_core_avx2.S | 4 +- .../x86_64/fpu/multiarch/svml_s_cbrtf8_core_avx2.S | 4 +- .../fpu/multiarch/svml_s_coshf16_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_s_coshf8_core_avx2.S | 4 +- .../fpu/multiarch/svml_s_erfcf16_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_s_erfcf8_core_avx2.S | 4 +- .../fpu/multiarch/svml_s_exp10f16_core_avx512.S | 4 +- .../fpu/multiarch/svml_s_exp10f8_core_avx2.S | 4 +- .../fpu/multiarch/svml_s_exp2f16_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_s_exp2f8_core_avx2.S | 4 +- .../fpu/multiarch/svml_s_expm1f16_core_avx512.S | 4 +- .../fpu/multiarch/svml_s_expm1f8_core_avx2.S | 4 +- .../fpu/multiarch/svml_s_hypotf16_core_avx512.S | 6 +- .../fpu/multiarch/svml_s_hypotf8_core_avx2.S | 6 +- .../fpu/multiarch/svml_s_log10f16_core_avx512.S | 4 +- .../fpu/multiarch/svml_s_log10f8_core_avx2.S | 4 +- .../fpu/multiarch/svml_s_log1pf16_core_avx512.S | 4 +- .../fpu/multiarch/svml_s_log1pf8_core_avx2.S | 4 +- .../fpu/multiarch/svml_s_log2f16_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_s_log2f8_core_avx2.S | 4 +- .../fpu/multiarch/svml_s_sinhf16_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_s_sinhf8_core_avx2.S | 4 +- .../fpu/multiarch/svml_s_tanf16_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_s_tanf8_core_avx2.S | 4 +- .../fpu/multiarch/svml_s_tanhf16_core_avx512.S | 4 +- .../x86_64/fpu/multiarch/svml_s_tanhf8_core_avx2.S | 4 +- sysdeps/x86_64/isa-default-impl.h | 59 ++++ sysdeps/x86_64/memchr.S | 357 +------------------- sysdeps/x86_64/multiarch/ifunc-evex.h | 29 +- sysdeps/x86_64/multiarch/ifunc-impl-list.c | 72 ++-- sysdeps/x86_64/multiarch/memchr-avx2.S | 5 +- sysdeps/x86_64/multiarch/memchr-evex.S | 5 +- sysdeps/x86_64/multiarch/memchr-sse2.S | 363 ++++++++++++++++++++- sysdeps/x86_64/multiarch/rawmemchr-avx2.S | 7 +- sysdeps/x86_64/multiarch/rawmemchr-evex.S | 7 +- sysdeps/x86_64/multiarch/rawmemchr-sse2.S | 198 ++++++++++- .../multiarch/rtld-memchr.S} | 4 +- .../multiarch/rtld-rawmemchr.S} | 4 +- sysdeps/x86_64/multiarch/strrchr-avx2.S | 2 +- sysdeps/x86_64/multiarch/wmemchr-avx2.S | 7 +- sysdeps/x86_64/multiarch/wmemchr-evex.S | 7 +- sysdeps/x86_64/multiarch/wmemchr-sse2.S | 9 +- sysdeps/x86_64/rawmemchr.S | 184 +---------- .../{pthread/tst-atfork3mod.c => x86_64/wmemchr.S} | 34 +- 102 files changed, 1104 insertions(+), 834 deletions(-) copy sysdeps/pthread/tst-pthread_cancel-exited.c => debug/tst-read-chk-cancel.c (57%) create mode 100644 sysdeps/x86/isa-ifunc-macros.h create mode 100644 sysdeps/x86/isa-level.h create mode 100644 sysdeps/x86_64/isa-default-impl.h copy sysdeps/{powerpc/powerpc64/multiarch/rtld-strcspn.c => x86_64/multiarch/rtld- [...] copy sysdeps/{powerpc/powerpc64/multiarch/rtld-strcspn.c => x86_64/multiarch/rtld- [...] copy sysdeps/{pthread/tst-atfork3mod.c => x86_64/wmemchr.S} (68%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years

[toolchain/ci/linux] branch linaro-local/ci/tcwg_gnu_native_check_binutils/master-arm updated (ca1fdab7fd27 -> de5c208d533a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_native_check_binutils/master-arm in repository toolchain/ci/linux. from ca1fdab7fd27 Merge tag 'efi-urgent-for-v5.19-1' of git://git.kernel.org [...] adds beca774fc51a 9p: fix fid refcount leak in v9fs_vfs_atomic_open_dotl adds e5690f263208 9p: fix fid refcount leak in v9fs_vfs_get_link adds 2a3dcbccd64b 9p: Fix refcounting during full path walks for fid lookups adds b0017602fdf6 9p: fix EBADF errors in cached mode adds 3abc3ae553c7 Merge tag '9p-for-5.19-rc4' of https://github.com/martinetd/linux adds 795285ef2425 selftests: Fix clang cross compilation adds 12a29115be72 selftests dma: fix compile error for dma_map_benchmark adds 3084a4ec7f9b selftests: vm: Fix resource leak when return error adds 9b4d5c01eb23 selftests: make use of GUP_TEST_FILE macro adds de5c208d533a Merge tag 'linux-kselftest-fixes-5.19-rc4' of git://git.ke [...] No new revisions were added by this update. Summary of changes: fs/9p/fid.c | 22 +++++++++------------- fs/9p/vfs_addr.c | 13 +++++++++++++ fs/9p/vfs_inode.c | 8 ++++---- fs/9p/vfs_inode_dotl.c | 3 +++ tools/testing/selftests/dma/Makefile | 1 + tools/testing/selftests/dma/dma_map_benchmark.c | 2 +- tools/testing/selftests/lib.mk | 25 +++++++++++++++++++++++-- tools/testing/selftests/vm/gup_test.c | 4 ++-- tools/testing/selftests/vm/ksm_tests.c | 2 ++ 9 files changed, 58 insertions(+), 22 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu_native_check_binutils/master-arm updated (98b6e62cf5e -> 31ce821a790)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_native_check_binutils/master-arm in repository toolchain/ci/gcc. from 98b6e62cf5e RISC-V: Add -mtune=thead-c906 to the invoke docs adds 038b077689b data-ref: Improve non-loop disambiguation [PR106019] adds d68d3664253 ubsan: default to trap on unreachable at -O0 and -Og [PR104642] adds d844478ab47 c++: Remove ifdefed code adds 445d8deffb6 d: Merge upstream dmd 6203135dc, druntime e150cca1, phobos [...] adds 349a39f0614 c++: class scope function lookup [PR105908] adds 5d0cf158229 Daily bump. adds 3104a9fa7e7 Fix typo adds d29f61a3291 c++: dependence of baselink [PR105964] adds 27e9bd91162 c++: tweak deduction with auto template parms adds 7f52df186de Replace REGNO with reg_or_subregno in pre_reload splitter. adds 31ce821a790 ipa-icf: skip variables with body_removed No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 50 ++++ gcc/DATESTAMP | 2 +- gcc/builtins.cc | 9 + gcc/cgraph.cc | 2 +- gcc/cgraphunit.cc | 3 +- gcc/common.opt | 4 + gcc/config/i386/sse.md | 12 +- gcc/cp/ChangeLog | 18 ++ gcc/cp/constexpr.cc | 29 +- gcc/cp/cp-gimplify.cc | 7 +- gcc/cp/module.cc | 16 +- gcc/cp/name-lookup.cc | 4 + gcc/cp/pt.cc | 11 + gcc/d/ChangeLog | 7 + gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/aggregate.h | 36 ++- gcc/d/dmd/clone.d | 9 +- gcc/d/dmd/denum.d | 14 +- gcc/d/dmd/dstruct.d | 33 ++- gcc/d/dmd/dsymbolsem.d | 29 +- gcc/d/dmd/enum.h | 13 +- gcc/d/dmd/escape.d | 40 ++- gcc/d/dmd/expression.d | 2 +- gcc/d/dmd/func.d | 21 +- gcc/d/dmd/parse.d | 4 +- gcc/d/dmd/statementsem.d | 25 +- gcc/d/dmd/typesem.d | 31 +- gcc/d/typeinfo.cc | 4 +- gcc/doc/invoke.texi | 14 + gcc/gimple-fold.cc | 7 +- gcc/gimple.cc | 13 + gcc/gimple.h | 1 + gcc/ipa-fnsummary.cc | 4 +- gcc/ipa-icf.cc | 7 +- gcc/ipa-prop.cc | 4 +- gcc/ipa.cc | 3 +- gcc/opts.cc | 4 + gcc/sanopt.cc | 10 +- gcc/testsuite/ChangeLog | 39 +++ gcc/testsuite/g++.dg/cpp0x/trailing16.C | 17 ++ gcc/testsuite/g++.dg/cpp1z/nontype-auto21.C | 20 ++ gcc/testsuite/g++.dg/ubsan/return-8a.C | 16 + gcc/testsuite/g++.dg/ubsan/return-8b.C | 17 ++ gcc/testsuite/g++.dg/ubsan/return-8d.C | 16 + gcc/testsuite/g++.dg/ubsan/return-8e.C | 17 ++ gcc/testsuite/gcc.dg/vect/bb-slp-pr106019.c | 15 + gcc/testsuite/gdc.test/compilable/b16360.d | 39 --- gcc/testsuite/gdc.test/compilable/inliner.d | 21 ++ gcc/testsuite/gdc.test/compilable/inliner2.d | 27 ++ .../gdc.test/fail_compilation/fail17927.d | 8 +- .../gdc.test/fail_compilation/fail20108.d | 2 +- .../gdc.test/fail_compilation/fail_scope.d | 8 +- gcc/testsuite/gdc.test/fail_compilation/ice12574.d | 2 +- .../gdc.test/fail_compilation/previewin.d | 2 +- .../gdc.test/fail_compilation/previewin2.d | 18 ++ gcc/testsuite/gdc.test/fail_compilation/retscope.d | 12 +- .../gdc.test/fail_compilation/retscope2.d | 4 +- .../gdc.test/fail_compilation/retscope6.d | 12 +- .../gdc.test/fail_compilation/test14238.d | 2 +- .../gdc.test/fail_compilation/test17423.d | 2 +- .../gdc.test/fail_compilation/test17450.d | 4 +- .../gdc.test/fail_compilation/test20245.d | 8 +- .../gdc.test/fail_compilation/test22818.d | 2 +- .../gdc.test/fail_compilation/typeerrors.d | 2 +- .../gdc.test/fail_compilation/udaparams.d | 4 +- gcc/testsuite/gdc.test/fail_compilation/udatypes.d | 8 + gcc/testsuite/gdc.test/runnable/ice10086b.d | 50 ++++ gcc/testsuite/gdc.test/runnable/inline3.d | 44 +++ gcc/testsuite/gdc.test/runnable/staticforeach.d | 29 ++ gcc/testsuite/gdc.test/runnable_cxx/cppa.d | 20 +- .../gdc.test/runnable_cxx/extra-files/cppb.cpp | 30 +- gcc/tree-cfg.cc | 7 +- gcc/tree-data-ref.cc | 19 ++ gcc/tree-ssa-loop-ivcanon.cc | 7 +- gcc/tree-ssa-loop-ivopts.cc | 2 +- gcc/tree-ssa-sccvn.cc | 2 +- gcc/tree-switch-conversion.h | 2 +- gcc/tree.cc | 40 +++ gcc/tree.h | 5 + gcc/ubsan.cc | 48 ++- gcc/ubsan.h | 1 + libphobos/ChangeLog | 7 + libphobos/libdruntime/MERGE | 2 +- libphobos/libdruntime/core/stdc/config.d | 31 ++ libphobos/libdruntime/core/stdc/errno.d | 137 +++++++++ libphobos/libdruntime/core/stdc/stdarg.d | 21 ++ libphobos/libdruntime/core/stdc/stddef.d | 5 + libphobos/libdruntime/core/stdc/stdint.d | 35 +++ libphobos/libdruntime/core/stdc/stdio.d | 72 +++++ libphobos/libdruntime/core/stdc/stdlib.d | 1 + libphobos/libdruntime/core/sys/elf/package.d | 63 ++++ libphobos/libdruntime/core/sys/posix/fcntl.d | 6 + libphobos/libdruntime/core/sys/windows/winsock2.d | 14 +- libphobos/libdruntime/core/thread/osthread.d | 4 +- libphobos/libdruntime/core/thread/threadbase.d | 12 +- libphobos/libdruntime/core/time.d | 4 +- libphobos/libdruntime/core/vararg.d | 17 ++ libphobos/libdruntime/rt/critical_.d | 4 +- libphobos/libdruntime/rt/dmain2.d | 16 +- libphobos/libdruntime/rt/lifetime.d | 6 +- libphobos/libdruntime/rt/minfo.d | 216 +------------- libphobos/libdruntime/rt/monitor_.d | 6 +- libphobos/src/MERGE | 2 +- libphobos/src/std/complex.d | 2 +- libphobos/src/std/experimental/logger/core.d | 329 ++++----------------- libphobos/src/std/experimental/logger/package.d | 20 -- libphobos/src/std/file.d | 30 +- libphobos/src/std/math/algebraic.d | 6 +- libphobos/src/std/math/hardware.d | 6 +- libphobos/src/std/math/trigonometry.d | 46 +-- libphobos/src/std/numeric.d | 44 ++- libphobos/src/std/stdio.d | 12 +- libphobos/src/std/sumtype.d | 50 +++- libphobos/testsuite/libphobos.cycles/cycles.exp | 2 +- libstdc++-v3/ChangeLog | 23 ++ 115 files changed, 1551 insertions(+), 854 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp0x/trailing16.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/nontype-auto21.C create mode 100644 gcc/testsuite/g++.dg/ubsan/return-8a.C create mode 100644 gcc/testsuite/g++.dg/ubsan/return-8b.C create mode 100644 gcc/testsuite/g++.dg/ubsan/return-8d.C create mode 100644 gcc/testsuite/g++.dg/ubsan/return-8e.C create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr106019.c delete mode 100644 gcc/testsuite/gdc.test/compilable/b16360.d create mode 100644 gcc/testsuite/gdc.test/compilable/inliner.d create mode 100644 gcc/testsuite/gdc.test/compilable/inliner2.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/previewin2.d create mode 100644 gcc/testsuite/gdc.test/fail_compilation/udatypes.d create mode 100644 gcc/testsuite/gdc.test/runnable/inline3.d -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gnu_native_check_binutils/master-arm updated (4491a7c1aa -> 570e911f4e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_native_check_binutils/master-arm in repository toolchain/ci/binutils-gdb. from 4491a7c1aa readelf: replace xmalloc with malloc in slurp_relr_relocs adds b215cdf529 RISC-V: Fix inconsistent error message (range) adds dd8cc00cac RISC-V: Prepare i18n for required ISA extensions adds 1176bc3876 RISC-V: Add 'H' to canonical extension ordering adds c625f4ed05 RISC-V: Use single h extension to control hypervisor CSRs an [...] adds afc41ffb99 RISC-V: Reorder the prefixed extensions which are out of order. adds f18acc9c4e Binutils support for split-dwarf and dwarf-5 adds 90b7a5df15 aarch64: Disallow copy relocations on protected data adds 3af607d998 Use unique_xmalloc_ptr in interp adds ee04bfc01e Move mi_interpreter to mi-interp.h adds b2a696a881 Use std::string for interpreter_p adds 325600eb11 Automatic date update in version.in adds 4fb55bf6a9 aarch64: Define elf_backend_extern_protected_data to 0 [PR 18705] adds 83c325007c aarch64: Allow PC-relative relocations against protected STT [...] new ecc741e64e Re: PowerPC64: stub debug dump new 570e911f4e PowerPC64: fix assertion in ppc_build_one_stub with -Os code The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: bfd/elf64-ppc.c | 103 +++++++++++++-------- bfd/elfnn-aarch64.c | 32 ++++++- bfd/elfxx-riscv.c | 68 ++++---------- bfd/version.h | 2 +- binutils/ChangeLog | 13 ++- binutils/dwarf.c | 57 +++++++++--- binutils/dwarf.h | 1 + gas/config/tc-riscv.c | 12 ++- gas/testsuite/gas/riscv/csr-version-1p10.d | 100 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p10.l | 100 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p11.d | 100 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p11.l | 100 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p12.l | 50 ++++++++++ gas/testsuite/gas/riscv/csr-version-1p9p1.d | 100 ++++++++++---------- gas/testsuite/gas/riscv/csr-version-1p9p1.l | 100 ++++++++++---------- gas/testsuite/gas/riscv/h-ext-32.d | 2 +- gas/testsuite/gas/riscv/h-ext-64.d | 2 +- gas/testsuite/gas/riscv/march-fail-order-x-z.d | 3 - gas/testsuite/gas/riscv/march-fail-order-x-z.l | 2 - gas/testsuite/gas/riscv/march-fail-order-x.d | 3 - gas/testsuite/gas/riscv/march-fail-order-x.l | 2 - gas/testsuite/gas/riscv/march-fail-order-z.d | 3 - gas/testsuite/gas/riscv/march-fail-order-z.l | 2 - .../gas/riscv/march-fail-single-prefix-h.d | 3 - gas/testsuite/gas/riscv/march-fail-unknown-h.d | 3 - gdb/interps.c | 15 +-- gdb/interps.h | 10 +- gdb/main.c | 24 ++--- gdb/main.h | 2 +- gdb/mi/mi-common.h | 50 ---------- gdb/mi/mi-interp.h | 50 ++++++++++ gdb/mi/mi-main.c | 2 +- gdb/tui/tui-interp.c | 9 +- include/opcode/riscv-opc.h | 50 +++++----- include/opcode/riscv.h | 1 + ld/testsuite/ld-aarch64/aarch64-elf.exp | 10 ++ ld/testsuite/ld-aarch64/copy-reloc-protected.d | 2 + ld/testsuite/ld-aarch64/pcrel-protected.s | 11 +++ ld/testsuite/ld-aarch64/pcrel_pic_protected.d | 7 ++ ld/testsuite/ld-aarch64/protected-data.d | 2 +- ld/testsuite/ld-aarch64/protected.s | 8 ++ opcodes/riscv-opc.c | 38 ++++---- 42 files changed, 686 insertions(+), 568 deletions(-) delete mode 100644 gas/testsuite/gas/riscv/march-fail-order-x-z.d delete mode 100644 gas/testsuite/gas/riscv/march-fail-order-x-z.l delete mode 100644 gas/testsuite/gas/riscv/march-fail-order-x.d delete mode 100644 gas/testsuite/gas/riscv/march-fail-order-x.l delete mode 100644 gas/testsuite/gas/riscv/march-fail-order-z.d delete mode 100644 gas/testsuite/gas/riscv/march-fail-order-z.l delete mode 100644 gas/testsuite/gas/riscv/march-fail-single-prefix-h.d delete mode 100644 gas/testsuite/gas/riscv/march-fail-unknown-h.d create mode 100644 ld/testsuite/ld-aarch64/copy-reloc-protected.d create mode 100644 ld/testsuite/ld-aarch64/pcrel-protected.s create mode 100644 ld/testsuite/ld-aarch64/pcrel_pic_protected.d create mode 100644 ld/testsuite/ld-aarch64/protected.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years

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Tcwg-commits June 2022