Tcwg-commits February 2022

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9652 discussions

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_O1 updated (bb88f10425 -> 3c4c0a18c8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_O1 in repository toolchain/ci/binutils-gdb. from bb88f10425 Automatic date update in version.in adds 20ea3acc72 ld: Keep indirect symbol from IR if referenced from shared object adds e867795e8b gdb: use python to colorize disassembler output adds 7b8c55afd0 gdb/python: move styling support to gdb.styling adds 13eb081a83 Remove LA_PRINT_TYPE adds 362501dc5c Remove LA_PRINT_CHAR adds 660da3c14b Remove LA_PRINT_STRING adds a532eb7277 microblaze: fix fsqrt collicion to build on glibc-2.35 adds 9d67b0a097 sim cris: Correct PRIu32 to PRIx32 adds 3293b4f667 sim/testsuite/cris: Assembler testcase for PRIx32 usage bug adds 3e6dc39ed7 sim/testsuite: Set global_cc_os also when no compiler is found adds 56ba3848dc sim/testsuite/cris/c: Use -sim3 but only for newlib targets adds 46f238477f sim/testsuite/cris/hw/rv-n-cris/irq1.ms: Disable due to randomness adds 81064d7abc sim/testsuite: Support "requires: simoption <--name-of-option>" adds 6f62dbfb12 sim/testsuite/cris: As applicable, require simoption --cris- [...] adds e7e980c6fa sim cris: Unbreak --disable-sim-hardware builds adds dc4e1fde36 sim: Fix use of out-of-tree assembler and linker when testing adds 81011383d9 sim: Add sim_dump_memory for debugging adds 4b0e74fd18 sim/testsuite/cris: Remove faulty use of basename in C tests adds 234f5865fa sim/testsuite/cris: If failing compilation, mark C tests as errors adds 62e2e6d120 Automatic date update in version.in new a1faa5ea86 Revert "PR28824, relro security issues, x86 keep COMMONPAGES [...] new 3c4c0a18c8 x86-64: Use MAXPAGESIZE for the relro segment alignment The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: bfd/elflink.c | 5 +- bfd/version.h | 2 +- gdb/NEWS | 6 + gdb/ada-valprint.c | 2 +- gdb/c-valprint.c | 9 +- gdb/cli/cli-style.c | 44 ++++ gdb/cli/cli-style.h | 3 + gdb/data-directory/Makefile.in | 1 + gdb/disasm.c | 58 ++++- gdb/disasm.h | 25 ++ gdb/doc/gdb.texinfo | 15 ++ gdb/extension-priv.h | 6 + gdb/extension.c | 20 ++ gdb/extension.h | 8 + gdb/guile/scm-type.c | 3 +- gdb/language.h | 14 -- gdb/python/lib/gdb/__init__.py | 20 -- gdb/python/lib/gdb/styling.py | 50 ++++ gdb/python/py-type.c | 5 +- gdb/python/python.c | 85 ++++++- gdb/symmisc.c | 18 +- gdb/testsuite/gdb.base/style.exp | 82 ++++++- gdb/typeprint.c | 7 +- gdb/ui-file.h | 8 + gdb/valprint.c | 9 +- gdb/varobj.c | 4 +- ld/emultempl/elf-x86.em | 1 - ld/ld.h | 4 - ld/ldexp.c | 5 +- ld/testsuite/ld-plugin/lto.exp | 26 +++ ld/testsuite/ld-plugin/pr28879a.cc | 7 + ld/testsuite/ld-plugin/pr28879b.cc | 8 + ld/testsuite/ld-x86-64/plt-main-bnd.dd | 2 +- ld/testsuite/ld-x86-64/plt-main-ibt-x32.dd | 2 +- ld/testsuite/ld-x86-64/plt-main-ibt.dd | 2 +- ld/testsuite/ld-x86-64/pr14207.d | 6 +- ld/testsuite/ld-x86-64/pr18176.d | 3 +- ld/testsuite/ld-x86-64/pr20830a-now.d | 10 +- ld/testsuite/ld-x86-64/pr20830a.d | 10 +- ld/testsuite/ld-x86-64/pr20830b-now.d | 12 +- ld/testsuite/ld-x86-64/pr20830b.d | 12 +- ld/testsuite/ld-x86-64/pr21038a-now.d | 10 +- ld/testsuite/ld-x86-64/pr21038a.d | 10 +- ld/testsuite/ld-x86-64/pr21038b-now.d | 8 +- ld/testsuite/ld-x86-64/pr21038b.d | 8 +- ld/testsuite/ld-x86-64/pr21038c-now.d | 12 +- ld/testsuite/ld-x86-64/pr21038c.d | 12 +- opcodes/ChangeLog | 5 + opcodes/microblaze-opc.h | 2 +- opcodes/microblaze-opcm.h | 3 +- sim/Makefile.in | 7 +- sim/common/sim-memopt.c | 10 + sim/configure | 356 +++++++++++++++++++++-------- sim/cris/sim-if.c | 10 +- sim/m4/sim_ac_toolchain.m4 | 21 +- sim/testsuite/cris/asm/endmem1.ms | 47 ++++ sim/testsuite/cris/asm/io1.ms | 1 + sim/testsuite/cris/asm/io2.ms | 1 + sim/testsuite/cris/asm/io3.ms | 1 + sim/testsuite/cris/asm/io6.ms | 1 + sim/testsuite/cris/asm/io7.ms | 1 + sim/testsuite/cris/c/c.exp | 18 +- sim/testsuite/cris/c/openpf1.c | 8 +- sim/testsuite/cris/c/stat3.c | 3 +- sim/testsuite/cris/hw/rv-n-cris/irq1.ms | 1 + sim/testsuite/lib/sim-defs.exp | 61 +++++ 66 files changed, 978 insertions(+), 258 deletions(-) create mode 100644 gdb/python/lib/gdb/styling.py create mode 100644 ld/testsuite/ld-plugin/pr28879a.cc create mode 100644 ld/testsuite/ld-plugin/pr28879b.cc create mode 100644 sim/testsuite/cris/asm/endmem1.ms -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_O1 updated (516c1f87 -> 41be0e83)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_O1 in repository toolchain/ci/base-artifacts. discards 516c1f87 0: update: binutils-gcc: 2 new 41be0e83 0: update: binutils-gcc: 2 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (516c1f87) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_bootstrap/master-aar [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1540 -> 1540 bytes 02-prepare_abe/console.log.xz | Bin 2756 -> 2752 bytes 04-build_abe-binutils/console.log.xz | Bin 38064 -> 38560 bytes 05-build_abe-bootstrap_O1/console.log.xz | Bin 265992 -> 264416 bytes 06-check_regression/console.log.xz | Bin 416 -> 416 bytes 07-update_baseline/console.log | 16 ++++++++-------- jenkins/manifest.sh | 12 ++++++------ 7 files changed, 14 insertions(+), 14 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_gnu_cross_build/master-arm updated (cc5ce8b8b6 -> 2d88a3a595)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/qemu. from cc5ce8b8b6 Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc [...] adds 620d0b49a4 common-user/host/sparc64: Fix safe_syscall_base adds c8c89a6a30 linux-user: Introduce host_signal_mask adds 9940799bde linux-user: Introduce host_sigcontext adds 238b32de39 linux-user: Move sparc/host-signal.h to sparc64/host-signal.h adds 4f152ef27e linux-user/include/host/sparc64: Fix host_sigcontext adds cfc2a2d69d accel/tcg: Optimize jump cache flush during tlb range flush adds 25e82fb769 softmmu/cpus: Check if the cpu work list is empty atomically adds c3e97f6406 replay: use CF_NOIRQ for special exception-replaying TB adds 7b17a47540 tcg/loongarch64: Fix fallout from recent MO_Q renaming adds b1ee3c6725 tcg/i386: Support raising sigbus for user-only adds f85ab3d2e5 tcg/aarch64: Support raising sigbus for user-only adds 8605cbcdee tcg/ppc: Support raising sigbus for user-only adds a3fb7c99c0 tcg/riscv: Support raising sigbus for user-only adds 1cd49868d4 tcg/s390x: Support raising sigbus for user-only adds fe1bee3a0a tcg/tci: Support raising sigbus for user-only adds 6f78c7b082 tcg/loongarch64: Support raising sigbus for user-only adds 01dfc0ed7f tcg/arm: Drop support for armv4 and armv5 hosts adds 6cef13940c tcg/arm: Remove use_armv5t_instructions adds bde2cdb59b tcg/arm: Remove use_armv6_instructions adds 367d43d85b tcg/arm: Check alignment for ldrd and strd adds 8821ec2323 tcg/arm: Support unaligned access for softmmu adds 4bb802073f tcg/arm: Reserve a register for guest_base adds 0c90fa5dce tcg/arm: Support raising sigbus for user-only adds 23a79c113e tcg/mips: Support unaligned access for user-only adds d9e5283465 tcg/mips: Support unaligned access for softmmu adds 414399b6b8 tcg/sparc: Use tcg_out_movi_imm13 in tcg_out_addsub2_i64 adds c71929c345 tcg/sparc: Split out tcg_out_movi_imm32 adds 92840d06fa tcg/sparc: Add scratch argument to tcg_out_movi_int adds 684db2a0b0 tcg/sparc: Improve code gen for shifted 32-bit constants adds 6a6bfa3c60 tcg/sparc: Convert patch_reloc to return bool adds c834b8d81b tcg/sparc: Use the constant pool for 64-bit constants adds e01d60f211 tcg/sparc: Add tcg_out_jmpl_const for better tail calls adds 321dbde33a tcg/sparc: Support unaligned access for user-only adds 5c1a101ef6 tests/tcg/multiarch: Add sigbus.c adds 50a75ff680 Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-t [...] adds aba8205be0 block: Lock AioContext for drain_end in blockdev-reopen adds ee81060237 iotests: Test blockdev-reopen with iothreads and throttling adds fdb8541b2e hw/block/fdc-isa: Respect QOM properties when building AML adds 2d88a3a595 Merge remote-tracking branch 'remotes/kwolf-gitlab/tags/for- [...] No new revisions were added by this update. Summary of changes: accel/tcg/cpu-exec.c | 3 +- accel/tcg/cputlb.c | 9 + blockdev.c | 11 +- common-user/host/sparc64/safe-syscall.inc.S | 5 +- hw/block/fdc-isa.c | 11 +- linux-user/include/host/aarch64/host-signal.h | 16 +- linux-user/include/host/alpha/host-signal.h | 14 +- linux-user/include/host/arm/host-signal.h | 14 +- linux-user/include/host/i386/host-signal.h | 14 +- linux-user/include/host/loongarch64/host-signal.h | 14 +- linux-user/include/host/mips/host-signal.h | 14 +- linux-user/include/host/ppc/host-signal.h | 14 +- linux-user/include/host/riscv/host-signal.h | 14 +- linux-user/include/host/s390/host-signal.h | 14 +- linux-user/include/host/sparc/host-signal.h | 63 ---- linux-user/include/host/sparc64/host-signal.h | 65 +++- linux-user/include/host/x86_64/host-signal.h | 14 +- linux-user/signal.c | 22 +- softmmu/cpus.c | 7 +- tcg/aarch64/tcg-target.c.inc | 91 ++++- tcg/aarch64/tcg-target.h | 2 - tcg/arm/tcg-target.c.inc | 410 +++++++++------------- tcg/arm/tcg-target.h | 6 +- tcg/i386/tcg-target.c.inc | 103 +++++- tcg/i386/tcg-target.h | 2 - tcg/loongarch64/tcg-target.c.inc | 73 +++- tcg/loongarch64/tcg-target.h | 2 - tcg/mips/tcg-target.c.inc | 387 ++++++++++++++++++-- tcg/mips/tcg-target.h | 2 - tcg/ppc/tcg-target.c.inc | 98 +++++- tcg/ppc/tcg-target.h | 2 - tcg/riscv/tcg-target.c.inc | 63 +++- tcg/riscv/tcg-target.h | 2 - tcg/s390x/tcg-target.c.inc | 59 +++- tcg/s390x/tcg-target.h | 2 - tcg/sparc/tcg-target.c.inc | 348 +++++++++++++++--- tcg/tci.c | 20 +- tests/qemu-iotests/245 | 36 +- tests/qemu-iotests/245.out | 4 +- tests/tcg/multiarch/sigbus.c | 68 ++++ 40 files changed, 1613 insertions(+), 505 deletions(-) delete mode 100644 linux-user/include/host/sparc/host-signal.h create mode 100644 tests/tcg/multiarch/sigbus.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

[toolchain/ci/gdb] branch linaro-local/ci/tcwg_gnu_cross_build/master-arm updated (a532eb7277 -> 62e2e6d120)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/gdb. from a532eb7277 microblaze: fix fsqrt collicion to build on glibc-2.35 adds 9d67b0a097 sim cris: Correct PRIu32 to PRIx32 adds 3293b4f667 sim/testsuite/cris: Assembler testcase for PRIx32 usage bug adds 3e6dc39ed7 sim/testsuite: Set global_cc_os also when no compiler is found adds 56ba3848dc sim/testsuite/cris/c: Use -sim3 but only for newlib targets adds 46f238477f sim/testsuite/cris/hw/rv-n-cris/irq1.ms: Disable due to randomness adds 81064d7abc sim/testsuite: Support "requires: simoption <--name-of-option>" adds 6f62dbfb12 sim/testsuite/cris: As applicable, require simoption --cris- [...] adds e7e980c6fa sim cris: Unbreak --disable-sim-hardware builds adds dc4e1fde36 sim: Fix use of out-of-tree assembler and linker when testing adds 81011383d9 sim: Add sim_dump_memory for debugging adds 4b0e74fd18 sim/testsuite/cris: Remove faulty use of basename in C tests adds 234f5865fa sim/testsuite/cris: If failing compilation, mark C tests as errors adds 62e2e6d120 Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- sim/Makefile.in | 7 +- sim/common/sim-memopt.c | 10 + sim/configure | 356 +++++++++++++++++++++++--------- sim/cris/sim-if.c | 10 +- sim/m4/sim_ac_toolchain.m4 | 21 +- sim/testsuite/cris/asm/endmem1.ms | 47 +++++ sim/testsuite/cris/asm/io1.ms | 1 + sim/testsuite/cris/asm/io2.ms | 1 + sim/testsuite/cris/asm/io3.ms | 1 + sim/testsuite/cris/asm/io6.ms | 1 + sim/testsuite/cris/asm/io7.ms | 1 + sim/testsuite/cris/c/c.exp | 18 +- sim/testsuite/cris/c/openpf1.c | 8 +- sim/testsuite/cris/c/stat3.c | 3 +- sim/testsuite/cris/hw/rv-n-cris/irq1.ms | 1 + sim/testsuite/lib/sim-defs.exp | 61 ++++++ 17 files changed, 432 insertions(+), 117 deletions(-) create mode 100644 sim/testsuite/cris/asm/endmem1.ms -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu_cross_build/master-arm updated (3d50dede07d -> 1f8a09d2f3c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/gcc. from 3d50dede07d libstdc++: Fix stream extraction of IEEE128 long double [PR100912] adds 19b517dff37 Fortran: improve error recovery on bad array section adds 16b65b08484 Use correct names for __ibm128 if long double is IEEE 128-bit. adds 7a1b179b08b Update -Warray-bounds documentation [PR104355]. adds 1f8a09d2f3c Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 37 +++++++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 6 ++ gcc/config/rs6000/rs6000.cc | 6 ++ gcc/cp/ChangeLog | 6 ++ gcc/doc/invoke.texi | 24 +++-- gcc/fortran/ChangeLog | 6 ++ gcc/fortran/expr.cc | 8 +- gcc/testsuite/ChangeLog | 36 +++++++ gcc/testsuite/gcc.target/powerpc/pr104253.c | 156 ++++++++++++++++++++++++++++ gcc/testsuite/gfortran.dg/pr104211.f90 | 11 ++ libstdc++-v3/ChangeLog | 30 ++++++ 12 files changed, 316 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/pr104253.c create mode 100644 gcc/testsuite/gfortran.dg/pr104211.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gnu_cross_build/master-arm updated (a532eb7277 -> 62e2e6d120)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/binutils-gdb. from a532eb7277 microblaze: fix fsqrt collicion to build on glibc-2.35 adds 9d67b0a097 sim cris: Correct PRIu32 to PRIx32 adds 3293b4f667 sim/testsuite/cris: Assembler testcase for PRIx32 usage bug adds 3e6dc39ed7 sim/testsuite: Set global_cc_os also when no compiler is found adds 56ba3848dc sim/testsuite/cris/c: Use -sim3 but only for newlib targets adds 46f238477f sim/testsuite/cris/hw/rv-n-cris/irq1.ms: Disable due to randomness adds 81064d7abc sim/testsuite: Support "requires: simoption <--name-of-option>" adds 6f62dbfb12 sim/testsuite/cris: As applicable, require simoption --cris- [...] adds e7e980c6fa sim cris: Unbreak --disable-sim-hardware builds adds dc4e1fde36 sim: Fix use of out-of-tree assembler and linker when testing adds 81011383d9 sim: Add sim_dump_memory for debugging adds 4b0e74fd18 sim/testsuite/cris: Remove faulty use of basename in C tests adds 234f5865fa sim/testsuite/cris: If failing compilation, mark C tests as errors adds 62e2e6d120 Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- sim/Makefile.in | 7 +- sim/common/sim-memopt.c | 10 + sim/configure | 356 +++++++++++++++++++++++--------- sim/cris/sim-if.c | 10 +- sim/m4/sim_ac_toolchain.m4 | 21 +- sim/testsuite/cris/asm/endmem1.ms | 47 +++++ sim/testsuite/cris/asm/io1.ms | 1 + sim/testsuite/cris/asm/io2.ms | 1 + sim/testsuite/cris/asm/io3.ms | 1 + sim/testsuite/cris/asm/io6.ms | 1 + sim/testsuite/cris/asm/io7.ms | 1 + sim/testsuite/cris/c/c.exp | 18 +- sim/testsuite/cris/c/openpf1.c | 8 +- sim/testsuite/cris/c/stat3.c | 3 +- sim/testsuite/cris/hw/rv-n-cris/irq1.ms | 1 + sim/testsuite/lib/sim-defs.exp | 61 ++++++ 17 files changed, 432 insertions(+), 117 deletions(-) create mode 100644 sim/testsuite/cris/asm/endmem1.ms -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_cross_build/master-arm updated (0f5dd97c -> 373f1bbb)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/base-artifacts. discards 0f5dd97c 0: update: binutils-gcc-linux-glibc-gdb-qemu: 7 new 373f1bbb 0: update: binutils-gcc-linux-glibc-gdb-qemu: 7 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (0f5dd97c) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_cross_build/master-a [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1536 -> 1568 bytes 02-prepare_abe/console.log.xz | Bin 2772 -> 2772 bytes 04-build_abe-binutils/console.log.xz | Bin 30136 -> 29984 bytes 05-build_abe-stage1/console.log.xz | Bin 90520 -> 90240 bytes 07-build_abe-linux/console.log.xz | Bin 9044 -> 8816 bytes 08-build_abe-glibc/console.log.xz | Bin 230300 -> 231492 bytes 09-build_abe-stage2/console.log.xz | Bin 222248 -> 220980 bytes 10-build_abe-gdb/console.log.xz | Bin 36964 -> 37032 bytes 11-build_abe-qemu/console.log.xz | Bin 30728 -> 30476 bytes 12-check_regression/console.log.xz | Bin 416 -> 416 bytes 13-update_baseline/console.log | 2 +- jenkins/manifest.sh | 22 +++++++++++----------- 12 files changed, 12 insertions(+), 12 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

[binutils-gdb] branch master updated (62e2e6d120f -> 3c4c0a18c8f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 62e2e6d120f Automatic date update in version.in new a1faa5ea862 Revert "PR28824, relro security issues, x86 keep COMMONPAGE [...] new 3c4c0a18c8f x86-64: Use MAXPAGESIZE for the relro segment alignment The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ld/emultempl/elf-x86.em | 1 - ld/ld.h | 4 ---- ld/ldexp.c | 5 +---- ld/testsuite/ld-x86-64/plt-main-bnd.dd | 2 +- ld/testsuite/ld-x86-64/plt-main-ibt-x32.dd | 2 +- ld/testsuite/ld-x86-64/plt-main-ibt.dd | 2 +- ld/testsuite/ld-x86-64/pr14207.d | 6 +++--- ld/testsuite/ld-x86-64/pr18176.d | 3 +-- ld/testsuite/ld-x86-64/pr20830a-now.d | 10 +++++----- ld/testsuite/ld-x86-64/pr20830a.d | 10 +++++----- ld/testsuite/ld-x86-64/pr20830b-now.d | 12 ++++++------ ld/testsuite/ld-x86-64/pr20830b.d | 12 ++++++------ ld/testsuite/ld-x86-64/pr21038a-now.d | 10 +++++----- ld/testsuite/ld-x86-64/pr21038a.d | 10 +++++----- ld/testsuite/ld-x86-64/pr21038b-now.d | 8 ++++---- ld/testsuite/ld-x86-64/pr21038b.d | 8 ++++---- ld/testsuite/ld-x86-64/pr21038c-now.d | 12 ++++++------ ld/testsuite/ld-x86-64/pr21038c.d | 12 ++++++------ 18 files changed, 60 insertions(+), 69 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 updated (cc5ce8b8b6 -> 2d88a3a595)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 in repository toolchain/ci/qemu. from cc5ce8b8b6 Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc [...] adds 620d0b49a4 common-user/host/sparc64: Fix safe_syscall_base adds c8c89a6a30 linux-user: Introduce host_signal_mask adds 9940799bde linux-user: Introduce host_sigcontext adds 238b32de39 linux-user: Move sparc/host-signal.h to sparc64/host-signal.h adds 4f152ef27e linux-user/include/host/sparc64: Fix host_sigcontext adds cfc2a2d69d accel/tcg: Optimize jump cache flush during tlb range flush adds 25e82fb769 softmmu/cpus: Check if the cpu work list is empty atomically adds c3e97f6406 replay: use CF_NOIRQ for special exception-replaying TB adds 7b17a47540 tcg/loongarch64: Fix fallout from recent MO_Q renaming adds b1ee3c6725 tcg/i386: Support raising sigbus for user-only adds f85ab3d2e5 tcg/aarch64: Support raising sigbus for user-only adds 8605cbcdee tcg/ppc: Support raising sigbus for user-only adds a3fb7c99c0 tcg/riscv: Support raising sigbus for user-only adds 1cd49868d4 tcg/s390x: Support raising sigbus for user-only adds fe1bee3a0a tcg/tci: Support raising sigbus for user-only adds 6f78c7b082 tcg/loongarch64: Support raising sigbus for user-only adds 01dfc0ed7f tcg/arm: Drop support for armv4 and armv5 hosts adds 6cef13940c tcg/arm: Remove use_armv5t_instructions adds bde2cdb59b tcg/arm: Remove use_armv6_instructions adds 367d43d85b tcg/arm: Check alignment for ldrd and strd adds 8821ec2323 tcg/arm: Support unaligned access for softmmu adds 4bb802073f tcg/arm: Reserve a register for guest_base adds 0c90fa5dce tcg/arm: Support raising sigbus for user-only adds 23a79c113e tcg/mips: Support unaligned access for user-only adds d9e5283465 tcg/mips: Support unaligned access for softmmu adds 414399b6b8 tcg/sparc: Use tcg_out_movi_imm13 in tcg_out_addsub2_i64 adds c71929c345 tcg/sparc: Split out tcg_out_movi_imm32 adds 92840d06fa tcg/sparc: Add scratch argument to tcg_out_movi_int adds 684db2a0b0 tcg/sparc: Improve code gen for shifted 32-bit constants adds 6a6bfa3c60 tcg/sparc: Convert patch_reloc to return bool adds c834b8d81b tcg/sparc: Use the constant pool for 64-bit constants adds e01d60f211 tcg/sparc: Add tcg_out_jmpl_const for better tail calls adds 321dbde33a tcg/sparc: Support unaligned access for user-only adds 5c1a101ef6 tests/tcg/multiarch: Add sigbus.c adds 50a75ff680 Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-t [...] adds aba8205be0 block: Lock AioContext for drain_end in blockdev-reopen adds ee81060237 iotests: Test blockdev-reopen with iothreads and throttling adds fdb8541b2e hw/block/fdc-isa: Respect QOM properties when building AML adds 2d88a3a595 Merge remote-tracking branch 'remotes/kwolf-gitlab/tags/for- [...] No new revisions were added by this update. Summary of changes: accel/tcg/cpu-exec.c | 3 +- accel/tcg/cputlb.c | 9 + blockdev.c | 11 +- common-user/host/sparc64/safe-syscall.inc.S | 5 +- hw/block/fdc-isa.c | 11 +- linux-user/include/host/aarch64/host-signal.h | 16 +- linux-user/include/host/alpha/host-signal.h | 14 +- linux-user/include/host/arm/host-signal.h | 14 +- linux-user/include/host/i386/host-signal.h | 14 +- linux-user/include/host/loongarch64/host-signal.h | 14 +- linux-user/include/host/mips/host-signal.h | 14 +- linux-user/include/host/ppc/host-signal.h | 14 +- linux-user/include/host/riscv/host-signal.h | 14 +- linux-user/include/host/s390/host-signal.h | 14 +- linux-user/include/host/sparc/host-signal.h | 63 ---- linux-user/include/host/sparc64/host-signal.h | 65 +++- linux-user/include/host/x86_64/host-signal.h | 14 +- linux-user/signal.c | 22 +- softmmu/cpus.c | 7 +- tcg/aarch64/tcg-target.c.inc | 91 ++++- tcg/aarch64/tcg-target.h | 2 - tcg/arm/tcg-target.c.inc | 410 +++++++++------------- tcg/arm/tcg-target.h | 6 +- tcg/i386/tcg-target.c.inc | 103 +++++- tcg/i386/tcg-target.h | 2 - tcg/loongarch64/tcg-target.c.inc | 73 +++- tcg/loongarch64/tcg-target.h | 2 - tcg/mips/tcg-target.c.inc | 387 ++++++++++++++++++-- tcg/mips/tcg-target.h | 2 - tcg/ppc/tcg-target.c.inc | 98 +++++- tcg/ppc/tcg-target.h | 2 - tcg/riscv/tcg-target.c.inc | 63 +++- tcg/riscv/tcg-target.h | 2 - tcg/s390x/tcg-target.c.inc | 59 +++- tcg/s390x/tcg-target.h | 2 - tcg/sparc/tcg-target.c.inc | 348 +++++++++++++++--- tcg/tci.c | 20 +- tests/qemu-iotests/245 | 36 +- tests/qemu-iotests/245.out | 4 +- tests/tcg/multiarch/sigbus.c | 68 ++++ 40 files changed, 1613 insertions(+), 505 deletions(-) delete mode 100644 linux-user/include/host/sparc/host-signal.h create mode 100644 tests/tcg/multiarch/sigbus.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

[toolchain/ci/gdb] branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 updated (a532eb7277 -> 62e2e6d120)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-aarch64 in repository toolchain/ci/gdb. from a532eb7277 microblaze: fix fsqrt collicion to build on glibc-2.35 new 9d67b0a097 sim cris: Correct PRIu32 to PRIx32 new 3293b4f667 sim/testsuite/cris: Assembler testcase for PRIx32 usage bug new 3e6dc39ed7 sim/testsuite: Set global_cc_os also when no compiler is found new 56ba3848dc sim/testsuite/cris/c: Use -sim3 but only for newlib targets new 46f238477f sim/testsuite/cris/hw/rv-n-cris/irq1.ms: Disable due to randomness new 81064d7abc sim/testsuite: Support "requires: simoption <--name-of-option>" new 6f62dbfb12 sim/testsuite/cris: As applicable, require simoption --cris- [...] new e7e980c6fa sim cris: Unbreak --disable-sim-hardware builds new dc4e1fde36 sim: Fix use of out-of-tree assembler and linker when testing new 81011383d9 sim: Add sim_dump_memory for debugging new 4b0e74fd18 sim/testsuite/cris: Remove faulty use of basename in C tests new 234f5865fa sim/testsuite/cris: If failing compilation, mark C tests as errors new 62e2e6d120 Automatic date update in version.in The 13 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: bfd/version.h | 2 +- sim/Makefile.in | 7 +- sim/common/sim-memopt.c | 10 + sim/configure | 356 +++++++++++++++++++++++--------- sim/cris/sim-if.c | 10 +- sim/m4/sim_ac_toolchain.m4 | 21 +- sim/testsuite/cris/asm/endmem1.ms | 47 +++++ sim/testsuite/cris/asm/io1.ms | 1 + sim/testsuite/cris/asm/io2.ms | 1 + sim/testsuite/cris/asm/io3.ms | 1 + sim/testsuite/cris/asm/io6.ms | 1 + sim/testsuite/cris/asm/io7.ms | 1 + sim/testsuite/cris/c/c.exp | 18 +- sim/testsuite/cris/c/openpf1.c | 8 +- sim/testsuite/cris/c/stat3.c | 3 +- sim/testsuite/cris/hw/rv-n-cris/irq1.ms | 1 + sim/testsuite/lib/sim-defs.exp | 61 ++++++ 17 files changed, 432 insertions(+), 117 deletions(-) create mode 100644 sim/testsuite/cris/asm/endmem1.ms -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 6 months

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Tcwg-commits February 2022