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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/release-aarch64-bootstrap_lto
in repository toolchain/ci/base-artifacts.
from 5112043324 38: onsuccess: #152: 2: Success after binutils/gcc: 13 commits
new f7f61b0d71 39: onsuccess: #153: 2: Success after binutils/gcc: 14 commits
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Summary of changes:
01-reset_artifacts/console.log.xz | Bin 1728 -> 1732 bytes
02-prepare_abe/console.log.xz | Bin 2748 -> 2764 bytes
04-build_abe-binutils/console.log.xz | Bin 37988 -> 37896 bytes
05-build_abe-bootstrap_lto/console.log.xz | Bin 273548 -> 273476 bytes
06-check_regression/console.log.xz | Bin 2856 -> 2796 bytes
dashboard/dashboard-generate.sh | 2 +-
git/binutils_rev | 2 +-
git/gcc_rev | 2 +-
mail/jira-body.txt | 2 +-
mail/mail-body.txt | 2 +-
mail/mail-subject.txt | 2 +-
manifest.sh | 20 ++++++++++----------
12 files changed, 16 insertions(+), 16 deletions(-)
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unknown user pushed a change to branch master
in repository binutils-gdb.
from a4c4d804d66 Revert "sim: mn10300: drop unused sim-main.c"
new d9e217e950b sim: cgen: move cgen-types.h include to cgen-defs.h
new 3eaecff5137 sim: cgen: move symcat.h include to where it's used
new 10861ec94fe sim: ppc: drop unused types from sim-main.h
new 110028744cd sim: lm32/m32r: drop redundant opcode/cgen.h include
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Summary of changes:
sim/bpf/sim-main.h | 1 -
sim/common/cgen-defs.h | 2 ++
sim/common/cgen-mem.h | 2 ++
sim/common/sim-close.c | 2 ++
sim/common/sim-core.h | 1 +
sim/common/sim-types.h | 2 ++
sim/cris/sim-main.h | 2 --
sim/frv/sim-main.h | 2 --
sim/iq2000/sim-main.h | 2 --
sim/lm32/sim-main.h | 3 ---
sim/m32r/m32r-sim.h | 2 ++
sim/m32r/sim-main.h | 3 ---
sim/or1k/sim-main.h | 1 -
sim/ppc/sim-main.h | 7 -------
14 files changed, 11 insertions(+), 21 deletions(-)
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-defconfig
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from 11bddc07c6 30: onsuccess: #273: boot: Success after binutils/qemu: 213 commits
new 3d05480b61 31: onsuccess: #274: boot: Success after binutils/linux/qemu [...]
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Summary of changes:
01-reset_artifacts/console.log.xz | Bin 1748 -> 1784 bytes
02-prepare_abe/console.log.xz | Bin 2768 -> 2804 bytes
03-build_abe-binutils/console.log.xz | Bin 30620 -> 31024 bytes
04-build_kernel_llvm/console.log.xz | Bin 64764 -> 66056 bytes
05-build_abe-qemu/console.log.xz | Bin 31440 -> 32216 bytes
06-build_linux/console.log.xz | Bin 3488 -> 3504 bytes
07-boot_linux/console.log.xz | Bin 6040 -> 6056 bytes
08-check_regression/console.log.xz | Bin 3268 -> 3812 bytes
09-update_baseline/console.log | 8 ++++----
dashboard/dashboard-generate.sh | 2 +-
git/binutils_rev | 2 +-
git/linux_rev | 2 +-
git/qemu_rev | 2 +-
mail/jira-body.txt | 2 +-
mail/mail-body.txt | 2 +-
mail/mail-subject.txt | 2 +-
manifest.sh | 26 +++++++++++++-------------
17 files changed, 24 insertions(+), 24 deletions(-)
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unknown user pushed a change to branch master
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from 7e76cd96950 Remove not needed assert macro which fails.
new 85112fbbfd9 RISC-V: Fix muti-line condition format
new 9374f766a75 RISC-V: Fix incorrect annotation
new 37fd10fd3eb RISC-V: Remove side effects of vsetvl/vsetvlmax intriniscs [...]
new b47b33c799b RISC-V: Remove side effects of vsetvl pattern in RTL.
new 55d65ad4fd8 RISC-V: Update vsetvl/vsetvlmax intrinsics to the latest api name.
new a143c3f7a61 RISC-V: Support vle.v/vse.v intrinsics
new 16eb1f43ab4 RISC-V: Fix vle constraints
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Summary of changes:
gcc/config/riscv/riscv-protos.h | 1 +
gcc/config/riscv/riscv-v.cc | 10 +-
gcc/config/riscv/riscv-vector-builtins-bases.cc | 50 ++++-
gcc/config/riscv/riscv-vector-builtins-bases.h | 2 +
.../riscv/riscv-vector-builtins-functions.def | 3 +
gcc/config/riscv/riscv-vector-builtins-shapes.cc | 37 +++-
gcc/config/riscv/riscv-vector-builtins-shapes.h | 1 +
gcc/config/riscv/riscv-vector-builtins-types.def | 49 ++++-
gcc/config/riscv/riscv-vector-builtins.cc | 236 ++++++++++++++++++++-
gcc/config/riscv/riscv-vector-builtins.def | 122 +++++------
gcc/config/riscv/riscv-vector-builtins.h | 65 ++++++
gcc/config/riscv/riscv-vsetvl.cc | 38 ++--
gcc/config/riscv/t-riscv | 2 +-
gcc/config/riscv/vector.md | 42 +++-
.../gcc.target/riscv/rvv/base/vle-constraint-1.c | 109 ++++++++++
gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c | 220 +++++++++----------
16 files changed, 774 insertions(+), 213 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vle-constraint-1.c
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unknown user pushed a change to branch master
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from 681a422b855 sim: mn10300: drop unused sim-main.c
new a4c4d804d66 Revert "sim: mn10300: drop unused sim-main.c"
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sim/mn10300/sim-main.c | 9 +++++++++
1 file changed, 9 insertions(+)
create mode 100644 sim/mn10300/sim-main.c
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unknown user pushed a change to branch master
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from 8ec5fcb6fc7 libstdc++: Improve output of default contract violation han [...]
new 7e76cd96950 Remove not needed assert macro which fails.
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gcc/fortran/trans-array.cc | 1 -
gcc/testsuite/gfortran.dg/pr106731.f90 | 58 ++++++++++++++++++++++++++++++++++
2 files changed, 58 insertions(+), 1 deletion(-)
create mode 100644 gcc/testsuite/gfortran.dg/pr106731.f90
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