[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_O1 updated (491d5b3cf82 -> c390c5df71b)
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_O1
in repository toolchain/ci/gcc.
from 491d5b3cf82 dwarf2unwind : Force the CFA after remember/restore pairs [ [...]
adds 3104dbdcf4a Do not call Set_Cloned_Subtype on private type
adds 8893888621f Daily bump.
adds 76c99cb1133 Fix __sprintfkf prototype in libgcc.
adds 34d39d14091 IBM Z: Run mul-signed-overflow tests only on z14
adds ff92ede8d26 vrp: Improve register_edge_assert_for [PR95757]
adds 796a35b2bd6 IBM Z: arch14: Add command line options
adds 2bd58910b04 IBM Z: arch14: New instrinsics
adds d6378b9785b c++: Avoid building garbage trees from tsubst_requires_expr
adds 04b10596fe2 c++: Some preparatory type canonicalization fixes
adds 276cb81bec6 c++: Delay normalizing nested requirements until satisfaction
adds e52f8ec25c0 c++: Fix satisfaction of placeholder type constraints [PR96443]
adds f8e4d7a6597 analyzer: remove dead code
adds 168b75ff54b Fix PR ada/99095
adds 5a233ae4d8c dwarf2out: Fix up split-dwarf .debug_macro handling [PR99319]
adds 66ecb059c9d PR c++/99251 - inconsistent -Wnonnull warning behaviour wit [...]
adds 397ed1dbffe PR middle-end/99295 - documentation on __attribute__((mallo [...]
adds e7ca37649e4 PR middle-end/99276 - grammar in diagnostics for overflowin [...]
adds 41fbacdd103 diagnostics: fix ICE on fix-it hints on very long lines [PR99323]
adds df003d1e0bf libbacktrace: pass -1 to error callback for unrecognized DWARF
adds d1776b77570 compiler: allow //go:embed in files underscore-importing embed
adds 8b6ebc025cf [PATCH] Fix Ada bootstrap failure on Cygwin since switch to [...]
adds 7fddf3dbb98 outputs.exp: skip @file -save-temps if target has -L or -I
adds 1c4b7b367cf aix: Fix TLS thread pointer function names.
adds d97a92dca90 Daily bump.
adds 9b2084db9f9 libbacktrace: don't special case file 0
adds f8e7f3f3f33 cgraph: flatten and same_body aliases [PR96078]
adds 006693a59f7 libgfortran: Fix negation for largest integer [PR81986]
adds 4ad5b1915d5 cfgrtl: Fix up fixup_partitions caused ICE [PR99085]
adds b5040344b9c dwarf2out: Fix -gsplit-dwarf on riscv or other non-.uleb128 [...]
adds ba09d11a9d0 c-family: Avoid ICE on va_arg [PR99324]
adds f1b13064609 i386: Fix a peephole2 for -mavx512vl -mno-avx512bw [PR99321]
adds 357c4350680 Fix ICE with pathologically large frames
adds a7267237371 libstdc++: Don't use reserved identifiers in simd headers
adds 8c4f0c0ceb3 c++: namespace reachability [PR 99344]
adds 8cfa06570dd testsuite: i386: Fix gcc.target/i386/pr95798-?.c on Solaris
adds 00d79dc4be0 gcov: use mmap pools for KVP.
adds 5bc3a2bc8a8 libstdc++: Update Solaris baselines for GCC 11.1
adds 74aee6d2087 c++: C++17 and decltype of multi-operator expression [PR95675]
adds 15cf7fe3556 arm: Ignore --with-mode when CPU only supports one instruct [...]
adds 1dabbfb0f4a c++: ICE with deduction guide in checking type-dep [PR99009 [...]
adds fa6092d2cdc sparcv9: Disable -Wuninitialized warnings breaking bootstra [...]
adds 0b8fa12015f c++: Fix -fstrong-eval-order for operator &&, || and , [PR82959]
adds 949eab55b6f testsuite: aarch64: Add tests for narrowing-arithmetic intrinsics
adds fd85814c4be testsuite: aarch64: Add tests for v[r]shrn_high intrinsics
adds 3a0fbf7604e testsuite: aarch64: Add tests for v[q]mov[u]n_high intrinsics
adds 39d7eb8a73d testsuite: aarch64: Add tests for vcvt FP intrinsics
adds 662ef5b54de c++: Clean up normalization and satisfaction routines
adds 5a559ace9b8 c++: Unify REQUIRES_EXPR evaluation / diagnostic routines
adds d6177870dd2 d: Fix heap-buffer-overflow in checkModFileAlias [PR 99337]
adds 499193a692e c++: Defer specialization registration [PR 99170]
new 49df367b179 c++: Add fixed test [PR96474]
new c390c5df71b c++: Defer cloning to post-loading [PR 99170]
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
gcc/ChangeLog | 125 +++
gcc/DATESTAMP | 2 +-
gcc/ada/ChangeLog | 18 +
gcc/ada/cstreams.c | 5 +
gcc/ada/sem_ch3.adb | 2 +-
gcc/ada/sem_ch8.adb | 10 +-
gcc/analyzer/ChangeLog | 5 +
gcc/analyzer/diagnostic-manager.cc | 6 +-
gcc/builtins.c | 3 +-
gcc/c-family/c-common.c | 6 +-
gcc/cfgrtl.c | 59 +-
gcc/cgraph.h | 14 +
gcc/cgraphunit.c | 7 +-
gcc/common/config/arm/arm-common.c | 49 +-
gcc/common/config/s390/s390-common.c | 4 +
gcc/config.gcc | 2 +-
gcc/config/arm/arm.h | 10 +-
gcc/config/i386/i386.c | 5 +-
gcc/config/i386/i386.md | 11 +-
gcc/config/i386/predicates.md | 4 +
gcc/config/rs6000/rs6000.md | 4 +-
gcc/config/s390/driver-native.c | 2 +-
gcc/config/s390/s390-builtin-types.def | 3 +
gcc/config/s390/s390-builtins.def | 12 +
gcc/config/s390/s390-c.c | 2 +-
gcc/config/s390/s390-opts.h | 1 +
gcc/config/s390/s390.c | 10 +
gcc/config/s390/s390.h | 20 +-
gcc/config/s390/s390.md | 19 +-
gcc/config/s390/s390.opt | 3 +
gcc/config/s390/vecintrin.h | 6 +
gcc/config/s390/vx-builtins.md | 55 ++
gcc/config/sparc/t-sparc | 4 +
gcc/cp/ChangeLog | 99 +++
gcc/cp/call.c | 17 +
gcc/cp/class.c | 21 +-
gcc/cp/constexpr.c | 6 +-
gcc/cp/constraint.cc | 906 +++++++++------------
gcc/cp/cp-gimplify.c | 7 +-
gcc/cp/cp-tree.h | 24 +-
gcc/cp/cvt.c | 2 +-
gcc/cp/module.cc | 311 ++++---
gcc/cp/name-lookup.c | 54 +-
gcc/cp/name-lookup.h | 5 +-
gcc/cp/parser.c | 12 +
gcc/cp/pt.c | 117 ++-
gcc/cp/rtti.c | 24 +-
gcc/d/dmd/MERGE | 2 +-
gcc/d/dmd/dmodule.c | 2 +-
gcc/diagnostic-show-locus.c | 4 +-
gcc/doc/extend.texi | 19 +-
gcc/dwarf2out.c | 60 +-
gcc/gcov-io.h | 3 -
gcc/go/gofrontend/MERGE | 2 +-
gcc/go/gofrontend/embed.cc | 15 -
gcc/go/gofrontend/gogo.cc | 5 +
gcc/go/gofrontend/gogo.h | 11 +-
gcc/go/gofrontend/parse.cc | 2 +-
gcc/testsuite/ChangeLog | 71 ++
gcc/testsuite/g++.dg/concepts/abbrev9.C | 26 +
gcc/testsuite/g++.dg/cpp0x/decltype-call5.C | 7 +
gcc/testsuite/g++.dg/cpp0x/decltype-call6.C | 12 +
gcc/testsuite/g++.dg/cpp1z/auto1.C | 13 +
gcc/testsuite/g++.dg/cpp1z/class-deduction81.C | 20 +
gcc/testsuite/g++.dg/cpp1z/class-deduction82.C | 12 +
gcc/testsuite/g++.dg/cpp1z/class-deduction83.C | 13 +
gcc/testsuite/g++.dg/cpp1z/eval-order10.C | 27 +
.../g++.dg/cpp2a/class-deduction-aggr10.C | 21 +
gcc/testsuite/g++.dg/cpp2a/class-deduction-aggr8.C | 19 +
gcc/testsuite/g++.dg/cpp2a/class-deduction-aggr9.C | 18 +
gcc/testsuite/g++.dg/cpp2a/concepts-lambda15.C | 16 +
gcc/testsuite/g++.dg/cpp2a/concepts-placeholder3.C | 19 +
gcc/testsuite/g++.dg/cpp2a/concepts-return-req2.C | 13 +
gcc/testsuite/g++.dg/cpp2a/concepts-ts1.C | 2 +-
gcc/testsuite/g++.dg/ext/attr-flatten1.C | 9 +
gcc/testsuite/g++.dg/modules/namespace-2_a.C | 8 +-
gcc/testsuite/g++.dg/modules/pr99344_a.C | 23 +
gcc/testsuite/g++.dg/modules/pr99344_b.C | 2 +
gcc/testsuite/g++.dg/warn/Wnonnull12.C | 29 +
gcc/testsuite/g++.dg/warn/Wnonnull9.C | 20 +-
gcc/testsuite/gcc.c-torture/compile/pr99324.c | 19 +
gcc/testsuite/gcc.dg/graphite/pr99085.c | 20 +
gcc/testsuite/gcc.dg/pr99323-1.c | 17 +
gcc/testsuite/gcc.dg/pr99323-2.c | 11 +
gcc/testsuite/gcc.misc-tests/outputs.exp | 12 +
.../aarch64/advsimd-intrinsics/vXXXhn_high.inc | 65 ++
.../aarch64/advsimd-intrinsics/vaddhn_high.c | 32 +
.../aarch64/advsimd-intrinsics/vcvt_fXX_fXX.c | 100 +++
.../gcc.target/aarch64/advsimd-intrinsics/vcvtx.c | 83 ++
.../aarch64/advsimd-intrinsics/vmovn_high.c | 73 ++
.../aarch64/advsimd-intrinsics/vqmovn_high.c | 121 +++
.../aarch64/advsimd-intrinsics/vqmovun_high.c | 91 +++
.../aarch64/advsimd-intrinsics/vraddhn_high.c | 32 +
.../aarch64/advsimd-intrinsics/vrshrn_high_n.c | 177 ++++
.../aarch64/advsimd-intrinsics/vrsubhn_high.c | 32 +
.../aarch64/advsimd-intrinsics/vshrn_high_n.c | 93 +++
.../aarch64/advsimd-intrinsics/vsubhn_high.c | 32 +
gcc/testsuite/gcc.target/i386/pr95798-1.c | 2 +-
gcc/testsuite/gcc.target/i386/pr95798-2.c | 2 +-
gcc/testsuite/gcc.target/i386/pr99321.c | 41 +
.../gcc.target/s390/mul-signed-overflow-1.c | 2 +-
.../gcc.target/s390/mul-signed-overflow-2.c | 2 +-
.../s390/zvector/vec-nnpa-fp16-convert.c | 34 +
.../s390/zvector/vec-nnpa-fp32-convert-1.c | 27 +
.../s390/zvector/vec_convert_from_fp16.c | 12 +
.../gcc.target/s390/zvector/vec_convert_to_fp16.c | 12 +
.../s390/zvector/vec_extend_to_fp32_hi.c | 12 +
.../s390/zvector/vec_extend_to_fp32_lo.c | 12 +
.../gcc.target/s390/zvector/vec_round_from_fp32.c | 12 +
gcc/testsuite/gnat.dg/limited5.adb | 17 +
gcc/testsuite/lib/target-supports.exp | 16 +
gcc/tree-vrp.c | 22 +-
libbacktrace/ChangeLog | 7 +
libbacktrace/backtrace.h | 15 +-
libbacktrace/dwarf.c | 89 +-
libcpp/ChangeLog | 6 +
libcpp/line-map.c | 8 +
libgcc/ChangeLog | 6 +
libgcc/config.in | 3 +
libgcc/config/rs6000/_sprintfkf.c | 1 +
libgcc/config/rs6000/_sprintfkf.h | 3 +-
libgcc/configure | 4 +-
libgcc/configure.ac | 2 +-
libgcc/libgcov-driver.c | 11 +-
libgcc/libgcov.h | 42 +-
libgfortran/runtime/string.c | 2 +-
.../post/i386-solaris/amd64/baseline_symbols.txt | 98 +++
.../abi/post/i386-solaris/baseline_symbols.txt | 98 +++
.../abi/post/sparc-solaris/baseline_symbols.txt | 98 +++
.../sparc-solaris/sparcv9/baseline_symbols.txt | 98 +++
libstdc++-v3/include/experimental/bits/simd.h | 12 +-
.../include/experimental/bits/simd_builtin.h | 4 +-
libstdc++-v3/include/experimental/bits/simd_x86.h | 4 +-
133 files changed, 3511 insertions(+), 953 deletions(-)
create mode 100644 gcc/testsuite/g++.dg/concepts/abbrev9.C
create mode 100644 gcc/testsuite/g++.dg/cpp0x/decltype-call5.C
create mode 100644 gcc/testsuite/g++.dg/cpp0x/decltype-call6.C
create mode 100644 gcc/testsuite/g++.dg/cpp1z/auto1.C
create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction81.C
create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction82.C
create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction83.C
create mode 100644 gcc/testsuite/g++.dg/cpp1z/eval-order10.C
create mode 100644 gcc/testsuite/g++.dg/cpp2a/class-deduction-aggr10.C
create mode 100644 gcc/testsuite/g++.dg/cpp2a/class-deduction-aggr8.C
create mode 100644 gcc/testsuite/g++.dg/cpp2a/class-deduction-aggr9.C
create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-lambda15.C
create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-placeholder3.C
create mode 100644 gcc/testsuite/g++.dg/cpp2a/concepts-return-req2.C
create mode 100644 gcc/testsuite/g++.dg/ext/attr-flatten1.C
create mode 100644 gcc/testsuite/g++.dg/modules/pr99344_a.C
create mode 100644 gcc/testsuite/g++.dg/modules/pr99344_b.C
create mode 100644 gcc/testsuite/g++.dg/warn/Wnonnull12.C
create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr99324.c
create mode 100644 gcc/testsuite/gcc.dg/graphite/pr99085.c
create mode 100644 gcc/testsuite/gcc.dg/pr99323-1.c
create mode 100644 gcc/testsuite/gcc.dg/pr99323-2.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn_high.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn_high.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_fXX_fXX.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtx.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovn_high.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqmovn_high.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqmovun_high.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vraddhn_high.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshrn_high_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsubhn_high.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshrn_high_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubhn_high.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr99321.c
create mode 100644 gcc/testsuite/gcc.target/s390/zvector/vec-nnpa-fp16-convert.c
create mode 100644 gcc/testsuite/gcc.target/s390/zvector/vec-nnpa-fp32-convert-1.c
create mode 100644 gcc/testsuite/gcc.target/s390/zvector/vec_convert_from_fp16.c
create mode 100644 gcc/testsuite/gcc.target/s390/zvector/vec_convert_to_fp16.c
create mode 100644 gcc/testsuite/gcc.target/s390/zvector/vec_extend_to_fp32_hi.c
create mode 100644 gcc/testsuite/gcc.target/s390/zvector/vec_extend_to_fp32_lo.c
create mode 100644 gcc/testsuite/gcc.target/s390/zvector/vec_round_from_fp32.c
create mode 100644 gcc/testsuite/gnat.dg/limited5.adb
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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_O1 updated (c49ea864 -> b3e834d6)
by git＠git.linaro.org
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_O1
in repository toolchain/ci/base-artifacts.
discards c49ea864 0: update: gcc-491d5b3cf8216f9285a67aa213b9a66b0035137b: 1
new b3e834d6 0: update: gcc-c390c5df71bbc95627c8e5e649a3161091239fd9: 1
This update added new revisions after undoing existing revisions.
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* -- * -- B -- O -- O -- O (c49ea864)
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N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-master-arm-boots [...]
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Summary of changes:
01-reset_artifacts/console.log | 130 +-
02-prepare_abe/console.log | 178 +-
04-build_abe-bootstrap_O1/console.log | 89692 ++++++++++++++++---------------
05-check_regression/console.log | 6 +-
06-update_baseline/console.log | 4 +-
console.log | 90186 ++++++++++++++++----------------
jenkins/manifest.sh | 10 +-
7 files changed, 90080 insertions(+), 90126 deletions(-)
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[gcc] branch devel/c++-coroutines updated (d2b5331ce90 -> 0d9b2595523)
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unknown user pushed a change to branch devel/c++-coroutines
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from d2b5331ce90 Merge master r11-7459.
adds e7ca37649e4 PR middle-end/99276 - grammar in diagnostics for overflowin [...]
adds 41fbacdd103 diagnostics: fix ICE on fix-it hints on very long lines [PR99323]
adds df003d1e0bf libbacktrace: pass -1 to error callback for unrecognized DWARF
adds d1776b77570 compiler: allow //go:embed in files underscore-importing embed
adds 8b6ebc025cf [PATCH] Fix Ada bootstrap failure on Cygwin since switch to [...]
adds 7fddf3dbb98 outputs.exp: skip @file -save-temps if target has -L or -I
adds 1c4b7b367cf aix: Fix TLS thread pointer function names.
adds d97a92dca90 Daily bump.
adds 9b2084db9f9 libbacktrace: don't special case file 0
adds f8e7f3f3f33 cgraph: flatten and same_body aliases [PR96078]
adds 006693a59f7 libgfortran: Fix negation for largest integer [PR81986]
adds 4ad5b1915d5 cfgrtl: Fix up fixup_partitions caused ICE [PR99085]
adds b5040344b9c dwarf2out: Fix -gsplit-dwarf on riscv or other non-.uleb128 [...]
adds ba09d11a9d0 c-family: Avoid ICE on va_arg [PR99324]
adds f1b13064609 i386: Fix a peephole2 for -mavx512vl -mno-avx512bw [PR99321]
adds 357c4350680 Fix ICE with pathologically large frames
adds a7267237371 libstdc++: Don't use reserved identifiers in simd headers
adds 8c4f0c0ceb3 c++: namespace reachability [PR 99344]
adds 8cfa06570dd testsuite: i386: Fix gcc.target/i386/pr95798-?.c on Solaris
adds 00d79dc4be0 gcov: use mmap pools for KVP.
adds 5bc3a2bc8a8 libstdc++: Update Solaris baselines for GCC 11.1
adds 74aee6d2087 c++: C++17 and decltype of multi-operator expression [PR95675]
adds 15cf7fe3556 arm: Ignore --with-mode when CPU only supports one instruct [...]
adds 1dabbfb0f4a c++: ICE with deduction guide in checking type-dep [PR99009 [...]
adds fa6092d2cdc sparcv9: Disable -Wuninitialized warnings breaking bootstra [...]
adds 0b8fa12015f c++: Fix -fstrong-eval-order for operator &&, || and , [PR82959]
adds 949eab55b6f testsuite: aarch64: Add tests for narrowing-arithmetic intrinsics
adds fd85814c4be testsuite: aarch64: Add tests for v[r]shrn_high intrinsics
adds 3a0fbf7604e testsuite: aarch64: Add tests for v[q]mov[u]n_high intrinsics
adds 39d7eb8a73d testsuite: aarch64: Add tests for vcvt FP intrinsics
adds 662ef5b54de c++: Clean up normalization and satisfaction routines
adds 5a559ace9b8 c++: Unify REQUIRES_EXPR evaluation / diagnostic routines
adds d6177870dd2 d: Fix heap-buffer-overflow in checkModFileAlias [PR 99337]
new 0d9b2595523 Merge master r11-7492.
The 1 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
gcc/ChangeLog | 86 +++
gcc/DATESTAMP | 2 +-
gcc/ada/ChangeLog | 12 +
gcc/ada/cstreams.c | 5 +
gcc/analyzer/ChangeLog | 5 +
gcc/builtins.c | 3 +-
gcc/c-family/c-common.c | 6 +-
gcc/cfgrtl.c | 59 +-
gcc/cgraph.h | 14 +
gcc/cgraphunit.c | 7 +-
gcc/common/config/arm/arm-common.c | 49 +-
gcc/config/arm/arm.h | 10 +-
gcc/config/i386/i386.c | 5 +-
gcc/config/i386/i386.md | 11 +-
gcc/config/i386/predicates.md | 4 +
gcc/config/rs6000/rs6000.md | 4 +-
gcc/config/sparc/t-sparc | 4 +
gcc/cp/ChangeLog | 91 +++
gcc/cp/call.c | 17 +
gcc/cp/constexpr.c | 6 +-
gcc/cp/constraint.cc | 644 +++++++++------------
gcc/cp/cp-gimplify.c | 7 +-
gcc/cp/cp-tree.h | 7 +-
gcc/cp/cvt.c | 2 +-
gcc/cp/module.cc | 127 ++--
gcc/cp/name-lookup.c | 54 +-
gcc/cp/name-lookup.h | 5 +-
gcc/cp/pt.c | 36 +-
gcc/d/dmd/MERGE | 2 +-
gcc/d/dmd/dmodule.c | 2 +-
gcc/diagnostic-show-locus.c | 4 +-
gcc/dwarf2out.c | 31 +-
gcc/gcov-io.h | 3 -
gcc/go/gofrontend/MERGE | 2 +-
gcc/go/gofrontend/embed.cc | 15 -
gcc/go/gofrontend/gogo.cc | 5 +
gcc/go/gofrontend/gogo.h | 11 +-
gcc/go/gofrontend/parse.cc | 2 +-
gcc/testsuite/ChangeLog | 55 ++
.../{udlit-nosuffix-neg.C => decltype-call5.C} | 8 +-
gcc/testsuite/g++.dg/cpp0x/decltype-call6.C | 12 +
gcc/testsuite/g++.dg/cpp1z/class-deduction81.C | 20 +
gcc/testsuite/g++.dg/cpp1z/class-deduction82.C | 12 +
gcc/testsuite/g++.dg/cpp1z/eval-order10.C | 27 +
.../g++.dg/cpp2a/class-deduction-aggr10.C | 21 +
gcc/testsuite/g++.dg/cpp2a/class-deduction-aggr8.C | 19 +
gcc/testsuite/g++.dg/cpp2a/class-deduction-aggr9.C | 18 +
gcc/testsuite/g++.dg/ext/attr-flatten1.C | 9 +
gcc/testsuite/g++.dg/modules/namespace-2_a.C | 8 +-
gcc/testsuite/g++.dg/modules/pr99344_a.C | 23 +
.../g++.dg/modules/{bfield-1_b.C => pr99344_b.C} | 4 +-
gcc/testsuite/gcc.c-torture/compile/pr99324.c | 19 +
gcc/testsuite/gcc.dg/graphite/pr99085.c | 20 +
gcc/testsuite/gcc.dg/pr99323-1.c | 17 +
gcc/testsuite/gcc.dg/pr99323-2.c | 11 +
gcc/testsuite/gcc.misc-tests/outputs.exp | 12 +
.../aarch64/advsimd-intrinsics/vXXXhn_high.inc | 65 +++
.../aarch64/advsimd-intrinsics/vaddhn_high.c | 32 +
.../aarch64/advsimd-intrinsics/vcvt_fXX_fXX.c | 100 ++++
.../gcc.target/aarch64/advsimd-intrinsics/vcvtx.c | 83 +++
.../aarch64/advsimd-intrinsics/vmovn_high.c | 73 +++
.../aarch64/advsimd-intrinsics/vqmovn_high.c | 121 ++++
.../aarch64/advsimd-intrinsics/vqmovun_high.c | 91 +++
.../aarch64/advsimd-intrinsics/vraddhn_high.c | 32 +
.../aarch64/advsimd-intrinsics/vrshrn_high_n.c | 177 ++++++
.../aarch64/advsimd-intrinsics/vrsubhn_high.c | 32 +
.../aarch64/advsimd-intrinsics/vshrn_high_n.c | 93 +++
.../aarch64/advsimd-intrinsics/vsubhn_high.c | 32 +
gcc/testsuite/gcc.target/i386/pr95798-1.c | 2 +-
gcc/testsuite/gcc.target/i386/pr95798-2.c | 2 +-
gcc/testsuite/gcc.target/i386/pr99321.c | 41 ++
libbacktrace/ChangeLog | 7 +
libbacktrace/backtrace.h | 15 +-
libbacktrace/dwarf.c | 89 +--
libcpp/ChangeLog | 6 +
libcpp/line-map.c | 8 +
libgcc/ChangeLog | 6 +
libgcc/config.in | 3 +
libgcc/configure | 4 +-
libgcc/configure.ac | 2 +-
libgcc/libgcov-driver.c | 11 +-
libgcc/libgcov.h | 42 +-
libgfortran/runtime/string.c | 2 +-
.../post/i386-solaris/amd64/baseline_symbols.txt | 98 ++++
.../abi/post/i386-solaris/baseline_symbols.txt | 98 ++++
.../abi/post/sparc-solaris/baseline_symbols.txt | 98 ++++
.../sparc-solaris/sparcv9/baseline_symbols.txt | 98 ++++
libstdc++-v3/include/experimental/bits/simd.h | 12 +-
.../include/experimental/bits/simd_builtin.h | 4 +-
libstdc++-v3/include/experimental/bits/simd_x86.h | 4 +-
90 files changed, 2627 insertions(+), 630 deletions(-)
copy gcc/testsuite/g++.dg/cpp0x/{udlit-nosuffix-neg.C => decltype-call5.C} (50%)
create mode 100644 gcc/testsuite/g++.dg/cpp0x/decltype-call6.C
create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction81.C
create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction82.C
create mode 100644 gcc/testsuite/g++.dg/cpp1z/eval-order10.C
create mode 100644 gcc/testsuite/g++.dg/cpp2a/class-deduction-aggr10.C
create mode 100644 gcc/testsuite/g++.dg/cpp2a/class-deduction-aggr8.C
create mode 100644 gcc/testsuite/g++.dg/cpp2a/class-deduction-aggr9.C
create mode 100644 gcc/testsuite/g++.dg/ext/attr-flatten1.C
create mode 100644 gcc/testsuite/g++.dg/modules/pr99344_a.C
copy gcc/testsuite/g++.dg/modules/{bfield-1_b.C => pr99344_b.C} (60%)
create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr99324.c
create mode 100644 gcc/testsuite/gcc.dg/graphite/pr99085.c
create mode 100644 gcc/testsuite/gcc.dg/pr99323-1.c
create mode 100644 gcc/testsuite/gcc.dg/pr99323-2.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vXXXhn_high.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddhn_high.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvt_fXX_fXX.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtx.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmovn_high.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqmovn_high.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vqmovun_high.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vraddhn_high.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrshrn_high_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrsubhn_high.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vshrn_high_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubhn_high.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr99321.c
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[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-release-aarch64-bootstrap_debug updated (1b3bb23a576 -> 2939b358936)
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-release-aarch64-bootstrap_debug
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from 1b3bb23a576 arm: force use of r4 for __gnu_cmse_nonsecure_call when !FP [...]
adds 0babbc4c67b Daily bump.
adds b580cc4bdb8 RISC-V: Implement __builtin_thread_pointer
adds 62125ef043e Fix ICE in compute_fn_summary
adds 7297af89ea2 Fix PR ada/99095
adds 4812c9a6aa3 Daily bump.
adds 186573a26a1 debug: fix switch lowering debug info
adds 9272936ac5f tree-optimization/97897 - complex lowering on abnormal edges
adds 4f0d8562af8 tree-optimization/98526 - fix vectorizer reduction cost
adds 268b54382e5 tree-optimization/98640 - fix bogus sign-extension with VN
adds 85977f624a3 tree-optimization/98758 - fix integer arithmetic in data-re [...]
adds 2939b358936 Fix ICE with pathologically large frames
No new revisions were added by this update.
Summary of changes:
gcc/ChangeLog | 37 ++++++++++++++++++++++
gcc/DATESTAMP | 2 +-
gcc/ada/ChangeLog | 7 ++++
gcc/ada/sem_ch8.adb | 10 +++++-
gcc/config/i386/i386.c | 5 ++-
gcc/config/riscv/riscv.md | 8 +++++
gcc/doc/extend.texi | 11 +++++++
gcc/ipa-fnsummary.c | 15 ++++++---
gcc/testsuite/ChangeLog | 19 +++++++++++
gcc/testsuite/gcc.dg/pr97897.c | 14 ++++++++
gcc/testsuite/gcc.dg/torture/pr98640.c | 22 +++++++++++++
gcc/testsuite/gcc.dg/torture/pr98758.c | 13 ++++++++
.../gcc.target/riscv/read-thread-pointer.c | 7 ++++
gcc/testsuite/gnat.dg/limited5.adb | 17 ++++++++++
gcc/tree-complex.c | 5 ++-
gcc/tree-data-ref.c | 12 +++----
gcc/tree-ssa-sccvn.c | 15 +++++----
gcc/tree-switch-conversion.c | 11 ++++---
gcc/tree-switch-conversion.h | 8 ++---
gcc/tree-vect-loop.c | 17 ++++++----
20 files changed, 221 insertions(+), 34 deletions(-)
create mode 100644 gcc/testsuite/gcc.dg/pr97897.c
create mode 100644 gcc/testsuite/gcc.dg/torture/pr98640.c
create mode 100644 gcc/testsuite/gcc.dg/torture/pr98758.c
create mode 100644 gcc/testsuite/gcc.target/riscv/read-thread-pointer.c
create mode 100644 gcc/testsuite/gnat.dg/limited5.adb
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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-release-aarch64-bootstrap_debug updated (ec87cd43 -> 912cdef2)
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discards ec87cd43 0: update: gcc-1b3bb23a576e6a864f540e3bea5097f47fea507c: 1
new 912cdef2 0: update: gcc-2939b358936bb824330888def98ad848dea41483: 1
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Summary of changes:
01-reset_artifacts/console.log | 236 +-
02-prepare_abe/console.log | 260 +-
04-build_abe-bootstrap_debug/console.log | 68036 ++++++++++++++--------------
05-check_regression/console.log | 4 +-
06-update_baseline/console.log | 2 +-
console.log | 68584 ++++++++++++++---------------
jenkins/manifest.sh | 10 +-
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[toolchain/ci/newlib] branch linaro-local/ci/tcwg_bmk_stm32/gnu_eabi-master-arm_eabi-coremark-O3 updated (9ad86f619 -> 182ba1f02)
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_stm32/gnu_eabi-master-arm_eabi-coremark-O3
in repository toolchain/ci/newlib.
from 9ad86f619 Cygwin: fstatat: call fstat64 instead of fstat
adds fa22eea29 Cygwin: pty: Add workaround for rlwrap 0.40 or later.
adds 974e6d76d Cygwin: console: Revise the code to switch xterm mode.
adds 85ea2614f Cygwin: pty: Make close_pseudoconsole() be a static member function.
adds 226ed24f2 Cygwin: Add Ben Wijen to list of contributors
adds 17ede0eae syscalls.cc: Fix num_links
adds cbeb1009a syscalls.cc: Use EISDIR
adds 9e88e840c cxx.cc: Fix dynamic initialization for static local variables
adds 72770148a Cygwin: pty: Prevent pty from changing code page of parent console.
adds 25ce7a624 Cygwin: pty: Make master thread functions be static.
adds a776a0ce2 Cygwin: pty: Set input_available_event only for cygwin pipe.
adds 31ccf4058 Cygwin: document a recent bug fix
adds 877f0d13f Cygwin: rmdir: handle /dev in fhandler_dev::rmdir
adds 59ccb3a00 Cygwin: spawn.cc: Fix typo in comment by commit 974e6d76.
adds 62e739b51 Cygwin: pty: Lessen the side effect of workaround for rlwarp.
adds 5755870f7 Cygwin: pty: Reduce buffer size in get_console_process_id().
adds a53333458 Cygwin: console: Fix "Bad file descriptor" error in script command.
adds 0c0ff5dc2 Cygwin: Move post-dir unlink check
adds 4aefad2bb Cygwin: normalize_posix_path: fix error handling when .. is e [...]
adds a60a4501b Cygwin: ptsname_r: always return an error number on failure
adds cb41c375a syscalls.cc: unlink_nt: Try FILE_DISPOSITION_IGNORE_READONLY_ [...]
adds 460eb128c Cygwin: console: Add missing guard regarding attach_mutex.
adds f4cac1217 syscalls.cc: Deduplicate remove
adds b32f6dd40 Cygwin: chown: make sure ctime gets updated when necessary
adds 3388a5a42 Align *utime*() with POSIX/glibc
adds 5b941f21b Cygwin: Align *utime*() with POSIX/glibc
adds 10d083c74 Cygwin: pty: Inherit typeahead data between two input pipes.
adds 442093214 Cygwin: pty: Keep code page between non-cygwin apps.
adds 8aeb3f3e5 Cygwin: pty: Make apps using console APIs be able to debug with gdb.
adds 253352e79 Cygwin: pty: Allow multiple apps to enable pseudo console sim [...]
adds 883abd9d7 Cygwin: fchmodat: add limited support for AT_SYMLINK_NOFOLLOW
adds 0b64cc681 Cygwin: console: Make read() thread-safe.
adds f186f61d6 Cygwin: pty: Make slave read() thread-safe.
adds 6ab2d284e Cygwin: console: Align the behaviour against signal with pty.
adds 6c1552b0d Cygwin: exceptions.cc: Suspend all threads in sig_handle_tty_stop().
adds 3d256e22e Cygwin: getdtablesize: always return OPEN_MAX_MAX
adds b9cbc49b7 Cygwin: sysconf, getrlimit: don't call getdtablesize
adds 5b8358e6e Cygwin: remove the OPEN_MAX_MAX macro
adds c09320552 Cygwin: include/cygwin/limits.h: new header
adds 05e275166 Cygwin: recognize native Windows AF_UNIX sockets as reparse points
adds d4a756f13 fhandler_serial.cc: MARK and SPACE parity for serial port
adds 6aa0ab1c5 RISC-V: Use __bss_start for the starting point of .bss.
adds 55a6e49a0 Removed Soft float from MIPS
adds d8ee63450 FTW Port for Newlib
adds 3192da8f8 Cygwin: drop ftw.h in favor of new newlib ftw.h
adds 89b383321 Revert "Cygwin: fstat_helper: always use handle in call to ge [...]
adds c875ed374 Cygwin: don't copy path_conv in fhandler_base::reset
adds 5f0913df1 Cygwin: drop path_conv::reset_conv_handle
adds d0e0a59e7 Cygwin: check path_conv_handle for NULL before trying to dup it
adds 5fea2f87d Cygwin: fhandler: clean up 'copyto' logic
adds 62ee6581a Cygwin: Have tmpfile(3) use O_TMPFILE
adds 67043f48d Cygwin: only export tmpfile64 on 32 bit
adds f20641789 Cygwin: pty: Reduce unecessary input transfer.
new 2b94fad48 Cygwin: pty: Fix a bug in input transfer for GDB.
new ad2877505 Cygwin: console: Abort read() on signal if SA_RESTART is not set.
new 2caca3030 winsup/doc/posix.xml: add note for getrlimit, setrlimit, xref [...]
new 571e73067 Complete revert of 2019-08-19, st_atime in libc/include/sys/stat.h
new ff4440fcf Cygwin: console: Introduce new thread which handles input signal.
new c1a565c39 Include malloc.h in libc/stdlib/aligned_alloc.c
new a8d99824b cpuinfo: fix check for cpuid 0x80000007 support
new 038d4a78f cpuinfo: add AVX features; move SME, SEV/_ES features
new 2b9219b4a Cygwin: console: Fix SIGWINCH handling in Win7.
new 48285aa36 Cygwin: console: Fix handling of Ctrl-S in Win7.
new b07b5829f Cygwin: Add console fix regarding Ctrl-Z etc. to release notes.
new 9a7e6073d Cygwin: pty: Reflect tty settings to pseudo console mode.
new 1c70319bd Cygwin: pty: Make tty setting NOFLSH work.
new 9677efcf0 Cygwin: pty: Make FLUSHO and Ctrl-O work.
new b56a37143 Cygwin: console: Add support for FLUSHO and Ctrl-O.
new 543e39bb1 Cygwin: default to O_BINARY in fhandler_base::reset_to_open_b [...]
new 6d898f43f Cygwin: realpath: fix cygwin installation dir being access vi [...]
new e67679fca Cygwin: define fhandler_fifo::fstat
new 70f636086 Cygwin: fstat_helper: always use handle in call to get_file_a [...]
new 246121534 Cygwin: FIFO: temporarily keep a conv_handle in syscalls.cc:open
new 18b91fbe5 Cygwin: pty: Fix segfault caused when tcflush() is called.
new 6cde7279a Cygwin: console: Prevent NULL pointer access in close().
new 2911d50e7 Bump config.guess and config.sub
new 949fe7bec Cygwin: AF_UNIX: allow opening with the O_PATH flag
new 117ddd9dd Cygwin: facl: fail with EBADF on files opened with O_PATH
new 1a6fd3f05 Set __IEEE_BIG_ENDIAN for big endian RISC-V
new 26478769a RISC-V: Fix optimized strcmp on big endian
new 2f24c0b99 Cygwin: fix fstat on sockets that are not socket files
new 8889d2101 Cygwin: fix fstatvfs on sockets that are not socket files
new 1a9ceab5d Cygwin: fix fchmod on sockets that are not socket files
new cb0e71d3f Cygwin: fix fchown on sockets that are not socket files
new 012427c96 Cygwin: fix facl on sockets that are not socket files
new 425203384 Cygwin: fix linkat(2) on sockets that are not socket files
new 182ba1f02 Cygwin: simplify linkat with AT_EMPTY_PATH
The 34 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
config.guess | 536 ++++---
config.sub | 681 +++++----
libgloss/riscv/crt0.S | 2 +-
newlib/libc/include/ftw.h | 66 +
newlib/libc/include/machine/ieeefp.h | 4 +
newlib/libc/include/sys/_default_fcntl.h | 2 +-
newlib/libc/include/sys/stat.h | 6 +-
newlib/libc/include/sys/time.h | 6 +-
newlib/libc/machine/mips/machine/fenv-softfloat.h | 49 +-
newlib/libc/machine/riscv/strcmp.S | 40 +-
newlib/libc/posix/Makefile.am | 2 +-
newlib/libc/posix/ftw.c | 33 +
newlib/libc/posix/nftw.c | 154 ++
newlib/libc/stdlib/aligned_alloc.c | 1 +
newlib/libm/machine/mips/fenv.c | 10 -
winsup/CONTRIBUTORS | 1 +
winsup/cygwin/Makefile.in | 2 +-
winsup/cygwin/cxx.cc | 10 -
winsup/cygwin/cygheap.cc | 13 +
winsup/cygwin/dir.cc | 2 -
winsup/cygwin/dtable.cc | 10 +-
winsup/cygwin/dtable.h | 2 -
winsup/cygwin/exceptions.cc | 3 +
winsup/cygwin/fcntl.cc | 2 +-
winsup/cygwin/fhandler.cc | 16 +-
winsup/cygwin/fhandler.h | 479 +++---
winsup/cygwin/fhandler_console.cc | 605 +++++---
winsup/cygwin/fhandler_dev.cc | 7 +
winsup/cygwin/fhandler_disk_file.cc | 39 +-
winsup/cygwin/fhandler_fifo.cc | 23 +
winsup/cygwin/fhandler_pipe.cc | 4 +-
winsup/cygwin/fhandler_proc.cc | 46 +-
winsup/cygwin/fhandler_serial.cc | 11 +-
winsup/cygwin/fhandler_socket_local.cc | 39 +-
winsup/cygwin/fhandler_socket_unix.cc | 82 +-
winsup/cygwin/fhandler_termios.cc | 6 +-
winsup/cygwin/fhandler_tty.cc | 1606 +++++++++++++++++----
winsup/cygwin/include/cygwin/limits.h | 65 +
winsup/cygwin/include/ftw.h | 63 -
winsup/cygwin/include/limits.h | 85 +-
winsup/cygwin/include/sys/termios.h | 1 +
winsup/cygwin/ntdll.h | 3 +-
winsup/cygwin/path.cc | 8 +-
winsup/cygwin/path.h | 8 +-
winsup/cygwin/release/3.2.0 | 19 +
winsup/cygwin/resource.cc | 5 +-
winsup/cygwin/sec_acl.cc | 5 +
winsup/cygwin/select.cc | 108 +-
winsup/cygwin/select.h | 7 +
winsup/cygwin/spawn.cc | 154 +-
winsup/cygwin/syscalls.cc | 173 ++-
winsup/cygwin/sysconf.cc | 11 +-
winsup/cygwin/times.cc | 8 +-
winsup/cygwin/tty.cc | 106 +-
winsup/cygwin/tty.h | 49 +-
winsup/cygwin/wincap.cc | 11 +
winsup/cygwin/wincap.h | 56 +-
winsup/doc/new-features.xml | 8 +
winsup/doc/posix.xml | 101 +-
59 files changed, 3969 insertions(+), 1685 deletions(-)
create mode 100644 newlib/libc/include/ftw.h
create mode 100644 newlib/libc/posix/ftw.c
create mode 100644 newlib/libc/posix/nftw.c
create mode 100644 winsup/cygwin/include/cygwin/limits.h
delete mode 100644 winsup/cygwin/include/ftw.h
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[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_stm32/gnu_eabi-master-arm_eabi-coremark-O3 updated (05a30af3f23 -> d6177870dd2)
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_stm32/gnu_eabi-master-arm_eabi-coremark-O3
in repository toolchain/ci/gcc.
from 05a30af3f23 libstdc++: Implement N3644 for _GLIBCXX_DEBUG iterators
adds 505caa7295b [gcn offloading] Only supported in 64-bit configurations
adds 088e46b8d4d declare getpass in analyzer/sensitive-1.c test
adds 6541fcadc86 use sigjmp_buf for analyzer sigsetjmp tests
adds 3651c1b5c9c calibrate intervals to avoid zero in futures poll test
adds bdd1b1f5552 PR fortran/93340 - fix missed substring simplifications
adds f6ffd449e0c c++: Tweak g++.dg/template/pr98372.C.
adds 8a18261afd9 analyzer: const fixes [PR98679]
adds dea4a32b24f analyzer: fixes to -fdump-analyzer-json
adds fe701195313 slp: elide intermediate nodes for complex add and avoid truncate
adds 500600c7840 slp: Support optimizing load distribution
adds e09173d84da slp: support complex multiply and complex multiply conjugate
adds 31fac31800b slp: support complex FMA and complex FMA conjugate
adds 478e571a3ee slp: support complex FMS and complex FMS conjugate
adds b50df1e749b slp: Add complex operations class to share first match amon [...]
adds 59832db9a71 slp: Add Tests for complex mul, mls and mla"
adds f1096055854 Add GCC_EXTRA_DIAGNOSTIC_OUTPUT environment variable for fi [...]
adds 02e7af1122c libstdc++: Implement N3644 for _GLIBCXX_DEBUG iterators
adds 387f6c15d30 Handle fancy_abort before diagnostic initialization [PR98586]
adds f1fc27b6c51 c++: Minor refactoring in process_init_constructor_record
adds b95d97f1a5f jit: remove "Alpha" warning from docs
adds 5fff80fd79c Daily bump.
adds b0ccd3922f5 compiler: add support for reading embedcfg files
adds c4eec1efae0 testsuite: Fix sed script errors in complex tests
adds 2ea6f4a377e tree-optimization/98685 - fix placement of extern converts
adds 7432f255b70 arm: Auto-vectorization for MVE: vshl
adds bfab355012c arm: Auto-vectorization for MVE: vshr
adds 0411ae7f08e libatomic, libgomp, libitc: Fix bootstrap [PR70454]
adds cb60334b716 testsuite/96098 - remove redundant testcase
adds 1a630642009 arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics
adds d03f14c354a testsuite/96147 - remove scanning for ! vect_hw_misalign
adds e1bd80fb706 testsuite/96147 - key scanning on vect_hw_misalign
adds aa4ee5798fe testsuite/96147 - scan for vectorized load
adds b36c9cd0947 testsuite/96147 - align vector access
adds dc8475e3348 Pytest in tests: improve
adds 446703ccc2c tree-optimization/96376 - do not check alignment for invari [...]
adds f1d054017ef Revert "arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 [...]
adds 63999d751df arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics
adds f9a577927eb IBM Z: Fix linking to libatomic in target test cases
adds 7f6cdaa9a8d rtl-ssa: Fix a silly typo
adds f2cc526f47a recog: Fix insn_change_watermark destructor
adds 5a783f42d77 aarch64: Add a minipass for fusing CC insns [PR88836]
adds 492b90f33df c++: Fix langspecs with -fsyntax-only [PR98591]
adds 1ba71fabb78 preprocessor: Make quoting : [PR 95253]
adds 7d0df0aeb67 i386: Use cpp_define_formatted for __SIZEOF_FLOAT80__ definition
adds d3959070aa4 [PATCH] aarch64: Implement vmlsl[_high]* intrinsics using builtins
adds 50dbced2f37 openmp: Change the way of building of reduction array type
adds adb520606ce c-family: Improve MEM_REF printing for diagnostics [PR98597]
adds a3128bf0128 bootstrap: fix failing diagnostic selftest on Windows [PR98696]
adds aaec739250b testsuite: Add testcase coverage for already fixed [PR96671]
adds c0194736b47 gcc.dg/analyzer tests: use __builtin_alloca, not alloca.h
adds cd09079cfd5 c++: Fix list-init of array of no-copy type [PR63707]
adds ad260343385 AArch64: Add NEON, SVE and SVE2 RTL patterns for Multiply, [...]
adds 424deca72b6 c++: Fix copy elision for base initialization
adds d75199f7823 c++: Avoid redundant copy in {} init [PR98642]
adds e63c2161d09 drop -dumpbase-ext from producer string
adds 5c046034e3e match.pd: Optimize (x < 0) ^ (y < 0) to (x ^ y) < 0 etc. [PR96681]
adds 0425f4c1b63 match.pd: Generalize the PR64309 simplifications [PR96669]
adds e1efa6af61a preprocessor: Make quoting : [PR 95253]
adds 9beb6d88eff c++: Fix qualified array-type construction [PR 98538]
adds b90e4a97419 fortran: Fixes a bug in ISO_Fortran_binding.c.
adds c029fcb5680 Reset force_source_line in final.c
adds f1ad419ebfd rs6000, vector integer multiply/divide/modulo instructions
adds 2f7f0d32e74 Daily bump.
adds 2c356f221bb libstdc++-v3: Add -fcf-protection=none to -march=i486
adds b673e7547fb cd_dce: Return TODO_update_address_taken from last cd_dce [ [...]
adds e2559c3945a match.pd: Optimize ((cst << x) & 1) [PR96669]
adds 7e02426ba0c nios2: Remove custom instruction warnings
adds 42f4e239924 nios2: Add -mcustom-fpu-cfg=fph2
adds 5e5d56919dd RTEMS: Add -mcustom-fpu-cfg=fph2 multilib
adds a6d22fb21c6 openmp: Add support for the OpenMP 5.0 task detach clause
adds a2960a04d51 testsuite: Fix up a testcase to find the right ISO_Fortran_ [...]
adds 59cf67d1cf7 Daily bump.
adds 3804e937b0e Default to DWARF5
adds 0f4c8f517b7 ipa: Adjust cgraph verifier to materialization on demand (P [...]
adds 192105b6a2a Avoid assuming SSA_NAME_IDENTIFIER is nonnull.
adds 56b5d13e278 aix: default to DWARF 4.
adds b654d23a470 testsuite: Skip DWARF 5 testcases on AIX.
adds 4c9bcd5c81a Daily bump.
adds 4905f404018 Fix ChangeLog entries.
adds 994fb69ac1b testsuite: powerpc fold-vec and sse updates.
adds d3b41bde961 libgomp: Don't access gomp_sem_t as int using atomics uncon [...]
adds 0f951b3dd34 RTEMS: Fix libgomp build
adds 2e43880dbd4 libstd++: : Add workaround for as Error: file number less t [...]
adds a81d2f1e414 libstdc++: Fix narrow char test to use stringbuf not wstringbuf
adds 104304cd246 testsuite/97299 - fix test condition of gcc.dg/vect/slp-reduc-3.c
adds acdc49fabf0 [arm,testsuite]: Fix options for vceqz_p64.c and vceqzq_p64.c
adds b8c3f5196e1 libgomp: enable linux-futex on riscv64
adds e393f03b1a7 testsuite/97494 - adjust gcc.dg/vect/slp-11b.c
adds ec153f96f89 libstdc++: Only test writing to wostream if supported [PR 98725]
adds c7e276b869b analyzer: use "malloc" attribute
adds 66cbe54960c Avoid no-stack-protector-attr fails on hppa*-*-*.
adds 76c1dd15e4a Skip asm goto tests on hppa*-*-*.
adds f56e14101b9 aix: document dwarf 4 default (and TPF default)
adds 9675ccd64ef widening_mul: Fix up signed multiplication overflow check h [...]
adds 32b6e917ac4 c++: Add CTAD + pack expansion testcase
adds a89c5d3539c [PR97847] IRA: Skip abnormal critical edge splitting
adds 325e70b47c6 libbacktrace: use correct directory/filename for DWARF 5
adds bfde774667f libbacktrace: don't fail tests if dwz fails
adds 9a3ab93ceb2 [committed] Minor fix to pr41445-7 testcase
adds ef1f8ee67d4 Daily bump.
adds c907e439413 compiler: read embedcfg files, parse go:embed directives
adds 9ee33d7c33f RISC-V: The 'multilib-generator' enhancement.
adds 665e80ca5ec Fix PR ada/98740
adds 9b8741c98f2 ipa-sra: Do not remove return values needed because of non-call EH
adds 049bfd186fa OpenMP/Fortran: Fixes for {use,is}_device_ptr
adds 7d6f7e92c3b ipa/97673 - fix input_location leak
adds 4b690f161b8 sparc,rtems: add __FIX_LEON3FT_TN0018 for affected targets
adds f27cd6f4226 middle-end/98638 - avoid SSA reference to stmts after SSA d [...]
adds 66dd412feea ipa/98330 - avoid ICEing on call indirect call
adds 8227106f566 [committed] Fix dwarf-float.c test in testsuite
adds 763b865a17d aarch64: Remove testing of saturation cumulative QC bit
adds 04b472ad0e1 aarch64: Relax flags of saturation builtins
adds 04cdb132020 [PATCH, rs6000] Update pr88233.c test (pr91799)
adds 6a2a38620cf alias: Fix offset checks involving section anchors [PR92294]
adds 6e6f3ed47e5 c++: Fix null this pointer [PR 98624]
adds 7266ff2a243 c++: Remove unused fn
adds c37f1d4081f c++: ICE when late parsing noexcept/NSDMI [PR98333]
adds 29853c65324 c++: Always check access during late-parsing of members [PR58993]
adds 9693e255ee2 PR middle-end/98664 - inconsistent -Wfree-nonheap-object fo [...]
adds d89b00c095e c++: ICE with USING_DECL redeclaration [PR98687]
adds eed40bca6f2 compiler: initialize variables with go:embed directives
adds 2b27f37f90c c++: Crash when deducing template arguments [PR98659]
adds a311dfaf92c Update gcc de.po.
adds 6bc6094fa3f testsuite: aix testsuite adjustments
adds f35a4f96373 Daily bump.
adds b83604c75fe dwarf2out: reset generation count in toplev::finalize [PR98751]
adds c05cdfb3f63 OpenMP/Fortran: Fix gfortran.dg/gomp/is_device_ptr-2.f90
adds 7ab1abf3b82 openmp: Don't ICE on detach clause with erroneous decl [PR98742]
adds 34599780d0d tree-optimization/98758 - fix integer arithmetic in data-re [...]
adds 4d2ecd960a0 builtins: Fix up two bugs in access_ref::inform_access [PR98721]
adds a95538b6c5a Fix gfortran.dg/gomp/task-detach-1.f90 for non 64bit pointers
adds ea74a3f548e vect: Fix VLA SLP invariant optimisation [PR98535]
adds 79e1251b642 c++: Defer access checking when processing bases [PR82613]
adds cafcfcb5840 c++: Fix tsubsting CLASS_PLACEHOLDER_TEMPLATE [PR95434]
adds 49e8c14ef6f Optimize combination of comparisons to dec+compare
adds 261cdd23195 Handle overflow in dependence analysis lambda ops gracefully
adds 4334b524274 [PR98722] LRA: Check that target has no 3-op add insn to tr [...]
adds 27c792895bd debug: Fix up DWARF 5 -g -flto -ffat-lto-objects [PR98765]
adds f8c67777661 rs6000: Fix rs6000_emit_le_vsx_store (PR98549)
adds e140f5fd3e2 aarch64: Split vec_selects of bottom elements into simple move
adds 911f797a9be c++: Avoid UB in signed shift [PR 98625]
adds 0bb27b81a76 libgomp: Fix up GOMP_task on s390x
adds 842afc4e289 Re: trapv question
adds fb39c4fe445 aix: make ctype_inline.h thread-safe and avoid _OBJ_DATA ch [...]
adds b93d0e36c0a Daily bump.
adds e711b67a908 Fix incorrect optimization by cprop_hardreg.
adds fa9d1ad2ff6 testsuite/98224 - un-XFAIL Walloca-2.c on ilp32
adds 8afef308b49 testsuite/98241 - remove ilp32 XFAIL of gcc.dg/pr78973.c
adds f46a40112ca testsuite/97299 - more gcc.dg/vect/slp-reduc-3.c massaging
adds eaf883710c0 Fortran: This patch fixes comments 23 and 24 of PR96320.
adds a1a967ce1ff libstdc++: Regenerate Makefile.in
adds 3c1cf7350bf c++: Stat-hack for members [PR 98530]
adds 9be0a89c95c gcc/fortran/intrinsic.texi: Fix typo
adds 0568f801eff arm: [testuiste] Fix ivopts.c target test [PR96372]
adds e154009f35a Fix typo in arm_mve.h __arm_vcmpneq_s8 return type
adds 279d3a89b79 d: Enable private member access for __traits
adds 43705f3fa34 aarch64: Use canonical RTL for sqdmlal patterns
adds 0fb7aa205af c++: Fix up potential_constant_expression_1 FOR/WHILE_STMT [...]
adds 7944753fad5 c++: Fix null this pointer [PR 98624]
adds f645da0e4ab c++: Fix excessive instantiation inside decltype [PR71879]
adds efb6bc55a93 fwprop: Allow (subreg (mem)) simplifications
adds 68ba1039c7d [PR98777] LRA: Use preliminary created pseudo for in LRA el [...]
adds 9929d04ee24 testsuite: Adjust cpp2a/lambda-uneval regrex
adds 7559d465fda Daily bump.
adds 070a1fb5f52 MAINTAINERS: Update my e-mail address
adds bca467e56fe c++: ICE with delayed noexcept and attribute used [PR97966]
adds ee78c20e74d Lower AVX512 vector comparison to AVX version when dest is vector.
adds 4e3beaca15c arm: Fix ICE with incompatible values for -mfp16-format [PR98636].
adds fd61ca67f97 tree-optimization/98786 - fix issue with phiopt and abnormals
adds e287a2a11d7 on ARRAY_REFs sign-extend offsets only from sizetype's prec [...]
adds 36fe1cdc953 match.pd: Replace incorrect simplifications into copysign [ [...]
adds 8bad25eb56b middle-end/98773 - always sign extend CHREC_RIGHT
adds 4804de453e7 driver: do not check file existence here [PR 98452]
adds b46027c6544 Drop time profile for multi-threaded training run.
adds b2922559758 rs6000: Support variable insert and Expand vec_insert in ex [...]
adds e3a8ef8ef2a rs6000: Enable vec_insert for P8 with rs6000_expand_vector_ [...]
adds 4be156d6bef middle-end/98793 - properly handle BLKmode vectors in vecto [...]
adds eee8ed2f22b testsuite: Uniquify test names [PR 98795]
adds 9d33785f57d tree-ssa-mathopts: Use proper poly_int64 comparison with pa [...]
adds d7e681fc3af Testcase for old PR 47059
adds bf8ee9e4eed Fortran: Fix for class functions as associated target [PR98565].
adds 25fc4d01a8e c++: ICE when mangling operator name [PR98545]
adds a9ed18295bf c++: Fix up ubsan false positives on references [PR95693]
adds 90cbc769006 c++: Fix base copy elision thinko [PR98744]
adds 32a93eac7ad MAINTAINERS: Add myself for write after approval
adds b485fa167ef dwarf2out: Always emit required 0 entries for DWARF 5 in *. [...]
adds d08677c11dc testsuite: Fix sse2-andnpd-1.c and sse-andnps-1.c testscase [...]
adds b30e19b517f testsuite: Fix a typo - UINON_TYPE to UNION_TYPE - in gcc.t [...]
adds 70ab52b8caf testsuite: Fix a typo - UINON_TYPE to UNION_TYPE - in gcc.t [...]
adds 9cead790738 doc: ensure GCC_EXTRA_DIAGNOSTIC_OUTPUT gets an HTML anchor
adds ab8cde87cac testsuite: Enable spbp.C on AIX.
adds 89100826ace c++: ICE with noexcept in class in member function [PR96623]
adds 16b7b8a32d4 aarch64: Use RTL builtins for integer mla intrinsics
adds 8502e23d1f2 Daily bump.
adds eb9883c1312 testsuite: fix gcc.target/powerpc ilp32 failures
adds a8cef3cba69 c++: 'this' injection and static member functions [PR97399]
adds c63f091db89 rs6000: Fix up __m64 typedef in mmintrin.h [PR97301]
adds 7e0f147a29f c++: private inheritance access diagnostics fix [PR17314]
adds 81f928ec8e8 libphobos: Fix executables segfault on mipsel architecture
adds 6b1633378b7 Daily bump.
adds 02551aa9996 Daily bump.
adds 389b67feac7 Arm: Add NEON and MVE complex mul, mla and mls patterns.
adds b7a0507ad9f fold: Fix up strn{case,}cmp folding [PR98771]
adds 28229916e1b RTEMS: Fix GCC specification
adds c6b0e33febb Fortran: Fix deferred character lengths in array constructo [...]
adds 5d01fc7c116 Fix internal error on extension with interface at -O2
adds 0433fc2d7d4 RTEMS: Fix default linker script
adds defc40db9e0 middle-end/98807 - more vector_element_bits fixes
adds 5089df534b8 Restore profile reproducibility.
adds e05a117dc4b Enable -fprofile-reproducible=parallel-runs for profiledbootstrap.
adds fe5cb7f94d4 configure: Add workaround for buggy binutils 2.35 [PR98811]
adds 10c83fb7131 gcc/fortran/intrinsic.texi: Fix typos
adds 94ff4c9dd98 c++: [[no_unique_address]] in empty base [PR98463]
adds d9ad3b422f0 Fix wrong format for fprintf.
adds 0194e2f02d7 libgomp: Add documentation for omp_fulfill_event runtime function
adds a43e0dfb63f Add test case for PR 96843.
adds 7d54cccad33 Commit test case for PR 96386.
adds d6f1cf644c4 PR c++/98646 - spurious -Wnonnull calling a member on the r [...]
adds a61efd46937 PR fortran/70070 - ICE on initializing character data beyon [...]
adds 161e4c08624 Daily bump.
adds 667c8e33270 skip asan-poisoning of discarded vars
adds 7423731691e dwarf2asm: Fix up -gdwarf-64 for 32-bit targets
adds eb77a934eec testsuite: Fix up pr98807.c on i686-linux [PR98807]
adds 5a36cae275a d: Merge upstream dmd 609c3ce2d, phobos 3dd5df686
adds d9f50366102 amdgcn: Allow V64DFmode min/max reductions
adds b3cc0c9a6ac testsuite/g++.dg/modules/modules.exp: Janitorial fixes
adds 80198c701a7 Commit test case for PR 67539.
adds d40b21eebc9 libgcov: improve profile reproducibility
adds 2e81b16c243 liblsan: build missing lsan_posix.cpp file
adds 4b59dbb5d67 middle-end/98726 - fix VECTOR_CST element access
adds 5bbc80d0e40 Fix dumping of VEC_WIDEN_{PLUS,MINUS}_{LO,HI}_EXPR
adds 17ad8cdebe6 aarch64: Tighten up checks for ubfix [PR98681]
adds 6e44c09b2df dwarf2asm: Fix bootstrap on powerpc*-*-* [PR98839]
adds 9c41bcc59c2 Fix PR ada/98228
adds e80f1f6b7a3 testsuite: Fix TBAA in sse*and*p[sd]*.c tests
adds a4dfd0f089a c++: constexpr and empty fields [PR97566]
adds 96253f069ea c++: Invisible refs are not restrict [PR97474]
adds 78739c2df78 c++: Add support for -std=c++23
adds e62bb7f0834 Daily bump.
adds efc9ccbfd0c varpool: Restore GENERIC TREE_READONLY automatic var optimi [...]
adds da5c25f3710 Rename PROP_trees to PROP_gimple
adds 003f0414291 Fortran: Fix ICE due to elemental procedure pointers [PR98472].
adds 6cf43433750 testsuite: Fix TBAA in {sse,avx}*and*p[sd]*.c tests
adds 530b1d68876 Fix ICE for [PR target/98833].
adds 686b1cdfdc4 libgcc, i386: Add .note.GNU-stack sections to the ms sse/av [...]
adds 4225af228b5 Fortran: Fix ICE due to elemental procedure pointers [PR93924/5].
adds f004d6d9fab libstdc++: Add string contains member functions for C++2b
adds 9d66505a5df aarch64: Use RTL builtins for integer mla_n intrinsics
adds a199da782fc libstdc++: Optimize std::string_view::find [PR 66414]
adds d2201ac0df4 aarch64: Use RTL builtins for integer mls intrinsics
adds 3fd10728cb1 aarch64: Use RTL builtins for integer mls_n intrinsics
adds c91db798ec6 tree-optimization/98854 - avoid some PHI BB vectorization
adds 2bcceb6fc59 libstdc++: Add std::experimental::simd from the Parallelism TS 2
adds 02e32295b28 libstdc++: Add simd testsuite
adds c31a633e13f libstdc++: Use printf to print control characters
adds d53a4f9b681 aarch64: Use RTL builtins for [su]mlal intrinsics
adds 3670dbe4905 libstdc++: Regenerate libstdc++ HTML docs
adds 7a279bed24e Combine patterns for p10 load-cmpi fusion
adds 55163419211 aarch64: Fix up *aarch64_bfxilsi_uxtw [PR98853]
adds 9cd7c32549f c++: Dependent using enum [PR97874]
adds 081c96621da [PR97684] IRA: Recalculate pseudo classes if we added new p [...]
adds 1cdca4261e8 Fix strides for C descriptors with stride > 2.
adds aa69f0a8203 Daily bump.
adds f76d0d86454 RISC-V: Fix -march option parsing when extension exists.
adds fbe37371cf3 rs6000: Fix vec insert ilp32 ICE and test failures [PR98799]
adds a523add327c rtl-optimization/80960 - avoid creating garbage RTL in DSE
adds c392d040f6c c++: Some C++20 and C++23 option help fixes
adds 33a7a93218b PR fortran/86470 - ICE with OpenMP, class(*) allocatable
adds f7a6d314e7f Fix LTO bootstrap on Windows
adds fdb904a1822 aarch64: Reimplement vshrn_n* intrinsics using builtins
adds d61ca09ec93 aarch64: Reimplement vshrn_high_n* intrinsics using builtins
adds af66f4f1b06 c++: header unit template alias merging [PR 98770]
adds 87301e3956d aarch64: Use RTL builtins for [su]mlal_n intrinsics
adds ff119f340e4 aarch64: Fix gcc.target/aarch64/narrow_high-intrinsics.c testism
adds 8a8e515c2bf aarch64: Use RTL builtins for [su]mlsl_n intrinsics
adds 6bb207b468d c++: Fix up handling of register ... asm ("...") vars in te [...]
adds e11e5d3889f Map long double built-ins correctly with IEEE 128-bit long double.
adds e28bd09498b testsuite: Fix up a testcase to find the right ISO_Fort [...]
adds 31a0ab9213f arm: Adjust cost of vector of constant zero
adds a054608c9c4 libstdc++: Fix copyright dates for simd headers and tests
adds 513ee7d2cd9 tree: Don't reuse types if TYPE_USER_ALIGN differ [PR94775]
adds 850a8ec54c4 c++: Fix -Weffc++ in templates [PR98841]
adds e6bce7fe17b gccgo driver: always act as though -g is passed
adds 85d04a2ecb7 Daily bump.
adds f8f5388c9e9 c++: Fix infinite looping with invalid operator [PR96137]
adds 280a59d9211 testsuite: Run vec_insert case on P8 and P9 with option specified
adds 9c445c07cda expand: Fix up find_bb_boundaries [PR98331]
adds e7429bc9d60 arm: Fix up -mcpu=iwmmxt ICEs [PR98849]
adds a8c455bafde rtl-optimization/98144 - tame REE memory usage
adds f4e426f7bd7 tree-optimization/97627 - Avoid computing niters for fake edges
adds cb52e59e338 rtl-optimization/98863 - fix PRE/CPROP memory usage check
adds 0833e3e1ff1 change unit of --param max-gcse-memory to kB
adds e053f96a9f5 aarch64: Use RTL builtins for [su]mlsl_lane[q] intrinsics
adds cb995de62aa aarch64: Reimplement vaddlv* intrinsics using builtins
adds d5e0d1f1d2c aarch64: Reimplement vabal* intrinsics using builtins
adds 9f499a86b29 aarch64: Re-implement vabal_high* intrinsics using builtins
adds 9b588cfb428 aarch64: Reimplement vabdl_high* intrinsics using builtins
adds ee4c4fe289e aarch64: Use RTL builtins for [su]mull_n intrinsics
adds a7f52181a6a rtl-optimization/98863 - tame i386 specific RPAD pass
adds 2dd1f944547 tree-optimization/98866 - Compile time hog in VRP
adds 83bdc9f7034 c++: Fix unordered entity array [PR 98843]
adds 91a95ad2ae0 [PATCH, rs6000] improve vec_ctf invalid parameter handling.
adds 726b7aa004d libgo: update to Go1.16rc1
adds 7f9f83ef300 [PR97701] LRA: Don't narrow class only for REG or MEM.
adds eb06fdd424b analyzer: consolidate conditionals in paths
adds 0202fa3d635 [PR97701] Modify test for trunk
adds fa00e35c178 [PATCH, rs6000] Fix typo in gcc.target/pr91903.c dg-require stanza
adds d761172d9b2 PR testsuite/98870: Fix IEEE 128-bit fortran test
adds 4d31df40899 internal/cpu: correctly link to getsystemcfg
adds 2900f2f2c5f Daily bump.
adds 25f303e9a27 testsuite: Fix up gomp/simd-{2,3}.c tests [PR98243]
adds accc5ba53e0 i386, df: Fix up gcc.c-torture/compile/20051216-1.c -O1 -ma [...]
adds 92dd3e71f95 libphobos: Synchronize libdruntime bindings with upstream druntime
adds 2e7750cb518 aix: Permit use of AIX Vector extended ABI mode
adds 349b909bb35 aix: add periods to option explanation.
adds 1242eb75b3d Fusion patterns for logical-logical
adds 245ccc8e6b1 testsuite: Update pr79251 ilp32 store counts.
adds 5dfbad4f7c4 Daily bump.
adds 98342bdd2b7 testsuite, Darwin : Skip ELF-specific tests.
adds 2b5af103482 Add missing definition of SIZE_MAX
adds 94d5ba26f93 Daily bump.
adds b90d051ecbc testsuite: Update pr79251 ilp32 store regex
adds 972918eea87 rtl-optimization/98863 - prune RD with LIVE in STV
adds bbe6998b227 RISC-V: Fix gcc.target/riscv/attribute-18.c
adds 1b303ef6cc8 c++: Add testcase for PR84494
adds 0a3eccb6ef9 AArch64: Change canonization of smlal and smlsl in order to [...]
adds 8db8a004762 testsuite: aarch64: Add tests for vmull_high intrinsics
adds bec5dbae564 testsuite: aarch64: Add tests for vmlXl_high intrinsics
adds 6e0a231a4aa c++: alias in qualified-id in template arg [PR98570]
adds bab669f2fc6 c++: Improve sorry for __builtin_has_attribute [PR98355]
adds 7e534fb7d82 c++: Fix ICE from verify_ctor_sanity [PR98295]
adds c2f8e378d64 Verify a warning for a class with a ref-qualified assignmen [...]
adds d7bd009ab00 Fix statistic accounting for auto_vec and auto_bitmap
adds 445d6db6490 Avoid -Wstringop-truncation.
adds 90c9b2c1768 libstdc++: Update C++17 status table for <charconv>
adds 0718336a528 Reset front end trees before they make it into the middle e [...]
adds 6a2053773b8 Document various BLOCK macros.
adds 6b2034c479e aarch64: Reimplement vabdl_* intrinsics using builtins
adds 8bfdf51d859 aarch64: Reimplement vmovl_high_* intrinsics using builtins
adds 11056ab7687 tree-optimization/98499 - fix modref analysis on RVO statements
adds 33a1e511b57 libstdc++: Make deque iterator operator- usable with value- [...]
adds 11d4ec5d45c analyzer: fix false positives with *UNKNOWN_PTR [PR98918]
adds 850e5878f8f aarch64: Reimplement vrshrn* intrinsics using builtins
adds f7884fb1761 Daily bump.
adds 6a481021a65 d: Fix junk in generated symbol on powerpc64-*-* [PR98921]
adds f2f639c4a78 analyzer: add more feasibility test cases [PR93355,PR96374]
adds 8a2750086d5 analyzer: directly explore within static functions [PR93355 [...]
adds 78811355689 restore current_function_decl after re-gimplifying nested A [...]
adds 250fd9fb118 arm: Auto-vectorization for MVE: vorn
adds bc7c2b34c34 PR target/98743: Fix ICE in convert_move for RISC-V
adds eedda4e1608 testsuite: Add testcase for already fixed PR [PR97960]
adds 1592b74350a tree-vect-patterns: Don't create over widening patterns for [...]
adds 886f9f519c0 libstdc++: Fix markup for status tables in docs
adds 7bcd5e09fb3 aarch64: Relax builtin flags for integer builtins
adds 5cebc818213 aarch64: Relax some builtins to AUTO_FP
adds e8062ad4680 aarch64: Add and use FLAG_LOAD in builtins
adds 4b8a7a6e81b aarch64: Relax flags for floating-point builtins to FP wher [...]
adds 13d8be91218 aarch64: Update flags for bfloat16 builtins
adds 831ff94a882 Fortran: Check remains fixed by patch for PRs 96100/101 [PR91862].
adds 8fdfd0cfdb7 aarch64: Reimplement vqmovun_high* intrinsics using builtins
adds d14cf89b942 aarch64: Reimplement vrsqrte* intrinsics with builtins
adds 709718d4d89 c++: Member fns and deduction guide rewriting [PR98929]
adds db53dd4f784 Add test-case.
adds 5d5130ad5c3 fix memory leaks
adds 8e4a738d254 gotools: for "make check" run "go test embed/internal/embedtest"
adds 548b75d8222 Daily bump.
adds 5e606ed90a1 slp: Split out patterns away from using SLP_ONLY into their [...]
adds 1b5572edb8c i386: Remove V1DImode shift expanders [PR98287]
adds eb69a49c4d3 lra-constraints: Fix error-recovery for bad inline-asms [PR97971]
adds 176c7bd840a ifcvt: Avoid ICEs trying to force_operand random RTL [PR97487]
adds 1b06fcb0c9e more memory leak fixes
adds e3f9f80bfa9 Fortran: Fix Array dependency with local coarrays [PR98913]
adds fc130ab54fd Assorted LTO fixes for Ada
adds e8c87bc07b5 Fix regression with partial rep clause on variant record type
adds 84110515b93 Fill up padding in lto_section struct.
adds 6dc82826ba6 lra: clear lra_insn_recog_data after simplifying a mem subreg
adds 719877b0796 aarch64: Use RTL builtins for [su]mlal_high intrinsics
adds 2dac6586004 aarch64: Use RTL builtins for [su]mlal_high_n intrinsics
adds b2c4cf7b19d aarch64: Use RTL builtins for [su]mlsl_high_n intrinsics
adds 9a00ff96fad aarch64: Use RTL builtins for [su]mlal_high_lane[q] intrinsics
adds 9633e579763 aarch64: Use RTL builtins for [su]mlsl_high_lane[q] intrinsics
adds 3535402e201 amdgcn: Add gfx908 support
adds 25fdd0d6df4 c++: ICE with late parsing of noexcept in nested class [PR98899]
adds 05c93a63a6b do not generate fusion.md, update contrib/gcc_update
adds 74f2ae3f1fc Fix earlier commit missing patch review changes
adds aa89c53c737 libstdc++: Support skip, only, expensive, and xfail markers [...]
adds 4f22942841e libstdc++: Fix NEON intrinsic types usage
adds db256f9bef8 libstdc++: Support -mlong-double-64 on PPC
adds abc540e30a3 libstdc++: Fix simd_mask<double> on POWER w/o POWER8
adds 471b1933484 libstdc++: Fix several check-simd interaction issues
adds b27ea896dd7 libstdc++: Fix DRIVEROPTS and TESTFLAGS processing
adds 0a8bc61fe02 libstdc++: Fix incorrect display of old test summaries
adds 71f9b9bd0ac libstdc++: Immediate feedback with -v
adds 81c2c32de9c libstdc++: Fix mask reduction of simd_mask<double> on POWER7
adds b83a52fe07b libstdc++: Skip testing hypot3 for long double on PPC
adds ec384c56900 libstdc++: Abort test after 1000 lines of output
adds 8f7ad986515 libstdc++: Support timeout and timeout-factor options
adds af60e4bd4b6 libstdc++: Improve test codegen for interpreting assembly
adds 4b940ccee19 libstc++: Implement hmin and hmax
adds 3de9bd16c91 libstdc++: Work around test failures using -mno-tree-vrp
adds 59887657418 libstdc++: Improve "find_first/last_set" for NEON
adds a6f08be383f libstdc++: Fix incorrect test for std::error_code comparisons
adds c926940f528 testsuite: Add test for already fixed PR [PR97804]
adds 530203d6e32 libgo: install new 1.16 packages
adds 1f69e63cfcc c++: Implement C++23 P0330 - Literal Suffixes for ptrdiff_t [...]
adds 5c3d388aee5 PR tree-optimization/98937 - pointer_query cache leaks
adds 5c62e4f255b c++: Fix alias comparison [PR98926]
adds b52a1dfe12a c++: Mark member functions as const [PR98951]
adds b1a207c6df0 libphobos: Merge upstream druntime 9d0c8364, phobos 9d575282e.
adds 34215a7a3a3 Fix typo in Fortran manual
adds ac16f4327fe libcpp: Fix up -fdirectives-only preprocessing [PR98882]
adds 9faaa80776a Daily bump.
adds 7b258ac7afa c++: subst failure in attribute argument [PR95192]
adds 787f3ebf00d c++: No aggregate CTAD with explicit dguide [PR98802]
adds 5eb792e7a12 doc: mention -mprefer-vector-width in target attrs
adds f0e618faeb6 Fortran: OpenMP/OpenACC diagnose substring rejections better
adds 7002a33d1ba tree-optimization/98855 - fix some vectorizer cost issues
adds 1d6228454c4 aarch64: Use RTL builtins for [su]mull_high_n intrinsics
adds aa652fb2a08 aarch64: Use RTL builtins for [su]mull_high_lane[q] intrinsics
adds e6cc142ad99 c++: fix string literal member initializer bug [PR90926]
adds e91f9da5792 c++, libcpp: Use make_signed_t<size_t> in the 1z diagnostics
adds 26fd3bf75b5 Correct date value of the __cpp_size_t_suffix macro.
adds 65c1cb35899 diagnostics: fix excessive range-printing involving macros [...]
adds 4e7c24d97dd c++: Empty args for variadic concept [PR98717]
adds ce5720447c6 PR c/97882 - Segmentation Fault on improper redeclaration o [...]
adds c1d56e6a737 d: Merge upstream dmd 46133f761, druntime 0fd4364c
adds 0b34dbc0a24 testsuite: Fix up pr25376.c on powerpc64-linux and array-qu [...]
adds cff6e8db880 openacc: Dereference BT_CLASS data pointers but not BT_DERI [...]
adds f743fe23166 openacc: Use class_pointer instead of pointer attribute for [...]
adds 9a4d32f85cc openacc: Allow strided arrays in update directives
adds b2d84e9f9cc openacc: Tests for character types in derived-type mappings
adds a19dd5e644a Daily bump.
adds b80fefd6264 Enable X86_TUNE_AVX256_UNALIGNED_{LOAD，STORE}_OPTIMAL in ge [...]
adds 8d0737d8f4b Fix ICE: Don't generate integer mask comparision for 128/25 [...]
adds 072f20c5559 PR target/98878 - Incorrect multilib list for riscv*-rtems
adds b6e7a749873 aarch64: Reimplement vget_low* intrinsics
adds d9bb52150db aarch64: Reimplement vget_high* intrinsics
adds b229baa75ce c++: Fix ICE with structured binding initialized to incompl [...]
adds 37876976b05 i386: Fix up TARGET_QIMODE_MATH for many AMD CPU tunings [PR98957]
adds 4ede02a5f2a debug: fix switch lowering debug info
adds 63538886d1f tree-optimization/98855 - redo BB vectorization costing
adds 6606b852bfa driver: error for nonexistent linker inputs [PR 98943]
adds 1cbc10d8944 c++: Fix ICE with invalid using enum [PR96462]
adds 7a18bc4ae62 c++: Fix bogus -Wvolatile warning in C++20 [PR98947]
adds 28c7a463e3c d: Remove the expansion of intrinsic and built-in codes fro [...]
adds a1265ee4780 Regenerate .pot files.
adds 1ed59127648 Daily bump.
adds 3d912941f29 Daily bump.
adds ba655760277 Daily bump.
adds fe2034e9c03 Correct typos in attribute malloc documentation.
adds 0d701e3eb89 opts: fix handling of -fpatchable-function-entries option
adds d4536e43131 lto/96591 - walk VECTOR_CST elements in walk_tree
adds 40c92180df9 middle-end/98974 - fixup after STMT_VINFO_VEC_STMTS rework
adds ec0a9b4e039 c++: Fix typo in CLASSTYPE_TI_TEMPLATE comment.
adds 432b9f610df mklog: automatically fill in generated entries
adds 57b17858a1b c++: cross-module __cxa_atexit use [PR 98531]
adds efcd941e86b c++: cleanup function name [PR 98531]
adds 2da7ce23cfd Daily bump.
adds a8dd2b3e965 c++: constexpr, union, and no_unique_address [PR98994]
adds bdbca69e072 c++: generic lambda, fn* conv, empty class [PR98326]
adds 57d705da0b9 c++: consteval and explicit instantiation [PR96905]
adds 283653f4559 tree-optimization/99017 - be more forgiving in BB vect costing
adds e5304598f14 calls: Fix a memory leak in maybe_warn_rdwr_sizes [PR99004]
adds e14ea108faa string: Add a workaround for -Wstringop-overread false posi [...]
adds 396cc31317e Fix O(region-size) unwind in VN
adds adeaa43ad3b libstdc++: Fix build failure for targets without unistd.h
adds 26a3f288f18 libstdc++: Make coroutine_handle<_Promise>::from_address() [...]
adds 92941cea2f0 c++: Fix indirect partitions [PR 98944]
adds bfdb7b8c6f5 libstdc++: Clear up directories created by tests
adds 73e52926b6c testsuite: aarch64: Add tests for vpaddq intrinsics
adds a11ef53238c aarch64: fix vector multiplication costs
adds 20f28986a8d Fix miscompilation of Python on HP-PA/Linux
adds 1d9f3b7ad4f analyzer: treat pointers written to *UNKNOWN as escaping [PR98575]
adds 790a8e8942b analyzer: support "_IO_"-prefixed variants of FILE * fns [PR98575]
adds f6be5d6ee31 libstdc++: Remove execution branch in deque iterator operator-
adds d2b1a6842c3 libstdc++: Add unordered containers heterogeneous lookup
adds 0a91b73e5b0 Daily bump.
adds b0fb2720d88 Revert "openacc: Allow strided arrays in update directives"
adds f7fb2f662fe openacc: Add XFAILs [PR98979]
adds e1782d8ad10 dwarf2out: Don't prune static data members initialized with [...]
adds d44f56f2b2d ICF: fix memory leak
adds 5da5d8a02c6 if-to-switch: fix a memory leak
adds d997565c41a tree-optimization/99024 - fix leak in loop vect analysis
adds 9eb7669cc04 ipa/99029 - fix memory leak in propagate_malloc
adds bd0e37f68a3 openmp: Temporarily disable into_ssa when gimplifying OpenM [...]
adds 72932511053 rtl-optimization/99054 - fix leak in fixup_partitions
adds 57d1b68d658 if-to-switch: fix memory leak in case merging
adds f8fac476b5c c++: generic lambdas and local-externs from outer scopes [P [...]
adds e4985357e5a fix memory leak in optimize pragma parsing
adds 6a6f74be9d6 libstdc++: Fix spelling of __MINGW32__ macros
adds 313e2dc377d libstdc++: Use correct error category for Windows error codes
adds 3df5b249b3c libstdc++: Re-enable workaround for _wstat64 bug [PR 88881]
adds 5874d156669 nvptx: properly use flag_patchable_function_entry
adds a8db7887dfb c++: Consider addresses of heap artificial vars always non- [...]
adds 20482cfcc1d i386: Fix ICEs due to simplify_gen_subreg returning NULL [PR99025]
adds 0f39fb7b001 varasm: Fix ICE with -fsyntax-only [PR99035]
adds 1f5c80883ef libcpp: fix ICE comparing macro locations without column in [...]
adds 21c6ad7a12f Add test for PR tree-optimization/92879.
adds 4b37c3ea8ab Daily bump.
adds 27a804bc628 c, c++: Plug -Wduplicated-cond memory leaks [PR99057]
adds 19c02324102 libgfortran: Fix unwanted end-of-record by checking if seen [...]
adds a5c4f5562a0 use -mfpu=auto for arm/simd/vmmla_1.c
adds 2e9dfa4bff2 Fortran: intrinsic.texi add missing arg to FINDLOC
adds 5ee5415af86 Fortran: Fix ICE after error regression [PR99060].
adds 22a6d99d0a0 reduce sparseset memory requirement
adds ff6903288d9 Fortran: Fix calls to associate name typebound subroutines [...]
adds 4af29981ab5 [aarch64][vect] Support V8QI->V8HI WIDEN_ patterns
adds 38c5703449c arm: Low overhead loop handle long range branches [PR98931]
adds cb168f779c8 c++: Fix ICE from op_unqualified_lookup [PR97582]
adds f0da1c0cb76 c++: ICE with unexpanded pack in do-while [PR99063]
adds 2dcdd15d0ba c++: Fix zero initialization of flexible array members [PR99033]
adds ce43c906049 libstdc++: Document when C++11/14/17 support became stable [...]
adds bc0f7db7ebb libstdc++: Fix versioned namespace build
adds 2432c479700 rs6000: Fix invalid address used in MMA built-in function
adds 88cfd531c69 c++: Endless loop with targ deduction in member tmpl [PR95888]
adds c36ad24e8a4 libgomp/i386: Move syscall asms to static inline wrapper.
adds 5e40542f878 libgomp/i386: Revert the type of syscall wrappers output ba [...]
adds 85cefe22564 Fix -freorder-blocks-and-partition glitch with Windows SEH
adds 0c5cdb31bd4 Daily bump.
adds 467a4820527 analyzer: fix ICE in print_mem_ref [PR98969]
adds 3e2f329e948 libbacktrace: check for objcopy --add-gnu-debuglink using --help
adds ac001ddd0cb c++: variadic lambda template and empty pack [PR97246]
adds 95d94b52ea8 tree-optimization/38474 - fix store-merging compile-time re [...]
adds cf059e1c099 c++: Fix endless errors on invalid requirement seq [PR97742]
adds bc6087c5754 Fix producer string memory leaks
adds 6cc886bf427 middle-end/38474 - fix alias walk budget accounting in IPA [...]
adds f699e0b1657 Fortran: Fix rank of assumed-rank array [PR99043]
adds 3fbf81a252d [Ada] Remove unused subprograms (continued)
adds 71b8ed7c61b testsuite, arm: Add -mthumb to pr98931.c [PR target/98931]
adds 4591f7e5329 libstdc++: Fix bootstrap with -fno-rtti [PR 99077]
adds 14b554c462d libstdc++: Fix errors when syncbuf is used without RTTI
adds e9c31052118 libstdc++: Only use dynamic_cast in tests when RTTI is enabled
adds 0bd242ec5ae libstdc++: Make test memory_resource work without exception [...]
adds c4ece1d96a1 libstdc++: XFAIL tests that depends on RTTI
adds 87eaa3c525e libstdc++: Add unused attributes to shared_ptr functions
adds 970ba719250 libstdc++: Fix errors in <experimental/internet>
adds d1a821b93c4 libstdc++: Include scope ID in net::internet::address_v6::t [...]
adds 4179ec10794 libstdc++: Make "nonexistent" paths less predictable in fil [...]
adds 1dfd95f0a0c libstdc++: Fix filesystem::rename on Windows [PR 98985]
adds b7210405ed8 libstdc++: Re-enable workaround for _wstat64 bug, again [PR 88881]
adds f60226fd723 df: Record all definitions in DF_LR_BB_INFO->def [PR98863]
adds adfee3c4c03 rtl-ssa: Use right obstack for temporary allocation
adds 0631e008adc libgfortran: Fix PR95647 by changing the interfaces of oper [...]
adds f3d7fd1475e PR c/99055 - memory leak in warn_parm_array_mismatch
adds 9769564e745 compiler: open byte slice and string embeds using the absol [...]
adds 8f93e1b8928 Expunge namespace-scope IDENTIFIER_TYPE_VALUE & global_type [...]
adds 0c27fe96f81 c++: Register streamed-in decls when new [PR 99040]
adds 8c4137c7ead c++: Seed imported bindings [PR 99039]
adds eb64b0b285b testsuite: Restrict gcc.dg/rtl/aarch64/multi-subreg-1.c tes [...]
adds fab095dad5e Daily bump.
adds 0f3a743b688 i386: Add combiner splitter to optimize V2SImode memory rot [...]
adds a3b38b77816 d: Merge upstream dmd 7132b3537
adds 05402ca65a6 passes: Enable split4 with selective scheduling 2 [PR98439]
adds a4953810bac RISC-V: Shorten memrefs improvement, partial fix 97417.
adds 18fabc35f47 RISC-V: Avoid zero/sign extend for volatile loads. Fix for 97417.
adds c8656df6667 Daily bump.
adds 4e3590d06cf libstdc++: Restore <unistd.h> in testsuite_fs.h header [PR 99096]
adds 9966699d7a9 Fix memory leak in ipa-refernece
adds c5ae38e8dc3 Daily bump.
adds 70099a6acf5 match.pd: Fix up A % (cast) (pow2cst << B) simplification [ [...]
adds 8ec4f693fb5 Fix cast in df_worklist_dataflow_doublequeue
adds 26cedbce4b4 Add 2 missing Param keywords.
adds 40f235b5f00 Fix 2 more leaks related to gen_command_line_string.
adds abe07a74bb7 rtl-ssa: Reduce the amount of temporary memory needed [PR98863]
adds d27153f038c libstdc++: Add missing return and use reserved name
adds cc9a0a3d79d libstdc++: Fix __thread_yield for non-gthreads targets
adds a33927c9ab4 rtl-optimization: Fix uninitialized use of opaque mode vari [...]
adds f9d4544df55 aarch64: Run SUBTARGET_INIT_BUILTINS if it exists
adds de594739f7e Daily bump.
adds 0b5c58c2dc3 gcc.misc-tests/outputs.exp (outest): Fix typo "is_target".
adds 1531f39268c openmp: Fix up vectorization simd call badness computation [...]
adds 3f16a167815 tree-optimization/38474 - improve PTA varinfo sorting
adds ebf9b6c13f0 Fortran: Reject DT as fmt in I/O statments [PR99111]
adds 72d78655a91 [PR98096] inline-asm: Take inout operands into account for [...]
adds 799478b8914 Fortran: %re/%im fixes for OpenMP/OpenACC + gfc_is_simplify [...]
adds 5d5e4f6ec64 [PATCH 3/3] MIPS: fix compact-branches test FAIL for PIC de [...]
adds 30a4d95bf76 c-family: ICE with assume_aligned attribute [PR99062]
adds b37695c9bf1 c++: directives-only preprocessing and include translation [...]
adds e7a8d69a557 compiler: unalias receiver type in export data
adds 0e804ce39a2 Daily bump.
adds 78a6d0e30d7 c++: Revert EXPR_LOCATION change to build_aggr_init_expr [PR96997]
adds 06505e701dc mips: Avoid out-of-bounds access in mips_symbol_insns [PR98491]
adds d46c7e2c546 c++: ICE with header-units [PR 99071]
adds 24bf79f1798 c++: More set_identifier_type_value fixing [PR 99116]
adds 7768cadb424 c++: Fix up build_zero_init_1 once more [PR99106]
adds d28f3da11d8 openacc: Fix lowering for derived-type mappings through arr [...]
adds 366cf1127a5 openacc: Strided array sections and components of derived-t [...]
adds e0139b2a912 analyzer: fix false leak involving params [PR98969]
adds d8889c99aab c++: Macros need to be GTY-reachable [PR 99023]
adds 963aecff247 testsuite: add regression test for PR analyzer/94596
adds acc0ee5c073 Daily bump.
adds decd8fb0128 i386: Fix up df uses in i386 splitters [PR99104]
adds f72e3d8c9ff array-bounds: Fix up ICE on overaligned variables [PR99109]
adds a1541628df8 i386: Avoid C++ global constructors in every object that in [...]
adds a2ef38b1f94 match.pd: Restrict clz cmp 0 replacement by single_use, PR99142
adds 7ee164dcfe3 middle-end/99122 - Issues with VLA parameter inlining
adds 3bfa96895b3 c++: Fix -std=c++20 ICE on virtual method call [PR99132]
adds a796f8a43a4 c++: Remove large abi-specific tests [PR 99150]
adds 1021222ee4d c++: Remove obsolete dg-module-headers [PR 99023]
adds d82f829905c c: Fix ICE with -fexcess-precision=standard [PR99136]
adds 1f9db6929d9 c++: header-unit build capability [PR 99023]
adds 6347f4a0904 Add retain attribute to place symbols in SHF_GNU_RETAIN section
adds d1efec57e27 [PR96264] LRA: Check output insn hard regs when updating av [...]
adds bf81237eccb Daily bump.
adds 187d0d5871b c++: Tuple of self-dependent classes [PR96926]
adds b258e263e0d jit: fix ICE on BUILT_IN_TRAP [PR99126]
adds d909ead6821 c++: Tweak PR969626 patch
adds 0b2b7ef3676 [PATCH v2] libiberty(argv.c): Fix memory leak in expandargv
adds 6070e39cd0a aarch64: Check predicate when using gen_vec_duplicate [PR98657]
adds f600f271b10 Fortran: Fix ubound simplifcation [PR99027]
adds 9d449189ee4 libstdc++: Fix __thread_relax for non-gthreads non-x86 targets
adds 37bde2f8726 tree-cfg: Fix up gimple_merge_blocks FORCED_LABEL handling [...]
adds 1a132c4d7cd arm: Fix ICE with -fstack-protector -mpure-code [PR98998]
adds 1a2a7096e5e middle-end/99122 - more VLA inlining fixes
adds c8d13835638 Fix typo in param description.
adds 72d91d6cd41 Fortran: Fix DTIO with type ICE [PR99146]
adds f86e187e12d Fortran: Fix coarray handling for gfc_dep_resolver [PR99010]
adds bfe83ae38e8 c++: Inform of CMI reads [PR 99166]
adds 3599ecb6a01 PR c/97172 - ICE: tree code 'ssa_name' is not supported in [...]
adds 7d524a5de33 Update .po files.
adds af027826292 PR fortran/99147 - Sanitizer detects heap-use-after-free in [...]
adds 13e6fadd96d libgo: update to Go1.16 release
adds d1e7e83aaf1 Update gcc fr.po.
adds dfa2f821c18 fortran: Object types should be declared before use in NAMELIST.
adds 14886cbe300 c++: Incorrect module-number ordering [PR 98741]
adds 50352c6cd2d Daily bump.
adds a974b8a592e IBM Z: Improve FPRX2 <-> TF conversions
adds b6e446cb581 IBM Z: Fix long double <-> DFP conversions
adds 93e8054406e testsuite: skip attr-retain-?.c on AIX
adds 470beb9219a libiberty: autogenerate aclocal.m4
adds b2a55cafa84 Daily bump.
adds 3cc5f8620d3 Revert: "i386: Remove REG_ALLOC_ORDER definition"
adds 2df374b337a PR fortran/99169 - Do not clobber allocatable intent(out) d [...]
adds 60b99ee3bc0 Daily bump.
adds 8a8eee6bdb9 tree-optimization/99165 - fix ICE in store-merging w/ non-call EH
adds 44841e1788c dump SLP subgraph before costing
adds 451002e6266 Fix ICE in tree_inlinable_function_p.
adds e9b34037cdd Fortran/OpenMP: Fix optional dummy procedures [PR99171]
adds 4c31a3a6d31 ira: Make sure allocno copies are ordered [PR98791]
adds c49fcfddaa4 c++: cross-header-unit template definitions [PR 99153]
adds d789cf134b7 Add mi_thunk support for vcalls on hppa.
adds afed55036b6 c++: Recursing header imports and other duplicates [PR 99174]
adds 6cb68940dcf cris: Fix addi insn mult vs. shift canonicalization
adds dd7376371f9 testsuite/gcc.target/cris/biap-mul.c: New test.
adds a7de0ffa34a testsuite/gcc.target/cris/biap.c: Add a Y+=X*2 to the Y+=X*4.
adds 8e99b5ba4c1 g++.dg/warn/Warray-bounds-10..13: Fix for 32-bit newlib targets
adds 781183595ac Add conversions between _Float128 and Decimal.
adds 692ba083d9a Fix a comment line that was too long.
adds a65b9ad863c aarch64: Add internal tune flag to minimise VL-based scalar ops
adds 609204abb88 Require SHF_GNU_RETAIN support for retain tests
adds 5ee4ba031dd analyzer: handle error/error_at_line [PR99196]
adds 2f5765cf251 Daily bump.
adds 222abf8be5a g++.dg/warn/Wplacement-new-size-1.C, -2, -6: Fix for defaul [...]
adds 635cf58ca34 Update gcc sv.po.
adds 198c56052ea libstdc++: Fix endianness issue with IBM long double [PR98384]
adds f4a3cea3fb0 rs6000: Use rldimi for vec init instead of shift + ior
adds 7e647d71d55 libstdc++: Fix up parallel_backend_serial.h [PR97549]
adds efa64fcce12 libstdc++: Fix up constexpr std::char_traits<char>::compare [...]
adds 37b64a3547b fold-const: Fix ICE in fold_read_from_constant_string on in [...]
adds 74af13c1747 config.sub, config.guess : Import upstream 2021-01-25.
adds e03e58c1844 Fix UBSAN in __ubsan::Value::getSIntValue
adds cac960a3ec4 c++: Micro-optimize instantiation_dependent_expression_p
adds 5bd7afb71fc c++: Fix folding of non-dependent BASELINKs [PR95468]
adds 3f838454578 IPA ICF + ASAN: do not merge vars with different alignment
adds 47145e6916f c++: typedef for linkage [PR 99208]
adds a6c7e0fcffc PR fortran/99206 - ICE in add_init_expr_to_sym, at fortran/ [...]
adds 29a5298955f Fortran: Fix for class defined operators [PR99124].
adds 6d134ca4b96 PR c++/99074 - crash in dynamic_cast<>() on null pointer
adds 77ef995c1fb rs6000: Add support for compatibility built-ins
adds 71e24b06014 Daily bump.
adds 084963dcaca c/99224 - avoid ICEing on invalid __builtin_next_arg
adds 66e070b00ff Revert: "Don't build insn-extract.o with rtl checking"
adds 5296bd57d06 slp: fix sharing of SLP only patterns.
adds 6e646abbe02 fold-const: Fix up ((1 << x) & y) != 0 folding for vectors [...]
adds f13d9e48eec coroutines : Adjust error handling for type-dependent corou [...]
adds 96c5a8589e0 [comitted] Testsuite: Disable PR99149 test on big-endian
adds 6c35e79b47a slp: fix accidental resource re-use of slp_tree (PR99220)
adds ea5a82df9ba PR middle-end/97172 - ICE: tree code 'ssa_name' is not supp [...]
adds be30dd89926 arm: Fix CMSE support detection in libgcc (PR target/99157)
adds 5159b88ef1a Fortran: Fix memory problems with assumed rank formal args [...]
adds fac929a22d7 Rename next_insn_prefixed_p for improved clarity.
adds d0453cf5c68 libstdc++: Fix failing tests due to 'u' identifier in kerne [...]
adds f90027d18a9 libstdc++: Define std::to_chars overloads for __ieee128 [PR 98389]
adds a13be187cb2 c++: modules & -fpreprocessed [PR 99072]
adds 70aa0e6eef9 libstdc++: Robustify long double std::to_chars testcase [PR98384]
adds 9e0d8a375ba cris: support -fstack-usage
adds 3dfd5493cf9 libstdc++: More efficient date from days
adds 97d6161f6a7 libstdc++: More efficient days from date
adds 126793971be libstdc++: More efficient is_leap
adds 8265ab07f3b libstdc++: More efficient last day of month
adds b6680c20845 [PR99123] inline-asm: Don't use decompose_mem_address to fi [...]
adds 35da095d7e0 libgcc: Avoid signed negation overflow in __powi?f2 [PR99236]
adds 9d2a69106be openmp: Diagnose invalid teams nested in target construct [ [...]
adds 9a4eb720b34 testsuite, coroutines : Make final_suspend calls noexcept.
adds f207eed69e2 c++: Macro location fixes [PR 98718]
adds cb0184b6a28 libstdc++: Fix __floating_to_chars_precision for __float128
adds 94bfe81afed libstdc++: Fix order of arguments to sprintf [PR 99261]
adds 4028d01a050 Daily bump.
adds a6baafcac53 analyzer: fix false positive on realloc [PR99193]
adds 5e7c0927cbd Make the PR99220 fix more robust
adds 3cf52b87ff6 vrp: Handle VCE in vrp_simplify_cond_using_ranges [PR80635]
adds 880682e7b23 match.pd: Use :s for (T)(A) + CST -> (T)(A + CST) [PR95798]
adds 1193d05465a tree-optimization/99253 - fix reduction path check
adds a21b99e8ceb Bump gcc/BASE-VER to 11.0.1 now that we are in stage4.
adds 7244879b883 libstdc++: Add std::to_underlying for C++23
adds 75c74a83ace libstdc++: Fix narrowing conversion in year_month_day [PR 99265]
adds 2bf9e68a958 c++: Fix typo in module-mapper [PR 98318]
adds e54e7286cc3 libstdc++: Update baseline symbols for {aarch64,ia64,m68k,r [...]
adds 31002af9040 libstdc++: Do not assume std::FILE is complete [PR 99270]
adds ed255fd5eda libstdc++: Document library versioning for GCC 11
adds 01c2ce169a0 PR middle-end/97172 - ICE: tree code 'ssa_name' is not supp [...]
adds 557a0d3b1b3 [PR99233] tesstsuite: Run test pr96264.c only for little endian
adds 28af4b9a7c5 slp: Don't traverse tree on (nil) nodes.
adds 232f7461167 pr95690.f90: move error line for CRIS.
adds a47cec4ca73 libstdc++: Use uint32_t for all year_month_day::_S_from_day [...]
adds 9f08c08531b c++tools: Make NETWORKING define check consistent [PR 98318]
adds 9592deabf3c c++: Rename new -flang-note-module-read option [PR 99166]
adds 44ab1cc1df6 arm: force use of r4 for __gnu_cmse_nonsecure_call when !FP [...]
adds 5051c121737 aarch64 : Mark rotate immediates with '#' as per DDI0487iFc.
adds 7005a50d012 coroutines : Remove throwing_cleanup marks from the ramp [P [...]
adds b8ff3f8efed coroutines : Call promise CTOR with parm copies [PR97587].
adds 2ffc26458dd c++: const_cast of null pointer in constant expr [PR99176]
adds 676f6f32771 c++: Fix CTAD of single-element initializer list [PR99103]
adds 7fb9a1e929d c++: Fix pretty printing the context of local class [PR99213]
adds d656bfda2d8 openmp: Fix intermittent hanging of task-detach-6 libgomp t [...]
adds daa6884432b Daily bump.
adds 6bd409cfc83 c++: abbreviated function template return type rewriting [PR98990]
adds a505fad4dd4 analyzer: eliminate dedupe_candidate [PR96374]
adds 2fbed0dc6c4 libgo: ensure memmove, memset 8 byte atomicity on ppc64x
adds 97989a2220c builtins: Fix typos in warn_for_access [PR99278]
adds 9967bbfcedd [PATCH v4 1/2] MIPS: unaligned load: use SImode for SUBREG [...]
adds b8d85f569a6 Optimize pcrel access of globals
adds 0159535adb0 rs6000: Fix ICE in rs6000_init_builtins when compiling with [...]
adds 7c657339d6a c++: Fix class NTTP constness handling [PR98810]
adds ff7a5154460 c/99275 - fix missing space in diagnostic
adds 27f9a87886d c++: Fix operator() lookup in lambdas [PR95451]
adds 0f161cc8494 c++: Implement P1102R2 - Down with ()!
adds c173346aac4 middle-end/99281 - avoid bitfield stores into addressable types
adds 1c922c1e56a Add missing dg-require-effective-target fpic directives to [...]
adds 9d5b4b60bdf revert just-added duplicate fpic target requirement
adds 95a82679f6a Update gcc de.po.
adds ded7355b3d9 analyzer: implement exploded_path copy ctor
adds 06a9f20f97e Daily bump.
adds 652623f7c68 gcse, ipa-devirt: Use %wd/%wu instead of HOST_WIDE_INT_PRIN [...]
adds 699672d4dcc libstdc++: Fix conversions from date types to integers [PR 99301]
adds e3eda9a0e12 libgomp, testsuite : Require alias support for PR96390 testcase.
adds a938e4616d6 Darwin : Update a disgnostic message [NFC].
adds 5d9d6c1cd8d c++: Allow GNU attributes before lambda -> [PR90333]
adds ec9dc4fa080 Daily bump.
adds d3805e6d575 typos: Fix various typos - mainly misspelled reference* [PR99304]
adds 3a77ca7d364 fortran: Replace double space in diagnostic with a single o [...]
adds 48ca2185bfb fortran: Fix up wording of 3 OpenMP diagnostic messages [PR99303]
adds 7e5d7fc7e6f c++: Fix attr-lambda3.C
adds 3c173f7890c testsuite, coroutines : Mark final awaiters and co_await op [...]
adds 6838d1b33dd Update gcc de.po, sv.po.
adds 2c83c3fbd2b Daily bump.
adds 074226d5aa8 Fix wrong result for 1.0/3.0 at -O2 -fno-omit-frame-pointer [...]
adds 150bde36c11 Fix ICE in compute_fn_summary
adds 2e0bb9eec2d c++: Completeness of typedef structs [PR 99294]
adds 4ed0a92f6cf s390: add exceptions for param modified by target pragma
adds 491d5b3cf82 dwarf2unwind : Force the CFA after remember/restore pairs [ [...]
adds 3104dbdcf4a Do not call Set_Cloned_Subtype on private type
adds 8893888621f Daily bump.
adds 76c99cb1133 Fix __sprintfkf prototype in libgcc.
adds 34d39d14091 IBM Z: Run mul-signed-overflow tests only on z14
adds ff92ede8d26 vrp: Improve register_edge_assert_for [PR95757]
adds 796a35b2bd6 IBM Z: arch14: Add command line options
adds 2bd58910b04 IBM Z: arch14: New instrinsics
adds d6378b9785b c++: Avoid building garbage trees from tsubst_requires_expr
adds 04b10596fe2 c++: Some preparatory type canonicalization fixes
adds 276cb81bec6 c++: Delay normalizing nested requirements until satisfaction
adds e52f8ec25c0 c++: Fix satisfaction of placeholder type constraints [PR96443]
adds f8e4d7a6597 analyzer: remove dead code
adds 168b75ff54b Fix PR ada/99095
adds 5a233ae4d8c dwarf2out: Fix up split-dwarf .debug_macro handling [PR99319]
adds 66ecb059c9d PR c++/99251 - inconsistent -Wnonnull warning behaviour wit [...]
adds 397ed1dbffe PR middle-end/99295 - documentation on __attribute__((mallo [...]
adds e7ca37649e4 PR middle-end/99276 - grammar in diagnostics for overflowin [...]
adds 41fbacdd103 diagnostics: fix ICE on fix-it hints on very long lines [PR99323]
adds df003d1e0bf libbacktrace: pass -1 to error callback for unrecognized DWARF
adds d1776b77570 compiler: allow //go:embed in files underscore-importing embed
adds 8b6ebc025cf [PATCH] Fix Ada bootstrap failure on Cygwin since switch to [...]
adds 7fddf3dbb98 outputs.exp: skip @file -save-temps if target has -L or -I
adds 1c4b7b367cf aix: Fix TLS thread pointer function names.
adds d97a92dca90 Daily bump.
adds 9b2084db9f9 libbacktrace: don't special case file 0
adds f8e7f3f3f33 cgraph: flatten and same_body aliases [PR96078]
adds 006693a59f7 libgfortran: Fix negation for largest integer [PR81986]
adds 4ad5b1915d5 cfgrtl: Fix up fixup_partitions caused ICE [PR99085]
adds b5040344b9c dwarf2out: Fix -gsplit-dwarf on riscv or other non-.uleb128 [...]
adds ba09d11a9d0 c-family: Avoid ICE on va_arg [PR99324]
adds f1b13064609 i386: Fix a peephole2 for -mavx512vl -mno-avx512bw [PR99321]
adds 357c4350680 Fix ICE with pathologically large frames
adds a7267237371 libstdc++: Don't use reserved identifiers in simd headers
adds 8c4f0c0ceb3 c++: namespace reachability [PR 99344]
adds 8cfa06570dd testsuite: i386: Fix gcc.target/i386/pr95798-?.c on Solaris
adds 00d79dc4be0 gcov: use mmap pools for KVP.
adds 5bc3a2bc8a8 libstdc++: Update Solaris baselines for GCC 11.1
adds 74aee6d2087 c++: C++17 and decltype of multi-operator expression [PR95675]
adds 15cf7fe3556 arm: Ignore --with-mode when CPU only supports one instruct [...]
adds 1dabbfb0f4a c++: ICE with deduction guide in checking type-dep [PR99009 [...]
adds fa6092d2cdc sparcv9: Disable -Wuninitialized warnings breaking bootstra [...]
adds 0b8fa12015f c++: Fix -fstrong-eval-order for operator &&, || and , [PR82959]
adds 949eab55b6f testsuite: aarch64: Add tests for narrowing-arithmetic intrinsics
adds fd85814c4be testsuite: aarch64: Add tests for v[r]shrn_high intrinsics
adds 3a0fbf7604e testsuite: aarch64: Add tests for v[q]mov[u]n_high intrinsics
adds 39d7eb8a73d testsuite: aarch64: Add tests for vcvt FP intrinsics
adds 662ef5b54de c++: Clean up normalization and satisfaction routines
adds 5a559ace9b8 c++: Unify REQUIRES_EXPR evaluation / diagnostic routines
adds d6177870dd2 d: Fix heap-buffer-overflow in checkModFileAlias [PR 99337]
No new revisions were added by this update.
Summary of changes:
ChangeLog | 19 +
MAINTAINERS | 3 +-
Makefile.in | 2 +-
c++tools/ChangeLog | 5 +
c++tools/server.cc | 14 +-
config.guess | 48 +-
config.sub | 23 +-
contrib/ChangeLog | 19 +
contrib/compare-lto | 21 +-
contrib/gcc_update | 1 +
contrib/mklog.py | 5 +
gcc/BASE-VER | 2 +-
gcc/ChangeLog | 2964 ++
gcc/DATESTAMP | 2 +-
gcc/Makefile.in | 7 +
gcc/ada/ChangeLog | 73 +
gcc/ada/Makefile.rtl | 12 +
gcc/ada/cstreams.c | 5 +
gcc/ada/gcc-interface/decl.c | 97 +-
gcc/ada/gcc-interface/trans.c | 35 +-
gcc/ada/gcc-interface/utils.c | 62 +-
gcc/ada/repinfo.adb | 49 +
gcc/ada/repinfo.ads | 58 +-
gcc/ada/sem_ch3.adb | 2 +-
gcc/ada/sem_ch8.adb | 10 +-
gcc/alias.c | 47 +-
gcc/analyzer/ChangeLog | 340 +
gcc/analyzer/analyzer.h | 3 +-
gcc/analyzer/checker-path.cc | 26 +
gcc/analyzer/checker-path.h | 55 +
gcc/analyzer/constraint-manager.cc | 2 +-
gcc/analyzer/diagnostic-manager.cc | 517 +-
gcc/analyzer/diagnostic-manager.h | 45 +-
gcc/analyzer/engine.cc | 210 +-
gcc/analyzer/exploded-graph.h | 6 +-
gcc/analyzer/pending-diagnostic.h | 2 +-
gcc/analyzer/program-state.cc | 4 +-
gcc/analyzer/region-model-impl-calls.cc | 58 +
gcc/analyzer/region-model-manager.cc | 13 +
gcc/analyzer/region-model-reachability.cc | 2 +
gcc/analyzer/region-model.cc | 151 +-
gcc/analyzer/region-model.h | 16 +-
gcc/analyzer/sm-file.cc | 11 +-
gcc/analyzer/sm-malloc.cc | 833 +-
gcc/analyzer/store.cc | 38 +-
gcc/analyzer/store.h | 4 +-
gcc/analyzer/supergraph.cc | 29 +-
gcc/analyzer/svalue.cc | 52 +-
gcc/analyzer/svalue.h | 20 +-
gcc/attribs.c | 38 +-
gcc/attribs.h | 5 +
gcc/bitmap.h | 6 +-
gcc/builtin-types.def | 8 +-
gcc/builtins.c | 49 +-
gcc/c-family/ChangeLog | 91 +
gcc/c-family/c-attribs.c | 40 +-
gcc/c-family/c-common.c | 9 +-
gcc/c-family/c-common.h | 4 +-
gcc/c-family/c-cppbuiltin.c | 5 +
gcc/c-family/c-lex.c | 8 +
gcc/c-family/c-opts.c | 29 +-
gcc/c-family/c-pragma.h | 3 +-
gcc/c-family/c-pretty-print.c | 286 +-
gcc/c-family/c-warn.c | 20 +-
gcc/c-family/c.opt | 34 +-
gcc/c/ChangeLog | 45 +
gcc/c/c-decl.c | 66 +-
gcc/c/c-parser.c | 75 +-
gcc/c/c-typeck.c | 74 +-
gcc/calls.c | 6 +-
gcc/cfgbuild.c | 1 +
gcc/cfgexpand.c | 8 +-
gcc/cfgrtl.c | 67 +-
gcc/cgraph.c | 4 +-
gcc/cgraph.h | 14 +
gcc/cgraphunit.c | 7 +-
gcc/common.opt | 14 +-
gcc/common/config/arm/arm-common.c | 49 +-
gcc/common/config/riscv/riscv-common.c | 4 +-
gcc/common/config/s390/s390-common.c | 4 +
gcc/config.gcc | 12 +-
gcc/config/aarch64/aarch64-builtins.c | 1 +
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gcc/config/aarch64/aarch64-cost-tables.h | 18 +-
gcc/config/aarch64/aarch64-passes.def | 1 +
gcc/config/aarch64/aarch64-protos.h | 1 +
gcc/config/aarch64/aarch64-simd-builtins.def | 484 +-
gcc/config/aarch64/aarch64-simd.md | 1052 +-
gcc/config/aarch64/aarch64-sve.md | 62 +-
gcc/config/aarch64/aarch64-sve2.md | 42 +
gcc/config/aarch64/aarch64-tuning-flags.def | 2 +
gcc/config/aarch64/aarch64.c | 40 +-
gcc/config/aarch64/aarch64.md | 21 +-
gcc/config/aarch64/arm_neon.h | 2136 +-
gcc/config/aarch64/iterators.md | 144 +-
gcc/config/aarch64/t-aarch64 | 6 +
gcc/config/arm/aarch-common-protos.h | 1 +
gcc/config/arm/aarch-cost-tables.h | 18 +-
gcc/config/arm/arm.c | 41 +-
gcc/config/arm/arm.h | 10 +-
gcc/config/arm/arm.md | 10 +
gcc/config/arm/arm_mve.h | 2 +-
gcc/config/arm/arm_neon.h | 31 +
gcc/config/arm/iterators.md | 43 +-
gcc/config/arm/mve.md | 83 +-
gcc/config/arm/neon.md | 72 +-
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gcc/config/arm/unspecs.md | 6 +-
gcc/config/arm/vec-common.md | 115 +
gcc/config/cris/cris.c | 28 +-
gcc/config/cris/cris.md | 33 +-
gcc/config/darwin-protos.h | 1 +
gcc/config/darwin.c | 10 +
gcc/config/darwin.h | 5 +
gcc/config/gcn/gcn-opts.h | 3 +-
gcc/config/gcn/gcn.c | 6 +-
gcc/config/gcn/gcn.opt | 3 +
gcc/config/gcn/mkoffload.c | 264 +-
gcc/config/gcn/t-gcn-hsa | 4 +-
gcc/config/gcn/t-omp-device | 2 +-
gcc/config/host-darwin.c | 3 +-
gcc/config/i386/i386-c.c | 9 +-
gcc/config/i386/i386-expand.c | 57 +-
gcc/config/i386/i386-features.c | 20 +-
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gcc/config/i386/i386.md | 49 +-
gcc/config/i386/mmx.md | 17 +-
gcc/config/i386/predicates.md | 51 +
gcc/config/i386/sse.md | 276 +-
gcc/config/i386/winnt.c | 21 +-
gcc/config/i386/x86-tune.def | 10 +-
gcc/config/mips/mips.c | 4 +-
gcc/config/nios2/nios2.c | 51 +-
gcc/config/nios2/t-rtems | 146 +-
gcc/config/nvptx/nvptx.c | 6 +-
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gcc/config/riscv/arch-canonicalize | 14 +-
gcc/config/riscv/multilib-generator | 12 +-
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gcc/config/riscv/riscv.c | 41 +-
gcc/config/rs6000/aix71.h | 3 +
gcc/config/rs6000/aix72.h | 3 +
gcc/config/rs6000/altivec.h | 4 +
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gcc/config/rs6000/fusion.md | 2661 ++
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gcc/config/rs6000/mma.md | 8 +-
gcc/config/rs6000/mmintrin.h | 3 +-
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gcc/config/rs6000/rs6000-c.c | 46 +-
gcc/config/rs6000/rs6000-call.c | 98 +-
gcc/config/rs6000/rs6000-cpus.def | 10 +-
gcc/config/rs6000/rs6000-passes.def | 8 +
gcc/config/rs6000/rs6000-pcrel-opt.c | 910 +
gcc/config/rs6000/rs6000-protos.h | 6 +
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gcc/config/rs6000/rs6000.md | 38 +-
gcc/config/rs6000/rs6000.opt | 27 +
gcc/config/rs6000/t-rs6000 | 11 +-
gcc/config/rs6000/vsx.md | 233 +-
gcc/config/rtems.h | 8 +-
gcc/config/s390/driver-native.c | 2 +-
gcc/config/s390/s390-builtin-types.def | 3 +
gcc/config/s390/s390-builtins.def | 12 +
gcc/config/s390/s390-c.c | 2 +-
gcc/config/s390/s390-opts.h | 1 +
gcc/config/s390/s390.c | 10 +
gcc/config/s390/s390.h | 20 +-
gcc/config/s390/s390.md | 19 +-
gcc/config/s390/s390.opt | 3 +
gcc/config/s390/vecintrin.h | 6 +
gcc/config/s390/vector.md | 108 +-
gcc/config/s390/vx-builtins.md | 55 +
gcc/config/sparc/rtemself.h | 2 +
gcc/config/sparc/t-sparc | 4 +
gcc/configure | 6 +-
gcc/configure.ac | 8 +-
gcc/cp/ChangeLog | 899 +
gcc/cp/Make-lang.in | 2 +-
gcc/cp/call.c | 369 +-
gcc/cp/class.c | 98 +-
gcc/cp/constexpr.c | 226 +-
gcc/cp/constraint.cc | 914 +-
gcc/cp/coroutines.cc | 47 +-
gcc/cp/cp-gimplify.c | 21 +-
gcc/cp/cp-tree.h | 78 +-
gcc/cp/cvt.c | 11 +-
gcc/cp/decl.c | 142 +-
gcc/cp/decl2.c | 3 -
gcc/cp/error.c | 7 +-
gcc/cp/expr.c | 14 +-
gcc/cp/init.c | 39 +-
gcc/cp/lambda.c | 3 +-
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gcc/cp/mangle.c | 13 +-
gcc/cp/mapper-client.cc | 2 +-
gcc/cp/module.cc | 806 +-
gcc/cp/name-lookup.c | 568 +-
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gcc/cp/pt.c | 496 +-
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gcc/cp/search.c | 63 +-
gcc/cp/semantics.c | 111 +-
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gcc/d/dmd/apply.c | 2 +-
gcc/d/dmd/arrayop.c | 11 +-
gcc/d/dmd/arraytypes.h | 2 +-
gcc/d/dmd/ast_node.h | 2 +-
gcc/d/dmd/attrib.c | 471 +-
gcc/d/dmd/attrib.h | 15 +-
gcc/d/dmd/blockexit.c | 4 +-
gcc/d/dmd/canthrow.c | 16 +-
gcc/d/dmd/clone.c | 42 +-
gcc/d/dmd/compiler.h | 9 +-
gcc/d/dmd/complex_t.h | 2 +-
gcc/d/dmd/cond.c | 19 +-
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gcc/d/dmd/constfold.c | 2 +-
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gcc/d/dmd/ctfeexpr.c | 2 +-
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gcc/d/dmd/dimport.c | 209 +-
gcc/d/dmd/dinterpret.c | 40 +-
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gcc/d/dmd/dscope.c | 10 +-
gcc/d/dmd/dstruct.c | 318 +-
gcc/d/dmd/dsymbol.c | 58 +-
gcc/d/dmd/dsymbol.h | 11 +-
gcc/d/dmd/dsymbolsem.c | 5486 ++++
gcc/d/dmd/dtemplate.c | 1184 +-
gcc/d/dmd/dversion.c | 15 +-
gcc/d/dmd/entity.c | 2 +-
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gcc/d/dmd/expression.h | 15 +-
gcc/d/dmd/expressionsem.c | 470 +-
gcc/d/dmd/func.c | 2958 +-
gcc/d/dmd/globals.h | 2 +-
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.../aarch64/advsimd-intrinsics/vcvt_fXX_fXX.c | 100 +
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.../advsimd-intrinsics/vmlXl_high_laneq.inc | 71 +
.../aarch64/advsimd-intrinsics/vmlXl_high_n.inc | 62 +
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[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk_stm32/gnu_eabi-master-arm_eabi-coremark-O3 updated (58eadc4b69 -> 1bfa81acbf)
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_stm32/gnu_eabi-master-arm_eabi-coremark-O3
in repository toolchain/ci/binutils-gdb.
from 58eadc4b69 Fix building gdb with gcc-4.x
adds c14dee84dd Update my email address (long overdue!)
adds 17e8913732 Add myself to gdb/MAINTAINERS
adds 5aa06b1b14 Automatic date update in version.in
adds 5fda40b28f gas: make [248]byte directives available everywhere
adds 3624a6c15c PR26539, memory leak in inflate.c
adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status
adds 7cf91a2481 sim: m32r: clean up redundant test coverage
adds 89bfc2a429 sim: frv: clean up redundant test coverage
adds 137d6efd8a sim: mips: delete empty stub test dir
adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness
adds bb3eddb5bd sim: testsuite: delete configure script
adds dcd709e056 RISC-V: Comments tidy and improvement.
adds b800637e76 RISC-V: Error and warning messages tidy.
adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...]
adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...]
adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32
adds 5a11fff005 gdb/tui: compare pointer to nullptr, not 0
adds e403a898b5 Automatic date update in version.in
adds 1368b914e9 sim: testsuite: flatten tree
adds eb6e6af8c1 PR26002 undefined symbol VER_NDX_GLOBAL vs. VER_NDX_LOCAL
adds ad92f33d38 Tidy inflateEnd calls
adds 68b007788a ld/x86: Add -z report-relative-reloc
adds 75a933f399 ld/elf/x86: Don't compare IFUNC address in the shared object
adds 514fca98df Automatic date update in version.in
adds edf0f284b1 PR binutils/23460: Increase the max number of open files to 20
adds d46153313b Automatic date update in version.in
adds 25294ff049 gold: Remove the circular IFUNC dependency in ifuncmain6pie
adds 994b251328 ld/elf: Ignore section symbols when matching linkonce with comdat
adds 44365e88c0 PR27198, segv in S_IS_WEAK
adds cecb191290 gdb: const-ify unpack_* functions in remote.c
adds e3b2741b16 gdb: const-ify remote_target::add_current_inferior_and_threa [...]
adds b5c8f22d28 gdb: move remote_target::start_remote variable to narrower scope
adds aa2838ccc5 gdb: const-ify hostio methods parameter in remote.c
adds d3d7d1ba3b [gdb/tdep] Handle si_addr_bnd in compat_siginfo_from_siginfo
adds 326adec374 PR26378, sections initialised only by linker scripts are alw [...]
adds 6a9ad81c44 gdb/riscv: use a single regset supply function for riscv fbs [...]
adds 705989f19a as: Automatically enable DWARF5 support
adds 02baa13385 gdb/testsuite: remove actual addresses from some test names
adds 4cfcd3b333 sim: common: modernize gennltvals.sh
adds 5e25901fcc sim: common: delete configure & Makefile
adds f89f33e57c sim: common: simplify version script
adds f0c1efa53d Automatic date update in version.in
adds 85e963f185 ld: Just xfail riscv little endian targets for compressed1d.d test.
adds 0e7620dcdc sim: bfin: delete accidental ADI copyright
adds a75a6a4164 [GOLD] powerpc assertion failure
adds 30845f113a PowerPC use_local_plt
adds 0c4e2c6c88 [gdb/testsuite] Fix gdb.arch/i386-mpx.exp with -m32
adds 1485212328 [gdb/testsuite] Fix gdb.base/step-over-syscall.exp with -m32
adds c98de297b3 libctf, ld: fix data symbol test with newer GCC
adds e05a3e5a49 libctf: lookup_by_name: do not return success for nonexisten [...]
adds 26503e2f5e libctf, create: fix ctf_type_add of structs with unnamed members
adds ccbe4c82d5 Use gdb::array_view for setting value bytes in trad-frame
adds c65ca138c4 sim: ppc: update version script usage
adds bdec2917b1 Convert some frame functions to use gdb::array_view.
adds a9a87d3525 trad-frame cleanups
adds 1c3b85ad28 use DISABLE_COPY_AND_ASSIGN in switch_thru_all_uis
adds 11321a0505 Automatic date update in version.in
adds 8bd10d6b16 PowerPC64 synthetic symbols
adds 4bd7c90276 PowerPC: Don't generate unused section symbols
adds 037e8112b9 [gdb/server] Don't overwrite fs/gs_base with -m32
adds 6f52fdf404 Fix a few stap parser issues and add a new test for probe ex [...]
adds 1402665c8f [gdb/testsuite] Skip gdb.rust/*.exp for target board unix/-m32
adds 7c794afd54 [gdb/testsuite] Fix gdb.python/py-format-string.exp with -m32
adds 6571ffc620 gdb/testsuite: add links for handled control sequences in li [...]
adds c3e96aa78f gdb/testsuite: rename _cur_x/_cur_y to _cur_col/_cur_row in [...]
adds 3f0781f389 Automatic date update in version.in
adds a6c11cbb14 gdb/remote.c: address conflicting enum and method name
adds 6bd434d6ca gdb: make some variables static
adds 17e593e966 gdb/dwarf: add some logging in dwarf2/read.c
adds de53369b2e gdb/dwarf: add assertion in maybe_queue_comp_unit
adds f9e9ba90b3 gdb/testsuite: use multi_line in gdb.base/skip.exp
adds d4dd4fca16 gdb: change debug_bfd_cache to bool
adds c78eec4424 mips XPASS pr26936
adds 498ff0328f PR27218, memory access violation in dwarf2dbg.c
adds be07043ea8 PR27221, 058430b4a1 warnings while assembling the Linux kernel
adds 7cb6d92a3f gdb: convert arm to new-style debug macros
adds 325d39e4e0 Add Python support for hardware breakpoints
adds a72d0f3d69 gdb/doc: reorder and group sections relating to aliases
adds 730af66356 gdb/testsuite: improve logging in lib/tuiterm.exp
adds 439706e6a9 gdb: use interruptible_select when connecting to a remote
adds 1e15fcac94 gdb: convert bfd-cache to new-style debug macros
adds d3abc0cee0 gdb: remove unused f77_array_offset_tbl from f-valprint.c
adds a59902a7c1 gdb: convert auto-load to new-style debug macros
adds d5d24e12f9 Fix build errors for armhf
adds cd211c75cb Handle additional connection error
adds e534c7e8c4 Automatic date update in version.in
adds c651f0a614 MAINTAINERS: Update my e-mail address
adds cc4bc93e52 gdb/doc: down case contents of @var
adds fe461d2f70 gdb/doc: move @menu to the end of the node
adds 5b7d941b90 gdb: add owner-related methods to struct type
adds 3062502019 gdb: remove TYPE_OBJFILE_OWNED macro
adds 344e9841d9 gdb: remove TYPE_OBJFILE macro
adds baf2b57f18 gdb: move set remote commands to remote.c
adds cda09ec9f9 gdb: move remote_debug to remote.{h,c}
adds 02349803fc gdb: change remote_debug to bool
adds 2189c31265 gdb: add remote_debug_printf
adds d8c4766d31 gdb/doc: don't rely on @menu item within the docs
adds e7b430724d gdb: don't print escape characters when a style is disabled
adds 9d2d8a16e1 gdb: add new version style
adds 0ac85db529 gdb/testsuite: eliminate gdb_suppress_tests mechanism
adds 705646c074 Fix expected output of gdb.base/line65535.exp with dwarf-5
adds e753591581 Automatic date update in version.in
adds 1af4c9c420 Disable bracketed paste mode in GDB tests
adds ef45cb65a7 Use readline's variant of Windows patch
adds d3ee35dbf7 Improve gdb_tilde_expand logic.
adds dd5ca05f47 gdb: fix regression in copy_type_recursive
adds c99d72de18 Automatic date update in version.in
adds 9f7f6cb8d2 Remove call to reset from compile_to_object
adds 18454c151f DWARF-5: Fix parsing DWARF-5 line number tables
adds 3637a558a5 Use std::vector for "registers_used" in compile feature
adds b10bae1875 Avoid crash when "compile" expression uses cooked register
adds 68fcee4fa7 PR27228, .reloc wrong symbol emitted for undefined local symbol
adds 9b351c9bc9 Minor updates to the 'how to make a release' document
adds eea133e655 gas: Add a testcase for PR gas/27228
adds 940d0202fd DWARF-5: Ignore empty range in DWARF-5 line number tables
adds 123b18bf62 Automatic date update in version.in
adds b8df69003d Update linker scripts with the names of new DWARF-5 debug sections.
adds 04de9f3e31 gdb/doc: move @menu blocks to the end of their enclosing @node
adds 9e42b97628 Add some more DWARF-5 sections
adds acd6125f01 Add test case for symbol menu for local enumerators
adds 191849105b Specially handle array contexts in Ada expression resolution
adds a625a8c9eb Fix fixed-point regression with recent GCC
adds f3bdc2dbb9 gdb/docs: add parentheses in Python examples using print
adds 9f6c202e57 [gdb/symtab] Handle DW_AT_ranges with DW_FORM_sec_off in par [...]
adds 01a01e0ab3 Automatic date update in version.in
adds d0021af39c [gdb/testsuite] Fix gdb.opt/solib-intra-step.exp with -m32
adds 4ca40594f9 [gdb/testsuite] Fix gdb.threads/killed-outside.exp with -m32
adds d56834cbfb arc: Log "pc" value in "arc_skip_prologue"
adds e37709f090 Fix thinko in objcopy's memory freeing code.
adds ac3571d941 Fix the date for the last entry in gdb/ChangeLog
adds d0cc52bdf2 gdb: Add default reggroups for ARC
adds 4287950e54 pr27228 testcase
adds 9886ff0319 gas byte test
adds a45ef9a30b gas testsuite tidy
adds 1c9c9b9b55 PR27226, ld.bfd contains huge .rodata section
adds c3ffb8f340 Segmentation fault i386-gen
adds 4cb1265b3f bfd: add elfcore_write_file_note
adds 4ef367bffd Use debug_prefixed_printf_cond in windows-nat.c
adds 1f583bc2fc nios2: Don't disable relaxation with --gdwarf-N
adds c22788d614 Automatic date update in version.in
adds 2eda57ef61 ld: Fix a typo in testsuite/ld-x86-64/bnd-plt-1.d
adds 67965ba289 Simplify the code at the end of objcopy's main() function.
adds f04ce15e83 ld: depend on libctf
adds bb3c2d4d94 Remove extra space after @pxref in gdb.texinfo
adds 807f647cac GDB: aarch64: Add ability to displaced step over a BR/BLR in [...]
adds 59b59f08f6 Avoid use after free with logging and debug redirect.
adds 07b8b9e7c5 Automatic date update in version.in
adds 22efa3d307 [gdb/testsuite] Fix ERROR in gdb.dwarf2/dw2-out-of-range-end [...]
adds 2f985dd1ac [gdb/testsuite] Fix gdb.ada/out_of_line_in_inlined.exp with [...]
adds def97fb945 PR27259, SHF_LINK_ORDER self-link
adds 2a7f6487d0 [gdb/breakpoints] Fix longjmp master breakpoint with separat [...]
adds 24cf63899b gdb: update comment for execute_command_to_string
adds 47918cca26 gdb/testsuite: unset XDG_CONFIG_HOME
adds 0318cca493 gold: Skip address size and segment selector for DWARF5
adds a7ad3cb1ff Fix binutils tools so that they can cope with the special /d [...]
adds 53e556e5b4 ld: Add a test for PR ld/27259
adds cc3edc5274 Improve windres's handling of pathnames containing special c [...]
adds 6ac373717c gdb: rename type::{arch,objfile} -> type::{arch_owner,objfil [...]
adds 8ee511afd8 gdb: rename get_type_arch to type::arch
adds c47b145e1a [gdb/testsuite] Fix g0 search in gdb.arch/i386-sse-stack-align.exp
adds cdeba395cf [gdb/testsuite] Fix gdb.arch/i386-gnu-cfi.exp
adds f237f998d1 gdb/tui: remove special handling of locator/status window
adds 0f93c3a25b gdb: remove unneeded switch_to_thread from thr_try_catch_cmd
adds 986dbd541a Automatic date update in version.in
adds c4566785ac PR27271, c6x-uclinux-ld segfaults linking ld-uClibc-1.0.37.so
adds 620ec3caae [gdb/testsuite] Fix gdb.opt/solib-intra-step.exp with -m32 a [...]
adds ebde6f2ddc [gdb/breakpoint] Fix stepping past non-stmt line-table entries
adds 6efcd6f329 Automatic date update in version.in
adds 008a02e36d sim: readd myself as a maintainer
adds 481fac96bd sim: common: sort nltvals.def
adds f4dd74915b sim: hw: replace fgets with getline
adds 88f68ee277 sim: m68hc11: stop making hardware conditional
adds 18d4b488f4 sim: profile: fix bucketing with 64-bit targets
adds d4e3adda12 sim: watchpoints: change sizeof_pc to sizeof(sim_cia)
adds ee64caae5b sim: m68hc11: include stdlib.h for prototypes
adds fb8d4e59af sim: m68hc11: tweak printf-style funcs
adds b9e016f517 sim: m68hc11: localize a few functions
adds 683b8d961e sim: m68hc11: fix printf size warnings
adds ca51543cf5 Automatic date update in version.in
adds 9a7ba4aa0e sim: common: change gennltvals helper to Python
adds 3c811346e9 sim: moxie: cleanup build warnings
adds 44b30b7f0e sim: v850: fix handling of SYS_times
adds 5f05936d9b sim: v850: cleanup build warnings
adds 5bc4f5ca15 sim: cgen-accfp: Fix pointer sign warnings
adds ba2f0de216 sim: bpf/or1k: fix CGEN_TRACE_EXTRACT name
adds bccec180ce sim: bpf: fix mainloop extract call
adds 6451541244 sim: cgen-trace: tweak printf call
adds 4ebf566ea5 Automatic date update in version.in
adds 7bba67ec7c PR27283 gas for alpha fails to build with gcc 11
adds 49daa38f31 Re: ld: Add a test for PR ld/27259
adds a5f92c6756 ldgram.y low_level_library_NAME_list
adds 82a1fd3a49 gdb: unify parts of the Linux and FreeBSD core dumping code
adds 40726f16a8 ld script expression parsing
adds fb6c220ebd ld --defsym
adds 72a51a0603 Small updates to the 'how to make a release' document follow [...]
adds 34c10233cd Wrong operand for SADDR (rl78)
adds c39c86378f [gdb/testsuite] Fix gdb.dwarf2/fission-reread.exp with .gdb_index
adds 1f568f9a0d Add Genode target support
adds 82e3e87da4 Automatic date update in version.in
adds 2bd3e4b8d2 [gdb/symtab] Fix assert in write_one_signatured_type
adds 9918bff7cf PR27311, ld.bfd (symbol from plugin): undefined reference
adds 5424d7ed94 readelf: Add 'R' and 'D' to "Key to Flags:"
adds a0c1eeba9b gdb/dwarf: change read_loclist_index complaints into errors
adds 5e4d9bbc4b gdb/dwarf: fix bound check in read_rnglist_index
adds 05787bad36 gdb/dwarf: add missing bound check to read_loclist_index
adds 0c800c6ebc gdb/dwarf: remove unnecessary check in read_{rng,loc}list_index
adds b1829e1bf2 gdb/dwarf: few fixes for handling DW_FORM_{rng,loc}listx
adds a1c4010369 gdb/dwarf: read correct rnglist/loclist header in read_{rng, [...]
adds 962effa790 gdb/testsuite: add .debug_rnglists tests
adds 6b0933da34 gdb/testsuite: DWARF assembler: add context parameters to _location
adds ecfda20dcc gdb/testsuite: add .debug_loclists tests
adds 2b0c7f41d1 gdb/dwarf: split dwarf2_cu::ranges_base in two
adds e57933dc9c gdb/dwarf: make read_{loc,rng}list_index return sect_offset
adds 9307efbe9e gdb/testsuite: add test for .debug_{rng,loc}lists section wi [...]
adds e0bd9202fb gdb/testsuite: use proc_with_prefix in gdb.base/scope.exp
adds 2e3773ff54 Inferior without argument prints detail of current inferior.
adds 0e33957abf Automatic date update in version.in
adds 2ab76a181f Fix attaching in non-stop mode (PR gdb/27055)
adds 621cc31071 Fix "target extended-remote" + "maint set target-non-stop" + [...]
adds 92234eb192 Testcase for attaching in non-stop mode
adds b0083dd72f Fix a couple vStopped pending ack bugs
adds 7e9cf1fe36 gdbserver: spurious SIGTRAP w/ detach while step-over in progress
adds d758e62c0e Factor out after-stop event handling code from stop_all_threads
adds 9147506842 prepare_for_detach: don't release scoped_restore at the end
adds 8ff531399b prepare_for_detach and ongoing displaced stepping
adds e87f0fe823 detach and breakpoint removal
adds ac7d717c1e detach with in-line step over in progress
adds 408f66864a detach in all-stop with threads running
adds a71501e25f Testcase for detaching while stepping over breakpoint
adds 6955136728 PR27311 again, ld.bfd (symbol from plugin): undefined reference
adds 95b91a043a pr27270 and pr27284, ar segfaults and wrong file mode
adds f01fb44c06 Re: PR27311, ld.bfd (symbol from plugin): undefined reference
adds 61ecbbae8e IBM Z: Add missing vector formats to .insn docs
adds 72d383bb08 gdb: infrun: move stop_soon variable to inner scoped in hand [...]
adds e3714e037b Automatic date update in version.in
adds 7d409ac001 PR27311, (symbol from plugin): undefined reference, hidden sym
adds 24075dcc85 RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instructions.
adds 37707bd822 ld: Restore PR ld/15146 tests
adds 1a2f1b54a5 x86-64: Provide more info when failed to convert GOTPCREL
adds 35a01a0454 libctf, ld: fix symtypetab and var section population under ld -r
adds 78f28b89e8 libctf: rip out dead code handling typedefs with no name
adds caa170493e libctf: prohibit nameless ints, floats, typedefs and forwards
adds 5dacd11ddc libctf: fix uninitialized variable in symbol serialization e [...]
adds ee87f50b8d libctf: always name nameless types "", never NULL
adds 6b36ddeb1e gdb: make async event handlers clear themselves
adds baa8575b29 gdb: make remote target clear its handler in remote_target::wait
adds 85d3ad8e0b gdb: make record-btrace clear event handler in wait
adds fdbc5215e7 gdb: make record-full clear async handler in wait
adds 3eccb1c8bf gdb: Use correct feature in tdesc-regs for ARC
adds 6ff267e186 gdb: make target_is_non_stop_p return bool
adds a9ab6e2ea0 Automatic date update in version.in
adds b9249c461c sim: riscv: new port
adds 04b4939b03 gdb: riscv: enable sim integration
adds c180f095f3 PR27345, binutils/arsup.c: lstat() not available on all targets
adds cb4ff67af3 RISC-V: PR27348, Remove obsolete Xcustom support.
adds 5f40035fb8 RISC-V: PR27348, Remove the obsolete OP_*CUSTOM_IMM.
adds 554c30abef ld testsuite on x86_64 with --enable-shared
adds 887854bae4 Fix typos in comments added in PR 27252 fix
adds fc9a13fbdd [gdb/symtab] Fix indentation in create_cus_from_debug_names_list
adds d3b54e63f4 [gdb/symtab] Fix duplicate CUs in create_cus_from_debug_names_list
adds ae71049661 [gdb/exp] Fix assert when adding ptr to imaginary unit
adds a22ec6e8a4 [gdb/testsuite] Add KFAILs for PR symtab/24549
adds e37d88e5e5 Remove Richard Henderson as the Alpha maintainer
adds 1b30f42106 Extract symbol-writing function from parsers
adds bdfea17ea9 Return unique_ptr from language_defn::get_compile_context
adds 0e857c8288 [gdb/breakpoints] Fix segfault for catch syscall -1
adds e77b0004dd [gdb/symtab] Handle DW_TAG_type_unit in process_psymtab_comp_unit
adds 7c6944ab9b [gdb/breakpoints] Handle glibc with debuginfo in create_exce [...]
adds 0110ec824e gdb: symmisc.c: remove std_{in,out,err}
adds 9c9d63b15a gnulib: update to 776af40e0
adds 51a2525281 PR27349, ar breaks symlinks
adds 2c6f2aa664 Automatic date update in version.in
adds aa09469fc6 sim: drop use of bfd/configure.host
adds 7a36eeea26 sim: common: switch AC_CONFIG_HEADERS
adds 8e25beb4af sim: igen: drop libiberty linkage
adds cd89c53f6d sim: add ChangeLog entries for last commits
adds 4c0d76b9c4 sim: watchpoints: use common sim_pc_get
adds 7a9bd3b4e2 sim: erc32/m32c/rl78: add sim_memory_map stub for gdb
adds c0e5674584 [gdb/testsuite] Fix gdb.tui/tui-layout-asm.exp with -m32
adds cca043e071 Automatic date update in version.in
adds de8d420310 asan: unwind-ia64.c: stack buffer overflow
adds 83962f8340 Also compare frame_id_is_next in frapy_richcompare
adds 5fc2d6aa06 Refresh regs window in display_registers_from
adds 3537bc23d9 Don't fill regs window with a negative number of spaces
adds 4cf28e918a Don't draw register sub windows outside the visible area
adds 38a143aa8c ld: Remove x86 ISA level run-time tests
adds d6f2700b48 Automatic date update in version.in
adds 5fb9763991 gdb/testsuite: fix implementation of delete line in tuiterm.exp
adds cd074e0415 gdb/tui: fix issue with handling the return character
adds 0309f9549d sim/rx: define sim_memory_map
adds 93a01471f3 sim/rx: fix an issue where we try to modify a const string
adds 1c3e93a41f sim/rx: fill in missing 'void' for empty argument lists
adds 73d4725f21 sim/rx: mark some functions as static
adds 4b42639636 sim/rx: delete an unused function
adds b9fe995797 sim/rx: provide a format string for printf
adds 783a7b12d3 sim/rx: move some variable declarations to the start of the block
adds ae41b4ce9f sim/rx: use PRIx64 in printf format string
adds fab2b376e3 sim/rx: add some missing includes
adds da9ecd6085 sim/rx: avoid pointer arithmetic on void * pointers
adds 6bf99988c6 sim/rx: enable build with warnings
adds 2708dbbd58 gdb/python: reformat an error string
adds a53a265752 gdb/tui: restore delete of window objects
adds 1cf2399651 gdb/tui: don't add windows to global list from tui_layout:wi [...]
adds e0c23e11da gdb/python: don't allow the user to delete window title attributes
adds 29db1eb339 gdb: return true in TuiWindow.is_valid only if TUI is enabled
adds 9b3e4b5d74 gdb: Do not interrupt atomic sequences for ARC
adds 4001d90dde [gdb/testsuite] Use DW_FORM_ref_addr in gdb.dwarf2/enqueued- [...]
adds 80b652efa2 Fix an illegal memory access when parsing a corrupt assembler file.
adds 3d4aae4860 Build gdb.base/gnu-ifunc.exp with lazy binding
adds bfd428bc12 opcodes: tic54x: namespace exported variables
adds 32d5141c70 Automatic date update in version.in
adds 52563b0f1c Add a test for PR 27355 - where corrupt assembler .file dire [...]
adds 4a68fcd7f7 Prevent a bad .Psize expression from triggering a memory acc [...]
adds a57d17732e Remove arm-symbianelf
adds 9b87f84a35 [binutils] Handle DW_UT_skeleton/split_compile in process_de [...]
adds 284beb431f Add a sanity check of files include by .incbin.
adds 5f128a25f2 [binutils] Handle DW_FORM_ref_sig8 in get_type_abbrev_from_form
adds a4f0544b1b Avoid crash in resolve_dynamic_struct
adds f73e424f7b Avoid crash from coerce_unspec_val_to_type
adds b61f78118a [testsuite] Don't use 'testfile' before 'standard_testfile'.
adds 03642b7189 gdb: revert "gdb: unify parts of the Linux and FreeBSD core [...]
adds cf2b207529 [gdb/symtab] Fix element type modification in read_array_type
adds 238ebeb127 Automatic date update in version.in
adds 9bb305b389 Fix typo in stap_parse_argument_conditionally
adds 01e8b831f5 Remove debugging code accidentally included with the fix for [...]
adds ee4c3d8801 [gdb/testsuite] Fix tcl ERROR in gdb_load_no_complaints
adds 52ff20fe7b [binutils] Handle presence of both .debug_ranges and .debug_ [...]
adds ebbc3a7d56 gdb: Delete SYMBOL_OBJ_SECTION and MSYMBOL_OBJ_SECTION
adds a52d653e91 gdb: delete SYMBOL_SECTION and MSYMBOL_SECTION macros
adds 830c5a1ffb intl: Allow building both with old bison and bison >= 3 [PR92008]
adds adda0248ed intl: Unbreak intl build with bison 3 when no regeneration i [...]
adds 53d4244ec0 intl: always picify
adds aee224d643 intl: turn LIBINTL into -L / -l form
adds 9514861402 bfd, opcodes, libctf: support --with-included-gettext
adds cbd8f5bbcc libctf: require a Tcl capable of try/catch to run tests
adds 758f590744 libctf: add missing header in BFD ELF check
adds e92c8eb86d gdb/fortran: add parser support for lbound and ubound
adds d9d9d8ef8c [binutils] Handle absolute DW_AT_dwo_name
adds 933feaf37e Re: Remove arm-symbianelf
adds 18b8df43bd gdb: Remove arm-symbianelf support
adds 25ad1e83c8 gdb/testsuite: use "set sysroot" in gdb.multi/multi-target.exp.tcl
adds 10ed138aa3 Automatic date update in version.in
adds 160fe19337 gdb: adjust comment in gdb.multi/multi-target.exp.tcl
adds 6db658c517 PR27291, integer overflow in bfd_get_section_contents
adds 1cfcf3004e PR27290, PR27293, PR27295, various avr objdump fixes
adds 31c711a2b3 PR27294, avr OOM
adds 1db66e348a gdb: add obj_section function to bound_minimal_symbol
adds f4be677293 gdb/testsuite: split 'maint info sections' tests to a new file
adds 4790db1496 gdb: 'maint info sections' - handle the no executable case
adds bf3386f0c1 gdb: change 'maint info section' to use command options
adds a1670b7263 gdb/testsuite: remove old comment
adds 769c253f45 Revert "ia64: Check UNDEFWEAK_NO_DYNAMIC_RELOC"
adds 234b98ced2 Remove ia64 from obsolete list
adds b260f8d60c Fix two Fortran regressions
adds 05f68f52ef [gdb/symtab] Handle DW_FORM_strx in form_requires_reprocessing
adds a5a310d616 Automatic date update in version.in
adds d60f79984a [binutils] Print DWO ID
adds 95abb3944c [binutils] Fix printing of .debug_str_offsets
adds 528a4f87c6 [binutils] Fix typo in comment in dwarf.h
adds 3c1d41015b gas testsuite: adjust recently added tests for hppa
adds 8f054a7a5a binutils test pr25662: don't use single character labels
adds 17e04eff81 binutils testsuite: replace unresolved with unsupported
adds 96df3e28b8 gdb/fortran: support ALLOCATED builtin
adds c46b706620 Change the readelf and objdump programs so that they will au [...]
adds c054dcd552 Minor constification in gdbreplay
adds 089436f787 [gdb/threads] Fix lin_thread_get_thread_signals for glibc 2.28
adds 77fba254d9 Add stdio support to gdbreplay
adds ceda7cf7f7 Automatic date update in version.in
adds adeab0c5b3 config/debuginfod: do not include pkg.m4 directly
adds 652f80e07b sim: common: delete unused aclocal.m4
adds 136da8cd9c sim: switch to AC_CONFIG_MACRO_DIRS
adds 9ee455572d sim: rx: mitigate fread warning
adds b0dcd7d832 sim: testsuite: push $arch out to targets
adds f5b2658b0f Automatic date update in version.in
adds 5b1f6c9570 ld testsuite: change unresolved to unsupported/fail
adds 0d0a0d86c8 Regen for binutils/aclocal.m4 change
adds 1944212b42 objdump: don't add an extra entry to syms array
adds d7a7af8ff4 Modernise _bfd_elf_mips_get_relocated_section_contents
adds a5e6af6d17 Automatic date update in version.in
adds 8b78cbec31 alpha_ecoff_get_relocated_section_contents
adds 1781a9d0f3 nds32_elf_get_relocated_section_contents
adds 208599d928 objdump: don't cache section contents in load_specific_debug [...]
adds 8c6740616c bfd: use $(LN_S) in favor of "cp -p" when populating pre-bui [...]
adds ba2b480f10 IBM Z: Implement instruction set extensions
adds 94ae6062ab Automatic date update in version.in
adds 7043388668 demand_copy_C_string NUL check
adds 9a12b194b0 PR27426, More bugs in dwarf2dbg.c
adds 7b54caddca ubsan: shift exponent is too large
adds e6ca18783f Dwarf: fix build with old gcc
adds c2f1204d1f x86: make 16-bit ENQCMD test actually test ENQCMD
adds b818b220e4 x86: have preprocessor expand macros
adds cbe6869656 x86: make common property tests common
adds 014d61ea14 x86: record register use for SIMD insns without respective e [...]
adds 3d70986f21 x86: honor template rather than actual operands when updatin [...]
adds 394ae71f02 x86: CVTPI2PD has special behavior
adds ca1289b9f3 gas: Allow SHF_GNU_RETAIN on all sections
adds 7d2e5095c6 Correction of gdb.dwarf2/pr13961.S
adds 0b5500cdd5 Automatic date update in version.in
adds 0d6aab7776 RISC-V: PR27200, allow the first input non-ABI binary to be [...]
adds b9b204b311 read_leb128 overflow checking
adds 089485ff86 h8300 complains about new section defined without attributes
adds 22e6d16f9b [PR cli/17290] gdb/doc: Fix show remote interrupt-*.
adds afadac6170 Automatic date update in version.in
adds 6a780b6766 Fix completion related libstdc++ assert when using -D_GLIBCXX_DEBUG
adds 3d73d29e4e RISC-V: Add bfd/cpu-riscv.h to support all spec versions con [...]
adds b0e4d2bd9b gdb: add missing full stops in --help
adds a364a116f9 ld: remove stray debug fprintf
adds acde209241 gdb/testsuite: only run gdb.arch/i386-biarch-core.exp on sui [...]
adds 8568422270 Fix a problem merging empty annobin notes on ppc64le targets.
adds 26f53cd385 Introduce expression::evaluate
adds 668c18f17f Automatic date update in version.in
adds 3685de750e binutils: Avoid renaming over existing files
adds 0be51eb4c3 pr26548 test
adds 2f973f134d Wrong ELF class plugin vs. gcc ld version
adds 5a9f5403c7 RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types [...]
adds 8488c357ce amd64-linux-siginfo.c: Adjust include order to avoid gnulib error
adds 0257c2ff4f Fix compile time warnings when building riscv assembler.
adds ca6afb81ca Automatic date update in version.in
adds c3bf9dc5aa Include ld-lib.exp from ctf-lib.exp
adds 4d496013a2 Fail run_dump_test when an error is expected but not seen
adds 8c3853d9e8 readelf: Replace procesor with processor
adds 3e8bb3e934 sim: merge configure.tgt into configure.ac
adds f4f60336da libctf, include: find types of symbols by name
adds 03c653093d libctf: add a NEWS
adds f9eb406771 Automatic date update in version.in
adds 93993f6784 libctf AC_CANONICAL_TARGET
adds 89753bbf81 Warn when a script redefines a symbol
adds 760b3e8bc9 sim: common: split up acinclude.m4 into individual m4 files
adds 48ef615826 Automatic date update in version.in
adds e9d18e0649 Don't handle BFD_RELOC_16 in XCOFF reloc_type_lookup
adds de146e1946 gdb: push target earlier in procfs_target::attach (PR 27435)
adds f53fc42716 gdb: add asserts in thread code
adds 15908a11ba Change target_bfd_reopen to take a gdb_bfd_ref_ptr
adds f16ccf47d8 Automatic date update in version.in
adds 897608ed56 gdb: linux-nat: make linux_nat_filter_event return void
adds 1a48f0027d gdbserver: linux-low: make linux_process_target::filter_even [...]
adds 616c069a3f gdb/dwarf: don't enqueue CU in maybe_queue_comp_unit if alre [...]
adds 08ac57714c gdb/dwarf: create and destroy dwarf2_per_bfd's CUs-to-expand queue
adds cca8873dd5 PR27456, lstat in rename.c on MinGW
adds c42c71a152 Use make_tempname file descriptor in smart_rename
adds 55add51eef PR23691, gas .y files vs. automatic make dependencies
adds 8139dc77d9 Automatic date update in version.in
adds 93af1b046b PR27459, segmentation fault in go32exe_check_format
adds c74147bbe0 Remove support for old v1 & v2 style GNU build notes.
adds 9d3fcfe068 Fix a potential integer overflow when adding together sectio [...]
adds bc3c0632a2 gdb: call value_ind for pointers to dynamic types in UNOP_IN [...]
adds 895b7b4e4b gdb/riscv: select rv32 target by default when requested
adds 02a7930992 gdb: add a new 'maint info target-sections' command
adds 19cf757a87 gdb: spread a little 'const' through the target_section_table code
adds b91919ac8b gdb/testsuite: enable gdb.base/sect-cmd.exp test for all targets
adds 02f7d26b0b gdb: make the target_sections table private within program_space
adds 336aa7b740 gdb: move get_section_table from exec_target to dummy_target
adds dd80d75040 gdb: use std::string instead of a fixed size buffer
adds 665af52ec2 Fix aarch64-linux-hw-point.c build problem
adds 268c77c1b0 Add comment regarding include order of <sys/ptrace.h> and <a [...]
adds aa659cfad6 [gdb/symtab] Handle DW_AT_decl_file with form DW_FORM_implic [...]
adds 40b02646ec Re: Use make_tempname file descriptor in smart_rename
adds 39b0759693 Automatic date update in version.in
adds bbaddd4bbe PR27441, inconsistency in weak definitions
adds 170f4b23b6 gdb/fortran: add support for legacy .xor. operator
adds faeb9f13c1 gdb/fortran: add support for ASSOCIATED builtin
adds 68337b8be3 gdb/fortran: don't access non-existent type fields
adds 3c27360bc4 ld: correct description of behavior for symbols redefined by script
adds 30c80d8833 [gdb/symtab] Fix wrong unit_type Dwarf Error
adds 2450ad54ce gdb/mi: Remove extra \n from tsv and and traceframe notifications
adds d4ff3cbfdb gdb/testsuite: Add a missing -wrap in gdb_test_multiple
adds e38332c286 Add initial support for .debug_sup sections.
adds 64d38fdd99 Fix initial thread state of non-threaded remote targets
adds dffdd8b51f gdb: relax assertion in target_mourn_inferior
adds 0f977b7715 Add comment regarding include order of <sys/ptrace.h> and <a [...]
adds 26b43ca6e6 Fix date in ChangeLog
adds 06172a2c98 Automatic date update in version.in
adds 8255cf421c libctf regen for NEWS
adds bfece7562d Add PR27441 testcase
adds cb51b708fd testsuite: note on use_gdb_stub usage
adds 32e4f96cec Add support for the split DWARF forms.
adds f821878623 testsuite: Remove extra \n from expected output of tsv notif [...]
adds 0e12f6c802 Add support for decoding DWARF v5 DW_AT_addr_base tags.
adds fe0171d248 Correct an error message in the ARM assembler.
adds 7fe1b1388f nm: Add --quiet to suppress "no symbols" diagnostic
adds 0cf9ea0b16 Automatic date update in version.in
adds 573dc0cc43 Minor fix in skip_ctf_tests
adds bb3a4efe13 [PR gdb/27393] set directories: handle empty dirs.
adds b2287f90e4 Automatic date update in version.in
adds f8069d55c1 sim: delete redundant SIM_EXTRA_ALL
adds ed30adf750 sim: delete unused SIM_EXTRA_LIBDEPS
adds ebe9564b99 sim: require AC_PROG_CPP explicitly
adds a3e2cc64a6 sim: use AC_CHECK_TOOL to find ar
adds c25ea03dd6 sim: set up build-time compiler settings
adds 9ea3e81ca0 sim: igen: delete unused FOR_BUILD vars
adds 88d7273afd sim: igen: delete more unused toolchain settings
adds 9f34b60a43 sim: igen: drop config.h & header checking
adds 1dbde357be Add missing changes to Makefile.tpl
adds cf850febf6 Automatic date update in version.in
adds 6a1224ec76 PR27128, nm -P portable output format regression
adds 7824c1d22f Weak references to __start_/__stop_ symbols
adds 8ee10e8609 PR27451, -z start_stop_gc
adds ecd65684f5 Warn for missing separate debug files only if needed
adds ba6eb62ff0 Add DWARF-5 section names to PE and PEP linker scripts.
adds ec11fcffc0 Automatic date update in version.in
adds f5b9c288a3 PowerPC64 undefined weak visibility vs GOT optimisation
adds b80e421f91 PR27451, -z start_stop_gc for powerpc64
adds eaa2913a7a libctf: ctf_archive_next should set the parent name consistently
adds ac36e134d9 libctf: reimplement many _iter iterators in terms of _next
adds fd12633780 libctf: fix ChangeLog date
adds 8915c559d4 libctf, include: remove the nondeduplicating CTF linker
adds 478c04a55e libctf: remove reference to "unconflicted link mode".
adds f5060e5633 libctf: add a deduplicator-specific type mapping table
adds 4659554b28 libctf: minor error-handling fixes
adds cf6a0b989a libctf: fix signed/unsigned comparison confusion
adds 8e7e446446 libctf: free ctf_dynsyms properly
adds 211bcd0133 bfd, ld, libctf: skip zero-refcount strings in CTF string reporting
adds ca8f6bc629 Fix the BFD library's parsing of DIEs where specification at [...]
adds 1228719f31 Check objfile->sf in ada-lang.c
adds bdcccc5639 Use new for ada_symbol_cache
adds 886d459fbe Simplify resolve_subexp by using C++ algorithms
adds d1183b064c Return a vector from ada_lookup_symbol_list
adds 5f9febe0f6 Use std::string rather than grow_vect
adds bbcdf9ab73 Rewrite GNAT-encoded fixed point types in DWARF reader
adds b4f26d541a Import GNU Readline 8.1
adds 19a9185537 Fix Readline 8.1 build on mingw
adds ca87bad0e9 Automatic date update in version.in
adds dc83f2d20e Split relocation defines out of coff/internal.h
adds 270f32fc50 ld-gc tests on underscore targets
adds 5789f845fb --gc-sections with groups and start/stop syms
adds fd5c076a06 PR27493, objcopy --weaken-symbol does not weaken undefined symbols
adds b93a3ed0a8 testsuite: extend nopie handling to add -fno-pie to compiler flags
adds e71dbd0304 testsuite, gdb.btrace: remove assembly-check in delta.exp
adds f0778fc1cf testsuite, gdb.btrace: pass rn-dl-bind.exp with clang
adds c7c7253a47 testsuite, gdb.btrace: move -Wl,-x to ldflags
adds d2c5f24eed testsuite, gdb.btrace: adjust expected output to pass with clang
adds 26ed1478d1 testsuite, gdb.btrace: remove implicit debug option in stepi.exp
adds 32c5299909 testsuite, gdb.btrace: adjust expected source line in non-stop.exp
adds 8233378104 gdb, testsuite: enforce lazy binding for gdb.btrace/rn-dl-bind.exp
adds 75363b6d60 x86: infer operand count of templates
adds 1bfa81acbf Minor Ada-related cleanups
No new revisions were added by this update.
Summary of changes:
ChangeLog | 18 +
Makefile.def | 1 +
Makefile.in | 1 +
Makefile.tpl | 5 +
bfd/ChangeLog | 341 +
bfd/Makefile.am | 2 +-
bfd/Makefile.in | 2 +-
bfd/coff-alpha.c | 26 +-
bfd/coff-rs6000.c | 3 -
bfd/coff-stgo32.c | 4 +-
bfd/coff64-rs6000.c | 3 -
bfd/compress.c | 3 +-
bfd/config.bfd | 13 +-
bfd/configure | 13 +-
bfd/configure.ac | 13 +-
bfd/cpu-riscv.c | 123 +-
bfd/cpu-riscv.h | 81 +
bfd/doc/Makefile.am | 44 +-
bfd/doc/Makefile.in | 44 +-
bfd/dwarf2.c | 138 +-
bfd/elf-bfd.h | 5 +-
bfd/elf-linker-x86.h | 3 +
bfd/elf-strtab.c | 4 +-
bfd/elf.c | 8 +
bfd/elf32-arm.c | 1091 +-
bfd/elf32-avr.c | 16 +-
bfd/elf32-ft32.c | 3 +-
bfd/elf32-i386.c | 36 +
bfd/elf32-nds32.c | 5 +-
bfd/elf32-ppc.c | 55 +-
bfd/elf32-rl78.c | 2 +-
bfd/elf64-ppc.c | 95 +-
bfd/elf64-x86-64.c | 46 +-
bfd/elflink.c | 62 +-
bfd/elfnn-ia64.c | 20 +-
bfd/elfnn-riscv.c | 388 +-
bfd/elfxx-mips.c | 114 +-
bfd/elfxx-riscv.c | 69 +-
bfd/elfxx-riscv.h | 16 +-
bfd/elfxx-x86.c | 50 +-
bfd/elfxx-x86.h | 4 +
bfd/libbfd.c | 23 +-
bfd/linker.c | 1 +
bfd/po/SRC-POTFILES.in | 1 +
bfd/reloc.c | 2 +-
bfd/section.c | 6 +-
bfd/targets.c | 4 -
bfd/version.h | 2 +-
bfd/wasm-module.c | 27 +-
binutils/ChangeLog | 382 +
binutils/MAINTAINERS | 9 +-
binutils/Makefile.in | 3 +-
binutils/NEWS | 16 +
binutils/README-how-to-make-a-release | 64 +-
binutils/aclocal.m4 | 1 +
binutils/ar.c | 25 +-
binutils/arsup.c | 48 +-
binutils/bucomm.c | 15 +
binutils/bucomm.h | 3 +-
binutils/config.in | 3 +
binutils/configure | 29 +-
binutils/configure.ac | 14 +
binutils/doc/Makefile.in | 3 +-
binutils/doc/binutils.texi | 34 +-
binutils/doc/debug.options.texi | 21 +-
binutils/dwarf.c | 416 +-
binutils/dwarf.h | 5 +-
binutils/elfedit.c | 14 +
binutils/nm.c | 35 +-
binutils/objcopy.c | 115 +-
binutils/objdump.c | 114 +-
binutils/od-elf32_avr.c | 127 +-
binutils/readelf.c | 55 +-
binutils/rename.c | 215 +-
binutils/testsuite/binutils-all/ar.exp | 22 +-
binutils/testsuite/binutils-all/compress.exp | 25 +-
binutils/testsuite/binutils-all/objcopy.exp | 22 +-
binutils/testsuite/binutils-all/objdump.exp | 6 +-
binutils/testsuite/binutils-all/pr25662.s | 4 +-
binutils/testsuite/binutils-all/pr26548.d | 13 +
binutils/testsuite/binutils-all/pr26548.s | 40 +
binutils/testsuite/binutils-all/pr26548e.d | 11 +
binutils/testsuite/binutils-all/readelf.exp | 87 +-
binutils/testsuite/binutils-all/retain1a.d | 2 +
binutils/testsuite/lib/binutils-common.exp | 687 +-
binutils/unwind-ia64.c | 4 +
binutils/windres.c | 31 +-
config/ChangeLog | 5 +-
config/debuginfod.m4 | 2 -
configure | 3 -
configure.ac | 3 -
gas/ChangeLog | 398 +
gas/Makefile.am | 151 +-
gas/Makefile.in | 148 +-
gas/NEWS | 2 +
gas/config/bfin-lex-wrapper.c | 2 +-
gas/config/bfin-lex.l | 2 +-
gas/config/obj-elf.c | 22 +-
gas/config/tc-alpha.c | 2 +-
gas/config/tc-arm.c | 8 +-
gas/config/tc-i386.c | 25 +-
gas/config/tc-nios2.c | 4 -
gas/config/tc-riscv.c | 809 +-
gas/config/tc-riscv.h | 6 +-
gas/config/tc-s390.c | 2 +
gas/config/tc-tic54x.c | 28 +-
gas/config/te-symbian.h | 22 -
gas/configure | 8 +-
gas/configure.ac | 8 +-
gas/configure.tgt | 5 +-
gas/doc/as.texi | 7 -
gas/doc/c-riscv.texi | 160 +-
gas/doc/c-s390.texi | 57 +-
gas/dwarf2dbg.c | 59 +-
gas/listing.c | 20 +-
gas/po/POTFILES.in | 2 +-
gas/read.c | 16 +-
gas/testsuite/gas/all/byte.d | 4 -
gas/testsuite/gas/all/byte.l | 3 -
gas/testsuite/gas/all/byte.s | 2 -
gas/testsuite/gas/all/gas.exp | 7 +-
gas/testsuite/gas/all/local-label-overflow.d | 5 +-
gas/testsuite/gas/all/none.d | 2 +-
gas/testsuite/gas/all/pr27381.d | 4 +
gas/testsuite/gas/all/pr27381.err | 2 +
gas/testsuite/gas/all/pr27381.s | 1 +
gas/testsuite/gas/all/pr27384.d | 4 +
gas/testsuite/gas/all/pr27384.err | 4 +
gas/testsuite/gas/all/pr27384.s | 4 +
gas/testsuite/gas/all/sleb128-2.d | 2 +-
gas/testsuite/gas/all/sleb128-4.d | 3 +-
gas/testsuite/gas/all/sleb128-5.d | 2 +-
gas/testsuite/gas/all/sleb128-7.d | 2 +-
gas/testsuite/gas/all/sleb128-9.d | 2 +-
gas/testsuite/gas/all/string.d | 2 +-
gas/testsuite/gas/arm/arch4t-eabi.d | 2 +-
gas/testsuite/gas/arm/arch4t.d | 2 +-
gas/testsuite/gas/arm/got_prel.d | 2 +-
gas/testsuite/gas/arm/mapdir.d | 2 +-
gas/testsuite/gas/arm/mapmisc.d | 2 +-
gas/testsuite/gas/arm/mapsecs.d | 2 +-
gas/testsuite/gas/arm/mapshort-eabi.d | 2 +-
gas/testsuite/gas/arm/pr27411.d | 2 +
gas/testsuite/gas/arm/pr27411.l | 6 +
gas/testsuite/gas/arm/pr27411.s | 14 +
gas/testsuite/gas/arm/thumb-eabi.d | 2 +-
gas/testsuite/gas/arm/thumb.d | 2 +-
gas/testsuite/gas/arm/thumbrel.d | 2 +-
gas/testsuite/gas/elf/bignums.d | 2 +-
gas/testsuite/gas/elf/dwarf-5-file0.d | 2 +-
gas/testsuite/gas/elf/dwarf2-20.d | 4 -
gas/testsuite/gas/elf/elf.exp | 9 +-
gas/testsuite/gas/elf/group0c.d | 2 +-
gas/testsuite/gas/elf/group1a.d | 2 +-
gas/testsuite/gas/elf/missing-build-notes.d | 2 +-
gas/testsuite/gas/elf/pr27228.d | 10 +
gas/testsuite/gas/elf/pr27228.s | 5 +
gas/testsuite/gas/elf/pr27355.d | 3 +
gas/testsuite/gas/elf/pr27355.err | 5 +
gas/testsuite/gas/elf/pr27355.s | 4 +
gas/testsuite/gas/elf/section-symbol-redef.d | 2 +-
gas/testsuite/gas/elf/section0.d | 2 +-
gas/testsuite/gas/elf/section1.d | 2 +-
gas/testsuite/gas/elf/section10.d | 2 +-
gas/testsuite/gas/elf/section11.d | 4 +-
gas/testsuite/gas/elf/section15.d | 2 +-
gas/testsuite/gas/elf/section28.d | 16 +
gas/testsuite/gas/elf/section28.s | 11 +
gas/testsuite/gas/elf/section29.d | 11 +
gas/testsuite/gas/elf/section29.s | 4 +
gas/testsuite/gas/elf/section4.d | 2 +-
gas/testsuite/gas/elf/section6.d | 2 +-
gas/testsuite/gas/elf/section7.d | 2 +-
gas/testsuite/gas/elf/symtab.d | 4 +-
gas/testsuite/gas/elf/symtab.s | 2 +-
gas/testsuite/gas/elf/warn-2.s | 7 -
gas/testsuite/gas/i386/enqcmd-16bit.d | 27 +-
gas/testsuite/gas/i386/enqcmd-16bit.s | 2 +-
gas/testsuite/gas/i386/i386.exp | 34 +-
gas/testsuite/gas/i386/pr27198.d | 2 +
gas/testsuite/gas/i386/pr27198.err | 5 +
gas/testsuite/gas/i386/pr27198.s | 1 +
gas/testsuite/gas/i386/property-12.d | 2 +-
gas/testsuite/gas/i386/property-4.d | 2 +-
gas/testsuite/gas/i386/property-5.d | 2 +-
gas/testsuite/gas/i386/property-cvtpi2pd.d | 9 +
gas/testsuite/gas/i386/property-cvtpi2pd.s | 2 +
gas/testsuite/gas/i386/property-cvtpi2ps.d | 9 +
gas/testsuite/gas/i386/property-cvtpi2ps.s | 2 +
gas/testsuite/gas/i386/property-ldmxcsr.d | 9 +
gas/testsuite/gas/i386/property-ldmxcsr.s | 2 +
gas/testsuite/gas/i386/property-vldmxcsr.d | 9 +
gas/testsuite/gas/i386/property-vldmxcsr.s | 2 +
gas/testsuite/gas/i386/property-vzeroall.d | 9 +
gas/testsuite/gas/i386/property-vzeroall.s | 2 +
gas/testsuite/gas/i386/sse-check-error.l | 91 +-
gas/testsuite/gas/i386/sse-check-warn.e | 17 +-
gas/testsuite/gas/i386/sse-check.d | 2 +
gas/testsuite/gas/i386/sse-check.s | 4 +
gas/testsuite/gas/i386/sse2avx.d | 2 +
gas/testsuite/gas/i386/sse2avx.s | 2 +
gas/testsuite/gas/i386/x86-64-property-10.d | 10 -
gas/testsuite/gas/i386/x86-64-property-11.d | 10 -
gas/testsuite/gas/i386/x86-64-property-12.d | 10 -
gas/testsuite/gas/i386/x86-64-property-13.d | 10 -
gas/testsuite/gas/i386/x86-64-property-2.d | 10 -
gas/testsuite/gas/i386/x86-64-property-3.d | 10 -
gas/testsuite/gas/i386/x86-64-property-4.d | 10 -
gas/testsuite/gas/i386/x86-64-property-5.d | 10 -
gas/testsuite/gas/i386/x86-64-property-6.d | 10 -
gas/testsuite/gas/i386/x86-64-sse-check-error.l | 94 +-
gas/testsuite/gas/i386/x86-64-sse2avx.d | 2 +
gas/testsuite/gas/i386/x86-64-sse2avx.s | 2 +
gas/testsuite/gas/lns/lns-diag-1.l | 2 -
gas/testsuite/gas/m68hc11/indexed12.d | 4 -
gas/testsuite/gas/mach-o/sections-1.d | 2 +-
gas/testsuite/gas/macros/irp.d | 2 +-
gas/testsuite/gas/macros/repeat.d | 2 +-
gas/testsuite/gas/macros/rept.d | 2 +-
gas/testsuite/gas/macros/test2.d | 2 +-
gas/testsuite/gas/macros/test3.d | 1 -
gas/testsuite/gas/macros/vararg.d | 2 +-
gas/testsuite/gas/nios2/relax.d | 25 +
gas/testsuite/gas/nios2/relax.s | 5 +
gas/testsuite/gas/ppc/power4.d | 1 -
gas/testsuite/gas/ppc/test1elf32.d | 1 -
gas/testsuite/gas/ppc/test1elf64.d | 1 -
gas/testsuite/gas/riscv/bitmanip-insns-32.d | 37 -
gas/testsuite/gas/riscv/bitmanip-insns-64.d | 55 -
gas/testsuite/gas/riscv/bitmanip-insns.s | 58 -
gas/testsuite/gas/riscv/insn.d | 26 +-
gas/testsuite/gas/riscv/insn.s | 24 +-
gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +-
.../gas/riscv/priv-reg-fail-read-only-01.l | 136 +-
.../gas/riscv/priv-reg-fail-read-only-02.l | 48 +-
gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +-
.../gas/riscv/priv-reg-fail-version-1p10.l | 48 +-
.../gas/riscv/priv-reg-fail-version-1p11.l | 46 +-
.../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +-
gas/testsuite/gas/s390/s390.exp | 1 +
gas/testsuite/gas/s390/zarch-arch14.d | 31 +
gas/testsuite/gas/s390/zarch-arch14.s | 24 +
gas/testsuite/gas/xgate/insns-dwarf2.d | 2 +-
gas/write.c | 4 +-
gdb/ChangeLog | 1504 ++
gdb/MAINTAINERS | 5 +-
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sim/testsuite/configure | 3264 -----
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sim/testsuite/cr16/misc.exp | 32 +
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sim/testsuite/cris/ChangeLog | 208 +
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sim/testsuite/cris/asm/asm.exp | 49 +
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sim/testsuite/{sim => }/frv/beqlr.cgs | 0
sim/testsuite/{sim => }/frv/bge.cgs | 0
sim/testsuite/{sim => }/frv/bgelr.cgs | 0
sim/testsuite/{sim => }/frv/bgt.cgs | 0
sim/testsuite/{sim => }/frv/bgtlr.cgs | 0
sim/testsuite/{sim => }/frv/bhi.cgs | 0
sim/testsuite/{sim => }/frv/bhilr.cgs | 0
sim/testsuite/{sim => }/frv/ble.cgs | 0
sim/testsuite/{sim => }/frv/blelr.cgs | 0
sim/testsuite/{sim => }/frv/bls.cgs | 0
sim/testsuite/{sim => }/frv/blslr.cgs | 0
sim/testsuite/{sim => }/frv/blt.cgs | 0
sim/testsuite/{sim => }/frv/bltlr.cgs | 0
sim/testsuite/{sim => }/frv/bn.cgs | 0
sim/testsuite/{sim => }/frv/bnc.cgs | 0
sim/testsuite/{sim => }/frv/bnclr.cgs | 0
sim/testsuite/{sim => }/frv/bne.cgs | 0
sim/testsuite/{sim => }/frv/bnelr.cgs | 0
sim/testsuite/{sim => }/frv/bnlr.cgs | 0
sim/testsuite/{sim => }/frv/bno.cgs | 0
sim/testsuite/{sim => }/frv/bnolr.cgs | 0
sim/testsuite/{sim => }/frv/bnv.cgs | 0
sim/testsuite/{sim => }/frv/bnvlr.cgs | 0
sim/testsuite/{sim => }/frv/bp.cgs | 0
sim/testsuite/{sim => }/frv/bplr.cgs | 0
sim/testsuite/{sim => }/frv/bra.cgs | 0
sim/testsuite/{sim => }/frv/bralr.cgs | 0
sim/testsuite/{sim => }/frv/branch.pcgs | 0
sim/testsuite/{sim => }/frv/break.cgs | 0
sim/testsuite/{sim => }/frv/bv.cgs | 0
sim/testsuite/{sim => }/frv/bvlr.cgs | 0
sim/testsuite/frv/cache.ms | 168 +
sim/testsuite/{sim => }/frv/cadd.cgs | 0
sim/testsuite/{sim => }/frv/caddcc.cgs | 0
sim/testsuite/{sim => }/frv/call.cgs | 0
sim/testsuite/{sim => }/frv/call.pcgs | 0
sim/testsuite/{sim => }/frv/callil.cgs | 0
sim/testsuite/{sim => }/frv/calll.cgs | 0
sim/testsuite/{sim => }/frv/cand.cgs | 0
sim/testsuite/{sim => }/frv/candcc.cgs | 0
sim/testsuite/{sim => }/frv/ccalll.cgs | 0
sim/testsuite/{sim => }/frv/cckc.cgs | 0
sim/testsuite/{sim => }/frv/cckeq.cgs | 0
sim/testsuite/{sim => }/frv/cckge.cgs | 0
sim/testsuite/{sim => }/frv/cckgt.cgs | 0
sim/testsuite/{sim => }/frv/cckhi.cgs | 0
sim/testsuite/{sim => }/frv/cckle.cgs | 0
sim/testsuite/{sim => }/frv/cckls.cgs | 0
sim/testsuite/{sim => }/frv/ccklt.cgs | 0
sim/testsuite/{sim => }/frv/cckn.cgs | 0
sim/testsuite/{sim => }/frv/ccknc.cgs | 0
sim/testsuite/{sim => }/frv/cckne.cgs | 0
sim/testsuite/{sim => }/frv/cckno.cgs | 0
sim/testsuite/{sim => }/frv/ccknv.cgs | 0
sim/testsuite/{sim => }/frv/cckp.cgs | 0
sim/testsuite/{sim => }/frv/cckra.cgs | 0
sim/testsuite/{sim => }/frv/cckv.cgs | 0
sim/testsuite/{sim => }/frv/ccmp.cgs | 0
sim/testsuite/{sim => }/frv/cfabss.cgs | 0
sim/testsuite/{sim => }/frv/cfadds.cgs | 0
sim/testsuite/{sim => }/frv/cfckeq.cgs | 0
sim/testsuite/{sim => }/frv/cfckge.cgs | 0
sim/testsuite/{sim => }/frv/cfckgt.cgs | 0
sim/testsuite/{sim => }/frv/cfckle.cgs | 0
sim/testsuite/{sim => }/frv/cfcklg.cgs | 0
sim/testsuite/{sim => }/frv/cfcklt.cgs | 0
sim/testsuite/{sim => }/frv/cfckne.cgs | 0
sim/testsuite/{sim => }/frv/cfckno.cgs | 0
sim/testsuite/{sim => }/frv/cfcko.cgs | 0
sim/testsuite/{sim => }/frv/cfckra.cgs | 0
sim/testsuite/{sim => }/frv/cfcku.cgs | 0
sim/testsuite/{sim => }/frv/cfckue.cgs | 0
sim/testsuite/{sim => }/frv/cfckug.cgs | 0
sim/testsuite/{sim => }/frv/cfckuge.cgs | 0
sim/testsuite/{sim => }/frv/cfckul.cgs | 0
sim/testsuite/{sim => }/frv/cfckule.cgs | 0
sim/testsuite/{sim => }/frv/cfcmps.cgs | 0
sim/testsuite/{sim => }/frv/cfdivs.cgs | 0
sim/testsuite/{sim => }/frv/cfitos.cgs | 0
sim/testsuite/{sim => }/frv/cfmadds.cgs | 0
sim/testsuite/{sim => }/frv/cfmas.cgs | 0
sim/testsuite/{sim => }/frv/cfmovs.cgs | 0
sim/testsuite/{sim => }/frv/cfmss.cgs | 0
sim/testsuite/{sim => }/frv/cfmsubs.cgs | 0
sim/testsuite/{sim => }/frv/cfmuls.cgs | 0
sim/testsuite/{sim => }/frv/cfnegs.cgs | 0
sim/testsuite/{sim => }/frv/cfsqrts.cgs | 0
sim/testsuite/{sim => }/frv/cfstoi.cgs | 0
sim/testsuite/{sim => }/frv/cfsubs.cgs | 0
sim/testsuite/{sim => }/frv/cjmpl.cgs | 0
sim/testsuite/{sim => }/frv/ckc.cgs | 0
sim/testsuite/{sim => }/frv/ckeq.cgs | 0
sim/testsuite/{sim => }/frv/ckge.cgs | 0
sim/testsuite/{sim => }/frv/ckgt.cgs | 0
sim/testsuite/{sim => }/frv/ckhi.cgs | 0
sim/testsuite/{sim => }/frv/ckle.cgs | 0
sim/testsuite/{sim => }/frv/ckls.cgs | 0
sim/testsuite/{sim => }/frv/cklt.cgs | 0
sim/testsuite/{sim => }/frv/ckn.cgs | 0
sim/testsuite/{sim => }/frv/cknc.cgs | 0
sim/testsuite/{sim => }/frv/ckne.cgs | 0
sim/testsuite/{sim => }/frv/ckno.cgs | 0
sim/testsuite/{sim => }/frv/cknv.cgs | 0
sim/testsuite/{sim => }/frv/ckp.cgs | 0
sim/testsuite/{sim => }/frv/ckra.cgs | 0
sim/testsuite/{sim => }/frv/ckv.cgs | 0
sim/testsuite/{sim => }/frv/cld.cgs | 0
sim/testsuite/{sim => }/frv/cldbf.cgs | 0
sim/testsuite/{sim => }/frv/cldbfu.cgs | 0
sim/testsuite/{sim => }/frv/cldd.cgs | 0
sim/testsuite/{sim => }/frv/clddf.cgs | 0
sim/testsuite/{sim => }/frv/clddfu.cgs | 0
sim/testsuite/{sim => }/frv/clddu.cgs | 0
sim/testsuite/{sim => }/frv/cldf.cgs | 0
sim/testsuite/{sim => }/frv/cldfu.cgs | 0
sim/testsuite/{sim => }/frv/cldhf.cgs | 0
sim/testsuite/{sim => }/frv/cldhfu.cgs | 0
sim/testsuite/{sim => }/frv/cldq.cgs | 0
sim/testsuite/{sim => }/frv/cldqu.cgs | 0
sim/testsuite/{sim => }/frv/cldsb.cgs | 0
sim/testsuite/{sim => }/frv/cldsbu.cgs | 0
sim/testsuite/{sim => }/frv/cldsh.cgs | 0
sim/testsuite/{sim => }/frv/cldshu.cgs | 0
sim/testsuite/{sim => }/frv/cldu.cgs | 0
sim/testsuite/{sim => }/frv/cldub.cgs | 0
sim/testsuite/{sim => }/frv/cldubu.cgs | 0
sim/testsuite/{sim => }/frv/clduh.cgs | 0
sim/testsuite/{sim => }/frv/clduhu.cgs | 0
sim/testsuite/{sim => }/frv/clrfa.cgs | 0
sim/testsuite/{sim => }/frv/clrfr.cgs | 0
sim/testsuite/{sim => }/frv/clrga.cgs | 0
sim/testsuite/{sim => }/frv/clrgr.cgs | 0
sim/testsuite/{sim => }/frv/cmaddhss.cgs | 0
sim/testsuite/{sim => }/frv/cmaddhus.cgs | 0
sim/testsuite/{sim => }/frv/cmand.cgs | 0
sim/testsuite/{sim => }/frv/cmbtoh.cgs | 0
sim/testsuite/{sim => }/frv/cmbtohe.cgs | 0
sim/testsuite/{sim => }/frv/cmcpxis.cgs | 0
sim/testsuite/{sim => }/frv/cmcpxiu.cgs | 0
sim/testsuite/{sim => }/frv/cmcpxrs.cgs | 0
sim/testsuite/{sim => }/frv/cmcpxru.cgs | 0
sim/testsuite/{sim => }/frv/cmexpdhd.cgs | 0
sim/testsuite/{sim => }/frv/cmexpdhw.cgs | 0
sim/testsuite/{sim => }/frv/cmhtob.cgs | 0
sim/testsuite/{sim => }/frv/cmmachs.cgs | 0
sim/testsuite/{sim => }/frv/cmmachu.cgs | 0
sim/testsuite/{sim => }/frv/cmmulhs.cgs | 0
sim/testsuite/{sim => }/frv/cmmulhu.cgs | 0
sim/testsuite/{sim => }/frv/cmnot.cgs | 0
sim/testsuite/{sim => }/frv/cmor.cgs | 0
sim/testsuite/{sim => }/frv/cmov.cgs | 0
sim/testsuite/{sim => }/frv/cmovfg.cgs | 0
sim/testsuite/{sim => }/frv/cmovfgd.cgs | 0
sim/testsuite/{sim => }/frv/cmovgf.cgs | 0
sim/testsuite/{sim => }/frv/cmovgfd.cgs | 0
sim/testsuite/{sim => }/frv/cmp.cgs | 0
sim/testsuite/{sim => }/frv/cmpb.cgs | 0
sim/testsuite/{sim => }/frv/cmpba.cgs | 0
sim/testsuite/{sim => }/frv/cmpi.cgs | 0
sim/testsuite/{sim => }/frv/cmqmachs.cgs | 0
sim/testsuite/{sim => }/frv/cmqmachu.cgs | 0
sim/testsuite/{sim => }/frv/cmqmulhs.cgs | 0
sim/testsuite/{sim => }/frv/cmqmulhu.cgs | 0
sim/testsuite/{sim => }/frv/cmsubhss.cgs | 0
sim/testsuite/{sim => }/frv/cmsubhus.cgs | 0
sim/testsuite/{sim => }/frv/cmxor.cgs | 0
sim/testsuite/{sim => }/frv/cnot.cgs | 0
sim/testsuite/{sim => }/frv/commitfa.cgs | 0
sim/testsuite/{sim => }/frv/commitfr.cgs | 0
sim/testsuite/{sim => }/frv/commitga.cgs | 0
sim/testsuite/{sim => }/frv/commitgr.cgs | 0
sim/testsuite/{sim => }/frv/cop1.cgs | 0
sim/testsuite/{sim => }/frv/cop2.cgs | 0
sim/testsuite/{sim => }/frv/cor.cgs | 0
sim/testsuite/{sim => }/frv/corcc.cgs | 0
sim/testsuite/{sim => }/frv/cscan.cgs | 0
sim/testsuite/{sim => }/frv/csdiv.cgs | 0
sim/testsuite/{sim => }/frv/csll.cgs | 0
sim/testsuite/{sim => }/frv/csllcc.cgs | 0
sim/testsuite/{sim => }/frv/csmul.cgs | 0
sim/testsuite/{sim => }/frv/csmulcc.cgs | 0
sim/testsuite/{sim => }/frv/csra.cgs | 0
sim/testsuite/{sim => }/frv/csracc.cgs | 0
sim/testsuite/{sim => }/frv/csrl.cgs | 0
sim/testsuite/{sim => }/frv/csrlcc.cgs | 0
sim/testsuite/{sim => }/frv/cst.cgs | 0
sim/testsuite/{sim => }/frv/cstb.cgs | 0
sim/testsuite/{sim => }/frv/cstbf.cgs | 0
sim/testsuite/{sim => }/frv/cstbfu.cgs | 0
sim/testsuite/{sim => }/frv/cstbu.cgs | 0
sim/testsuite/{sim => }/frv/cstd.cgs | 0
sim/testsuite/{sim => }/frv/cstdf.cgs | 0
sim/testsuite/{sim => }/frv/cstdfu.cgs | 0
sim/testsuite/{sim => }/frv/cstdu.cgs | 0
sim/testsuite/{sim => }/frv/cstf.cgs | 0
sim/testsuite/{sim => }/frv/cstfu.cgs | 0
sim/testsuite/{sim => }/frv/csth.cgs | 0
sim/testsuite/{sim => }/frv/csthf.cgs | 0
sim/testsuite/{sim => }/frv/csthfu.cgs | 0
sim/testsuite/{sim => }/frv/csthu.cgs | 0
sim/testsuite/{sim => }/frv/cstq.cgs | 0
sim/testsuite/{sim => }/frv/cstu.cgs | 0
sim/testsuite/{sim => }/frv/csub.cgs | 0
sim/testsuite/{sim => }/frv/csubcc.cgs | 0
sim/testsuite/{sim => }/frv/cswap.cgs | 0
sim/testsuite/{sim => }/frv/cudiv.cgs | 0
sim/testsuite/{sim => }/frv/cxor.cgs | 0
sim/testsuite/{sim => }/frv/cxorcc.cgs | 0
sim/testsuite/{sim => }/frv/dcef.cgs | 0
sim/testsuite/{sim => }/frv/dcei.cgs | 0
sim/testsuite/{sim => }/frv/dcf.cgs | 0
sim/testsuite/{sim => }/frv/dci.cgs | 0
sim/testsuite/frv/exit47.ms | 11 +
sim/testsuite/{sim => }/frv/fabsd.cgs | 0
sim/testsuite/{sim => }/frv/fabss.cgs | 0
sim/testsuite/{sim => }/frv/faddd.cgs | 0
sim/testsuite/{sim => }/frv/fadds.cgs | 0
sim/testsuite/{sim => }/frv/fbeq.cgs | 0
sim/testsuite/{sim => }/frv/fbeqlr.cgs | 0
sim/testsuite/{sim => }/frv/fbge.cgs | 0
sim/testsuite/{sim => }/frv/fbgelr.cgs | 0
sim/testsuite/{sim => }/frv/fbgt.cgs | 0
sim/testsuite/{sim => }/frv/fbgtlr.cgs | 0
sim/testsuite/{sim => }/frv/fble.cgs | 0
sim/testsuite/{sim => }/frv/fblelr.cgs | 0
sim/testsuite/{sim => }/frv/fblg.cgs | 0
sim/testsuite/{sim => }/frv/fblglr.cgs | 0
sim/testsuite/{sim => }/frv/fblt.cgs | 0
sim/testsuite/{sim => }/frv/fbltlr.cgs | 0
sim/testsuite/{sim => }/frv/fbne.cgs | 0
sim/testsuite/{sim => }/frv/fbnelr.cgs | 0
sim/testsuite/{sim => }/frv/fbno.cgs | 0
sim/testsuite/{sim => }/frv/fbnolr.cgs | 0
sim/testsuite/{sim => }/frv/fbo.cgs | 0
sim/testsuite/{sim => }/frv/fbolr.cgs | 0
sim/testsuite/{sim => }/frv/fbra.cgs | 0
sim/testsuite/{sim => }/frv/fbralr.cgs | 0
sim/testsuite/{sim => }/frv/fbu.cgs | 0
sim/testsuite/{sim => }/frv/fbue.cgs | 0
sim/testsuite/{sim => }/frv/fbuelr.cgs | 0
sim/testsuite/{sim => }/frv/fbug.cgs | 0
sim/testsuite/{sim => }/frv/fbuge.cgs | 0
sim/testsuite/{sim => }/frv/fbugelr.cgs | 0
sim/testsuite/{sim => }/frv/fbuglr.cgs | 0
sim/testsuite/{sim => }/frv/fbul.cgs | 0
sim/testsuite/{sim => }/frv/fbule.cgs | 0
sim/testsuite/{sim => }/frv/fbulelr.cgs | 0
sim/testsuite/{sim => }/frv/fbullr.cgs | 0
sim/testsuite/{sim => }/frv/fbulr.cgs | 0
sim/testsuite/{sim => }/frv/fcbeqlr.cgs | 0
sim/testsuite/{sim => }/frv/fcbgelr.cgs | 0
sim/testsuite/{sim => }/frv/fcbgtlr.cgs | 0
sim/testsuite/{sim => }/frv/fcblelr.cgs | 0
sim/testsuite/{sim => }/frv/fcblglr.cgs | 0
sim/testsuite/{sim => }/frv/fcbltlr.cgs | 0
sim/testsuite/{sim => }/frv/fcbnelr.cgs | 0
sim/testsuite/{sim => }/frv/fcbnolr.cgs | 0
sim/testsuite/{sim => }/frv/fcbolr.cgs | 0
sim/testsuite/{sim => }/frv/fcbralr.cgs | 0
sim/testsuite/{sim => }/frv/fcbuelr.cgs | 0
sim/testsuite/{sim => }/frv/fcbugelr.cgs | 0
sim/testsuite/{sim => }/frv/fcbuglr.cgs | 0
sim/testsuite/{sim => }/frv/fcbulelr.cgs | 0
sim/testsuite/{sim => }/frv/fcbullr.cgs | 0
sim/testsuite/{sim => }/frv/fcbulr.cgs | 0
sim/testsuite/{sim => }/frv/fckeq.cgs | 0
sim/testsuite/{sim => }/frv/fckge.cgs | 0
sim/testsuite/{sim => }/frv/fckgt.cgs | 0
sim/testsuite/{sim => }/frv/fckle.cgs | 0
sim/testsuite/{sim => }/frv/fcklg.cgs | 0
sim/testsuite/{sim => }/frv/fcklt.cgs | 0
sim/testsuite/{sim => }/frv/fckne.cgs | 0
sim/testsuite/{sim => }/frv/fckno.cgs | 0
sim/testsuite/{sim => }/frv/fcko.cgs | 0
sim/testsuite/{sim => }/frv/fckra.cgs | 0
sim/testsuite/{sim => }/frv/fcku.cgs | 0
sim/testsuite/{sim => }/frv/fckue.cgs | 0
sim/testsuite/{sim => }/frv/fckug.cgs | 0
sim/testsuite/{sim => }/frv/fckuge.cgs | 0
sim/testsuite/{sim => }/frv/fckul.cgs | 0
sim/testsuite/{sim => }/frv/fckule.cgs | 0
sim/testsuite/{sim => }/frv/fcmpd.cgs | 0
sim/testsuite/{sim => }/frv/fcmps.cgs | 0
sim/testsuite/{sim => }/frv/fdabss.cgs | 0
sim/testsuite/{sim => }/frv/fdadds.cgs | 0
sim/testsuite/{sim => }/frv/fdcmps.cgs | 0
sim/testsuite/{sim => }/frv/fddivs.cgs | 0
sim/testsuite/{sim => }/frv/fditos.cgs | 0
sim/testsuite/{sim => }/frv/fdivd.cgs | 0
sim/testsuite/{sim => }/frv/fdivs.cgs | 0
sim/testsuite/{sim => }/frv/fdmadds.cgs | 0
sim/testsuite/{sim => }/frv/fdmas.cgs | 0
sim/testsuite/{sim => }/frv/fdmovs.cgs | 0
sim/testsuite/{sim => }/frv/fdmss.cgs | 0
sim/testsuite/{sim => }/frv/fdmulcs.cgs | 0
sim/testsuite/{sim => }/frv/fdmuls.cgs | 0
sim/testsuite/{sim => }/frv/fdnegs.cgs | 0
sim/testsuite/{sim => }/frv/fdsads.cgs | 0
sim/testsuite/{sim => }/frv/fdsqrts.cgs | 0
sim/testsuite/{sim => }/frv/fdstoi.cgs | 0
sim/testsuite/{sim => }/frv/fdsubs.cgs | 0
sim/testsuite/{sim => }/frv/fdtoi.cgs | 0
sim/testsuite/{sim => }/frv/fitod.cgs | 0
sim/testsuite/{sim => }/frv/fitos.cgs | 0
sim/testsuite/{sim => }/frv/fmad.cgs | 0
sim/testsuite/{sim => }/frv/fmaddd.cgs | 0
sim/testsuite/{sim => }/frv/fmadds.cgs | 0
sim/testsuite/{sim => }/frv/fmas.cgs | 0
sim/testsuite/{sim => }/frv/fmovd.cgs | 0
sim/testsuite/{sim => }/frv/fmovs.cgs | 0
sim/testsuite/{sim => }/frv/fmsd.cgs | 0
sim/testsuite/{sim => }/frv/fmss.cgs | 0
sim/testsuite/{sim => }/frv/fmsubd.cgs | 0
sim/testsuite/{sim => }/frv/fmsubs.cgs | 0
sim/testsuite/{sim => }/frv/fmuld.cgs | 0
sim/testsuite/{sim => }/frv/fmuls.cgs | 0
sim/testsuite/{sim => }/frv/fnegd.cgs | 0
sim/testsuite/{sim => }/frv/fnegs.cgs | 0
sim/testsuite/{sim => }/frv/fnop.cgs | 0
sim/testsuite/{sim => }/frv/fr400/addss.cgs | 0
sim/testsuite/frv/fr400/allinsn.exp | 21 +
sim/testsuite/{sim => }/frv/fr400/csdiv.cgs | 0
sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr400/masaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr400/maveh.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mclracc.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs | 0
sim/testsuite/{sim => }/frv/fr400/movgs.cgs | 0
sim/testsuite/{sim => }/frv/fr400/movsg.cgs | 0
sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr400/scutss.cgs | 0
sim/testsuite/{sim => }/frv/fr400/sdiv.cgs | 0
sim/testsuite/{sim => }/frv/fr400/sdivi.cgs | 0
sim/testsuite/{sim => }/frv/fr400/slass.cgs | 0
sim/testsuite/{sim => }/frv/fr400/smass.cgs | 0
sim/testsuite/{sim => }/frv/fr400/smsss.cgs | 0
sim/testsuite/{sim => }/frv/fr400/smu.cgs | 0
sim/testsuite/{sim => }/frv/fr400/subss.cgs | 0
sim/testsuite/{sim => }/frv/fr400/udiv.cgs | 0
sim/testsuite/{sim => }/frv/fr400/udivi.cgs | 0
sim/testsuite/frv/fr500/allinsn.exp | 21 +
sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs | 0
sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs | 0
sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs | 0
sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs | 0
sim/testsuite/{sim => }/frv/fr500/dcpl.cgs | 0
sim/testsuite/{sim => }/frv/fr500/dcul.cgs | 0
sim/testsuite/{sim => }/frv/fr500/mclracc.cgs | 0
sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs | 0
sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs | 0
sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs | 0
sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs | 0
sim/testsuite/frv/fr550/allinsn.exp | 21 +
sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmaddhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmcpxiu.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmcpxru.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmmachs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmmachu.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmqaddhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmqaddhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmqmachs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmqmachu.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmqsubhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmqsubhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmsubhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/dcpl.cgs | 0
sim/testsuite/{sim => }/frv/fr550/dcul.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mabshs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/maddhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/maddhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/masaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mmachs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mmachu.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/msubhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/msubhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mtrap.cgs | 0
sim/testsuite/{sim => }/frv/fr550/udiv.cgs | 0
sim/testsuite/{sim => }/frv/fr550/udivi.cgs | 0
sim/testsuite/{sim => }/frv/fsqrtd.cgs | 0
sim/testsuite/{sim => }/frv/fsqrts.cgs | 0
sim/testsuite/{sim => }/frv/fstoi.cgs | 0
sim/testsuite/{sim => }/frv/fsubd.cgs | 0
sim/testsuite/{sim => }/frv/fsubs.cgs | 0
sim/testsuite/{sim => }/frv/fteq.cgs | 0
sim/testsuite/{sim => }/frv/ftge.cgs | 0
sim/testsuite/{sim => }/frv/ftgt.cgs | 0
sim/testsuite/{sim => }/frv/ftieq.cgs | 0
sim/testsuite/{sim => }/frv/ftige.cgs | 0
sim/testsuite/{sim => }/frv/ftigt.cgs | 0
sim/testsuite/{sim => }/frv/ftile.cgs | 0
sim/testsuite/{sim => }/frv/ftilg.cgs | 0
sim/testsuite/{sim => }/frv/ftilt.cgs | 0
sim/testsuite/{sim => }/frv/ftine.cgs | 0
sim/testsuite/{sim => }/frv/ftino.cgs | 0
sim/testsuite/{sim => }/frv/ftio.cgs | 0
sim/testsuite/{sim => }/frv/ftira.cgs | 0
sim/testsuite/{sim => }/frv/ftiu.cgs | 0
sim/testsuite/{sim => }/frv/ftiue.cgs | 0
sim/testsuite/{sim => }/frv/ftiug.cgs | 0
sim/testsuite/{sim => }/frv/ftiuge.cgs | 0
sim/testsuite/{sim => }/frv/ftiul.cgs | 0
sim/testsuite/{sim => }/frv/ftle.cgs | 0
sim/testsuite/{sim => }/frv/ftlg.cgs | 0
sim/testsuite/{sim => }/frv/ftlt.cgs | 0
sim/testsuite/{sim => }/frv/ftne.cgs | 0
sim/testsuite/{sim => }/frv/ftno.cgs | 0
sim/testsuite/{sim => }/frv/fto.cgs | 0
sim/testsuite/{sim => }/frv/ftra.cgs | 0
sim/testsuite/{sim => }/frv/ftu.cgs | 0
sim/testsuite/{sim => }/frv/ftue.cgs | 0
sim/testsuite/{sim => }/frv/ftug.cgs | 0
sim/testsuite/{sim => }/frv/ftuge.cgs | 0
sim/testsuite/{sim => }/frv/ftul.cgs | 0
sim/testsuite/{sim => }/frv/ftule.cgs | 0
sim/testsuite/frv/grloop.ms | 13 +
sim/testsuite/frv/hello.ms | 19 +
sim/testsuite/{sim => }/frv/icei.cgs | 0
sim/testsuite/{sim => }/frv/ici.cgs | 0
sim/testsuite/{sim => }/frv/icpl.cgs | 0
sim/testsuite/{sim => }/frv/icul.cgs | 0
sim/testsuite/frv/interrupts.exp | 21 +
.../{sim => }/frv/interrupts/Ipipe-fr400.cgs | 0
.../{sim => }/frv/interrupts/Ipipe-fr500.cgs | 0
.../{sim => }/frv/interrupts/badalign-fr550.cgs | 0
.../{sim => }/frv/interrupts/badalign.cgs | 0
.../{sim => }/frv/interrupts/compound-fr550.cgs | 0
.../{sim => }/frv/interrupts/compound.cgs | 0
.../frv/interrupts/data_store_error-fr550.cgs | 0
.../{sim => }/frv/interrupts/data_store_error.cgs | 0
.../frv/interrupts/fp_exception-fr550.cgs | 0
.../{sim => }/frv/interrupts/fp_exception.cgs | 0
sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs | 0
.../frv/interrupts/insn_access_error-fr550.cgs | 0
.../{sim => }/frv/interrupts/insn_access_error.cgs | 0
.../{sim => }/frv/interrupts/mp_exception.cgs | 0
.../frv/interrupts/privileged_instruction.cgs | 0
.../{sim => }/frv/interrupts/regalign.cgs | 0
sim/testsuite/{sim => }/frv/interrupts/reset.cgs | 0
.../{sim => }/frv/interrupts/shadow_regs.cgs | 0
sim/testsuite/{sim => }/frv/interrupts/timer.cgs | 0
sim/testsuite/{sim => }/frv/jmpil.cgs | 0
sim/testsuite/{sim => }/frv/jmpl.cgs | 0
sim/testsuite/{sim => }/frv/jmpl.pcgs | 0
sim/testsuite/{sim => }/frv/ld.cgs | 0
sim/testsuite/{sim => }/frv/ldbf.cgs | 0
sim/testsuite/{sim => }/frv/ldbfi.cgs | 0
sim/testsuite/{sim => }/frv/ldbfu.cgs | 0
sim/testsuite/{sim => }/frv/ldc.cgs | 0
sim/testsuite/{sim => }/frv/ldcu.cgs | 0
sim/testsuite/{sim => }/frv/ldd.cgs | 0
sim/testsuite/{sim => }/frv/lddc.cgs | 0
sim/testsuite/{sim => }/frv/lddcu.cgs | 0
sim/testsuite/{sim => }/frv/lddf.cgs | 0
sim/testsuite/{sim => }/frv/lddfi.cgs | 0
sim/testsuite/{sim => }/frv/lddfu.cgs | 0
sim/testsuite/{sim => }/frv/lddi.cgs | 0
sim/testsuite/{sim => }/frv/lddu.cgs | 0
sim/testsuite/{sim => }/frv/ldf.cgs | 0
sim/testsuite/{sim => }/frv/ldfi.cgs | 0
sim/testsuite/{sim => }/frv/ldfu.cgs | 0
sim/testsuite/{sim => }/frv/ldhf.cgs | 0
sim/testsuite/{sim => }/frv/ldhfi.cgs | 0
sim/testsuite/{sim => }/frv/ldhfu.cgs | 0
sim/testsuite/{sim => }/frv/ldi.cgs | 0
sim/testsuite/{sim => }/frv/ldq.cgs | 0
sim/testsuite/{sim => }/frv/ldqc.cgs | 0
sim/testsuite/{sim => }/frv/ldqcu.cgs | 0
sim/testsuite/{sim => }/frv/ldqf.cgs | 0
sim/testsuite/{sim => }/frv/ldqfi.cgs | 0
sim/testsuite/{sim => }/frv/ldqfu.cgs | 0
sim/testsuite/{sim => }/frv/ldqi.cgs | 0
sim/testsuite/{sim => }/frv/ldqu.cgs | 0
sim/testsuite/{sim => }/frv/ldsb.cgs | 0
sim/testsuite/{sim => }/frv/ldsbi.cgs | 0
sim/testsuite/{sim => }/frv/ldsbu.cgs | 0
sim/testsuite/{sim => }/frv/ldsh.cgs | 0
sim/testsuite/{sim => }/frv/ldshi.cgs | 0
sim/testsuite/{sim => }/frv/ldshu.cgs | 0
sim/testsuite/{sim => }/frv/ldu.cgs | 0
sim/testsuite/{sim => }/frv/ldub.cgs | 0
sim/testsuite/{sim => }/frv/ldubi.cgs | 0
sim/testsuite/{sim => }/frv/ldubu.cgs | 0
sim/testsuite/{sim => }/frv/lduh.cgs | 0
sim/testsuite/{sim => }/frv/lduhi.cgs | 0
sim/testsuite/{sim => }/frv/lduhu.cgs | 0
sim/testsuite/{sim => }/frv/lrbranch.pcgs | 0
sim/testsuite/{sim => }/frv/mabshs.cgs | 0
sim/testsuite/{sim => }/frv/maddhss.cgs | 0
sim/testsuite/{sim => }/frv/maddhus.cgs | 0
sim/testsuite/{sim => }/frv/mand.cgs | 0
sim/testsuite/{sim => }/frv/maveh.cgs | 0
sim/testsuite/{sim => }/frv/mbtoh.cgs | 0
sim/testsuite/{sim => }/frv/mbtohe.cgs | 0
sim/testsuite/{sim => }/frv/mclracc.cgs | 0
sim/testsuite/{sim => }/frv/mcmpsh.cgs | 0
sim/testsuite/{sim => }/frv/mcmpuh.cgs | 0
sim/testsuite/{sim => }/frv/mcop1.cgs | 0
sim/testsuite/{sim => }/frv/mcop2.cgs | 0
sim/testsuite/{sim => }/frv/mcplhi.cgs | 0
sim/testsuite/{sim => }/frv/mcpli.cgs | 0
sim/testsuite/{sim => }/frv/mcpxis.cgs | 0
sim/testsuite/{sim => }/frv/mcpxiu.cgs | 0
sim/testsuite/{sim => }/frv/mcpxrs.cgs | 0
sim/testsuite/{sim => }/frv/mcpxru.cgs | 0
sim/testsuite/{sim => }/frv/mcut.cgs | 0
sim/testsuite/{sim => }/frv/mcuti.cgs | 0
sim/testsuite/{sim => }/frv/mcutss.cgs | 0
sim/testsuite/{sim => }/frv/mcutssi.cgs | 0
sim/testsuite/{sim => }/frv/mdaddaccs.cgs | 0
sim/testsuite/{sim => }/frv/mdasaccs.cgs | 0
sim/testsuite/{sim => }/frv/mdcutssi.cgs | 0
sim/testsuite/{sim => }/frv/mdpackh.cgs | 0
sim/testsuite/{sim => }/frv/mdrotli.cgs | 0
sim/testsuite/{sim => }/frv/mdsubaccs.cgs | 0
sim/testsuite/{sim => }/frv/mdunpackh.cgs | 0
sim/testsuite/{sim => }/frv/membar.cgs | 0
sim/testsuite/{sim => }/frv/mexpdhd.cgs | 0
sim/testsuite/{sim => }/frv/mexpdhw.cgs | 0
sim/testsuite/{sim => }/frv/mhdseth.cgs | 0
sim/testsuite/{sim => }/frv/mhdsets.cgs | 0
sim/testsuite/{sim => }/frv/mhsethih.cgs | 0
sim/testsuite/{sim => }/frv/mhsethis.cgs | 0
sim/testsuite/{sim => }/frv/mhsetloh.cgs | 0
sim/testsuite/{sim => }/frv/mhsetlos.cgs | 0
sim/testsuite/{sim => }/frv/mhtob.cgs | 0
sim/testsuite/frv/misc.exp | 21 +
sim/testsuite/{sim => }/frv/mmachs.cgs | 0
sim/testsuite/{sim => }/frv/mmachu.cgs | 0
sim/testsuite/{sim => }/frv/mmrdhs.cgs | 0
sim/testsuite/{sim => }/frv/mmrdhu.cgs | 0
sim/testsuite/{sim => }/frv/mmulhs.cgs | 0
sim/testsuite/{sim => }/frv/mmulhu.cgs | 0
sim/testsuite/{sim => }/frv/mmulxhs.cgs | 0
sim/testsuite/{sim => }/frv/mmulxhu.cgs | 0
sim/testsuite/{sim => }/frv/mnop.cgs | 0
sim/testsuite/{sim => }/frv/mnot.cgs | 0
sim/testsuite/{sim => }/frv/mor.cgs | 0
sim/testsuite/{sim => }/frv/mov.cgs | 0
sim/testsuite/{sim => }/frv/movfg.cgs | 0
sim/testsuite/{sim => }/frv/movfgd.cgs | 0
sim/testsuite/{sim => }/frv/movfgq.cgs | 0
sim/testsuite/{sim => }/frv/movgf.cgs | 0
sim/testsuite/{sim => }/frv/movgfd.cgs | 0
sim/testsuite/{sim => }/frv/movgfq.cgs | 0
sim/testsuite/{sim => }/frv/movgs.cgs | 0
sim/testsuite/{sim => }/frv/movsg.cgs | 0
sim/testsuite/{sim => }/frv/mpackh.cgs | 0
sim/testsuite/{sim => }/frv/mqcpxis.cgs | 0
sim/testsuite/{sim => }/frv/mqcpxiu.cgs | 0
sim/testsuite/{sim => }/frv/mqcpxrs.cgs | 0
sim/testsuite/{sim => }/frv/mqcpxru.cgs | 0
sim/testsuite/{sim => }/frv/mqlclrhs.cgs | 0
sim/testsuite/{sim => }/frv/mqlmths.cgs | 0
sim/testsuite/{sim => }/frv/mqmachs.cgs | 0
sim/testsuite/{sim => }/frv/mqmachu.cgs | 0
sim/testsuite/{sim => }/frv/mqmacxhs.cgs | 0
sim/testsuite/{sim => }/frv/mqmulhs.cgs | 0
sim/testsuite/{sim => }/frv/mqmulhu.cgs | 0
sim/testsuite/{sim => }/frv/mqmulxhs.cgs | 0
sim/testsuite/{sim => }/frv/mqmulxhu.cgs | 0
sim/testsuite/{sim => }/frv/mqsaths.cgs | 0
sim/testsuite/{sim => }/frv/mqsllhi.cgs | 0
sim/testsuite/{sim => }/frv/mqsrahi.cgs | 0
sim/testsuite/{sim => }/frv/mqxmachs.cgs | 0
sim/testsuite/{sim => }/frv/mqxmacxhs.cgs | 0
sim/testsuite/{sim => }/frv/mrdacc.cgs | 0
sim/testsuite/{sim => }/frv/mrdaccg.cgs | 0
sim/testsuite/{sim => }/frv/mrotli.cgs | 0
sim/testsuite/{sim => }/frv/mrotri.cgs | 0
sim/testsuite/{sim => }/frv/msaths.cgs | 0
sim/testsuite/{sim => }/frv/msathu.cgs | 0
sim/testsuite/{sim => }/frv/msllhi.cgs | 0
sim/testsuite/{sim => }/frv/msrahi.cgs | 0
sim/testsuite/{sim => }/frv/msrlhi.cgs | 0
sim/testsuite/{sim => }/frv/msubhss.cgs | 0
sim/testsuite/{sim => }/frv/msubhus.cgs | 0
sim/testsuite/{sim => }/frv/mtrap.cgs | 0
sim/testsuite/{sim => }/frv/munpackh.cgs | 0
sim/testsuite/{sim => }/frv/mwcut.cgs | 0
sim/testsuite/{sim => }/frv/mwcuti.cgs | 0
sim/testsuite/{sim => }/frv/mwtacc.cgs | 0
sim/testsuite/{sim => }/frv/mwtaccg.cgs | 0
sim/testsuite/{sim => }/frv/mxor.cgs | 0
sim/testsuite/{sim => }/frv/nandcr.cgs | 0
sim/testsuite/{sim => }/frv/nandncr.cgs | 0
sim/testsuite/{sim => }/frv/nfadds.cgs | 0
sim/testsuite/{sim => }/frv/nfdadds.cgs | 0
sim/testsuite/{sim => }/frv/nfdcmps.cgs | 0
sim/testsuite/{sim => }/frv/nfddivs.cgs | 0
sim/testsuite/{sim => }/frv/nfditos.cgs | 0
sim/testsuite/{sim => }/frv/nfdivs.cgs | 0
sim/testsuite/{sim => }/frv/nfdmadds.cgs | 0
sim/testsuite/{sim => }/frv/nfdmas.cgs | 0
sim/testsuite/{sim => }/frv/nfdmss.cgs | 0
sim/testsuite/{sim => }/frv/nfdmulcs.cgs | 0
sim/testsuite/{sim => }/frv/nfdmuls.cgs | 0
sim/testsuite/{sim => }/frv/nfdsads.cgs | 0
sim/testsuite/{sim => }/frv/nfdsqrts.cgs | 0
sim/testsuite/{sim => }/frv/nfdstoi.cgs | 0
sim/testsuite/{sim => }/frv/nfdsubs.cgs | 0
sim/testsuite/{sim => }/frv/nfitos.cgs | 0
sim/testsuite/{sim => }/frv/nfmadds.cgs | 0
sim/testsuite/{sim => }/frv/nfmas.cgs | 0
sim/testsuite/{sim => }/frv/nfmss.cgs | 0
sim/testsuite/{sim => }/frv/nfmsubs.cgs | 0
sim/testsuite/{sim => }/frv/nfmuls.cgs | 0
sim/testsuite/{sim => }/frv/nfsqrts.cgs | 0
sim/testsuite/{sim => }/frv/nfstoi.cgs | 0
sim/testsuite/{sim => }/frv/nfsubs.cgs | 0
sim/testsuite/{sim => }/frv/nld.cgs | 0
sim/testsuite/{sim => }/frv/nldbf.cgs | 0
sim/testsuite/{sim => }/frv/nldbfi.cgs | 0
sim/testsuite/{sim => }/frv/nldbfu.cgs | 0
sim/testsuite/{sim => }/frv/nldd.cgs | 0
sim/testsuite/{sim => }/frv/nlddf.cgs | 0
sim/testsuite/{sim => }/frv/nlddfi.cgs | 0
sim/testsuite/{sim => }/frv/nlddfu.cgs | 0
sim/testsuite/{sim => }/frv/nlddi.cgs | 0
sim/testsuite/{sim => }/frv/nlddu.cgs | 0
sim/testsuite/{sim => }/frv/nldf.cgs | 0
sim/testsuite/{sim => }/frv/nldfi.cgs | 0
sim/testsuite/{sim => }/frv/nldfu.cgs | 0
sim/testsuite/{sim => }/frv/nldhf.cgs | 0
sim/testsuite/{sim => }/frv/nldhfi.cgs | 0
sim/testsuite/{sim => }/frv/nldhfu.cgs | 0
sim/testsuite/{sim => }/frv/nldi.cgs | 0
sim/testsuite/{sim => }/frv/nldq.cgs | 0
sim/testsuite/{sim => }/frv/nldqf.cgs | 0
sim/testsuite/{sim => }/frv/nldqfi.cgs | 0
sim/testsuite/{sim => }/frv/nldqfu.cgs | 0
sim/testsuite/{sim => }/frv/nldqu.cgs | 0
sim/testsuite/{sim => }/frv/nldsb.cgs | 0
sim/testsuite/{sim => }/frv/nldsbi.cgs | 0
sim/testsuite/{sim => }/frv/nldsbu.cgs | 0
sim/testsuite/{sim => }/frv/nldsh.cgs | 0
sim/testsuite/{sim => }/frv/nldshi.cgs | 0
sim/testsuite/{sim => }/frv/nldshu.cgs | 0
sim/testsuite/{sim => }/frv/nldu.cgs | 0
sim/testsuite/{sim => }/frv/nldub.cgs | 0
sim/testsuite/{sim => }/frv/nldubi.cgs | 0
sim/testsuite/{sim => }/frv/nldubu.cgs | 0
sim/testsuite/{sim => }/frv/nlduh.cgs | 0
sim/testsuite/{sim => }/frv/nlduhi.cgs | 0
sim/testsuite/{sim => }/frv/nlduhu.cgs | 0
sim/testsuite/{sim => }/frv/nop.cgs | 0
sim/testsuite/{sim => }/frv/norcr.cgs | 0
sim/testsuite/{sim => }/frv/norncr.cgs | 0
sim/testsuite/{sim => }/frv/not.cgs | 0
sim/testsuite/{sim => }/frv/notcr.cgs | 0
sim/testsuite/{sim => }/frv/nsdiv.cgs | 0
sim/testsuite/{sim => }/frv/nsdivi.cgs | 0
sim/testsuite/{sim => }/frv/nudiv.cgs | 0
sim/testsuite/{sim => }/frv/nudivi.cgs | 0
sim/testsuite/{sim => }/frv/or.cgs | 0
sim/testsuite/{sim => }/frv/orcc.cgs | 0
sim/testsuite/{sim => }/frv/orcr.cgs | 0
sim/testsuite/{sim => }/frv/ori.cgs | 0
sim/testsuite/{sim => }/frv/oricc.cgs | 0
sim/testsuite/{sim => }/frv/orncr.cgs | 0
sim/testsuite/frv/parallel.exp | 21 +
sim/testsuite/{sim => }/frv/ret.cgs | 0
sim/testsuite/{sim => }/frv/rett.cgs | 0
sim/testsuite/{sim => }/frv/scan.cgs | 0
sim/testsuite/{sim => }/frv/scani.cgs | 0
sim/testsuite/{sim => }/frv/sdiv.cgs | 0
sim/testsuite/{sim => }/frv/sdivi.cgs | 0
sim/testsuite/{sim => }/frv/sethi.cgs | 0
sim/testsuite/{sim => }/frv/sethilo.pcgs | 0
sim/testsuite/{sim => }/frv/setlo.cgs | 0
sim/testsuite/{sim => }/frv/setlos.cgs | 0
sim/testsuite/{sim => }/frv/sll.cgs | 0
sim/testsuite/{sim => }/frv/sllcc.cgs | 0
sim/testsuite/{sim => }/frv/slli.cgs | 0
sim/testsuite/{sim => }/frv/sllicc.cgs | 0
sim/testsuite/{sim => }/frv/smul.cgs | 0
sim/testsuite/{sim => }/frv/smulcc.cgs | 0
sim/testsuite/{sim => }/frv/smuli.cgs | 0
sim/testsuite/{sim => }/frv/smulicc.cgs | 0
sim/testsuite/{sim => }/frv/sra.cgs | 0
sim/testsuite/{sim => }/frv/sracc.cgs | 0
sim/testsuite/{sim => }/frv/srai.cgs | 0
sim/testsuite/{sim => }/frv/sraicc.cgs | 0
sim/testsuite/{sim => }/frv/srl.cgs | 0
sim/testsuite/{sim => }/frv/srlcc.cgs | 0
sim/testsuite/{sim => }/frv/srli.cgs | 0
sim/testsuite/{sim => }/frv/srlicc.cgs | 0
sim/testsuite/{sim => }/frv/st.cgs | 0
sim/testsuite/{sim => }/frv/stb.cgs | 0
sim/testsuite/{sim => }/frv/stbf.cgs | 0
sim/testsuite/{sim => }/frv/stbfi.cgs | 0
sim/testsuite/{sim => }/frv/stbfu.cgs | 0
sim/testsuite/{sim => }/frv/stbi.cgs | 0
sim/testsuite/{sim => }/frv/stbu.cgs | 0
sim/testsuite/{sim => }/frv/stc.cgs | 0
sim/testsuite/{sim => }/frv/stcu.cgs | 0
sim/testsuite/{sim => }/frv/std.cgs | 0
sim/testsuite/{sim => }/frv/std.pcgs | 0
sim/testsuite/{sim => }/frv/stdc.cgs | 0
sim/testsuite/{sim => }/frv/stdc.pcgs | 0
sim/testsuite/{sim => }/frv/stdcu.cgs | 0
sim/testsuite/{sim => }/frv/stdf.cgs | 0
sim/testsuite/{sim => }/frv/stdf.pcgs | 0
sim/testsuite/{sim => }/frv/stdfi.cgs | 0
sim/testsuite/{sim => }/frv/stdfu.cgs | 0
sim/testsuite/{sim => }/frv/stdi.cgs | 0
sim/testsuite/{sim => }/frv/stdu.cgs | 0
sim/testsuite/{sim => }/frv/stf.cgs | 0
sim/testsuite/{sim => }/frv/stfi.cgs | 0
sim/testsuite/{sim => }/frv/stfu.cgs | 0
sim/testsuite/{sim => }/frv/sth.cgs | 0
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rename sim/testsuite/{sim => }/aarch64/tbnz.s (100%)
rename sim/testsuite/{sim => }/aarch64/testutils.inc (100%)
rename sim/testsuite/{sim => }/aarch64/uzp.s (100%)
rename sim/testsuite/{sim => }/aarch64/xtl.s (100%)
rename sim/testsuite/{sim => }/aarch64/xtn.s (100%)
create mode 100644 sim/testsuite/arm/ChangeLog
rename sim/testsuite/{sim => }/arm/adc.cgs (100%)
rename sim/testsuite/{sim => }/arm/add.cgs (100%)
create mode 100644 sim/testsuite/arm/allinsn.exp
rename sim/testsuite/{sim => }/arm/and.cgs (100%)
rename sim/testsuite/{sim => }/arm/b.cgs (100%)
rename sim/testsuite/{sim => }/arm/bic.cgs (100%)
rename sim/testsuite/{sim => }/arm/bl.cgs (100%)
rename sim/testsuite/{sim => }/arm/bx.cgs (100%)
rename sim/testsuite/{sim => }/arm/cmn.cgs (100%)
rename sim/testsuite/{sim => }/arm/cmp.cgs (100%)
rename sim/testsuite/{sim => }/arm/eor.cgs (100%)
rename sim/testsuite/{sim => }/arm/hello.ms (100%)
create mode 100644 sim/testsuite/arm/iwmmxt/iwmmxt.exp
rename sim/testsuite/{sim => }/arm/iwmmxt/tbcst.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/testutils.inc (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/textrm.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/tinsr.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/tmia.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/tmiaph.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/tmiaxy.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/tmovmsk.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wacc.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wadd.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/waligni.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/walignr.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wand.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wandn.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wavg2.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wcmpeq.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wcmpgt.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wmac.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wmadd.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wmax.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wmin.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wmov.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wmul.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wor.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wpack.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wror.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wsad.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wshufh.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wsll.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wsra.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wsrl.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wsub.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wunpckeh.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wunpckel.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wunpckih.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wunpckil.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wxor.cgs (100%)
rename sim/testsuite/{sim => }/arm/iwmmxt/wzero.cgs (100%)
rename sim/testsuite/{sim => }/arm/ldm.cgs (100%)
rename sim/testsuite/{sim => }/arm/ldr.cgs (100%)
rename sim/testsuite/{sim => }/arm/ldrb.cgs (100%)
rename sim/testsuite/{sim => }/arm/ldrh.cgs (100%)
rename sim/testsuite/{sim => }/arm/ldrsb.cgs (100%)
rename sim/testsuite/{sim => }/arm/ldrsh.cgs (100%)
rename sim/testsuite/{sim => }/arm/misaligned1.ms (100%)
rename sim/testsuite/{sim => }/arm/misaligned2.ms (100%)
rename sim/testsuite/{sim => }/arm/misaligned3.ms (100%)
create mode 100644 sim/testsuite/arm/misc.exp
rename sim/testsuite/{sim => }/arm/mla.cgs (100%)
rename sim/testsuite/{sim => }/arm/mov.cgs (100%)
rename sim/testsuite/{sim => }/arm/movw-movt.ms (100%)
rename sim/testsuite/{sim => }/arm/mrs.cgs (100%)
rename sim/testsuite/{sim => }/arm/msr.cgs (100%)
rename sim/testsuite/{sim => }/arm/mul.cgs (100%)
rename sim/testsuite/{sim => }/arm/mvn.cgs (100%)
rename sim/testsuite/{sim => }/arm/orr.cgs (100%)
rename sim/testsuite/{sim => }/arm/rsb.cgs (100%)
rename sim/testsuite/{sim => }/arm/rsc.cgs (100%)
rename sim/testsuite/{sim => }/arm/sbc.cgs (100%)
rename sim/testsuite/{sim => }/arm/smlal.cgs (100%)
rename sim/testsuite/{sim => }/arm/smull.cgs (100%)
rename sim/testsuite/{sim => }/arm/stm.cgs (100%)
rename sim/testsuite/{sim => }/arm/str.cgs (100%)
rename sim/testsuite/{sim => }/arm/strb.cgs (100%)
rename sim/testsuite/{sim => }/arm/strh.cgs (100%)
rename sim/testsuite/{sim => }/arm/sub.cgs (100%)
rename sim/testsuite/{sim => }/arm/swi.cgs (100%)
rename sim/testsuite/{sim => }/arm/swp.cgs (100%)
rename sim/testsuite/{sim => }/arm/swpb.cgs (100%)
rename sim/testsuite/{sim => }/arm/teq.cgs (100%)
rename sim/testsuite/{sim => }/arm/testutils.inc (100%)
rename sim/testsuite/{sim => }/arm/thumb/adc.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/add-hd-hs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/add-hd-rs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/add-rd-hs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/add-sp.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/add.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/addi.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/addi8.cgs (100%)
create mode 100644 sim/testsuite/arm/thumb/allthumb.exp
rename sim/testsuite/{sim => }/arm/thumb/and.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/asr.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/b.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bcc.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bcs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/beq.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bge.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bgt.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bhi.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bic.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bl-hi.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bl-lo.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ble.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bls.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/blt.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bmi.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bne.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bpl.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bvc.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bvs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bx-hs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bx-rs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/cmn.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/cmp-hd-hs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/cmp-hd-rs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/cmp-rd-hs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/cmp.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/eor.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/lda-pc.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/lda-sp.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ldmia.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ldr-imm.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ldr-pc.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ldr-sprel.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ldr.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ldrb-imm.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ldrb.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ldrh-imm.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ldrh.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ldsb.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ldsh.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/lsl.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/lsr.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/mov-hd-hs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/mov-hd-rs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/mov-rd-hs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/mov.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/mul.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/mvn.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/neg.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/orr.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/pop-pc.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/pop.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/push-lr.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/push.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ror.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/sbc.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/stmia.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/str-imm.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/str-sprel.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/str.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/strb-imm.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/strb.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/strh-imm.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/strh.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/sub-sp.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/sub.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/subi.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/subi8.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/swi.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/testutils.inc (100%)
rename sim/testsuite/{sim => }/arm/thumb/tst.cgs (100%)
rename sim/testsuite/{sim => }/arm/tst.cgs (100%)
rename sim/testsuite/{sim => }/arm/umlal.cgs (100%)
rename sim/testsuite/{sim => }/arm/umull.cgs (100%)
rename sim/testsuite/{sim => }/arm/xscale/blx.cgs (100%)
rename sim/testsuite/{sim => }/arm/xscale/mia.cgs (100%)
rename sim/testsuite/{sim => }/arm/xscale/miaph.cgs (100%)
rename sim/testsuite/{sim => }/arm/xscale/miaxy.cgs (100%)
rename sim/testsuite/{sim => }/arm/xscale/mra.cgs (100%)
rename sim/testsuite/{sim => }/arm/xscale/testutils.inc (100%)
create mode 100644 sim/testsuite/arm/xscale/xscale.exp
create mode 100644 sim/testsuite/avr/ChangeLog
create mode 100644 sim/testsuite/avr/allinsn.exp
rename sim/testsuite/{sim => }/avr/pass.s (100%)
rename sim/testsuite/{sim => }/avr/testutils.inc (100%)
rename sim/testsuite/{sim => }/bfin/.gitignore (100%)
rename sim/testsuite/{sim => }/bfin/10272_small.s (100%)
rename sim/testsuite/{sim => }/bfin/10436.s (100%)
rename sim/testsuite/{sim => }/bfin/10622.s (100%)
rename sim/testsuite/{sim => }/bfin/10742.s (100%)
rename sim/testsuite/{sim => }/bfin/10799.s (100%)
rename sim/testsuite/{sim => }/bfin/11080.s (100%)
rename sim/testsuite/{sim => }/bfin/7641.s (100%)
create mode 100644 sim/testsuite/bfin/ChangeLog
rename sim/testsuite/{sim => }/bfin/PN_generator.s (100%)
rename sim/testsuite/{sim => }/bfin/a0.s (100%)
rename sim/testsuite/{sim => }/bfin/a0shift.S (100%)
rename sim/testsuite/{sim => }/bfin/a1.s (100%)
rename sim/testsuite/{sim => }/bfin/a10.s (100%)
rename sim/testsuite/{sim => }/bfin/a11.S (100%)
rename sim/testsuite/{sim => }/bfin/a12.s (100%)
rename sim/testsuite/{sim => }/bfin/a2.s (100%)
rename sim/testsuite/{sim => }/bfin/a20.S (100%)
rename sim/testsuite/{sim => }/bfin/a21.s (100%)
rename sim/testsuite/{sim => }/bfin/a22.s (100%)
rename sim/testsuite/{sim => }/bfin/a23.s (100%)
rename sim/testsuite/{sim => }/bfin/a24.s (100%)
rename sim/testsuite/{sim => }/bfin/a25.s (100%)
rename sim/testsuite/{sim => }/bfin/a26.s (100%)
rename sim/testsuite/{sim => }/bfin/a3.s (100%)
rename sim/testsuite/{sim => }/bfin/a30.s (100%)
rename sim/testsuite/{sim => }/bfin/a4.s (100%)
rename sim/testsuite/{sim => }/bfin/a5.s (100%)
rename sim/testsuite/{sim => }/bfin/a6.s (100%)
rename sim/testsuite/{sim => }/bfin/a7.s (100%)
rename sim/testsuite/{sim => }/bfin/a8.s (100%)
rename sim/testsuite/{sim => }/bfin/a9.s (100%)
rename sim/testsuite/{sim => }/bfin/abs-2.S (100%)
rename sim/testsuite/{sim => }/bfin/abs-3.S (100%)
rename sim/testsuite/{sim => }/bfin/abs-4.S (100%)
rename sim/testsuite/{sim => }/bfin/abs.S (100%)
rename sim/testsuite/{sim => }/bfin/abs_acc.s (100%)
rename sim/testsuite/{sim => }/bfin/acc-rot.s (100%)
rename sim/testsuite/{sim => }/bfin/acp5_19.s (100%)
rename sim/testsuite/{sim => }/bfin/acp5_4.s (100%)
rename sim/testsuite/{sim => }/bfin/add_imm7.s (100%)
rename sim/testsuite/{sim => }/bfin/add_shift.S (100%)
rename sim/testsuite/{sim => }/bfin/add_sub_acc.s (100%)
rename sim/testsuite/{sim => }/bfin/addsub_flags.S (100%)
rename sim/testsuite/{sim => }/bfin/algnbug1.s (100%)
rename sim/testsuite/{sim => }/bfin/algnbug2.s (100%)
create mode 100644 sim/testsuite/bfin/allinsn.exp
rename sim/testsuite/{sim => }/bfin/argc.c (100%)
rename sim/testsuite/{sim => }/bfin/ashift.s (100%)
rename sim/testsuite/{sim => }/bfin/ashift_flags.s (100%)
rename sim/testsuite/{sim => }/bfin/ashift_left.s (100%)
rename sim/testsuite/{sim => }/bfin/b0.S (100%)
rename sim/testsuite/{sim => }/bfin/b1.s (100%)
rename sim/testsuite/{sim => }/bfin/b2.S (100%)
rename sim/testsuite/{sim => }/bfin/brcc.s (100%)
rename sim/testsuite/{sim => }/bfin/brevadd.s (100%)
rename sim/testsuite/{sim => }/bfin/byteop16m.s (100%)
rename sim/testsuite/{sim => }/bfin/byteop16p.s (100%)
rename sim/testsuite/{sim => }/bfin/byteop1p.s (100%)
rename sim/testsuite/{sim => }/bfin/byteop2p.s (100%)
rename sim/testsuite/{sim => }/bfin/byteop3p.s (100%)
rename sim/testsuite/{sim => }/bfin/byteunpack.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_arith_r_sft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_neg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_toggle.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_xb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_divq.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_divs.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_log_l_sft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_log_r_sft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_shadd_1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_shadd_2.s (100%)
rename sim/testsuite/{sim => }/bfin/c_br_preg_killed_ac.s (100%)
rename sim/testsuite/{sim => }/bfin/c_br_preg_killed_ex1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_br_preg_stall_ac.s (100%)
rename sim/testsuite/{sim => }/bfin/c_br_preg_stall_ex1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_bp1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_bp2.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_bp3.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_bp4.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brf_bp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_bp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_nbp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brf_fbkwd.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brf_nbp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brt_bp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brt_nbp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_kills_dhits.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_kills_dmiss.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr_pp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_calla_ljump.s (100%)
rename sim/testsuite/{sim => }/bfin/c_calla_subr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_ac.S (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_an.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_aq.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av0.S (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av1.S (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_az.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_flag_ccmv_depend.S (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft_s1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft_sn.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_s1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_sn.S (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_a0a1.S (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr_uu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3_uu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3_uu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr_uu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_pr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_pr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_and_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_minus_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_or_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_plus_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_xor_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_pr_plus_pr_sh1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_pr_plus_pr_sh2.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_add_i7_n.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_add_i7_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_eq_i7_n.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_eq_i7_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags.S (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags_2.S (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_n.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_n.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imgebl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imltbl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dagmodik_lz_inc_dec.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imgebl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imltbl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dagmodim_lz_inc_dec.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0_pm_a1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0a1s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_abs_a.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_neg_a.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_absabs.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_negneg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_abs.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_absabs.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_alhwx.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_awx.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop1ew.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop2.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop3.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_bytepack.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteunpack.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_disalnexcpt.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_max.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_maxmax.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_min.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_minmin.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_r_lh_a0pa1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_r_negneg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd12_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd12_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd20_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd20_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd12_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd12_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd20_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd20_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rlh_rnd.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rr_lph_a1a0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm_aa.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft_x.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft_x.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_saa.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sat_aa.S (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_search.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sgn.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_iuw32.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_ih.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_iu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_t.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_tu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_ih.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_iu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_t.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_tu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_iutsh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_ih.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_iu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_iutsh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_t.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_t.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_tu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_a0alr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align16.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align24.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_l.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_r.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expexp_r.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_ln.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_lp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rn.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_pack.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_r.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmax.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmaxvmax.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_a0alr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ippm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_ipp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_ipp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ippm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_ipp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_ipp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_except_illopcode.S (100%)
rename sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S (100%)
rename sim/testsuite/{sim => }/bfin/c_except_user_mode.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_disable.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_disable_enable.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_excpt.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_loopsetup_stld.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_nested.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_nmi.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_pending.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_pending_2.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_timer.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_timer_reload.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_timer_tcount.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_timer_tscale.S (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drlo.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_ibml.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_ibml.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_ibml.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_ibml.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_pibml.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_ppmm_hbx.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_mm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_pp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_mm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_pp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dr_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_st_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_hi.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_lo.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_h_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_lohi.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_hi.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_lo.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_lohi.s (100%)
rename sim/testsuite/{sim => }/bfin/c_linkage.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_alshft_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_arith_shft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_bitclr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_bitset.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_bittgl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_bittst.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft_astat.S (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft_astat.S (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_nbittst.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_bot.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_prelc.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_top.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_overlap.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_stld.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_prelc.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_topbotcntr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_mmr_interr_ctl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_mmr_loop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mmr_loop_user_except.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mmr_ppop_illegal_adr.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mmr_ppopm_illegal_adr.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mmr_timer.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mode_supervisor.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mode_user.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mode_user_superivsor.S (100%)
rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ld_ld.s (100%)
rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_2.s (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pcpr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_clisti_interr.S (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_csync_mmr.S (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_except_rtx.S (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_excpt.S (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pcpr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_nop.s (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_raise_rt_i_n.S (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_rts.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_neg_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_sft_2_1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_shadd_1_2.s (100%)
rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp_pair.s (100%)
rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_acc_acc.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_dag_lz_dep.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_dr_acc_acc.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dep_nostall.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_dr_imlb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_dr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dep_nostall.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dep_stall.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_imlb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dep_nostall.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dep_stall.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_pr_imlb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_pr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv_ppop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ac_regmv_pushpop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_dec_raise_pushpop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex1_brcc_mv_pop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex1_call_mv_pop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex1_j_mv_pop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_brcc_mv_pop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_call_mv_pop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_j_mv_pop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex2_brcc_mp_mv_pop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex2_mmr_mvpop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex2_mmrj_mvpop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex2_raise_mmr_mvpop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex2_raise_mmrj_mvpop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_brcc_mvp.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmr_mvp.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmrj_mvp.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_wb_cs_lsmmrj_mvp.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_wb_rti_lsmmrj_mvp.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_wb_rtn_lsmmrj_mvp.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_wb_rtx_lsmmrj_mvp.S (100%)
rename sim/testsuite/{sim => }/bfin/c_ujump.s (100%)
rename sim/testsuite/{sim => }/bfin/cc-alu.S (100%)
rename sim/testsuite/{sim => }/bfin/cc-astat-bits.s (100%)
rename sim/testsuite/{sim => }/bfin/cc0.s (100%)
rename sim/testsuite/{sim => }/bfin/cc1.s (100%)
rename sim/testsuite/{sim => }/bfin/cc5.S (100%)
rename sim/testsuite/{sim => }/bfin/cec-exact-exception.S (100%)
rename sim/testsuite/{sim => }/bfin/cec-ifetch.S (100%)
rename sim/testsuite/{sim => }/bfin/cec-multi-pending.S (100%)
rename sim/testsuite/{sim => }/bfin/cec-no-snen-reti.S (100%)
rename sim/testsuite/{sim => }/bfin/cec-non-operating-env.s (100%)
rename sim/testsuite/{sim => }/bfin/cec-raise-reti.S (100%)
rename sim/testsuite/{sim => }/bfin/cec-snen-reti.S (100%)
rename sim/testsuite/{sim => }/bfin/cec-syscfg-ssstep.S (100%)
rename sim/testsuite/{sim => }/bfin/cec-system-call.S (100%)
rename sim/testsuite/{sim => }/bfin/cir.s (100%)
rename sim/testsuite/{sim => }/bfin/cir1.s (100%)
rename sim/testsuite/{sim => }/bfin/cli-sti.s (100%)
rename sim/testsuite/{sim => }/bfin/cmpacc.s (100%)
rename sim/testsuite/{sim => }/bfin/cmpdreg.S (100%)
rename sim/testsuite/{sim => }/bfin/compare.s (100%)
rename sim/testsuite/{sim => }/bfin/conv_enc_gen.s (100%)
rename sim/testsuite/{sim => }/bfin/cycles.s (100%)
rename sim/testsuite/{sim => }/bfin/d0.s (100%)
rename sim/testsuite/{sim => }/bfin/d1.s (100%)
rename sim/testsuite/{sim => }/bfin/d2.s (100%)
rename sim/testsuite/{sim => }/bfin/dbg_brprd_ntkn_src_kill.S (100%)
rename sim/testsuite/{sim => }/bfin/dbg_brtkn_nprd_src_kill.S (100%)
rename sim/testsuite/{sim => }/bfin/dbg_jmp_src_kill.S (100%)
rename sim/testsuite/{sim => }/bfin/dbg_tr_basic.S (100%)
rename sim/testsuite/{sim => }/bfin/dbg_tr_simplejp.S (100%)
rename sim/testsuite/{sim => }/bfin/dbg_tr_tbuf0.S (100%)
rename sim/testsuite/{sim => }/bfin/dbg_tr_umode.S (100%)
rename sim/testsuite/{sim => }/bfin/disalnexcpt_implicit.S (100%)
rename sim/testsuite/{sim => }/bfin/div0.s (100%)
rename sim/testsuite/{sim => }/bfin/divq.s (100%)
rename sim/testsuite/{sim => }/bfin/dotproduct.s (100%)
rename sim/testsuite/{sim => }/bfin/dotproduct2.s (100%)
rename sim/testsuite/{sim => }/bfin/double_prec_mult.s (100%)
rename sim/testsuite/{sim => }/bfin/dsp_a4.s (100%)
rename sim/testsuite/{sim => }/bfin/dsp_a7.s (100%)
rename sim/testsuite/{sim => }/bfin/dsp_a8.s (100%)
rename sim/testsuite/{sim => }/bfin/dsp_d0.s (100%)
rename sim/testsuite/{sim => }/bfin/dsp_d1.s (100%)
rename sim/testsuite/{sim => }/bfin/dsp_neg.S (100%)
rename sim/testsuite/{sim => }/bfin/dsp_s1.s (100%)
rename sim/testsuite/{sim => }/bfin/e0.s (100%)
rename sim/testsuite/{sim => }/bfin/edn_snafu.s (100%)
rename sim/testsuite/{sim => }/bfin/eu_dsp32mac_s.s (100%)
rename sim/testsuite/{sim => }/bfin/events.s (100%)
rename sim/testsuite/{sim => }/bfin/f221.s (100%)
rename sim/testsuite/{sim => }/bfin/fact.s (100%)
rename sim/testsuite/{sim => }/bfin/fir.s (100%)
rename sim/testsuite/{sim => }/bfin/fsm.s (100%)
rename sim/testsuite/{sim => }/bfin/greg2.s (100%)
rename sim/testsuite/{sim => }/bfin/hwloop-bits.S (100%)
rename sim/testsuite/{sim => }/bfin/hwloop-branch-in.s (100%)
rename sim/testsuite/{sim => }/bfin/hwloop-branch-out.s (100%)
rename sim/testsuite/{sim => }/bfin/hwloop-lt-bits.s (100%)
rename sim/testsuite/{sim => }/bfin/hwloop-nested.s (100%)
rename sim/testsuite/{sim => }/bfin/i0.s (100%)
rename sim/testsuite/{sim => }/bfin/iir.s (100%)
rename sim/testsuite/{sim => }/bfin/issue103.s (100%)
rename sim/testsuite/{sim => }/bfin/issue109.s (100%)
rename sim/testsuite/{sim => }/bfin/issue112.s (100%)
rename sim/testsuite/{sim => }/bfin/issue113.s (100%)
rename sim/testsuite/{sim => }/bfin/issue117.s (100%)
rename sim/testsuite/{sim => }/bfin/issue118.s (100%)
rename sim/testsuite/{sim => }/bfin/issue119.s (100%)
rename sim/testsuite/{sim => }/bfin/issue121.s (100%)
rename sim/testsuite/{sim => }/bfin/issue123.s (100%)
rename sim/testsuite/{sim => }/bfin/issue124.s (100%)
rename sim/testsuite/{sim => }/bfin/issue125.s (100%)
rename sim/testsuite/{sim => }/bfin/issue126.s (100%)
rename sim/testsuite/{sim => }/bfin/issue127.s (100%)
rename sim/testsuite/{sim => }/bfin/issue129.s (100%)
rename sim/testsuite/{sim => }/bfin/issue139.S (100%)
rename sim/testsuite/{sim => }/bfin/issue140.S (100%)
rename sim/testsuite/{sim => }/bfin/issue142.s (100%)
rename sim/testsuite/{sim => }/bfin/issue144.s (100%)
rename sim/testsuite/{sim => }/bfin/issue146.S (100%)
rename sim/testsuite/{sim => }/bfin/issue175.s (100%)
rename sim/testsuite/{sim => }/bfin/issue205.s (100%)
rename sim/testsuite/{sim => }/bfin/issue257.s (100%)
rename sim/testsuite/{sim => }/bfin/issue272.S (100%)
rename sim/testsuite/{sim => }/bfin/issue83.s (100%)
rename sim/testsuite/{sim => }/bfin/issue89.s (100%)
rename sim/testsuite/{sim => }/bfin/l0.s (100%)
rename sim/testsuite/{sim => }/bfin/l0shift.s (100%)
rename sim/testsuite/{sim => }/bfin/l2_loop.s (100%)
rename sim/testsuite/{sim => }/bfin/link-2.s (100%)
rename sim/testsuite/{sim => }/bfin/link.s (100%)
rename sim/testsuite/{sim => }/bfin/lmu_cplb_multiple0.S (100%)
rename sim/testsuite/{sim => }/bfin/lmu_cplb_multiple1.S (100%)
rename sim/testsuite/{sim => }/bfin/lmu_excpt_align.S (100%)
rename sim/testsuite/{sim => }/bfin/lmu_excpt_default.S (100%)
rename sim/testsuite/{sim => }/bfin/lmu_excpt_illaddr.S (100%)
rename sim/testsuite/{sim => }/bfin/lmu_excpt_prot0.S (100%)
rename sim/testsuite/{sim => }/bfin/lmu_excpt_prot1.S (100%)
rename sim/testsuite/{sim => }/bfin/load.s (100%)
rename sim/testsuite/{sim => }/bfin/logic.s (100%)
rename sim/testsuite/{sim => }/bfin/loop_snafu.s (100%)
rename sim/testsuite/{sim => }/bfin/loop_strncpy.s (100%)
rename sim/testsuite/{sim => }/bfin/lp0.s (100%)
rename sim/testsuite/{sim => }/bfin/lp1.s (100%)
rename sim/testsuite/{sim => }/bfin/lsetup.s (100%)
rename sim/testsuite/{sim => }/bfin/m0boundary.s (100%)
rename sim/testsuite/{sim => }/bfin/m1.S (100%)
rename sim/testsuite/{sim => }/bfin/m10.s (100%)
rename sim/testsuite/{sim => }/bfin/m11.s (100%)
rename sim/testsuite/{sim => }/bfin/m12.s (100%)
rename sim/testsuite/{sim => }/bfin/m13.s (100%)
rename sim/testsuite/{sim => }/bfin/m14.s (100%)
rename sim/testsuite/{sim => }/bfin/m15.s (100%)
rename sim/testsuite/{sim => }/bfin/m16.s (100%)
rename sim/testsuite/{sim => }/bfin/m17.s (100%)
rename sim/testsuite/{sim => }/bfin/m2.s (100%)
rename sim/testsuite/{sim => }/bfin/m3.s (100%)
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rename sim/testsuite/{sim => }/cr16/xord.cgs (100%)
rename sim/testsuite/{sim => }/cr16/xorw.cgs (100%)
create mode 100644 sim/testsuite/cris/ChangeLog
rename sim/testsuite/{sim => }/cris/asm/abs.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addcpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addcv32c.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addcv32m.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addcv32r.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addi.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addiv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addoc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addom.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addoq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addqpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addswpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addxc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addxm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addxr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/andc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/andm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/andq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/andr.ms (100%)
create mode 100644 sim/testsuite/cris/asm/asm.exp
rename sim/testsuite/{sim => }/cris/asm/asr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/ba.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/badarch1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bare1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bare2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bare3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bas.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bccb.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bdapc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bdapm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bdapq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bdapqpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/biap.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/boundc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/boundm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/boundmv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/boundr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/break.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/btst.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/ccr-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/ccs-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/clearfv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/clearfv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/clrjmp1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/cmpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/cmpm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/cmpq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/cmpr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/cmpxc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/cmpxm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/dflags.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/dip.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/dstep.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/fidxd.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/fidxi.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/ftagd.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/ftagi.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/halt.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io4.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io5.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io6.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io7.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io8.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io9.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/jsr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/jsrmv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/jumpmp.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/jumppv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/lapc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/lsl.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/lsr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/lz.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/mcp.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movdelsr1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movecpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movecr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movecrt10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movecrt32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movect10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movei.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movempc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movemr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movemrv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movemrv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movepcb.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movepcd.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movepcw.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moveq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moveqpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/mover.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverbpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverdpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverpcb.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverpcd.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverpcw.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverwpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movesmp.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movmp.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movmp8.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movpmv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movpmv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movppc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movpr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movprv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movprv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movrss.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movscpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movscr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movsm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movsmpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movsr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movsrpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movssr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movucpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movucr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movum.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movumpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movur.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movurpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/mstep.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/msteppc1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/msteppc2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/msteppc3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/mulv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/mulv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/mulx.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/neg.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/nonvcv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/nopv10t.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/nopv32t.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/nopv32t2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/nopv32t3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/nopv32t4.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/not.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/op3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/opterr1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/opterr2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/opterr3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/opterr4.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/opterr5.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/option1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/option2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/option3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/option4.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/orc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/orm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/orq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/orr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/pcplus.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/pid1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw11.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw12.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw13.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw14.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw15.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw16.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw17.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw4.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw5.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw6.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw7.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw8.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw9.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/ret.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/rfe.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/rfg.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/rfn.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/sbfs.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/scc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/sfe.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/subc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/subm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/subq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/subqpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/subr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/subxc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/subxm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/subxr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/swap.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tb.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/test.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/testutils.inc (100%)
rename sim/testsuite/{sim => }/cris/asm/tjmpsrv32-2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tjmpsrv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tjsrcv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tjsrcv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmemv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmemv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmulv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmulv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmvm1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmvm2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmvmrv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmvmrv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmvrmv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmvrmv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/user.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x0-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x0-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x1-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x1-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x10-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x2-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x2-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x3-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x3-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x4-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x5-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x5-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x6-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x6-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x7-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x7-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x8-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x9-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/xor.ms (100%)
rename sim/testsuite/{sim => }/cris/c/access1.c (100%)
rename sim/testsuite/{sim => }/cris/c/append1.c (100%)
rename sim/testsuite/{sim => }/cris/c/badldso1.c (100%)
rename sim/testsuite/{sim => }/cris/c/badldso2.c (100%)
rename sim/testsuite/{sim => }/cris/c/badldso3.c (100%)
create mode 100644 sim/testsuite/cris/c/c.exp
rename sim/testsuite/{sim => }/cris/c/clone1.c (100%)
rename sim/testsuite/{sim => }/cris/c/clone2.c (100%)
rename sim/testsuite/{sim => }/cris/c/clone3.c (100%)
rename sim/testsuite/{sim => }/cris/c/clone4.c (100%)
rename sim/testsuite/{sim => }/cris/c/clone5.c (100%)
rename sim/testsuite/{sim => }/cris/c/clone6.c (100%)
rename sim/testsuite/{sim => }/cris/c/ex1.c (100%)
rename sim/testsuite/{sim => }/cris/c/exitg1.c (100%)
rename sim/testsuite/{sim => }/cris/c/exitg2.c (100%)
rename sim/testsuite/{sim => }/cris/c/fcntl1.c (100%)
rename sim/testsuite/{sim => }/cris/c/fcntl2.c (100%)
rename sim/testsuite/{sim => }/cris/c/fdopen1.c (100%)
rename sim/testsuite/{sim => }/cris/c/fdopen2.c (100%)
rename sim/testsuite/{sim => }/cris/c/freopen1.c (100%)
rename sim/testsuite/{sim => }/cris/c/freopen2.c (100%)
rename sim/testsuite/{sim => }/cris/c/ftruncate1.c (100%)
rename sim/testsuite/{sim => }/cris/c/ftruncate2.c (100%)
rename sim/testsuite/{sim => }/cris/c/getcwd1.c (100%)
rename sim/testsuite/{sim => }/cris/c/gettod.c (100%)
rename sim/testsuite/{sim => }/cris/c/hello.c (100%)
rename sim/testsuite/{sim => }/cris/c/helloaout.c (100%)
rename sim/testsuite/{sim => }/cris/c/hellodyn.c (100%)
rename sim/testsuite/{sim => }/cris/c/hellodyn2.c (100%)
rename sim/testsuite/{sim => }/cris/c/hellodyn3.c (100%)
rename sim/testsuite/{sim => }/cris/c/kill1.c (100%)
rename sim/testsuite/{sim => }/cris/c/kill2.c (100%)
rename sim/testsuite/{sim => }/cris/c/kill3.c (100%)
rename sim/testsuite/{sim => }/cris/c/mapbrk.c (100%)
rename sim/testsuite/{sim => }/cris/c/mmap1.c (100%)
rename sim/testsuite/{sim => }/cris/c/mmap2.c (100%)
rename sim/testsuite/{sim => }/cris/c/mmap3.c (100%)
rename sim/testsuite/{sim => }/cris/c/mmap4.c (100%)
rename sim/testsuite/{sim => }/cris/c/mmap5.c (100%)
rename sim/testsuite/{sim => }/cris/c/mmap6.c (100%)
rename sim/testsuite/{sim => }/cris/c/mmap7.c (100%)
rename sim/testsuite/{sim => }/cris/c/mmap8.c (100%)
rename sim/testsuite/{sim => }/cris/c/mprotect1.c (100%)
rename sim/testsuite/{sim => }/cris/c/mprotect2.c (100%)
rename sim/testsuite/{sim => }/cris/c/mremap.c (100%)
rename sim/testsuite/{sim => }/cris/c/openpf1.c (100%)
rename sim/testsuite/{sim => }/cris/c/openpf2.c (100%)
rename sim/testsuite/{sim => }/cris/c/openpf3.c (100%)
rename sim/testsuite/{sim => }/cris/c/openpf4.c (100%)
rename sim/testsuite/{sim => }/cris/c/openpf5.c (100%)
rename sim/testsuite/{sim => }/cris/c/pipe1.c (100%)
rename sim/testsuite/{sim => }/cris/c/pipe2.c (100%)
rename sim/testsuite/{sim => }/cris/c/pipe3.c (100%)
rename sim/testsuite/{sim => }/cris/c/pipe4.c (100%)
rename sim/testsuite/{sim => }/cris/c/pipe5.c (100%)
rename sim/testsuite/{sim => }/cris/c/pipe6.c (100%)
rename sim/testsuite/{sim => }/cris/c/pipe7.c (100%)
rename sim/testsuite/{sim => }/cris/c/readlink1.c (100%)
rename sim/testsuite/{sim => }/cris/c/readlink10.c (100%)
rename sim/testsuite/{sim => }/cris/c/readlink11.c (100%)
rename sim/testsuite/{sim => }/cris/c/readlink2.c (100%)
rename sim/testsuite/{sim => }/cris/c/readlink3.c (100%)
rename sim/testsuite/{sim => }/cris/c/readlink4.c (100%)
rename sim/testsuite/{sim => }/cris/c/readlink5.c (100%)
rename sim/testsuite/{sim => }/cris/c/readlink6.c (100%)
rename sim/testsuite/{sim => }/cris/c/readlink7.c (100%)
rename sim/testsuite/{sim => }/cris/c/readlink8.c (100%)
rename sim/testsuite/{sim => }/cris/c/readlink9.c (100%)
rename sim/testsuite/{sim => }/cris/c/rename2.c (100%)
rename sim/testsuite/{sim => }/cris/c/rtsigprocmask1.c (100%)
rename sim/testsuite/{sim => }/cris/c/rtsigprocmask2.c (100%)
rename sim/testsuite/{sim => }/cris/c/rtsigsuspend1.c (100%)
rename sim/testsuite/{sim => }/cris/c/rtsigsuspend2.c (100%)
rename sim/testsuite/{sim => }/cris/c/sched1.c (100%)
rename sim/testsuite/{sim => }/cris/c/sched2.c (100%)
rename sim/testsuite/{sim => }/cris/c/sched3.c (100%)
rename sim/testsuite/{sim => }/cris/c/sched4.c (100%)
rename sim/testsuite/{sim => }/cris/c/sched5.c (100%)
rename sim/testsuite/{sim => }/cris/c/sched6.c (100%)
rename sim/testsuite/{sim => }/cris/c/sched7.c (100%)
rename sim/testsuite/{sim => }/cris/c/sched8.c (100%)
rename sim/testsuite/{sim => }/cris/c/sched9.c (100%)
rename sim/testsuite/{sim => }/cris/c/seek1.c (100%)
rename sim/testsuite/{sim => }/cris/c/seek2.c (100%)
rename sim/testsuite/{sim => }/cris/c/seek3.c (100%)
rename sim/testsuite/{sim => }/cris/c/seek4.c (100%)
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rename sim/testsuite/{sim => }/frv/cld.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldbf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldbfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldd.cgs (100%)
rename sim/testsuite/{sim => }/frv/clddf.cgs (100%)
rename sim/testsuite/{sim => }/frv/clddfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/clddu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldhf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldhfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldq.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldqu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldsb.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldsbu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldsh.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldshu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldub.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldubu.cgs (100%)
rename sim/testsuite/{sim => }/frv/clduh.cgs (100%)
rename sim/testsuite/{sim => }/frv/clduhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/clrfa.cgs (100%)
rename sim/testsuite/{sim => }/frv/clrfr.cgs (100%)
rename sim/testsuite/{sim => }/frv/clrga.cgs (100%)
rename sim/testsuite/{sim => }/frv/clrgr.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmaddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmaddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmand.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmbtoh.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmbtohe.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmcpxis.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmcpxiu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmcpxrs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmcpxru.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmexpdhd.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmexpdhw.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmhtob.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmmulhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmmulhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmnot.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmor.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmov.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmovfg.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmovfgd.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmovgf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmovgfd.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmp.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmpb.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmpba.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmpi.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmqmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmqmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmqmulhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmqmulhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmsubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmsubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmxor.cgs (100%)
rename sim/testsuite/{sim => }/frv/cnot.cgs (100%)
rename sim/testsuite/{sim => }/frv/commitfa.cgs (100%)
rename sim/testsuite/{sim => }/frv/commitfr.cgs (100%)
rename sim/testsuite/{sim => }/frv/commitga.cgs (100%)
rename sim/testsuite/{sim => }/frv/commitgr.cgs (100%)
rename sim/testsuite/{sim => }/frv/cop1.cgs (100%)
rename sim/testsuite/{sim => }/frv/cop2.cgs (100%)
rename sim/testsuite/{sim => }/frv/cor.cgs (100%)
rename sim/testsuite/{sim => }/frv/corcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/cscan.cgs (100%)
rename sim/testsuite/{sim => }/frv/csdiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/csll.cgs (100%)
rename sim/testsuite/{sim => }/frv/csllcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/csmul.cgs (100%)
rename sim/testsuite/{sim => }/frv/csmulcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/csra.cgs (100%)
rename sim/testsuite/{sim => }/frv/csracc.cgs (100%)
rename sim/testsuite/{sim => }/frv/csrl.cgs (100%)
rename sim/testsuite/{sim => }/frv/csrlcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/cst.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstb.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstbf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstbfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstbu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstd.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstdf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstdfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstdu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/csth.cgs (100%)
rename sim/testsuite/{sim => }/frv/csthf.cgs (100%)
rename sim/testsuite/{sim => }/frv/csthfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/csthu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstq.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstu.cgs (100%)
rename sim/testsuite/{sim => }/frv/csub.cgs (100%)
rename sim/testsuite/{sim => }/frv/csubcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/cswap.cgs (100%)
rename sim/testsuite/{sim => }/frv/cudiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/cxor.cgs (100%)
rename sim/testsuite/{sim => }/frv/cxorcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/dcef.cgs (100%)
rename sim/testsuite/{sim => }/frv/dcei.cgs (100%)
rename sim/testsuite/{sim => }/frv/dcf.cgs (100%)
rename sim/testsuite/{sim => }/frv/dci.cgs (100%)
create mode 100644 sim/testsuite/frv/exit47.ms
rename sim/testsuite/{sim => }/frv/fabsd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fabss.cgs (100%)
rename sim/testsuite/{sim => }/frv/faddd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbeq.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbeqlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbge.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbgelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbgt.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbgtlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fble.cgs (100%)
rename sim/testsuite/{sim => }/frv/fblelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fblg.cgs (100%)
rename sim/testsuite/{sim => }/frv/fblglr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fblt.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbltlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbne.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbnelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbno.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbnolr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbo.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbolr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbra.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbralr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbue.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbuelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbug.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbuge.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbugelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbuglr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbul.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbule.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbulelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbullr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbulr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbeqlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbgelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbgtlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcblelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcblglr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbltlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbnelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbnolr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbolr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbralr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbuelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbugelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbuglr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbulelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbullr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbulr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckeq.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckge.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckgt.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckle.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcklg.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcklt.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckne.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckno.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcko.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckra.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcku.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckue.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckug.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckuge.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckul.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckule.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcmpd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcmps.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdabss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdcmps.cgs (100%)
rename sim/testsuite/{sim => }/frv/fddivs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fditos.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdivd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdivs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdmadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdmas.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdmovs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdmss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdmulcs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdmuls.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdnegs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdsads.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdsqrts.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdstoi.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdtoi.cgs (100%)
rename sim/testsuite/{sim => }/frv/fitod.cgs (100%)
rename sim/testsuite/{sim => }/frv/fitos.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmad.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmaddd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmas.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmovd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmovs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmsd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmsubd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmuld.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmuls.cgs (100%)
rename sim/testsuite/{sim => }/frv/fnegd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fnegs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fnop.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/addss.cgs (100%)
create mode 100644 sim/testsuite/frv/fr400/allinsn.exp
rename sim/testsuite/{sim => }/frv/fr400/csdiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/masaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/maveh.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mclracc.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/movgs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/movsg.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/scutss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/sdiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/sdivi.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/slass.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/smass.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/smsss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/smu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/subss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/udiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/udivi.cgs (100%)
create mode 100644 sim/testsuite/frv/fr500/allinsn.exp
rename sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/dcpl.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/dcul.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/mclracc.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs (100%)
create mode 100644 sim/testsuite/frv/fr550/allinsn.exp
rename sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmaddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmcpxiu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmcpxru.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmqaddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmqaddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmqmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmqmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmqsubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmqsubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmsubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/dcpl.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/dcul.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mabshs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/maddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/maddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/masaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/msubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/msubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mtrap.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/udiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/udivi.cgs (100%)
rename sim/testsuite/{sim => }/frv/fsqrtd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fsqrts.cgs (100%)
rename sim/testsuite/{sim => }/frv/fstoi.cgs (100%)
rename sim/testsuite/{sim => }/frv/fsubd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fteq.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftge.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftgt.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftieq.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftige.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftigt.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftile.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftilg.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftilt.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftine.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftino.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftio.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftira.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftiu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftiue.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftiug.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftiuge.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftiul.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftle.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftlg.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftlt.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftne.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftno.cgs (100%)
rename sim/testsuite/{sim => }/frv/fto.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftra.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftue.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftug.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftuge.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftul.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftule.cgs (100%)
create mode 100644 sim/testsuite/frv/grloop.ms
create mode 100644 sim/testsuite/frv/hello.ms
rename sim/testsuite/{sim => }/frv/icei.cgs (100%)
rename sim/testsuite/{sim => }/frv/ici.cgs (100%)
rename sim/testsuite/{sim => }/frv/icpl.cgs (100%)
rename sim/testsuite/{sim => }/frv/icul.cgs (100%)
create mode 100644 sim/testsuite/frv/interrupts.exp
rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr400.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr500.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/badalign-fr550.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/badalign.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/compound-fr550.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/compound.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/data_store_error-fr550.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/data_store_error.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/fp_exception-fr550.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/fp_exception.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error-fr550.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/mp_exception.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/privileged_instruction.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/regalign.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/reset.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/shadow_regs.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/timer.cgs (100%)
rename sim/testsuite/{sim => }/frv/jmpil.cgs (100%)
rename sim/testsuite/{sim => }/frv/jmpl.cgs (100%)
rename sim/testsuite/{sim => }/frv/jmpl.pcgs (100%)
rename sim/testsuite/{sim => }/frv/ld.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldbf.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldbfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldbfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldc.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldcu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldd.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddc.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddcu.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddf.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddi.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldf.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldhf.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldhfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldhfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldq.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqc.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqcu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqf.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldsb.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldsbi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldsbu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldsh.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldshi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldshu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldub.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldubi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldubu.cgs (100%)
rename sim/testsuite/{sim => }/frv/lduh.cgs (100%)
rename sim/testsuite/{sim => }/frv/lduhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/lduhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/lrbranch.pcgs (100%)
rename sim/testsuite/{sim => }/frv/mabshs.cgs (100%)
rename sim/testsuite/{sim => }/frv/maddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/maddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/mand.cgs (100%)
rename sim/testsuite/{sim => }/frv/maveh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mbtoh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mbtohe.cgs (100%)
rename sim/testsuite/{sim => }/frv/mclracc.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcmpsh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcmpuh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcop1.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcop2.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcplhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcpli.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcpxis.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcpxiu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcpxrs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcpxru.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcut.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcuti.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcutss.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcutssi.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdaddaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdasaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdcutssi.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdpackh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdrotli.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdsubaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdunpackh.cgs (100%)
rename sim/testsuite/{sim => }/frv/membar.cgs (100%)
rename sim/testsuite/{sim => }/frv/mexpdhd.cgs (100%)
rename sim/testsuite/{sim => }/frv/mexpdhw.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhdseth.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhdsets.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhsethih.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhsethis.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhsetloh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhsetlos.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhtob.cgs (100%)
create mode 100644 sim/testsuite/frv/misc.exp
rename sim/testsuite/{sim => }/frv/mmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmrdhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmrdhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmulhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmulhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmulxhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmulxhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mnop.cgs (100%)
rename sim/testsuite/{sim => }/frv/mnot.cgs (100%)
rename sim/testsuite/{sim => }/frv/mor.cgs (100%)
rename sim/testsuite/{sim => }/frv/mov.cgs (100%)
rename sim/testsuite/{sim => }/frv/movfg.cgs (100%)
rename sim/testsuite/{sim => }/frv/movfgd.cgs (100%)
rename sim/testsuite/{sim => }/frv/movfgq.cgs (100%)
rename sim/testsuite/{sim => }/frv/movgf.cgs (100%)
rename sim/testsuite/{sim => }/frv/movgfd.cgs (100%)
rename sim/testsuite/{sim => }/frv/movgfq.cgs (100%)
rename sim/testsuite/{sim => }/frv/movgs.cgs (100%)
rename sim/testsuite/{sim => }/frv/movsg.cgs (100%)
rename sim/testsuite/{sim => }/frv/mpackh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqcpxis.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqcpxiu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqcpxrs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqcpxru.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqlclrhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqlmths.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmacxhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmulhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmulhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmulxhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmulxhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqsaths.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqsllhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqsrahi.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqxmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqxmacxhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mrdacc.cgs (100%)
rename sim/testsuite/{sim => }/frv/mrdaccg.cgs (100%)
rename sim/testsuite/{sim => }/frv/mrotli.cgs (100%)
rename sim/testsuite/{sim => }/frv/mrotri.cgs (100%)
rename sim/testsuite/{sim => }/frv/msaths.cgs (100%)
rename sim/testsuite/{sim => }/frv/msathu.cgs (100%)
rename sim/testsuite/{sim => }/frv/msllhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/msrahi.cgs (100%)
rename sim/testsuite/{sim => }/frv/msrlhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/msubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/msubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/mtrap.cgs (100%)
rename sim/testsuite/{sim => }/frv/munpackh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mwcut.cgs (100%)
rename sim/testsuite/{sim => }/frv/mwcuti.cgs (100%)
rename sim/testsuite/{sim => }/frv/mwtacc.cgs (100%)
rename sim/testsuite/{sim => }/frv/mwtaccg.cgs (100%)
rename sim/testsuite/{sim => }/frv/mxor.cgs (100%)
rename sim/testsuite/{sim => }/frv/nandcr.cgs (100%)
rename sim/testsuite/{sim => }/frv/nandncr.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdcmps.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfddivs.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfditos.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdivs.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdmadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdmas.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdmss.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdmulcs.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdmuls.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdsads.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdsqrts.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdstoi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfitos.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfmadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfmas.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfmss.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfmsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfmuls.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfsqrts.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfstoi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/nld.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldbf.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldbfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldbfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldd.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlddf.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlddfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlddfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlddi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlddu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldf.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldhf.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldhfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldhfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldq.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldqf.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldqfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldqfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldqu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldsb.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldsbi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldsbu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldsh.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldshi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldshu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldub.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldubi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldubu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlduh.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlduhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlduhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nop.cgs (100%)
rename sim/testsuite/{sim => }/frv/norcr.cgs (100%)
rename sim/testsuite/{sim => }/frv/norncr.cgs (100%)
rename sim/testsuite/{sim => }/frv/not.cgs (100%)
rename sim/testsuite/{sim => }/frv/notcr.cgs (100%)
rename sim/testsuite/{sim => }/frv/nsdiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/nsdivi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nudiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/nudivi.cgs (100%)
rename sim/testsuite/{sim => }/frv/or.cgs (100%)
rename sim/testsuite/{sim => }/frv/orcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/orcr.cgs (100%)
rename sim/testsuite/{sim => }/frv/ori.cgs (100%)
rename sim/testsuite/{sim => }/frv/oricc.cgs (100%)
rename sim/testsuite/{sim => }/frv/orncr.cgs (100%)
create mode 100644 sim/testsuite/frv/parallel.exp
rename sim/testsuite/{sim => }/frv/ret.cgs (100%)
rename sim/testsuite/{sim => }/frv/rett.cgs (100%)
rename sim/testsuite/{sim => }/frv/scan.cgs (100%)
rename sim/testsuite/{sim => }/frv/scani.cgs (100%)
rename sim/testsuite/{sim => }/frv/sdiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/sdivi.cgs (100%)
rename sim/testsuite/{sim => }/frv/sethi.cgs (100%)
rename sim/testsuite/{sim => }/frv/sethilo.pcgs (100%)
rename sim/testsuite/{sim => }/frv/setlo.cgs (100%)
rename sim/testsuite/{sim => }/frv/setlos.cgs (100%)
rename sim/testsuite/{sim => }/frv/sll.cgs (100%)
rename sim/testsuite/{sim => }/frv/sllcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/slli.cgs (100%)
rename sim/testsuite/{sim => }/frv/sllicc.cgs (100%)
rename sim/testsuite/{sim => }/frv/smul.cgs (100%)
rename sim/testsuite/{sim => }/frv/smulcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/smuli.cgs (100%)
rename sim/testsuite/{sim => }/frv/smulicc.cgs (100%)
rename sim/testsuite/{sim => }/frv/sra.cgs (100%)
rename sim/testsuite/{sim => }/frv/sracc.cgs (100%)
rename sim/testsuite/{sim => }/frv/srai.cgs (100%)
rename sim/testsuite/{sim => }/frv/sraicc.cgs (100%)
rename sim/testsuite/{sim => }/frv/srl.cgs (100%)
rename sim/testsuite/{sim => }/frv/srlcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/srli.cgs (100%)
rename sim/testsuite/{sim => }/frv/srlicc.cgs (100%)
rename sim/testsuite/{sim => }/frv/st.cgs (100%)
rename sim/testsuite/{sim => }/frv/stb.cgs (100%)
rename sim/testsuite/{sim => }/frv/stbf.cgs (100%)
rename sim/testsuite/{sim => }/frv/stbfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/stbfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/stbi.cgs (100%)
rename sim/testsuite/{sim => }/frv/stbu.cgs (100%)
rename sim/testsuite/{sim => }/frv/stc.cgs (100%)
rename sim/testsuite/{sim => }/frv/stcu.cgs (100%)
rename sim/testsuite/{sim => }/frv/std.cgs (100%)
rename sim/testsuite/{sim => }/frv/std.pcgs (100%)
rename sim/testsuite/{sim => }/frv/stdc.cgs (100%)
rename sim/testsuite/{sim => }/frv/stdc.pcgs (100%)
rename sim/testsuite/{sim => }/frv/stdcu.cgs (100%)
rename sim/testsuite/{sim => }/frv/stdf.cgs (100%)
rename sim/testsuite/{sim => }/frv/stdf.pcgs (100%)
rename sim/testsuite/{sim => }/frv/stdfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/stdfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/stdi.cgs (100%)
rename sim/testsuite/{sim => }/frv/stdu.cgs (100%)
rename sim/testsuite/{sim => }/frv/stf.cgs (100%)
rename sim/testsuite/{sim => }/frv/stfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/stfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/sth.cgs (100%)
rename sim/testsuite/{sim => }/frv/sthf.cgs (100%)
rename sim/testsuite/{sim => }/frv/sthfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/sthfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/sthi.cgs (100%)
rename sim/testsuite/{sim => }/frv/sthu.cgs (100%)
rename sim/testsuite/{sim => }/frv/sti.cgs (100%)
rename sim/testsuite/{sim => }/frv/stq.cgs (100%)
rename sim/testsuite/{sim => }/frv/stq.pcgs (100%)
rename sim/testsuite/{sim => }/frv/stqc.cgs (100%)
rename sim/testsuite/{sim => }/frv/stqc.pcgs (100%)
rename sim/testsuite/{sim => }/frv/stqcu.cgs (100%)
rename sim/testsuite/{sim => }/frv/stqf.cgs (100%)
rename sim/testsuite/{sim => }/frv/stqf.pcgs (100%)
rename sim/testsuite/{sim => }/frv/stqfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/stqfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/stqi.cgs (100%)
rename sim/testsuite/{sim => }/frv/stqu.cgs (100%)
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create mode 100644 sim/testsuite/m68hc11/ChangeLog
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create mode 100644 sim/testsuite/microblaze/ChangeLog
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rename sim/testsuite/{sim => }/mips/utils-mdmx.inc (100%)
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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_stm32/gnu_eabi-master-arm_eabi-coremark-O3 updated (dc209e7b -> 56fcaef2)
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discards dc209e7b 0: init: binutils-gcc-newlib: 0
new 56fcaef2 0: update: binutils-gcc-newlib: 0
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01-reset_artifacts/console.log | 241 +-
02-prepare_abe/console.log | 444 +-
03-build_abe-binutils/console.log | 11980 +-
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06-build_abe-newlib/console.log | 56865 +++
06-build_abe-stage2/console.log | 91797 ----
07-build_abe-stage2/console.log | 108699 +++++
{07-true => 08-true}/console.log | 0
.../benchmark-start.log | 0
.../console.log | 88 +-
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10-update_baseline/console.log | 7 -
11-update_baseline/console.log | 36 +
console.log | 420172 ++++++++++--------
jenkins/manifest.sh | 26 +-
results | 4 +-
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rename {09-check_regression => 10-check_regression}/console.log (60%)
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create mode 100644 11-update_baseline/console.log
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[gcc] branch releases/gcc-9 updated (d57d8bb5c52 -> 03d7b32e0eb)
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from d57d8bb5c52 Fix ICE with pathologically large frames
new 03d7b32e0eb d: Fix heap-buffer-overflow in checkModFileAlias [PR 99337]
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