[binutils-gdb] branch master updated (a71501e25ff -> 6955136728a)
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from a71501e25ff Testcase for detaching while stepping over breakpoint
new 6955136728a PR27311 again, ld.bfd (symbol from plugin): undefined reference
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Summary of changes:
bfd/ChangeLog | 6 ++++++
bfd/elflink.c | 6 +++++-
ld/ChangeLog | 5 +++++
ld/testsuite/ld-ifunc/ifunc.exp | 4 ++--
4 files changed, 18 insertions(+), 3 deletions(-)
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[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-bootstrap_debug updated (2b5af103482 -> 548b75d8222)
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-bootstrap_debug
in repository toolchain/ci/gcc.
from 2b5af103482 Add missing definition of SIZE_MAX
adds 94d5ba26f93 Daily bump.
adds b90d051ecbc testsuite: Update pr79251 ilp32 store regex
adds 972918eea87 rtl-optimization/98863 - prune RD with LIVE in STV
adds bbe6998b227 RISC-V: Fix gcc.target/riscv/attribute-18.c
adds 1b303ef6cc8 c++: Add testcase for PR84494
adds 0a3eccb6ef9 AArch64: Change canonization of smlal and smlsl in order to [...]
adds 8db8a004762 testsuite: aarch64: Add tests for vmull_high intrinsics
adds bec5dbae564 testsuite: aarch64: Add tests for vmlXl_high intrinsics
adds 6e0a231a4aa c++: alias in qualified-id in template arg [PR98570]
adds bab669f2fc6 c++: Improve sorry for __builtin_has_attribute [PR98355]
adds 7e534fb7d82 c++: Fix ICE from verify_ctor_sanity [PR98295]
adds c2f8e378d64 Verify a warning for a class with a ref-qualified assignmen [...]
adds d7bd009ab00 Fix statistic accounting for auto_vec and auto_bitmap
adds 445d6db6490 Avoid -Wstringop-truncation.
adds 90c9b2c1768 libstdc++: Update C++17 status table for <charconv>
adds 0718336a528 Reset front end trees before they make it into the middle e [...]
adds 6a2053773b8 Document various BLOCK macros.
adds 6b2034c479e aarch64: Reimplement vabdl_* intrinsics using builtins
adds 8bfdf51d859 aarch64: Reimplement vmovl_high_* intrinsics using builtins
adds 11056ab7687 tree-optimization/98499 - fix modref analysis on RVO statements
adds 33a1e511b57 libstdc++: Make deque iterator operator- usable with value- [...]
adds 11d4ec5d45c analyzer: fix false positives with *UNKNOWN_PTR [PR98918]
adds 850e5878f8f aarch64: Reimplement vrshrn* intrinsics using builtins
adds f7884fb1761 Daily bump.
adds 6a481021a65 d: Fix junk in generated symbol on powerpc64-*-* [PR98921]
adds f2f639c4a78 analyzer: add more feasibility test cases [PR93355,PR96374]
adds 8a2750086d5 analyzer: directly explore within static functions [PR93355 [...]
adds 78811355689 restore current_function_decl after re-gimplifying nested A [...]
adds 250fd9fb118 arm: Auto-vectorization for MVE: vorn
adds bc7c2b34c34 PR target/98743: Fix ICE in convert_move for RISC-V
adds eedda4e1608 testsuite: Add testcase for already fixed PR [PR97960]
adds 1592b74350a tree-vect-patterns: Don't create over widening patterns for [...]
adds 886f9f519c0 libstdc++: Fix markup for status tables in docs
adds 7bcd5e09fb3 aarch64: Relax builtin flags for integer builtins
adds 5cebc818213 aarch64: Relax some builtins to AUTO_FP
adds e8062ad4680 aarch64: Add and use FLAG_LOAD in builtins
adds 4b8a7a6e81b aarch64: Relax flags for floating-point builtins to FP wher [...]
adds 13d8be91218 aarch64: Update flags for bfloat16 builtins
adds 831ff94a882 Fortran: Check remains fixed by patch for PRs 96100/101 [PR91862].
adds 8fdfd0cfdb7 aarch64: Reimplement vqmovun_high* intrinsics using builtins
adds d14cf89b942 aarch64: Reimplement vrsqrte* intrinsics with builtins
adds 709718d4d89 c++: Member fns and deduction guide rewriting [PR98929]
adds db53dd4f784 Add test-case.
adds 5d5130ad5c3 fix memory leaks
adds 8e4a738d254 gotools: for "make check" run "go test embed/internal/embedtest"
new 548b75d8222 Daily bump.
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Summary of changes:
gcc/ChangeLog | 192 ++++++++++++
gcc/DATESTAMP | 2 +-
gcc/analyzer/ChangeLog | 22 ++
gcc/analyzer/engine.cc | 68 +---
gcc/analyzer/region-model-manager.cc | 13 +
gcc/attribs.c | 32 ++
gcc/attribs.h | 3 +
gcc/bitmap.h | 6 +-
gcc/c/ChangeLog | 6 +
gcc/c/c-decl.c | 24 ++
gcc/config/aarch64/aarch64-builtins.c | 1 +
gcc/config/aarch64/aarch64-simd-builtins.def | 261 +++++++++-------
gcc/config/aarch64/aarch64-simd.md | 164 +++++++++-
gcc/config/aarch64/aarch64.md | 3 +
gcc/config/aarch64/arm_neon.h | 344 ++++++---------------
gcc/config/aarch64/iterators.md | 5 +
gcc/config/arm/iterators.md | 3 +-
gcc/config/arm/mve.md | 23 +-
gcc/config/arm/unspecs.md | 3 -
gcc/config/i386/i386-features.c | 2 +-
gcc/cp/ChangeLog | 38 +++
gcc/cp/constexpr.c | 1 +
gcc/cp/cp-tree.h | 9 +-
gcc/cp/error.c | 3 +-
gcc/cp/module.cc | 4 +-
gcc/cp/parser.c | 2 +-
gcc/cp/pt.c | 62 ++--
gcc/cp/tree.c | 7 +-
gcc/cp/typeck.c | 9 +-
gcc/d/ChangeLog | 5 +
gcc/d/dmd/MERGE | 2 +-
gcc/d/dmd/dmangle.c | 29 +-
gcc/d/dmd/root/outbuffer.c | 31 ++
gcc/d/dmd/root/outbuffer.h | 1 +
gcc/expr.c | 1 +
gcc/gimple-loop-interchange.cc | 10 +-
gcc/gimple-loop-jam.c | 6 +-
gcc/ipa-modref.c | 18 +-
gcc/testsuite/ChangeLog | 178 +++++++++++
gcc/testsuite/g++.dg/Wclass-memaccess-6.C | 18 ++
gcc/testsuite/g++.dg/cpp0x/alias-decl-targ1.C | 9 +
gcc/testsuite/g++.dg/cpp0x/constexpr-98295.C | 11 +
gcc/testsuite/g++.dg/cpp1y/constexpr-84494.C | 11 +
.../g++.dg/cpp1z/class-deduction-decltype1.C | 11 +
gcc/testsuite/g++.dg/ext/builtin-has-attribute2.C | 8 +
gcc/testsuite/g++.dg/opt/pr98743.C | 27 ++
gcc/testsuite/g++.dg/pr98499.C | 31 ++
gcc/testsuite/g++.dg/torture/pr97960.C | 30 ++
gcc/testsuite/gcc.dg/analyzer/conditionals-3.c | 8 +-
gcc/testsuite/gcc.dg/analyzer/data-model-1.c | 4 +-
gcc/testsuite/gcc.dg/analyzer/feasibility-1.c | 26 ++
gcc/testsuite/gcc.dg/analyzer/params.c | 4 +-
.../analyzer/pr93355-localealias-feasibility-2.c | 31 ++
.../analyzer/pr93355-localealias-feasibility-3.c | 64 ++++
gcc/testsuite/gcc.dg/analyzer/pr96651-2.c | 4 +-
gcc/testsuite/gcc.dg/analyzer/pr98918.c | 22 ++
gcc/testsuite/gcc.dg/analyzer/signal-4b.c | 18 +-
gcc/testsuite/gcc.dg/analyzer/single-field.c | 8 +-
.../gcc.dg/analyzer/torture/conditionals-2.c | 8 +-
gcc/testsuite/gcc.dg/asan/nested-1.c | 24 ++
gcc/testsuite/gcc.dg/pr97172.c | 50 +++
gcc/testsuite/gcc.dg/vect/pr92205.c | 2 +-
gcc/testsuite/gcc.dg/vect/pr98848.c | 18 ++
.../smlal-smlsl-mull-optimized.c | 45 +++
.../aarch64/advsimd-intrinsics/vmlXl_high.inc | 89 ++++++
.../aarch64/advsimd-intrinsics/vmlXl_high_lane.inc | 71 +++++
.../advsimd-intrinsics/vmlXl_high_laneq.inc | 71 +++++
.../aarch64/advsimd-intrinsics/vmlXl_high_n.inc | 62 ++++
.../aarch64/advsimd-intrinsics/vmlal_high.c | 20 ++
.../aarch64/advsimd-intrinsics/vmlal_high_lane.c | 16 +
.../aarch64/advsimd-intrinsics/vmlal_high_laneq.c | 16 +
.../aarch64/advsimd-intrinsics/vmlal_high_n.c | 16 +
.../aarch64/advsimd-intrinsics/vmlsl_high.c | 24 ++
.../aarch64/advsimd-intrinsics/vmlsl_high_lane.c | 20 ++
.../aarch64/advsimd-intrinsics/vmlsl_high_laneq.c | 20 ++
.../aarch64/advsimd-intrinsics/vmlsl_high_n.c | 20 ++
.../aarch64/advsimd-intrinsics/vmull_high.c | 78 +++++
.../aarch64/advsimd-intrinsics/vmull_high_lane.c | 69 +++++
.../aarch64/advsimd-intrinsics/vmull_high_laneq.c | 69 +++++
.../aarch64/advsimd-intrinsics/vmull_high_n.c | 61 ++++
.../gcc.target/aarch64/arg-type-diagnostics-1.c | 4 +-
.../gcc.target/aarch64/narrow_high-intrinsics.c | 4 +-
.../gcc.target/aarch64/simd/vmovl_high_1.c | 32 ++
gcc/testsuite/gcc.target/arm/simd/mve-vorn.c | 38 +++
gcc/testsuite/gcc.target/i386/pr97510.c | 18 ++
gcc/testsuite/gcc.target/powerpc/pr79251.p8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr79251.p9.c | 2 +-
gcc/testsuite/gcc.target/riscv/attribute-18.c | 2 +-
gcc/testsuite/gfortran.dg/pr91862.f90 | 26 ++
gcc/tree-nested.c | 4 +-
gcc/tree-ssa-loop-im.c | 1 +
gcc/tree-vect-patterns.c | 4 +
gcc/tree-vect-stmts.c | 13 -
gcc/tree.h | 18 +-
gcc/vec.h | 6 +-
gotools/ChangeLog | 8 +
gotools/Makefile.am | 26 +-
gotools/Makefile.in | 28 +-
libiberty/ChangeLog | 5 +
libiberty/dyn-string.c | 2 +-
libstdc++-v3/ChangeLog | 24 ++
libstdc++-v3/doc/html/manual/status.html | 33 +-
libstdc++-v3/doc/xml/manual/status_cxx2011.xml | 8 +-
libstdc++-v3/doc/xml/manual/status_cxx2014.xml | 6 +-
libstdc++-v3/doc/xml/manual/status_cxx2017.xml | 25 +-
libstdc++-v3/include/bits/stl_deque.h | 18 +-
.../testsuite/23_containers/deque/70303.cc | 67 ++++
.../testsuite/23_containers/vector/70303.cc | 67 ++++
108 files changed, 2683 insertions(+), 615 deletions(-)
create mode 100644 gcc/testsuite/g++.dg/Wclass-memaccess-6.C
create mode 100644 gcc/testsuite/g++.dg/cpp0x/alias-decl-targ1.C
create mode 100644 gcc/testsuite/g++.dg/cpp0x/constexpr-98295.C
create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-84494.C
create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction-decltype1.C
create mode 100644 gcc/testsuite/g++.dg/ext/builtin-has-attribute2.C
create mode 100644 gcc/testsuite/g++.dg/opt/pr98743.C
create mode 100644 gcc/testsuite/g++.dg/pr98499.C
create mode 100644 gcc/testsuite/g++.dg/torture/pr97960.C
create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr93355-localealias-feasibility-2.c
create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr93355-localealias-feasibility-3.c
create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr98918.c
create mode 100644 gcc/testsuite/gcc.dg/asan/nested-1.c
create mode 100644 gcc/testsuite/gcc.dg/pr97172.c
create mode 100644 gcc/testsuite/gcc.dg/vect/pr98848.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/smlal-smlsl [...]
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_high.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_high_ [...]
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_high_ [...]
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlXl_high_n.inc
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_high.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_high_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_high_laneq.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlal_high_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_high.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_high_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_high_laneq.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmlsl_high_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_high.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_high_lane.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_high_laneq.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmull_high_n.c
create mode 100644 gcc/testsuite/gcc.target/aarch64/simd/vmovl_high_1.c
create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vorn.c
create mode 100644 gcc/testsuite/gcc.target/i386/pr97510.c
create mode 100644 gcc/testsuite/gfortran.dg/pr91862.f90
create mode 100644 libstdc++-v3/testsuite/23_containers/deque/70303.cc
create mode 100644 libstdc++-v3/testsuite/23_containers/vector/70303.cc
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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-bootstrap_debug updated (749c50f1 -> 83115eec)
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discards 749c50f1 0: update: gcc-2b5af1034829f69be5e91fc39c10cea267a93025: 1
new 83115eec 0: update: gcc-548b75d82229cf30052db3ad13e34115335cd9d8: 1
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01-reset_artifacts/console.log | 128 +-
02-prepare_abe/console.log | 239 +-
04-build_abe-bootstrap_debug/console.log | 70950 ++++++++++++++--------------
05-check_regression/console.log | 6 +-
06-update_baseline/console.log | 2 +-
console.log | 71357 ++++++++++++++---------------
jenkins/manifest.sh | 10 +-
7 files changed, 71284 insertions(+), 71408 deletions(-)
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[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-Os-vs-Os_LTO updated (21c3f4b536 -> d2d12c7a98)
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-Os-vs-Os_LTO
in repository toolchain/ci/glibc.
from 21c3f4b536 Sync FDL from https://www.gnu.org/licenses/fdl-1.3.texi
adds fee3b889d8 Move generic nan-pseudo-number.h to ldbl-96
adds c2a150d089 posix: Sync regex code with gnulib
adds 4883360415 posix: Sync glob code with gnulib
adds 11b2858bd1 Sync intprops.h with gnulib
adds 9c774ad764 Sync flexmember.h with gnulib
adds 252864544a posix: Sync fnmatch with gnulib
adds 8cc1e39a36 Drop nan-pseudo-number.h usage from tests
adds f5a6f846b0 nptl: Remove set*id, set*gid files which are not built
adds cd6274089f aarch64: fix stack missing after sp is updated
adds 3ec5d83d2a x86-64: Avoid rep movsb with short distance [BZ #27130]
adds b47b07c92d hurd: Fix mmap(!MAP_FIXED) on bogus address
adds 6ea5b57afa x86: Check IFUNC definition in unrelocated executable [BZ #20019]
adds c50c65a8bf nptl: Fix comment typo in pthread_cond_wait.c
adds f5082c7010 aarch64: push the set of rules before falling into slow path
adds 6cc992412c alpha: Provide wait4 for static library [BZ #27150]
adds ef8c78a6c6 Import idx.h from gnulib
adds 47f4316095 Import filename.h from gnulib
adds 448a256359 malloc: Add scratch_buffer_dupfree
adds c6e0b0b5b0 stdlib: Sync canonicalize with gnulib [BZ #10635] [BZ #26592 [...]
adds ecdb06cdf2 support: Add support_small_thread_stack_size
adds 3016596a81 Add SEGV_MTEAERR and SEGV_MTESERR from Linux 5.10.
adds caa884dda7 Remove dbl-64/wordsize-64
adds 9e97f239ea Remove dbl-64/wordsize-64 (part 2)
adds ecce11aa07 x86: Support GNU_PROPERTY_X86_ISA_1_V[234] marker [BZ #26717]
adds 18b640c570 Update NEWS for CVE-2019-25013.
adds 2f056e8a5d aarch64: define PI_STATIC_AND_HIDDEN
adds eeaa19f75e mntent: Use __putc_unlocked instead of fputc_unlocked
adds 1b5c9dfeb2 ARC: Regenerate ulps
adds c6e2ca2c3f POSIX locale: Fix typo in comment
adds a7e9dbb774 Add xchdir to libsupport.
adds 7a72265436 Add xfchmod to libsupport
adds 2cd361b511 posix: Correct attribute access mode on readlinkat [BZ #27024].
adds c31b1f5231 riscv: support GNU indirect function
adds 313bfd505e riscv: Initialize $gp before resolving the IRELATIVE relocation
adds 1c426b1d59 Update STATX_ATTR_DAX value from Linux 5.10.
adds 7b9c3260bc support: Add xchmod wrapper
adds 42dda89dcb posix: Fix return value of system if shell can not be execut [...]
adds 4dddd7e9cb posix: Sync tempname with gnulib [BZ #26648]
adds bf7db6d369 math: Add BZ#18980 fix back on dbl-64 cosh
adds 87d583c6e8 install: Replace scripts/output-format.sed with objdump -f [ [...]
adds 0400f92833 Makerules: Do not require startup files for format.lds probe object
adds f430293d84 posix: consume less entropy on tempname
adds 2ef23b5205 x86: Set header.feature_1 in TCB for always-on CET [BZ #27177]
adds 86a4d3fa7d elf: work around a gcc bug in elf_get_dynamic_info
adds efbbd9c33a ldconfig/x86: Store ISA level in cache and aux cache
adds cf12900645 Use the right argument code in unnormal tests
adds 7137d682eb ifuncmain6pie: Remove the circular IFUNC dependency [BZ #20019]
adds d18f59bf92 Fix x86 build with --enable-tunable=no
adds 2d651eb926 x86: Move x86 processor cache info to cpu_features
adds cc528f9a7e math/test-tgmath2: Fix fabs failure when no long double
adds 86f65dffc2 ld.so: Add --list-tunables to print tunable values
adds 96f17e6e63 ARC: nofpu: Regenerate ulps
adds f678099de9 Update hppa libm-test-ulps
adds a031b3abad Update powerpc-nofpu libm-test-ulps.
adds 07169fcac7 Update arm libm-test-ulps.
adds 202586f73e Update MIPS libm-test-ulps.
adds 0887fff0b0 Hurd: Add rtld-strncpy-c.c
adds 0ec583d926 libmvec: Add extra-test-objs to test-extras
adds cabc8a2916 elf: Avoid RELATIVE relocation for _dl_sysinfo
adds 22b79ed7f4 Use <startup.h> in __libc_init_secure
adds 1006250ea2 posix: Fix regex_internal.h on bootstrap
adds 961d7cff51 stdlib: Add testcase for BZ #26241
adds d7ee6bd8c2 posix: Fix fnmatch.c on bootstrap
adds ff6d62e9ed <sys/platform/x86.h>: Remove the C preprocessor magic
adds 058308066c elf: Make the tunable struct definition internal only
adds bfe04789a8 elf: Avoid RELATIVE relocs in __tunables_init
adds 374cef32ac configure: Check for static PIE support
adds 04af1eb313 csu: Avoid weak ref for __ehdr_start in static PIE
adds 47618209d0 Use hidden visibility for early static PIE code
adds 86d439b06f csu: Move static pie self relocation later [BZ #27072]
adds 2682695e5c Make libc symbols hidden in static PIE
adds 28f2ce2772 aarch64: revert memcpy optimze for kunpeng to avoid performa [...]
adds 46c1c765d1 Revert "linux: Move {f}xstat{at} to compat symbols" for stat [...]
adds 7a5ab88e21 x86: Check ifunc resolver with CPU_FEATURE_USABLE [BZ #27072]
adds 527c89cd32 powerpc64: Select POWER9 machine for the scv instruction
adds f543259500 x86-64: Update tst-glibc-hwcaps-2.c for x86-64 baseline
adds 5f478eb0fb x86: Properly match CPU features in /proc/cpuinfo [BZ #27222]
adds 42d6270439 linux: mips: Fix getdents64 fallback on mips64-n32
adds 56ef6ab0cd manual: Correct argument order in mount examples [BZ #27207]
adds fcfa4bb48d Update C-SKY libm-test-ulps
adds 31f6488722 Fix misplaced const
adds c3c4a25e65 aarch64: Move and update the definition of MTE_ENABLED
adds ad47748992 Update INSTALL with package versions that are known to work
adds 04c6a8073d aarch64: Fix the list of tested IFUNC variants [BZ #26818]
adds 3725ee39db benchtests: Do not build bench-timing-type with MODULE_NAME=libc
adds df359a25ba Revert "Make libc symbols hidden in static PIE" [BZ #27237]
adds 7d88c6142c gconv: Fix assertion failure in ISO-2022-JP-3 module (bug 27256)
adds 01cdcf783a elf: Limit tst-prelink-cmp target archs
adds 429029a73e nsswitch: do not reload if "/" changes
adds 757a14b5ac Fix nss/tst-reload2 for systems without PATH_MAX
adds 5ee506ed35 powerpc64: Workaround sigtramp vdso return call
adds d04d64804d Update alpha libm-test-ulps
adds 341063c3b1 Update sparc libm-test-ulps
adds c177f6610c ia64: Fix brk call on statup
adds a7b21a7830 sh: Update libm-tests-ulps
adds 4a3f20b33a Update ia64 libm-test-ulps
adds 4e04691107 Update libc.pot for 2.33 release
adds 6032ae6514 Update translations
adds 04dff6fc0d x86: Properly set usable CET feature bits [BZ #26625]
adds 570bb42376 NEWS: Add entry for glibc-hwcaps and deprecate legacy hwcaps
adds d7f4f3f5fb NEWS: Mention CVE-2021-3326 (iconv assertion with ISO-20220-JP-3)
adds a50a080f6b elf: Fix tests that rely on ld.so.cache for cross-compiling
adds 934c48a05b NEWS: Fix typo in CVE-2021-3326 entry
adds 730ad885ef Update translations
adds 5e25920fb2 Update NEWS with bugs
adds 9826b03b74 Prepare for glibc 2.33 release
adds 2edf8f3d75 Open master branch for glibc 2.34 development
adds 02d393f248 elf: Replace a --defsym trick with an object file to be comp [...]
adds d5c8f98c5e tst-mallinfo2.c: Remove useless trailing semicolon for macro
adds 36231bee7a hurd TIOCFLUSH: Cope BSD 4.1 semantic
adds 6c57d32048 sysconf: Add _SC_MINSIGSTKSZ/_SC_SIGSTKSZ [BZ #20305]
adds fd4405747c hurd TIOCFLUSH: fix fixing argument
adds f9be44c7e6 libSegFault: Fix printing signal number [BZ #27249]
adds 57fb02b2cf Move _SC_MINSIGSTKSZ/_SC_SIGSTKSZ entry in NEWS
adds 0ca21427d9 Add MS_NOSYMFOLLOW from Linux 5.10 to <sys/mount.h>.
adds caa60b79f8 Fix version.h for glibc 2.34 development
adds 6e02b3e932 x86: Adding an upper bound for Enhanced REP MOVSB.
adds 9132010785 linux: Remove shmmax check from tst-sysvshm-linux
adds d2d12c7a98 tst-rtld-list-tunables.sh: Unset glibc tunables
No new revisions were added by this update.
Summary of changes:
ChangeLog.old/ChangeLog.22 | 12846 +++++++++++++++++++
INSTALL | 26 +-
Makerules | 16 +-
NEWS | 181 +-
benchtests/Makefile | 14 +-
benchtests/strcoll-inputs/filelist#en_US.UTF-8 | 1 -
bits/confname.h | 8 +-
.../linux/aarch64/libc-start.c => bits/sigstksz.h | 15 +-
config.h.in | 6 +
config.make.in | 1 -
configure | 32 +-
configure.ac | 15 +-
csu/libc-start.c | 15 +-
debug/segfault.c | 2 +-
elf/Makefile | 35 +-
elf/cache.c | 39 +-
elf/dl-cache.c | 4 +
elf/dl-main.h | 2 +-
elf/dl-reloc-static-pie.c | 2 +
elf/dl-support.c | 21 +-
elf/dl-sysdep.c | 9 +
elf/dl-tunable-types.h | 42 +-
elf/dl-tunables.c | 49 +-
elf/dl-tunables.h | 37 +-
elf/dl-usage.c | 7 +-
elf/elf.h | 35 +-
elf/enbl-secure.c | 10 +-
elf/get-dynamic-info.h | 41 +-
elf/ifuncmain6pie.c | 14 +-
elf/ifuncmod6.c | 8 +-
elf/ldconfig.c | 18 +-
elf/readelflib.c | 81 +-
elf/readlib.c | 7 +-
elf/rtld.c | 19 +
elf/tst-glibc-hwcaps-2-cache.c | 45 +
.../etc/ld.so.conf | 0
.../postclean.req | 0
elf/tst-glibc-hwcaps-2-cache.script | 8 +
.../ldconfig.run} | 0
.../ldconfig.run} | 0
.../multiarch/init-arch.h => elf/tst-prelink-cmp.c | 38 +-
elf/tst-prelink.exp | 1 -
elf/tst-rtld-list-tunables.exp | 14 +
elf/tst-rtld-list-tunables.sh | 45 +
iconvdata/Makefile | 4 +-
iconvdata/bug-iconv14.c | 127 +
iconvdata/iso-2022-jp-3.c | 67 +-
include/bits/sigstack.h | 5 +
include/bits/sigstksz.h | 7 +
include/features.h | 13 +-
include/filename.h | 112 +
include/idx.h | 114 +
include/intprops.h | 70 +-
include/scratch_buffer.h | 16 +
include/shlib-compat.h | 23 +-
io/bits/statx-generic.h | 2 +-
libc-abis | 1 +
localedata/locales/POSIX | 2 +-
malloc/Makefile | 1 +
malloc/Versions | 1 +
.../scratch_buffer_dupfree.c | 31 +-
malloc/tst-mallinfo2.c | 2 +-
malloc/tst-scratch_buffer.c | 26 +-
manual/conf.texi | 21 +
manual/creature.texi | 6 +
manual/install.texi | 24 +-
manual/platform.texi | 7 +-
manual/sysinfo.texi | 4 +-
manual/tunables.texi | 38 +
math/libm-test-driver.c | 17 +-
math/libm-test-fpclassify.inc | 18 +-
math/libm-test-isinf.inc | 18 +-
math/libm-test-isnan.inc | 18 +-
math/libm-test-issignaling.inc | 18 +-
math/test-tgmath2.c | 4 +-
misc/mntent_r.c | 12 +-
misc/sbrk.c | 4 +
nptl/Makefile | 4 -
nptl/pthread_cond_wait.c | 2 +-
nptl/pthread_setegid.c | 3 -
nptl/pthread_seteuid.c | 3 -
nptl/pthread_setgid.c | 3 -
nptl/pthread_setregid.c | 3 -
nptl/pthread_setresgid.c | 3 -
nptl/pthread_setresuid.c | 3 -
nptl/pthread_setreuid.c | 3 -
nptl/pthread_setuid.c | 3 -
nss/Makefile | 2 +-
nss/nss_database.c | 27 +
nss/nss_module.c | 13 +
nss/nss_module.h | 3 +
nss/tst-reload2.c | 130 +
nss/tst-reload2.root/etc/nsswitch.conf | 2 +
nss/tst-reload2.root/subdir/etc/group | 1 +
nss/tst-reload2.root/subdir/etc/nsswitch.conf | 2 +
nss/tst-reload2.root/tst-reload2.script | 3 +
po/be.po | 306 +-
po/bg.po | 680 +-
po/ca.po | 664 +-
po/cs.po | 680 +-
po/da.po | 610 +-
po/de.po | 680 +-
po/el.po | 376 +-
po/eo.po | 689 +-
po/es.po | 658 +-
po/fi.po | 606 +-
po/fr.po | 680 +-
po/gl.po | 532 +-
po/hr.po | 803 +-
po/hu.po | 420 +-
po/ia.po | 222 +-
po/id.po | 610 +-
po/it.po | 614 +-
po/ja.po | 614 +-
po/ko.po | 680 +-
po/libc.pot | 744 +-
po/lt.po | 410 +-
po/nb.po | 352 +-
po/nl.po | 680 +-
po/pl.po | 680 +-
po/pt.po | 4822 ++++++-
po/pt_BR.po | 694 +-
po/ru.po | 680 +-
po/rw.po | 14 +-
po/sk.po | 526 +-
po/sl.po | 340 +-
po/{pt_BR.po => sr.po} | 3751 +++---
po/sv.po | 680 +-
po/tr.po | 680 +-
po/uk.po | 680 +-
po/vi.po | 664 +-
po/zh_CN.po | 664 +-
po/zh_TW.po | 680 +-
posix/flexmember.h | 25 +-
posix/fnmatch.c | 548 +-
posix/fnmatch_loop.c | 1977 ++-
posix/glob.c | 1748 +--
posix/glob_pattern_p.c | 2 +-
posix/globfree.c | 2 +-
posix/regcomp.c | 2 +-
posix/regex.h | 17 +-
posix/regex_internal.c | 19 +-
posix/regex_internal.h | 20 +-
posix/sysconf.c | 3 +
posix/unistd.h | 2 +-
scripts/gen-tunables.awk | 16 +-
scripts/output-format.sed | 35 -
signal/Makefile | 5 +-
signal/signal.h | 1 +
signal/tst-minsigstksz-5.c | 84 +
stdlib/Makefile | 3 +-
stdlib/canonicalize.c | 546 +-
stdlib/test-bz22786.c | 11 +-
stdlib/tst-canon-bz26341.c | 101 +
stdlib/tst-system.c | 17 +
support/Makefile | 3 +
support/support_set_small_thread_stack_size.c | 12 +-
support/test-container.c | 26 +
.../linux/aarch64/libc-start.c => support/xchdir.c | 22 +-
.../linux/aarch64/libc-start.c => support/xchmod.c | 22 +-
.../aarch64/libc-start.c => support/xfchmod.c | 22 +-
support/xthread.h | 2 +
support/xunistd.h | 3 +
sysdeps/aarch64/Implies | 1 -
sysdeps/aarch64/configure | 9 +
sysdeps/aarch64/configure.ac | 7 +
sysdeps/aarch64/dl-tlsdesc.S | 4 +-
sysdeps/aarch64/multiarch/ifunc-impl-list.c | 8 +-
sysdeps/aarch64/multiarch/init-arch.h | 13 +-
sysdeps/aarch64/multiarch/memcpy.c | 2 +-
sysdeps/aarch64/multiarch/strlen.c | 11 +-
sysdeps/alpha/Implies | 1 -
sysdeps/alpha/fpu/libm-test-ulps | 23 +-
sysdeps/arc/fpu/libm-test-ulps | 8 +-
sysdeps/arc/nofpu/libm-test-ulps | 11 +-
sysdeps/arm/libm-test-ulps | 23 +-
sysdeps/csky/fpu/libm-test-ulps | 82 +-
sysdeps/csky/nofpu/libm-test-ulps | 33 +-
sysdeps/generic/dl-cache.h | 16 +-
.../libc-start.c => generic/dl-isa-level.h} | 21 +-
.../hurd/fxstat64.c => generic/elf-read-prop.h} | 30 +-
sysdeps/generic/ldconfig.h | 22 +-
sysdeps/generic/ldsodefs.h | 3 +
sysdeps/generic/startup.h | 26 +
sysdeps/hppa/fpu/libm-test-ulps | 23 +-
sysdeps/i386/configure | 3 +
sysdeps/i386/configure.ac | 3 +
sysdeps/i386/dl-machine.h | 16 +-
sysdeps/ia64/fpu/libm-test-ulps | 4 +-
sysdeps/ieee754/dbl-64/e_acosh.c | 50 +-
sysdeps/ieee754/dbl-64/e_cosh.c | 76 +-
sysdeps/ieee754/dbl-64/e_fmod.c | 202 +-
sysdeps/ieee754/dbl-64/e_log10.c | 42 +-
sysdeps/ieee754/dbl-64/s_frexp.c | 81 +-
sysdeps/ieee754/dbl-64/s_getpayload.c | 15 +-
sysdeps/ieee754/dbl-64/s_issignaling.c | 14 +-
sysdeps/ieee754/dbl-64/s_llround.c | 49 +-
sysdeps/ieee754/dbl-64/s_lround.c | 57 +-
sysdeps/ieee754/dbl-64/s_modf.c | 80 +-
sysdeps/ieee754/dbl-64/s_remquo.c | 43 +-
sysdeps/ieee754/dbl-64/s_roundeven.c | 79 +-
sysdeps/ieee754/dbl-64/s_scalbln.c | 63 +-
sysdeps/ieee754/dbl-64/s_scalbn.c | 63 +-
sysdeps/ieee754/dbl-64/s_setpayload_main.c | 42 +-
sysdeps/ieee754/dbl-64/s_totalorder.c | 32 +-
sysdeps/ieee754/dbl-64/s_totalordermag.c | 24 +-
sysdeps/ieee754/dbl-64/wordsize-64/e_acosh.c | 68 -
sysdeps/ieee754/dbl-64/wordsize-64/e_cosh.c | 85 -
sysdeps/ieee754/dbl-64/wordsize-64/e_fmod.c | 106 -
sysdeps/ieee754/dbl-64/wordsize-64/e_log10.c | 87 -
sysdeps/ieee754/dbl-64/wordsize-64/s_frexp.c | 66 -
sysdeps/ieee754/dbl-64/wordsize-64/s_getpayload.c | 35 -
sysdeps/ieee754/dbl-64/wordsize-64/s_issignaling.c | 43 -
sysdeps/ieee754/dbl-64/wordsize-64/s_llround.c | 75 -
sysdeps/ieee754/dbl-64/wordsize-64/s_lround.c | 86 -
sysdeps/ieee754/dbl-64/wordsize-64/s_modf.c | 65 -
sysdeps/ieee754/dbl-64/wordsize-64/s_remquo.c | 111 -
sysdeps/ieee754/dbl-64/wordsize-64/s_roundeven.c | 71 -
sysdeps/ieee754/dbl-64/wordsize-64/s_scalbln.c | 60 -
sysdeps/ieee754/dbl-64/wordsize-64/s_scalbn.c | 60 -
.../ieee754/dbl-64/wordsize-64/s_setpayload_main.c | 54 -
sysdeps/ieee754/dbl-64/wordsize-64/s_totalorder.c | 76 -
.../ieee754/dbl-64/wordsize-64/s_totalordermag.c | 73 -
.../ldbl-96}/nan-pseudo-number.h | 4 +-
sysdeps/mach/hurd/fxstat.c | 4 +-
sysdeps/mach/hurd/fxstat64.c | 2 +-
sysdeps/mach/hurd/fxstatat.c | 3 +-
sysdeps/mach/hurd/fxstatat64.c | 3 +-
.../mach/hurd/i386/i686/multiarch/rtld-strncpy-c.c | 1 +
sysdeps/mach/hurd/i386/ld.abilist | 1 -
sysdeps/mach/hurd/i386/libc.abilist | 1 +
sysdeps/mach/hurd/ioctl.c | 4 +
sysdeps/mach/hurd/lxstat.c | 2 +-
sysdeps/mach/hurd/lxstat64.c | 3 +-
sysdeps/mach/hurd/mmap.c | 9 +-
sysdeps/mach/hurd/xstat.c | 2 +-
sysdeps/mach/hurd/xstat64.c | 2 +-
sysdeps/mips/mips32/libm-test-ulps | 23 +-
sysdeps/mips/mips64/Implies | 1 -
sysdeps/mips/mips64/libm-test-ulps | 23 +-
sysdeps/posix/system.c | 4 +
sysdeps/posix/tempname.c | 291 +-
sysdeps/powerpc/nofpu/libm-test-ulps | 33 +-
sysdeps/powerpc/powerpc64/backtrace.c | 13 +-
sysdeps/powerpc/powerpc64/sysdep.h | 3 +
sysdeps/riscv/dl-irel.h | 56 +
sysdeps/riscv/dl-machine.h | 44 +-
sysdeps/s390/s390-64/Implies | 1 -
sysdeps/sh/libm-test-ulps | 42 +-
sysdeps/sparc/fpu/libm-test-ulps | 23 +-
sysdeps/sparc/sparc64/Implies | 1 -
sysdeps/unix/sysv/linux/aarch64/libc-start.c | 5 +
sysdeps/unix/sysv/linux/alpha/wait4.c | 2 +
sysdeps/unix/sysv/linux/arm/readelflib.c | 22 +-
sysdeps/unix/sysv/linux/bits/siginfo-consts.h | 6 +-
.../fxstat.c => unix/sysv/linux/bits/sigstksz.h} | 30 +-
sysdeps/unix/sysv/linux/faccessat.c | 3 +-
sysdeps/unix/sysv/linux/fxstat.c | 4 +-
sysdeps/unix/sysv/linux/fxstat64.c | 4 +-
sysdeps/unix/sysv/linux/fxstatat.c | 4 +-
sysdeps/unix/sysv/linux/fxstatat64.c | 4 +-
sysdeps/unix/sysv/linux/i386/ld.abilist | 1 -
sysdeps/unix/sysv/linux/i386/libc.abilist | 1 +
sysdeps/unix/sysv/linux/i386/startup.h | 29 +-
.../linux/{aarch64/libc-start.c => ia64/brk.c} | 18 +-
sysdeps/unix/sysv/linux/ia64/readelflib.c | 22 +-
.../libc-start.c => ia64/sysconf-sigstksz.h} | 21 +-
sysdeps/unix/sysv/linux/lxstat.c | 2 +-
sysdeps/unix/sysv/linux/lxstat64.c | 4 +-
sysdeps/unix/sysv/linux/mips/mips64/getdents64.c | 37 +-
sysdeps/unix/sysv/linux/mips/readelflib.c | 22 +-
sysdeps/unix/sysv/linux/powerpc/powerpc64/clone.S | 3 +
sysdeps/unix/sysv/linux/powerpc/readelflib.c | 22 +-
sysdeps/unix/sysv/linux/powerpc/sysdep.h | 5 +-
sysdeps/unix/sysv/linux/riscv/readelflib.c | 22 +-
sysdeps/unix/sysv/linux/s390/readelflib.c | 22 +-
sysdeps/unix/sysv/linux/sparc/readelflib.c | 22 +-
sysdeps/unix/sysv/linux/sys/mount.h | 2 +
.../unix/sysv/linux/sysconf-sigstksz.h | 41 +-
sysdeps/unix/sysv/linux/sysconf.c | 9 +
sysdeps/unix/sysv/linux/tst-getdents64.c | 29 +-
sysdeps/unix/sysv/linux/tst-sysvshm-linux.c | 26 +-
sysdeps/unix/sysv/linux/x86/dl-minsigstacksize.h | 83 +
sysdeps/unix/sysv/linux/x86/elf-read-prop.h | 60 +
.../unix/sysv/linux/x86/include/bits/sigstack.h | 5 +
sysdeps/unix/sysv/linux/x86/readelflib.c | 23 +-
sysdeps/unix/sysv/linux/x86_64/64/ld.abilist | 1 -
sysdeps/unix/sysv/linux/x86_64/64/libc.abilist | 1 +
sysdeps/unix/sysv/linux/x86_64/Makefile | 51 +
.../unix/sysv/linux/x86_64/tst-glibc-hwcaps-2.c | 83 +
sysdeps/unix/sysv/linux/x86_64/x32/ld.abilist | 1 -
sysdeps/unix/sysv/linux/x86_64/x32/libc.abilist | 1 +
.../sysv/linux/x86_64/x86-64-isa-level-VALUE.c | 4 +
sysdeps/unix/sysv/linux/xstat.c | 6 +-
sysdeps/unix/sysv/linux/xstat64.c | 5 +-
sysdeps/x86/Makefile | 59 +-
sysdeps/x86/Versions | 7 +-
posix/globfree.c => sysdeps/x86/abi-note.c | 38 +-
sysdeps/x86/bits/platform/x86.h | 299 +
sysdeps/x86/cacheinfo.c | 48 +-
sysdeps/x86/cacheinfo.h | 402 +-
sysdeps/x86/configure | 79 +
sysdeps/x86/configure.ac | 66 +
sysdeps/x86/cpu-features.c | 120 +-
sysdeps/x86/dl-cacheinfo.h | 473 +
sysdeps/x86/dl-cet.c | 21 +-
sysdeps/x86/dl-get-cpu-features.c | 8 +-
sysdeps/{generic/startup.h => x86/dl-isa-level.h} | 20 +-
.../libc-start.c => x86/dl-minsigstacksize.h} | 23 +-
sysdeps/x86/dl-prop.h | 113 +-
sysdeps/x86/fpu/nan-pseudo-number.h | 1 -
.../libc-start.c => x86/get-cpuid-feature-leaf.c} | 24 +-
sysdeps/x86/get-isa-level.h | 67 +
sysdeps/x86/include/cpu-features.h | 785 +-
sysdeps/x86/isa-level.c | 97 +
sysdeps/x86/libc-start.c | 5 +
sysdeps/x86/link_map.h | 18 +-
sysdeps/x86/sys/platform/x86.h | 777 +-
sysdeps/x86/tst-cet-legacy-10-static.c | 1 +
.../globfree.c => sysdeps/x86/tst-cet-legacy-10.c | 40 +-
sysdeps/x86/tst-cet-legacy-5.c | 11 +-
sysdeps/x86/tst-cet-legacy-6.c | 11 +-
sysdeps/x86/tst-cet-legacy-9-static.c | 1 +
.../x86/tst-cet-legacy-9.c | 38 +-
sysdeps/x86/tst-cpu-features-cpuinfo.c | 43 +-
sysdeps/x86/tst-get-cpu-features.c | 31 +-
sysdeps/x86/tst-ifunc-isa-1-static.c | 1 +
.../aarch64/libc-start.c => x86/tst-ifunc-isa-1.c} | 22 +-
sysdeps/x86/tst-ifunc-isa-2-static.c | 1 +
.../hurd/fxstatat.c => x86/tst-ifunc-isa-2.c} | 30 +-
sysdeps/x86/tst-ifunc-isa.h | 104 +
sysdeps/x86/tst-isa-level-1.c | 103 +
sysdeps/x86/tst-isa-level-mod-1-baseline.c | 1 +
sysdeps/x86/tst-isa-level-mod-1-v2.c | 1 +
sysdeps/x86/tst-isa-level-mod-1-v3.c | 1 +
sysdeps/x86/tst-isa-level-mod-1-v4.c | 1 +
.../libc-start.c => x86/tst-isa-level-mod-1.c} | 19 +-
sysdeps/x86/tst-setjmp-cet.c | 1 +
sysdeps/x86_64/Implies | 1 -
sysdeps/x86_64/configure | 3 +
sysdeps/x86_64/configure.ac | 3 +
sysdeps/x86_64/dl-hwcaps-subdirs.c | 30 +-
sysdeps/x86_64/dl-machine.h | 16 +-
sysdeps/x86_64/fpu/Makefile | 8 +
.../x86_64/multiarch/memmove-vec-unaligned-erms.S | 28 +-
sysdeps/x86_64/tst-glibc-hwcaps.c | 44 +-
version.h | 2 +-
347 files changed, 38033 insertions(+), 19132 deletions(-)
create mode 100644 ChangeLog.old/ChangeLog.22
copy sysdeps/unix/sysv/linux/aarch64/libc-start.c => bits/sigstksz.h (69%)
create mode 100644 elf/tst-glibc-hwcaps-2-cache.c
copy elf/{tst-glibc-hwcaps-cache.root => tst-glibc-hwcaps-2-cache.root}/etc/ld.so. [...]
copy elf/{tst-glibc-hwcaps-cache.root => tst-glibc-hwcaps-2-cache.root}/postclean. [...]
create mode 100644 elf/tst-glibc-hwcaps-2-cache.script
copy elf/{tst-glibc-hwcaps-cache.root/postclean.req => tst-glibc-hwcaps-prepend-ca [...]
copy elf/{tst-glibc-hwcaps-cache.root/postclean.req => tst-ldconfig-ld_so_conf-upd [...]
copy sysdeps/aarch64/multiarch/init-arch.h => elf/tst-prelink-cmp.c (50%)
delete mode 100644 elf/tst-prelink.exp
create mode 100644 elf/tst-rtld-list-tunables.exp
create mode 100755 elf/tst-rtld-list-tunables.sh
create mode 100644 iconvdata/bug-iconv14.c
create mode 100644 include/bits/sigstack.h
create mode 100644 include/bits/sigstksz.h
create mode 100644 include/filename.h
create mode 100644 include/idx.h
copy sysdeps/x86/fpu/nan-pseudo-number.h => malloc/scratch_buffer_dupfree.c (58%)
delete mode 100644 nptl/pthread_setegid.c
delete mode 100644 nptl/pthread_seteuid.c
delete mode 100644 nptl/pthread_setgid.c
delete mode 100644 nptl/pthread_setregid.c
delete mode 100644 nptl/pthread_setresgid.c
delete mode 100644 nptl/pthread_setresuid.c
delete mode 100644 nptl/pthread_setreuid.c
delete mode 100644 nptl/pthread_setuid.c
create mode 100644 nss/tst-reload2.c
create mode 100644 nss/tst-reload2.root/etc/nsswitch.conf
create mode 100644 nss/tst-reload2.root/subdir/etc/group
create mode 100644 nss/tst-reload2.root/subdir/etc/nsswitch.conf
create mode 100644 nss/tst-reload2.root/tst-reload2.script
copy po/{pt_BR.po => sr.po} (53%)
delete mode 100644 scripts/output-format.sed
create mode 100644 signal/tst-minsigstksz-5.c
create mode 100644 stdlib/tst-canon-bz26341.c
copy sysdeps/unix/sysv/linux/aarch64/libc-start.c => support/xchdir.c (68%)
copy sysdeps/unix/sysv/linux/aarch64/libc-start.c => support/xchmod.c (68%)
copy sysdeps/unix/sysv/linux/aarch64/libc-start.c => support/xfchmod.c (68%)
copy sysdeps/{unix/sysv/linux/aarch64/libc-start.c => generic/dl-isa-level.h} (68%)
copy sysdeps/{mach/hurd/fxstat64.c => generic/elf-read-prop.h} (59%)
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/e_acosh.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/e_cosh.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/e_fmod.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/e_log10.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_frexp.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_getpayload.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_issignaling.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_llround.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_lround.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_modf.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_remquo.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_roundeven.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_scalbln.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_scalbn.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_setpayload_main.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_totalorder.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_totalordermag.c
rename sysdeps/{generic => ieee754/ldbl-96}/nan-pseudo-number.h (87%)
create mode 100644 sysdeps/mach/hurd/i386/i686/multiarch/rtld-strncpy-c.c
create mode 100644 sysdeps/riscv/dl-irel.h
copy sysdeps/{mach/hurd/fxstat.c => unix/sysv/linux/bits/sigstksz.h} (58%)
copy sysdeps/unix/sysv/linux/{aarch64/libc-start.c => ia64/brk.c} (68%)
copy sysdeps/unix/sysv/linux/{aarch64/libc-start.c => ia64/sysconf-sigstksz.h} (68%)
copy posix/globfree.c => sysdeps/unix/sysv/linux/sysconf-sigstksz.h (50%)
create mode 100644 sysdeps/unix/sysv/linux/x86/dl-minsigstacksize.h
create mode 100644 sysdeps/unix/sysv/linux/x86/elf-read-prop.h
create mode 100644 sysdeps/unix/sysv/linux/x86/include/bits/sigstack.h
create mode 100644 sysdeps/unix/sysv/linux/x86_64/tst-glibc-hwcaps-2.c
create mode 100644 sysdeps/unix/sysv/linux/x86_64/x86-64-isa-level-VALUE.c
copy posix/globfree.c => sysdeps/x86/abi-note.c (52%)
create mode 100644 sysdeps/x86/bits/platform/x86.h
copy sysdeps/{generic/startup.h => x86/dl-isa-level.h} (56%)
copy sysdeps/{unix/sysv/linux/aarch64/libc-start.c => x86/dl-minsigstacksize.h} (62%)
copy sysdeps/{unix/sysv/linux/aarch64/libc-start.c => x86/get-cpuid-feature-leaf.c} (64%)
create mode 100644 sysdeps/x86/get-isa-level.h
create mode 100644 sysdeps/x86/isa-level.c
create mode 100644 sysdeps/x86/tst-cet-legacy-10-static.c
copy posix/globfree.c => sysdeps/x86/tst-cet-legacy-10.c (55%)
create mode 100644 sysdeps/x86/tst-cet-legacy-9-static.c
copy support/support_set_small_thread_stack_size.c => sysdeps/x86/tst-cet-legacy-9 [...]
create mode 100644 sysdeps/x86/tst-ifunc-isa-1-static.c
copy sysdeps/{unix/sysv/linux/aarch64/libc-start.c => x86/tst-ifunc-isa-1.c} (68%)
create mode 100644 sysdeps/x86/tst-ifunc-isa-2-static.c
copy sysdeps/{mach/hurd/fxstatat.c => x86/tst-ifunc-isa-2.c} (60%)
create mode 100644 sysdeps/x86/tst-ifunc-isa.h
create mode 100644 sysdeps/x86/tst-isa-level-1.c
create mode 100644 sysdeps/x86/tst-isa-level-mod-1-baseline.c
create mode 100644 sysdeps/x86/tst-isa-level-mod-1-v2.c
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copy sysdeps/{unix/sysv/linux/aarch64/libc-start.c => x86/tst-isa-level-mod-1.c} (68%)
create mode 100644 sysdeps/x86/tst-setjmp-cet.c
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[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-Os-vs-Os_LTO updated (ef370f933c0 -> 8e4a738d254)
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-Os-vs-Os_LTO
in repository toolchain/ci/gcc.
from ef370f933c0 Darwin : Adjust defaults for the linker.
adds 2eacfdbd6a2 Daily bump.
adds 37d0bb1f5b5 libiberty.h: punt duplicate strverscmp prototype
adds 3335c9f954f config: import pkg.m4 from pkg-config
adds f14f89c5c46 Bump copyright year
adds 2e96eec614e Daily bump.
adds c48514bea61 Update Copyright in ChangeLog files
adds e9f8a554efe Fix -save-temp leaking lto files in /tmp
adds b4cdbb93357 Remove duplicated ChangeLog entries from po/ChangeLog
adds 8869bd0efcd gcc-changelog: Ignore copyright years commits.
adds cf76bbf8a8c mklog.py: add --update-copyright option
adds 2a680610d1c Fix up indentation in update-copyright.py
adds f96f664cf6c Remove duplicate ChangeLog entries.
adds c00e2af3639 Add AMD and Ulf Adams as external authors
adds 99dee82307f Update copyright years.
adds ad64e807ffc match.pd: Fold x == ~x to false [PR96782]
adds 8837f82e4ba tree-optimization/98291 - allow SLP more vectorization of r [...]
adds ff6b4062479 avr.exp: convert Dos newlines to Unix ones
adds a40718b5fc8 Convert 2 files to utf8.
adds 0926259f9fc tree-optimization/98393 - properly init matches when failing SLP
adds ba15b0fa0df aarch64: Use the MUL VL form of SVE PRF[BHWD]
adds b41e6dd50f3 aarch64: Improve vcombine codegen [PR89057]
adds 13b80a7d1b9 tree-optimization/98282 - classify V_C_E<constant> as nary
adds 7f2b7317566 docs: Fix wording describing the hwaddress sanitizer
adds 39bd65faee3 tree-optimization/98464 - replace loop info with avail at uses
adds 24cd9afe617 loop-niter: Recognize popcount idioms even with char, short [...]
adds 9e79d76a16c tree-optimization/98308 - set vector type for mask of masked load
adds 6bbc196c64d [libcody] Windows absdir fix
adds 6288183377a [libcody] Remove some std::move [PR 98368]
adds aa204d51185 vect, aarch64: Fix alignment units for IFN_MASK* [PR95401]
adds a5469584f61 c++: Add stdlib module test cases
adds f262a351887 MAINTAINERS: Update my email address.
adds a000eb5918e C: Add test for incorrect warning for assignment of certain [...]
adds 7e73f511573 Daily bump.
adds 15af33a8806 analyzer: fix ICE with -fsanitize=undefined [PR98293]
adds bf183413c6f Go frontend: add -fgo-embedcfg option
adds 560d9915762 Fix testsuite/g++.dg/cpp1y/constexpr-66093.C execution failure...
adds 6b69738c1e3 Restore input_location after recursive expand_call_inline
adds 4615cde5d7e simplify-rtx: Optimize (x - 1) * y + y [PR98334]
adds a20893cf6b9 build: libcody: Link with -lsocket -lnsl if necessary [PR98316]
adds 01be45eccee vect: Fix missing alias checks for 128-bit SVE [PR98371]
adds 8a25be517f8 rtl-ssa: Fix updates to call clobbers [PR98403]
adds eac8675225c recog: Fix a constrain_operands corner case [PR97144]
adds e8beba1cfc7 explow, aarch64: Fix force-Pmode-to-mem for ILP32 [PR97269]
adds bea984814c6 i386: Optimize pmovskb on zero_extend of subreg HI of pmovs [...]
adds b679559385f arc: fix accumulator first register.
adds af60b0ec79e x86: Cast to unsigned short first for _mm_extract_pi16
adds 6ffaffd5d10 [c++]: Improve module-decl diagnostics [PR 98327]
adds 951bdbde6ad i386: Add _mm256_cmov_si256 [PR98521]
adds 1ff0ddcd8b4 i386: Prevent spurious FP exceptions with _mm_cvt{,t}ps_pi3 [...]
adds 01da03c915f tree-optimization/98381 - fix live bool vector extract
adds f7028937872 go: Fix -fgo-embedcfg= option description.
adds a7553ad60be store-merging: Handle vector CONSTRUCTORs using bswap [PR96239]
adds 5ca2400270e match.pd: Improve (A / (1 << B)) -> (A >> B) optimization [ [...]
adds 576714b309b phiopt: Optimize x < 0 ? ~y : y to (x >> 31) ^ y [PR96928]
adds 4ddee425b8c reassoc: Fix reassociation on 32-bit hosts with > 32767 bbs [...]
adds 26b5062be99 tree-optimization/98428 - avoid pre-existing vectors for loop SLP
adds 27aad521570 move SLP debug counter
adds af362af18f4 c++: ICE with deferred noexcept when deducing targs [PR82099]
adds 606f2af1973 c++: Fix ICE with __builtin_bit_cast [PR98469]
adds 33a63257701 tree-optimization/98516 - fix SLP permute opt materialization
adds 8ea81f56140 Don't link cc1 etc. against libcody.a
adds 407bcf8e28f A couple of comment tweaks
adds 6b577a17b26 nvptx: Cache stacks block for OpenMP kernel launch
adds 5de7bf5bc98 expand: Fold x - y < 0 to x < y during expansion [PR94802]
adds e2e2f3f2c94 c++: Fix deduction from the type of an NTTP
adds f6dd35cf930 x86: Use unsigned short to compute pextrw result
adds ae1ada95fee Add <source_location> to the precompiled header.
adds c5e94699efa d: Merge upstream dmd a5c86f5b9
adds db7ce388dce doc: reflect the publication of C++20 in invoke.texi and st [...]
adds a9f76d03bbc internal/cpu: more build fixes for Go1.16beta1 release
adds f47c00cf95d syscall: don't define sys_SETREUID and friends
adds e591f18ff87 xfail test that will never pass on i?86 FreeBSD
adds c21f47f4019 IBM Z: Fix check_effective_target_s390_z14_hw
adds f56de3557fa Update GNU/Hurd configure support
adds ad92bf4b165 doc: Re-add HSAIL to Language Standards
adds 651b8a50a6d Daily bump.
adds df1eba3cead analyzer: remove xfail [PR98223]
adds 23fc2be633c analyzer: add regression test for PR 98073
adds ac3966e315a analyzer: fix false leaks when writing through unknown ptrs [...]
adds 57706dd7e00 gcc-changelog: workaround for utf8 filenames
adds a05cc70a6c1 tree-optimization/98513 - fix bug in range intersection code
adds c9ee9c1e355 add signed_bool_precision attribute for GIMPLE FE use
adds cecf8c662de robustify vxworks glimits.h overriding
adds 758abf1ae31 add alignment to enable store merging in strict-alignment targets
adds 6d0b075d662 Fix libcody build on hppa*-*-hpux11.11.
adds e6a5daae7ec c++: Fix g++.dg/warn/Wmismatched-dealloc.C for C++11 [PR98566]
adds 8b6f1e8f97f PR fortran/78746 - invalid access after error recovery
adds 334a295fafd testsuite, coroutines : Fix a bad testcase [PR96504].
adds fd64f348a6b PR c++/98305 spurious -Wmismatched-new-delete on template instance
adds abb1b6058c0 PR c++/95768 - pretty-printer ICE on -Wuninitialized with a [...]
adds 15a47f437d2 [PR97978] LRA: Permit temporary allocation incorrectness af [...]
adds f05bbca3d95 sync libctf toplevel from binutils-gdb
adds 942ae5be662 Daily bump.
adds cffe6dd2ce3 analyzer: fix missing bitmap_clear [PR98564]
adds be6c485b24f analyzer: fix false leak reports when merging states [PR97074]
adds 1b566975242 Adjust testcase for PR 92658
adds d02a8b63e5a bswap: Fix up recent vector CONSTRUCTOR optimization [PR98568]
adds d54be5ad210 i386: Merge various insn name mapping code attributes
adds 78595e918ee gimple-isel: Fall back to using vcond_mask [PR98560]
adds 298e76e6562 gimple-isel: Check whether IFN_VCONDEQ is supported [PR98560]
adds 0f9d2c1a318 aarch64: Support conditional unpacked integer unary arithme [...]
adds 6bca2ebf106 i386: Optimize blsi followed by comparison [PR98567]
adds d54029179cb fix GIMPLE parser for loops
adds dddea6d4d81 d: Merge upstream dmd 9038e64c5.
adds 85fb1d7d5f4 Fortran: Improve resolution of associate variables. [PR93701].
adds 19f3c433cdc libstdc++: Fix long double to_chars testcase [PR98384]
adds c8d2ed112e7 Update cpplib es.po.
adds b87ec922c40 test: add new Go tests from source repo
adds 0677759f753 analyzer: fix ICE when DECL_INITIAL is error_mark_node [PR98580]
adds b7c3f201be5 libstdc++: Add support for C++20 barriers
adds 4d65a07d54b c++: Add some conversion sanity checking.
adds 6c59b8a93cf c++: Add TARGET_EXPR comments
adds 2f359597e49 c++: Fix thinko in auto return type checking [PR98441]
adds 178f0afce36 PR middle-end/98578 - ICE warning on uninitialized VLA access
adds aa4db31dd2a c++: Fix up tsubst of BIT_CAST_EXPR [PR98329]
adds 7d187e4f6f5 Daily bump.
adds 0b7b4710111 RISC-V: Move class riscv_subset_list and riscv_subset_t to [...]
adds e3354b6de7a RISC-V: Implement new style of architecture extension test macros.
adds 01d92cfd798 Fix array-quals-1.c for RISC-V
adds c231fca5de8 Fortran:Fix simplification of constructors with implied-do [...]
adds 21c1a30fc73 Fortran: Allow pointer deferred length associate selectors. [...]
adds c9d25aa7489 aarch64: Fix RTL patterns for UABA/SABA
adds cab822d4ea7 aarch64: Reimplement vaba* intrinsics using builtins
adds 79db5945ade aarch64: Reimplement vabd* intrinsics using builtins
adds e811f10b61a aarch64: Reimplement most vpadal intrinsics using builtins
adds 07fb24a3daf SVE2: Fix aarch64-sve2-acle-asm tests.
adds f3c5d1fa53a aarch64: Support conditional unpacked UXT on SVE
adds 5fe3e6bf061 aarch64: Support unpacked CNOT on SVE
adds 8f1cb70d7ca i386: Fix -mcmodel= vs. target attribute [PR98585]
adds 1b885264a48 x86-64: Use R10 for profiling large model
adds bdcde150450 tree-optimization/98544 - more permute optimization fixes
adds b407f233d7c fix vectorizer memleaks
adds 77a375a3ebf reset the SCEV htab after FRE in loop pipeline
adds 76be18f4429 x86-64: Use R10 and R11 for profiling large model with PIC
adds 98a1fb705ea c++: Fix access checking of scoped non-static member [PR98515]
adds bb1f0b50abb c++: ICE with constexpr call that returns a PMF [PR98551]
adds 98546324c79 Tweak dg-prune-output regex for out-of-build-tree contexts
adds f47df2af313 IBM Z: Introduce __LONG_DOUBLE_VX__ macro
adds 745d04e796c x86-64: Require lp64 for PR target/98482 tests
adds 0e47d6c808f IBM Z: Fix constraints in vpdi patterns
adds 0b874e0ffd5 ipa-modref: avoid linebreak split in debug print
adds bf5cbb9edff Daily bump.
adds 57450da2fef final: accept markers at line 0
adds 16dae48e9cd vregs: Fix up instantiate_virtual_regs_in_insn for asm goto [...]
adds 991656092f7 tree-cfg: Allow enum types as result of POINTER_DIFF_EXPR [ [...]
adds 859be2e44ac RTL: Update `const_double_zero' handling for mode and calla [...]
adds be7e807242b PDP11: Use a mode with `const_double_zero' expressions
adds c38bbf5eed1 VAX: Use a mode with `const_double_zero' expressions
adds 7f5c4d23db8 VAX: Remove a duplicate `cc' mode attribute
adds f2a5346244a VAX/testsuite: Remove notsi comparison elimination regressions
adds acae7b21bc0 d: Implement expression-based contract syntax
adds 7a103daef78 d: Support deprecated, @disable, and user-defined attribute [...]
adds 7da827c99c0 d: Synchronize testsuite with upstream dmd
adds 872373360da Daily bump.
adds 4a1d7f7e203 libstdc++: Suppress more vstring testsuite warnings. [PR 98613]
adds 366f86bd429 Daily bump.
adds bcb3065b2ba ira: Skip some pseudos in move_unallocated_pseudos
adds fa4586d8545 if-to-switch: remove memory leaks
adds 4e275dccfc2 Add pytest for a GCOV test-case
adds 64dc013853b aarch64: Reimplement vmovl*/vmovn* intrinsics using __built [...]
adds a2106317cd6 widening_mul: Pattern recognize unsigned multiplication wit [...]
adds 9febe9e4be7 widening_mul: Pattern recognize also signed multiplication [...]
adds 9a6c37e6ae5 reassoc: Reassociate integral multiplies [PR95867]
adds 39666d2b885 slp: fix is_linear_load_p to prevent multiple answers
adds bd4298e1927 slp: handle externals correctly in linear_loads_p
adds 0c18faac3fb slp: upgrade complex add to new format and fix memory leaks
adds 300a3ce5c56 tree-optimization/98221 - fix wrong unpack operation used f [...]
adds 928e96bbe98 d: Remove visibility and lookup deprecation
adds 04bff1bbfc1 tree-optimization/98526 - fix vectorizer reduction cost
adds 6ebf79fcd4c testsuite: Fix test failures from outputs.exp [PR98225]
adds 84684e0f78c tree-optimization/91403 - avoid excessive code-generation
adds 3b25e83536b Port update-copyright.py to Python3
adds 8c09b788a96 Make the serialized link target more verbose
adds 3dd0d3ee1d2 c++, abi: Fix abi_tag attribute handling [PR98481]
adds cbe9758ff49 Properly release symtab::m_clones.
adds b81fbfe1eb5 aarch64: Add support for unpacked SVE shifts
adds 48c7f5b8811 aarch64: Add support for unpacked SVE mult, max and min
adds ab76e3db6b8 aarch64: Add general unpacked SVE conditional binary arithmetic
adds 3f8b0bba035 aarch64: Add support for unpacked SVE ADR
adds 907ea379559 aarch64: Add support for unpacked SVE ABD
adds 7446de5a2af aarch64: Add support for unpacked SVE MULH
adds 37426e0f060 aarch64: Add support for unpacked SVE conditional BIC
adds a958b2fc6da aarch64: Add support for unpacked SVE ASRD
adds 67fbb7f0fda Daily bump.
adds ab88f360723 analyzer: fix ICE merging dereferencing unknown ptrs [PR98628]
adds 640296c367f make FOR_EACH_IMM_USE_STMT safe for early exits
adds 240f0a490da Delete dead code in ix86_expand_sse_comi.
adds 814299a9d49 c++: -Wmissing-field-initializers in unevaluated ctx [PR98620]
adds ab96073df00 MAINTAINERS: Add myself for write after approval
adds ff99d05f40f configure, make: Fix up --enable-link-serialization
adds 13d47c37a2c reassoc: Optimize in reassoc x < 0 && y < 0 to (x | y) < 0 [...]
adds 24ea113f75c widening_mul: Fix up ICE caused by my signed multiplication [...]
adds b2230210f17 gcov: add more debugging facility
adds e91910d3576 options: properly compare string arguments
adds 52a170b1a18 tree-optimization/98550 - fix BB vect unrolling check
adds e0bec6ceac4 c++: Fix ICE with CTAD in concept [PR98611]
adds cf2ac1c30af [PR97969] LRA: Transform pattern `plus (plus (hard reg, con [...]
adds 25bef68902f arm: Add movmisalign patterns for MVE (PR target/97875)
adds 1aff68d54c3 Fix typo in function-abi.h
adds 248feb2fa2c gcov: fix printf format for 32-bit hosts
adds e2aa8a5f982 libcody: Simplify configure [PR 98414, 98509]
adds 728fee7a798 MAINTAINERS: Fix spacing
adds 5a9cfad2de9 Avoid a couple more ICEs in print_mem_ref (PR c/98597).
adds cfaaa6a1ca7 syscall: ensure openat uses variadic libc wrapper
adds 6851dda2e79 Daily bump.
adds abb3993e49c amdgcn: Fix subdf3 pattern
adds c8812bac8ee amdgcn: Improve FP division accuracy
adds 3df6fac0080 amdgcn: Fix exec register live-on-entry to BB in md-reorg
adds 7993fe1877a amdgcn: Remove dead code for fixed v0 register
adds b668a06e37f i386: Optimize _mm_unpacklo_epi8 of 0 vector as second argu [...]
adds 3f325179b32 [PATCH v2] aarch64: Add cpu cost tables for A64FX
adds 6b70fa678b1 ipa: remove a dead code
adds 5d057bfeff7 i386: Add define_insn_and_split patterns for btrl [PR96938]
adds ffd28c265e6 tree-optimization/98640 - fix bogus sign-extension with VN
adds 4c598b038df doc: Fix typos in C++ Modules documentation
adds 0db5f488486 libstdc++: Remove <debug/array> from Doxygen config
adds 7875e8dc831 if-to-switch: fix also virtual phis
adds b1d1e2b54c6 i386, expand: Optimize also 256-bit and 512-bit permutatati [...]
adds 2b356e689c3 hurd: libgcc unwinding over signal trampolines with SIGINFO
adds c23aea6edc9 gcc-changelog: Allow modifications to old ChangeLogs without entry
adds f04e7e540e2 libstdc++: Fix typo in ChangeLog-2020
adds e9cb89b936f Hurd: Enable ifunc by default
adds 40b371a7c2f sh: Remove match_scratch operand test
adds 6d75168146f rtl-ssa: Fix reversed comparisons in accesses.h comment
adds 5ab67cdee61 aarch64: Tighten condition on sve/sel* tests
adds 3ddc18251a8 tree-optimization/92645 - improve SLP with existing vectors
adds cf7a3353061 aarch64: Add support for unpacked SVE MLA and MAD
adds 264a1269b44 aarch64: Add support for unpacked SVE MLS and MSB
adds 11cbea852b0 c++: Fix cp_build_function_call_vec [PR 98626]
adds a2d04f3d2c9 mklog: support define_insn_and_split format
adds 285fa338b06 tree-optimization/92645 - avoid harmful early BIT_FIELD_REF [...]
adds 7d7ef413ef1 gcc-changelog: Support multiline parentheses wrapping
adds 8fc183ccd06 match.pd: Fold (~X | C) ^ D into (X | C) ^ (~D ^ C) if (~D [...]
adds 796ead19f85 c++: Failure to lookup using-decl name [PR98231]
adds 8cba7cb3202 or1k: Implement profile hook calling _mcount
adds e1171c32502 or1k: Add builtin define to detect hard float
adds b77f6d2fa84 or1k: Support for softfloat to emulate hw exceptions
adds 6ed637c585b or1k: Add note to indicate execstack
adds e40fdcc4f42 or1k: Fixup exception header data encodings
adds be0851b8e93 Daily bump.
adds c7f1ff01a23 aarch64: Reimplement vmovn_high_* intrinsics using builtins
adds 52cd1cd1b67 aarch64: reimplement vqmovn_high* intrinsics using builtins
adds 48f8d1d48f2 aarch64: Reimplememnt vmovn/vmovl intrinsics with builtins instead
adds e45c41988bf vect: Account for unused IFN_LOAD_LANES results
adds 8f8762a2e86 match.pd: Optimize ~(X >> Y) to ~X >> Y if ~X can be simpli [...]
adds 0efdc7b31c2 i386: Fix the pmovzx SSE4.1 define_insn_and_split patterns [...]
adds 08a4adcf2b6 i386: Remove reduntand assignment in i386-options.c [PR98671]
adds d61d2a5f3ce c++: Fix erroneous parm comparison logic [PR 98372]
adds 194a9d67be4 libstdc++: Update copyright dates on new files
adds a802a2ef5f1 arm: Replace calls to __builtin_vcge* by <=,>= in arm_neon. [...]
adds a512079ef40 i386: Update PR target/95021 tests
adds 2182274f510 tree-optimization/98674 - improve dependence analysis
adds 5ebdd53534d i386: Resolve variable shadowing in i386-options.c [PR98671]
adds 77d372abec0 x86: Error on -fcf-protection with incompatible target
adds 236d6a33ca6 mklog: skip unsupported files
adds 7624c58c6b7 gcov: add one more pytest
adds aa3d33dccb5 RTEMS: Fix Ada build for riscv
adds 57a4f5e4eac libstdc++: Define function to throw filesystem_error [PR 98471]
adds 6106dfb9f73 [nvptx libgomp plugin] Build only in supported configurations
adds 9ac3e2feb3d libgo: update hurd support
adds d0d2becf2df PR fortran/98661 - valgrind issues with error recovery
adds c1a2cf88059 Revert "PR fortran/98661 - valgrind issues with error recovery"
adds 9e1e6e63104 PR fortran/98661 - valgrind issues with error recovery
adds 05a30af3f23 libstdc++: Implement N3644 for _GLIBCXX_DEBUG iterators
adds 505caa7295b [gcn offloading] Only supported in 64-bit configurations
adds 088e46b8d4d declare getpass in analyzer/sensitive-1.c test
adds 6541fcadc86 use sigjmp_buf for analyzer sigsetjmp tests
adds 3651c1b5c9c calibrate intervals to avoid zero in futures poll test
adds bdd1b1f5552 PR fortran/93340 - fix missed substring simplifications
adds f6ffd449e0c c++: Tweak g++.dg/template/pr98372.C.
adds 8a18261afd9 analyzer: const fixes [PR98679]
adds dea4a32b24f analyzer: fixes to -fdump-analyzer-json
adds fe701195313 slp: elide intermediate nodes for complex add and avoid truncate
adds 500600c7840 slp: Support optimizing load distribution
adds e09173d84da slp: support complex multiply and complex multiply conjugate
adds 31fac31800b slp: support complex FMA and complex FMA conjugate
adds 478e571a3ee slp: support complex FMS and complex FMS conjugate
adds b50df1e749b slp: Add complex operations class to share first match amon [...]
adds 59832db9a71 slp: Add Tests for complex mul, mls and mla"
adds f1096055854 Add GCC_EXTRA_DIAGNOSTIC_OUTPUT environment variable for fi [...]
adds 02e7af1122c libstdc++: Implement N3644 for _GLIBCXX_DEBUG iterators
adds 387f6c15d30 Handle fancy_abort before diagnostic initialization [PR98586]
adds f1fc27b6c51 c++: Minor refactoring in process_init_constructor_record
adds b95d97f1a5f jit: remove "Alpha" warning from docs
adds 5fff80fd79c Daily bump.
adds b0ccd3922f5 compiler: add support for reading embedcfg files
adds c4eec1efae0 testsuite: Fix sed script errors in complex tests
adds 2ea6f4a377e tree-optimization/98685 - fix placement of extern converts
adds 7432f255b70 arm: Auto-vectorization for MVE: vshl
adds bfab355012c arm: Auto-vectorization for MVE: vshr
adds 0411ae7f08e libatomic, libgomp, libitc: Fix bootstrap [PR70454]
adds cb60334b716 testsuite/96098 - remove redundant testcase
adds 1a630642009 arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics
adds d03f14c354a testsuite/96147 - remove scanning for ! vect_hw_misalign
adds e1bd80fb706 testsuite/96147 - key scanning on vect_hw_misalign
adds aa4ee5798fe testsuite/96147 - scan for vectorized load
adds b36c9cd0947 testsuite/96147 - align vector access
adds dc8475e3348 Pytest in tests: improve
adds 446703ccc2c tree-optimization/96376 - do not check alignment for invari [...]
adds f1d054017ef Revert "arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 [...]
adds 63999d751df arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics
adds f9a577927eb IBM Z: Fix linking to libatomic in target test cases
adds 7f6cdaa9a8d rtl-ssa: Fix a silly typo
adds f2cc526f47a recog: Fix insn_change_watermark destructor
adds 5a783f42d77 aarch64: Add a minipass for fusing CC insns [PR88836]
adds 492b90f33df c++: Fix langspecs with -fsyntax-only [PR98591]
adds 1ba71fabb78 preprocessor: Make quoting : [PR 95253]
adds 7d0df0aeb67 i386: Use cpp_define_formatted for __SIZEOF_FLOAT80__ definition
adds d3959070aa4 [PATCH] aarch64: Implement vmlsl[_high]* intrinsics using builtins
adds 50dbced2f37 openmp: Change the way of building of reduction array type
adds adb520606ce c-family: Improve MEM_REF printing for diagnostics [PR98597]
adds a3128bf0128 bootstrap: fix failing diagnostic selftest on Windows [PR98696]
adds aaec739250b testsuite: Add testcase coverage for already fixed [PR96671]
adds c0194736b47 gcc.dg/analyzer tests: use __builtin_alloca, not alloca.h
adds cd09079cfd5 c++: Fix list-init of array of no-copy type [PR63707]
adds ad260343385 AArch64: Add NEON, SVE and SVE2 RTL patterns for Multiply, [...]
adds 424deca72b6 c++: Fix copy elision for base initialization
adds d75199f7823 c++: Avoid redundant copy in {} init [PR98642]
adds e63c2161d09 drop -dumpbase-ext from producer string
adds 5c046034e3e match.pd: Optimize (x < 0) ^ (y < 0) to (x ^ y) < 0 etc. [PR96681]
adds 0425f4c1b63 match.pd: Generalize the PR64309 simplifications [PR96669]
adds e1efa6af61a preprocessor: Make quoting : [PR 95253]
adds 9beb6d88eff c++: Fix qualified array-type construction [PR 98538]
adds b90e4a97419 fortran: Fixes a bug in ISO_Fortran_binding.c.
adds c029fcb5680 Reset force_source_line in final.c
adds f1ad419ebfd rs6000, vector integer multiply/divide/modulo instructions
adds 2f7f0d32e74 Daily bump.
adds 2c356f221bb libstdc++-v3: Add -fcf-protection=none to -march=i486
adds b673e7547fb cd_dce: Return TODO_update_address_taken from last cd_dce [ [...]
adds e2559c3945a match.pd: Optimize ((cst << x) & 1) [PR96669]
adds 7e02426ba0c nios2: Remove custom instruction warnings
adds 42f4e239924 nios2: Add -mcustom-fpu-cfg=fph2
adds 5e5d56919dd RTEMS: Add -mcustom-fpu-cfg=fph2 multilib
adds a6d22fb21c6 openmp: Add support for the OpenMP 5.0 task detach clause
adds a2960a04d51 testsuite: Fix up a testcase to find the right ISO_Fortran_ [...]
adds 59cf67d1cf7 Daily bump.
adds 3804e937b0e Default to DWARF5
adds 0f4c8f517b7 ipa: Adjust cgraph verifier to materialization on demand (P [...]
adds 192105b6a2a Avoid assuming SSA_NAME_IDENTIFIER is nonnull.
adds 56b5d13e278 aix: default to DWARF 4.
adds b654d23a470 testsuite: Skip DWARF 5 testcases on AIX.
adds 4c9bcd5c81a Daily bump.
adds 4905f404018 Fix ChangeLog entries.
adds 994fb69ac1b testsuite: powerpc fold-vec and sse updates.
adds d3b41bde961 libgomp: Don't access gomp_sem_t as int using atomics uncon [...]
adds 0f951b3dd34 RTEMS: Fix libgomp build
adds 2e43880dbd4 libstd++: : Add workaround for as Error: file number less t [...]
adds a81d2f1e414 libstdc++: Fix narrow char test to use stringbuf not wstringbuf
adds 104304cd246 testsuite/97299 - fix test condition of gcc.dg/vect/slp-reduc-3.c
adds acdc49fabf0 [arm,testsuite]: Fix options for vceqz_p64.c and vceqzq_p64.c
adds b8c3f5196e1 libgomp: enable linux-futex on riscv64
adds e393f03b1a7 testsuite/97494 - adjust gcc.dg/vect/slp-11b.c
adds ec153f96f89 libstdc++: Only test writing to wostream if supported [PR 98725]
adds c7e276b869b analyzer: use "malloc" attribute
adds 66cbe54960c Avoid no-stack-protector-attr fails on hppa*-*-*.
adds 76c1dd15e4a Skip asm goto tests on hppa*-*-*.
adds f56e14101b9 aix: document dwarf 4 default (and TPF default)
adds 9675ccd64ef widening_mul: Fix up signed multiplication overflow check h [...]
adds 32b6e917ac4 c++: Add CTAD + pack expansion testcase
adds a89c5d3539c [PR97847] IRA: Skip abnormal critical edge splitting
adds 325e70b47c6 libbacktrace: use correct directory/filename for DWARF 5
adds bfde774667f libbacktrace: don't fail tests if dwz fails
adds 9a3ab93ceb2 [committed] Minor fix to pr41445-7 testcase
adds ef1f8ee67d4 Daily bump.
adds c907e439413 compiler: read embedcfg files, parse go:embed directives
adds 9ee33d7c33f RISC-V: The 'multilib-generator' enhancement.
adds 665e80ca5ec Fix PR ada/98740
adds 9b8741c98f2 ipa-sra: Do not remove return values needed because of non-call EH
adds 049bfd186fa OpenMP/Fortran: Fixes for {use,is}_device_ptr
adds 7d6f7e92c3b ipa/97673 - fix input_location leak
adds 4b690f161b8 sparc,rtems: add __FIX_LEON3FT_TN0018 for affected targets
adds f27cd6f4226 middle-end/98638 - avoid SSA reference to stmts after SSA d [...]
adds 66dd412feea ipa/98330 - avoid ICEing on call indirect call
adds 8227106f566 [committed] Fix dwarf-float.c test in testsuite
adds 763b865a17d aarch64: Remove testing of saturation cumulative QC bit
adds 04b472ad0e1 aarch64: Relax flags of saturation builtins
adds 04cdb132020 [PATCH, rs6000] Update pr88233.c test (pr91799)
adds 6a2a38620cf alias: Fix offset checks involving section anchors [PR92294]
adds 6e6f3ed47e5 c++: Fix null this pointer [PR 98624]
adds 7266ff2a243 c++: Remove unused fn
adds c37f1d4081f c++: ICE when late parsing noexcept/NSDMI [PR98333]
adds 29853c65324 c++: Always check access during late-parsing of members [PR58993]
adds 9693e255ee2 PR middle-end/98664 - inconsistent -Wfree-nonheap-object fo [...]
adds d89b00c095e c++: ICE with USING_DECL redeclaration [PR98687]
adds eed40bca6f2 compiler: initialize variables with go:embed directives
adds 2b27f37f90c c++: Crash when deducing template arguments [PR98659]
adds a311dfaf92c Update gcc de.po.
adds 6bc6094fa3f testsuite: aix testsuite adjustments
adds f35a4f96373 Daily bump.
adds b83604c75fe dwarf2out: reset generation count in toplev::finalize [PR98751]
adds c05cdfb3f63 OpenMP/Fortran: Fix gfortran.dg/gomp/is_device_ptr-2.f90
adds 7ab1abf3b82 openmp: Don't ICE on detach clause with erroneous decl [PR98742]
adds 34599780d0d tree-optimization/98758 - fix integer arithmetic in data-re [...]
adds 4d2ecd960a0 builtins: Fix up two bugs in access_ref::inform_access [PR98721]
adds a95538b6c5a Fix gfortran.dg/gomp/task-detach-1.f90 for non 64bit pointers
adds ea74a3f548e vect: Fix VLA SLP invariant optimisation [PR98535]
adds 79e1251b642 c++: Defer access checking when processing bases [PR82613]
adds cafcfcb5840 c++: Fix tsubsting CLASS_PLACEHOLDER_TEMPLATE [PR95434]
adds 49e8c14ef6f Optimize combination of comparisons to dec+compare
adds 261cdd23195 Handle overflow in dependence analysis lambda ops gracefully
adds 4334b524274 [PR98722] LRA: Check that target has no 3-op add insn to tr [...]
adds 27c792895bd debug: Fix up DWARF 5 -g -flto -ffat-lto-objects [PR98765]
adds f8c67777661 rs6000: Fix rs6000_emit_le_vsx_store (PR98549)
adds e140f5fd3e2 aarch64: Split vec_selects of bottom elements into simple move
adds 911f797a9be c++: Avoid UB in signed shift [PR 98625]
adds 0bb27b81a76 libgomp: Fix up GOMP_task on s390x
adds 842afc4e289 Re: trapv question
adds fb39c4fe445 aix: make ctype_inline.h thread-safe and avoid _OBJ_DATA ch [...]
adds b93d0e36c0a Daily bump.
adds e711b67a908 Fix incorrect optimization by cprop_hardreg.
adds fa9d1ad2ff6 testsuite/98224 - un-XFAIL Walloca-2.c on ilp32
adds 8afef308b49 testsuite/98241 - remove ilp32 XFAIL of gcc.dg/pr78973.c
adds f46a40112ca testsuite/97299 - more gcc.dg/vect/slp-reduc-3.c massaging
adds eaf883710c0 Fortran: This patch fixes comments 23 and 24 of PR96320.
adds a1a967ce1ff libstdc++: Regenerate Makefile.in
adds 3c1cf7350bf c++: Stat-hack for members [PR 98530]
adds 9be0a89c95c gcc/fortran/intrinsic.texi: Fix typo
adds 0568f801eff arm: [testuiste] Fix ivopts.c target test [PR96372]
adds e154009f35a Fix typo in arm_mve.h __arm_vcmpneq_s8 return type
adds 279d3a89b79 d: Enable private member access for __traits
adds 43705f3fa34 aarch64: Use canonical RTL for sqdmlal patterns
adds 0fb7aa205af c++: Fix up potential_constant_expression_1 FOR/WHILE_STMT [...]
adds 7944753fad5 c++: Fix null this pointer [PR 98624]
adds f645da0e4ab c++: Fix excessive instantiation inside decltype [PR71879]
adds efb6bc55a93 fwprop: Allow (subreg (mem)) simplifications
adds 68ba1039c7d [PR98777] LRA: Use preliminary created pseudo for in LRA el [...]
adds 9929d04ee24 testsuite: Adjust cpp2a/lambda-uneval regrex
adds 7559d465fda Daily bump.
adds 070a1fb5f52 MAINTAINERS: Update my e-mail address
adds bca467e56fe c++: ICE with delayed noexcept and attribute used [PR97966]
adds ee78c20e74d Lower AVX512 vector comparison to AVX version when dest is vector.
adds 4e3beaca15c arm: Fix ICE with incompatible values for -mfp16-format [PR98636].
adds fd61ca67f97 tree-optimization/98786 - fix issue with phiopt and abnormals
adds e287a2a11d7 on ARRAY_REFs sign-extend offsets only from sizetype's prec [...]
adds 36fe1cdc953 match.pd: Replace incorrect simplifications into copysign [ [...]
adds 8bad25eb56b middle-end/98773 - always sign extend CHREC_RIGHT
adds 4804de453e7 driver: do not check file existence here [PR 98452]
adds b46027c6544 Drop time profile for multi-threaded training run.
adds b2922559758 rs6000: Support variable insert and Expand vec_insert in ex [...]
adds e3a8ef8ef2a rs6000: Enable vec_insert for P8 with rs6000_expand_vector_ [...]
adds 4be156d6bef middle-end/98793 - properly handle BLKmode vectors in vecto [...]
adds eee8ed2f22b testsuite: Uniquify test names [PR 98795]
adds 9d33785f57d tree-ssa-mathopts: Use proper poly_int64 comparison with pa [...]
adds d7e681fc3af Testcase for old PR 47059
adds bf8ee9e4eed Fortran: Fix for class functions as associated target [PR98565].
adds 25fc4d01a8e c++: ICE when mangling operator name [PR98545]
adds a9ed18295bf c++: Fix up ubsan false positives on references [PR95693]
adds 90cbc769006 c++: Fix base copy elision thinko [PR98744]
adds 32a93eac7ad MAINTAINERS: Add myself for write after approval
adds b485fa167ef dwarf2out: Always emit required 0 entries for DWARF 5 in *. [...]
adds d08677c11dc testsuite: Fix sse2-andnpd-1.c and sse-andnps-1.c testscase [...]
adds b30e19b517f testsuite: Fix a typo - UINON_TYPE to UNION_TYPE - in gcc.t [...]
adds 70ab52b8caf testsuite: Fix a typo - UINON_TYPE to UNION_TYPE - in gcc.t [...]
adds 9cead790738 doc: ensure GCC_EXTRA_DIAGNOSTIC_OUTPUT gets an HTML anchor
adds ab8cde87cac testsuite: Enable spbp.C on AIX.
adds 89100826ace c++: ICE with noexcept in class in member function [PR96623]
adds 16b7b8a32d4 aarch64: Use RTL builtins for integer mla intrinsics
adds 8502e23d1f2 Daily bump.
adds eb9883c1312 testsuite: fix gcc.target/powerpc ilp32 failures
adds a8cef3cba69 c++: 'this' injection and static member functions [PR97399]
adds c63f091db89 rs6000: Fix up __m64 typedef in mmintrin.h [PR97301]
adds 7e0f147a29f c++: private inheritance access diagnostics fix [PR17314]
adds 81f928ec8e8 libphobos: Fix executables segfault on mipsel architecture
adds 6b1633378b7 Daily bump.
adds 02551aa9996 Daily bump.
adds 389b67feac7 Arm: Add NEON and MVE complex mul, mla and mls patterns.
adds b7a0507ad9f fold: Fix up strn{case,}cmp folding [PR98771]
adds 28229916e1b RTEMS: Fix GCC specification
adds c6b0e33febb Fortran: Fix deferred character lengths in array constructo [...]
adds 5d01fc7c116 Fix internal error on extension with interface at -O2
adds 0433fc2d7d4 RTEMS: Fix default linker script
adds defc40db9e0 middle-end/98807 - more vector_element_bits fixes
adds 5089df534b8 Restore profile reproducibility.
adds e05a117dc4b Enable -fprofile-reproducible=parallel-runs for profiledbootstrap.
adds fe5cb7f94d4 configure: Add workaround for buggy binutils 2.35 [PR98811]
adds 10c83fb7131 gcc/fortran/intrinsic.texi: Fix typos
adds 94ff4c9dd98 c++: [[no_unique_address]] in empty base [PR98463]
adds d9ad3b422f0 Fix wrong format for fprintf.
adds 0194e2f02d7 libgomp: Add documentation for omp_fulfill_event runtime function
adds a43e0dfb63f Add test case for PR 96843.
adds 7d54cccad33 Commit test case for PR 96386.
adds d6f1cf644c4 PR c++/98646 - spurious -Wnonnull calling a member on the r [...]
adds a61efd46937 PR fortran/70070 - ICE on initializing character data beyon [...]
adds 161e4c08624 Daily bump.
adds 667c8e33270 skip asan-poisoning of discarded vars
adds 7423731691e dwarf2asm: Fix up -gdwarf-64 for 32-bit targets
adds eb77a934eec testsuite: Fix up pr98807.c on i686-linux [PR98807]
adds 5a36cae275a d: Merge upstream dmd 609c3ce2d, phobos 3dd5df686
adds d9f50366102 amdgcn: Allow V64DFmode min/max reductions
adds b3cc0c9a6ac testsuite/g++.dg/modules/modules.exp: Janitorial fixes
adds 80198c701a7 Commit test case for PR 67539.
adds d40b21eebc9 libgcov: improve profile reproducibility
adds 2e81b16c243 liblsan: build missing lsan_posix.cpp file
adds 4b59dbb5d67 middle-end/98726 - fix VECTOR_CST element access
adds 5bbc80d0e40 Fix dumping of VEC_WIDEN_{PLUS,MINUS}_{LO,HI}_EXPR
adds 17ad8cdebe6 aarch64: Tighten up checks for ubfix [PR98681]
adds 6e44c09b2df dwarf2asm: Fix bootstrap on powerpc*-*-* [PR98839]
adds 9c41bcc59c2 Fix PR ada/98228
adds e80f1f6b7a3 testsuite: Fix TBAA in sse*and*p[sd]*.c tests
adds a4dfd0f089a c++: constexpr and empty fields [PR97566]
adds 96253f069ea c++: Invisible refs are not restrict [PR97474]
adds 78739c2df78 c++: Add support for -std=c++23
adds e62bb7f0834 Daily bump.
adds efc9ccbfd0c varpool: Restore GENERIC TREE_READONLY automatic var optimi [...]
adds da5c25f3710 Rename PROP_trees to PROP_gimple
adds 003f0414291 Fortran: Fix ICE due to elemental procedure pointers [PR98472].
adds 6cf43433750 testsuite: Fix TBAA in {sse,avx}*and*p[sd]*.c tests
adds 530b1d68876 Fix ICE for [PR target/98833].
adds 686b1cdfdc4 libgcc, i386: Add .note.GNU-stack sections to the ms sse/av [...]
adds 4225af228b5 Fortran: Fix ICE due to elemental procedure pointers [PR93924/5].
adds f004d6d9fab libstdc++: Add string contains member functions for C++2b
adds 9d66505a5df aarch64: Use RTL builtins for integer mla_n intrinsics
adds a199da782fc libstdc++: Optimize std::string_view::find [PR 66414]
adds d2201ac0df4 aarch64: Use RTL builtins for integer mls intrinsics
adds 3fd10728cb1 aarch64: Use RTL builtins for integer mls_n intrinsics
adds c91db798ec6 tree-optimization/98854 - avoid some PHI BB vectorization
adds 2bcceb6fc59 libstdc++: Add std::experimental::simd from the Parallelism TS 2
adds 02e32295b28 libstdc++: Add simd testsuite
adds c31a633e13f libstdc++: Use printf to print control characters
adds d53a4f9b681 aarch64: Use RTL builtins for [su]mlal intrinsics
adds 3670dbe4905 libstdc++: Regenerate libstdc++ HTML docs
adds 7a279bed24e Combine patterns for p10 load-cmpi fusion
adds 55163419211 aarch64: Fix up *aarch64_bfxilsi_uxtw [PR98853]
adds 9cd7c32549f c++: Dependent using enum [PR97874]
adds 081c96621da [PR97684] IRA: Recalculate pseudo classes if we added new p [...]
adds 1cdca4261e8 Fix strides for C descriptors with stride > 2.
adds aa69f0a8203 Daily bump.
adds f76d0d86454 RISC-V: Fix -march option parsing when extension exists.
adds fbe37371cf3 rs6000: Fix vec insert ilp32 ICE and test failures [PR98799]
adds a523add327c rtl-optimization/80960 - avoid creating garbage RTL in DSE
adds c392d040f6c c++: Some C++20 and C++23 option help fixes
adds 33a7a93218b PR fortran/86470 - ICE with OpenMP, class(*) allocatable
adds f7a6d314e7f Fix LTO bootstrap on Windows
adds fdb904a1822 aarch64: Reimplement vshrn_n* intrinsics using builtins
adds d61ca09ec93 aarch64: Reimplement vshrn_high_n* intrinsics using builtins
adds af66f4f1b06 c++: header unit template alias merging [PR 98770]
adds 87301e3956d aarch64: Use RTL builtins for [su]mlal_n intrinsics
adds ff119f340e4 aarch64: Fix gcc.target/aarch64/narrow_high-intrinsics.c testism
adds 8a8e515c2bf aarch64: Use RTL builtins for [su]mlsl_n intrinsics
adds 6bb207b468d c++: Fix up handling of register ... asm ("...") vars in te [...]
adds e11e5d3889f Map long double built-ins correctly with IEEE 128-bit long double.
adds e28bd09498b testsuite: Fix up a testcase to find the right ISO_Fort [...]
adds 31a0ab9213f arm: Adjust cost of vector of constant zero
adds a054608c9c4 libstdc++: Fix copyright dates for simd headers and tests
adds 513ee7d2cd9 tree: Don't reuse types if TYPE_USER_ALIGN differ [PR94775]
adds 850a8ec54c4 c++: Fix -Weffc++ in templates [PR98841]
adds e6bce7fe17b gccgo driver: always act as though -g is passed
adds 85d04a2ecb7 Daily bump.
adds f8f5388c9e9 c++: Fix infinite looping with invalid operator [PR96137]
adds 280a59d9211 testsuite: Run vec_insert case on P8 and P9 with option specified
adds 9c445c07cda expand: Fix up find_bb_boundaries [PR98331]
adds e7429bc9d60 arm: Fix up -mcpu=iwmmxt ICEs [PR98849]
adds a8c455bafde rtl-optimization/98144 - tame REE memory usage
adds f4e426f7bd7 tree-optimization/97627 - Avoid computing niters for fake edges
adds cb52e59e338 rtl-optimization/98863 - fix PRE/CPROP memory usage check
adds 0833e3e1ff1 change unit of --param max-gcse-memory to kB
adds e053f96a9f5 aarch64: Use RTL builtins for [su]mlsl_lane[q] intrinsics
adds cb995de62aa aarch64: Reimplement vaddlv* intrinsics using builtins
adds d5e0d1f1d2c aarch64: Reimplement vabal* intrinsics using builtins
adds 9f499a86b29 aarch64: Re-implement vabal_high* intrinsics using builtins
adds 9b588cfb428 aarch64: Reimplement vabdl_high* intrinsics using builtins
adds ee4c4fe289e aarch64: Use RTL builtins for [su]mull_n intrinsics
adds a7f52181a6a rtl-optimization/98863 - tame i386 specific RPAD pass
adds 2dd1f944547 tree-optimization/98866 - Compile time hog in VRP
adds 83bdc9f7034 c++: Fix unordered entity array [PR 98843]
adds 91a95ad2ae0 [PATCH, rs6000] improve vec_ctf invalid parameter handling.
adds 726b7aa004d libgo: update to Go1.16rc1
adds 7f9f83ef300 [PR97701] LRA: Don't narrow class only for REG or MEM.
adds eb06fdd424b analyzer: consolidate conditionals in paths
adds 0202fa3d635 [PR97701] Modify test for trunk
adds fa00e35c178 [PATCH, rs6000] Fix typo in gcc.target/pr91903.c dg-require stanza
adds d761172d9b2 PR testsuite/98870: Fix IEEE 128-bit fortran test
adds 4d31df40899 internal/cpu: correctly link to getsystemcfg
adds 2900f2f2c5f Daily bump.
adds 25f303e9a27 testsuite: Fix up gomp/simd-{2,3}.c tests [PR98243]
adds accc5ba53e0 i386, df: Fix up gcc.c-torture/compile/20051216-1.c -O1 -ma [...]
adds 92dd3e71f95 libphobos: Synchronize libdruntime bindings with upstream druntime
adds 2e7750cb518 aix: Permit use of AIX Vector extended ABI mode
adds 349b909bb35 aix: add periods to option explanation.
adds 1242eb75b3d Fusion patterns for logical-logical
adds 245ccc8e6b1 testsuite: Update pr79251 ilp32 store counts.
adds 5dfbad4f7c4 Daily bump.
adds 98342bdd2b7 testsuite, Darwin : Skip ELF-specific tests.
adds 2b5af103482 Add missing definition of SIZE_MAX
adds 94d5ba26f93 Daily bump.
adds b90d051ecbc testsuite: Update pr79251 ilp32 store regex
adds 972918eea87 rtl-optimization/98863 - prune RD with LIVE in STV
adds bbe6998b227 RISC-V: Fix gcc.target/riscv/attribute-18.c
adds 1b303ef6cc8 c++: Add testcase for PR84494
adds 0a3eccb6ef9 AArch64: Change canonization of smlal and smlsl in order to [...]
adds 8db8a004762 testsuite: aarch64: Add tests for vmull_high intrinsics
adds bec5dbae564 testsuite: aarch64: Add tests for vmlXl_high intrinsics
adds 6e0a231a4aa c++: alias in qualified-id in template arg [PR98570]
adds bab669f2fc6 c++: Improve sorry for __builtin_has_attribute [PR98355]
adds 7e534fb7d82 c++: Fix ICE from verify_ctor_sanity [PR98295]
adds c2f8e378d64 Verify a warning for a class with a ref-qualified assignmen [...]
adds d7bd009ab00 Fix statistic accounting for auto_vec and auto_bitmap
adds 445d6db6490 Avoid -Wstringop-truncation.
adds 90c9b2c1768 libstdc++: Update C++17 status table for <charconv>
adds 0718336a528 Reset front end trees before they make it into the middle e [...]
adds 6a2053773b8 Document various BLOCK macros.
adds 6b2034c479e aarch64: Reimplement vabdl_* intrinsics using builtins
adds 8bfdf51d859 aarch64: Reimplement vmovl_high_* intrinsics using builtins
adds 11056ab7687 tree-optimization/98499 - fix modref analysis on RVO statements
adds 33a1e511b57 libstdc++: Make deque iterator operator- usable with value- [...]
adds 11d4ec5d45c analyzer: fix false positives with *UNKNOWN_PTR [PR98918]
adds 850e5878f8f aarch64: Reimplement vrshrn* intrinsics using builtins
adds f7884fb1761 Daily bump.
adds 6a481021a65 d: Fix junk in generated symbol on powerpc64-*-* [PR98921]
adds f2f639c4a78 analyzer: add more feasibility test cases [PR93355,PR96374]
adds 8a2750086d5 analyzer: directly explore within static functions [PR93355 [...]
adds 78811355689 restore current_function_decl after re-gimplifying nested A [...]
adds 250fd9fb118 arm: Auto-vectorization for MVE: vorn
adds bc7c2b34c34 PR target/98743: Fix ICE in convert_move for RISC-V
adds eedda4e1608 testsuite: Add testcase for already fixed PR [PR97960]
adds 1592b74350a tree-vect-patterns: Don't create over widening patterns for [...]
adds 886f9f519c0 libstdc++: Fix markup for status tables in docs
adds 7bcd5e09fb3 aarch64: Relax builtin flags for integer builtins
adds 5cebc818213 aarch64: Relax some builtins to AUTO_FP
adds e8062ad4680 aarch64: Add and use FLAG_LOAD in builtins
adds 4b8a7a6e81b aarch64: Relax flags for floating-point builtins to FP wher [...]
adds 13d8be91218 aarch64: Update flags for bfloat16 builtins
adds 831ff94a882 Fortran: Check remains fixed by patch for PRs 96100/101 [PR91862].
adds 8fdfd0cfdb7 aarch64: Reimplement vqmovun_high* intrinsics using builtins
adds d14cf89b942 aarch64: Reimplement vrsqrte* intrinsics with builtins
adds 709718d4d89 c++: Member fns and deduction guide rewriting [PR98929]
adds db53dd4f784 Add test-case.
adds 5d5130ad5c3 fix memory leaks
adds 8e4a738d254 gotools: for "make check" run "go test embed/internal/embedtest"
No new revisions were added by this update.
Summary of changes:
ChangeLog | 40 +
MAINTAINERS | 12 +-
Makefile.def | 5 +-
Makefile.in | 44 +-
c++tools/ChangeLog | 16 +-
c++tools/Makefile.in | 3 +-
c++tools/configure | 211 +
c++tools/configure.ac | 10 +
c++tools/resolver.cc | 4 +-
config/ChangeLog | 9 +
config/ax_lib_socket_nsl.m4 | 40 +
config/pkg.m4 | 275 +
contrib/ChangeLog | 62 +
contrib/compare-lto | 21 +-
contrib/gcc-changelog/git_commit.py | 74 +-
contrib/gcc-changelog/git_email.py | 6 +-
contrib/gcc-changelog/git_repository.py | 6 +-
contrib/gcc-changelog/test_email.py | 15 +-
contrib/gcc-changelog/test_patches.txt | 82 +
contrib/mklog.py | 82 +-
contrib/test_mklog.py | 42 +
contrib/update-copyright.py | 29 +-
gcc/ABOUT-GCC-NLS | 2 +-
gcc/ChangeLog | 2589 ++++
gcc/DATESTAMP | 2 +-
gcc/LANGUAGES | 2 +-
gcc/Makefile.in | 23 +-
gcc/README.Portability | 2 +-
gcc/acinclude.m4 | 2 +-
gcc/aclocal.m4 | 1 +
gcc/ada/ChangeLog | 30 +
gcc/ada/Makefile.rtl | 5 +
gcc/ada/gcc-interface/trans.c | 35 +-
gcc/ada/gcc-interface/utils.c | 14 +-
gcc/ada/gnatvsn.ads | 2 +-
gcc/addresses.h | 2 +-
gcc/adjust-alignment.c | 2 +-
gcc/alias.c | 49 +-
gcc/alias.h | 2 +-
gcc/align.h | 2 +-
gcc/alloc-pool.c | 2 +-
gcc/alloc-pool.h | 2 +-
gcc/analyzer/ChangeLog | 197 +-
gcc/analyzer/analysis-plan.cc | 2 +-
gcc/analyzer/analysis-plan.h | 2 +-
gcc/analyzer/analyzer-logging.cc | 2 +-
gcc/analyzer/analyzer-logging.h | 2 +-
gcc/analyzer/analyzer-pass.cc | 2 +-
gcc/analyzer/analyzer-selftests.cc | 2 +-
gcc/analyzer/analyzer-selftests.h | 2 +-
gcc/analyzer/analyzer.cc | 2 +-
gcc/analyzer/analyzer.h | 5 +-
gcc/analyzer/analyzer.opt | 2 +-
gcc/analyzer/bar-chart.cc | 2 +-
gcc/analyzer/bar-chart.h | 2 +-
gcc/analyzer/call-string.cc | 2 +-
gcc/analyzer/call-string.h | 2 +-
gcc/analyzer/checker-path.cc | 28 +-
gcc/analyzer/checker-path.h | 57 +-
gcc/analyzer/complexity.cc | 2 +-
gcc/analyzer/complexity.h | 2 +-
gcc/analyzer/constraint-manager.cc | 2 +-
gcc/analyzer/constraint-manager.h | 2 +-
gcc/analyzer/diagnostic-manager.cc | 163 +-
gcc/analyzer/diagnostic-manager.h | 3 +-
gcc/analyzer/engine.cc | 100 +-
gcc/analyzer/engine.h | 2 +-
gcc/analyzer/exploded-graph.h | 6 +-
gcc/analyzer/function-set.cc | 2 +-
gcc/analyzer/function-set.h | 2 +-
gcc/analyzer/pending-diagnostic.cc | 2 +-
gcc/analyzer/pending-diagnostic.h | 4 +-
gcc/analyzer/program-point.cc | 2 +-
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gcc/analyzer/program-state.cc | 2 +-
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gcc/analyzer/reachability.h | 2 +-
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gcc/analyzer/region-model-manager.cc | 15 +-
gcc/analyzer/region-model-reachability.cc | 38 +-
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gcc/analyzer/region.cc | 7 +-
gcc/analyzer/region.h | 2 +-
gcc/analyzer/sm-file.cc | 2 +-
gcc/analyzer/sm-malloc.cc | 769 +-
gcc/analyzer/sm-malloc.dot | 2 +-
gcc/analyzer/sm-pattern-test.cc | 2 +-
gcc/analyzer/sm-sensitive.cc | 2 +-
gcc/analyzer/sm-signal.cc | 2 +-
gcc/analyzer/sm-taint.cc | 2 +-
gcc/analyzer/sm.cc | 2 +-
gcc/analyzer/sm.h | 2 +-
gcc/analyzer/state-purge.cc | 2 +-
gcc/analyzer/state-purge.h | 2 +-
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gcc/analyzer/store.h | 8 +-
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gcc/analyzer/supergraph.h | 2 +-
gcc/analyzer/svalue.cc | 18 +-
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gcc/array-traits.h | 2 +-
gcc/asan.c | 2 +-
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gcc/brig/brig-c.h | 2 +-
gcc/brig/brig-lang.c | 2 +-
gcc/brig/brigfrontend/brig-arg-block-handler.cc | 2 +-
gcc/brig/brigfrontend/brig-atomic-inst-handler.cc | 2 +-
gcc/brig/brigfrontend/brig-basic-inst-handler.cc | 2 +-
gcc/brig/brigfrontend/brig-branch-inst-handler.cc | 2 +-
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gcc/brig/brigfrontend/brig-mem-inst-handler.cc | 2 +-
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gcc/brig/brigfrontend/brig-queue-inst-handler.cc | 2 +-
gcc/brig/brigfrontend/brig-seg-inst-handler.cc | 2 +-
gcc/brig/brigfrontend/brig-signal-inst-handler.cc | 2 +-
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gcc/brig/brigfrontend/brig-variable-handler.cc | 2 +-
gcc/brig/brigfrontend/hsa-brig-format.h | 2 +-
gcc/brig/brigfrontend/phsa.h | 2 +-
gcc/brig/brigspec.c | 2 +-
gcc/brig/config-lang.in | 2 +-
gcc/brig/gccbrig.texi | 2 +-
gcc/brig/lang-specs.h | 2 +-
gcc/brig/lang.opt | 2 +-
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gcc/builtins.c | 247 +-
gcc/builtins.def | 2 +-
gcc/builtins.h | 2 +-
gcc/c-family/ChangeLog | 75 +-
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gcc/c-family/c-ada-spec.h | 2 +-
gcc/c-family/c-attribs.c | 43 +-
gcc/c-family/c-common.c | 4 +-
gcc/c-family/c-common.def | 2 +-
gcc/c-family/c-common.h | 6 +-
gcc/c-family/c-cppbuiltin.c | 2 +-
gcc/c-family/c-dump.c | 2 +-
gcc/c-family/c-format.c | 2 +-
gcc/c-family/c-format.h | 2 +-
gcc/c-family/c-gimplify.c | 2 +-
gcc/c-family/c-indentation.c | 2 +-
gcc/c-family/c-indentation.h | 2 +-
gcc/c-family/c-lex.c | 2 +-
gcc/c-family/c-objc.h | 2 +-
gcc/c-family/c-omp.c | 2 +-
gcc/c-family/c-opts.c | 31 +-
gcc/c-family/c-pch.c | 2 +-
gcc/c-family/c-ppoutput.c | 2 +-
gcc/c-family/c-pragma.c | 2 +-
gcc/c-family/c-pragma.h | 5 +-
gcc/c-family/c-pretty-print.c | 358 +-
gcc/c-family/c-pretty-print.h | 2 +-
gcc/c-family/c-semantics.c | 2 +-
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gcc/c-family/c-warn.c | 2 +-
gcc/c-family/c.opt | 28 +-
gcc/c-family/cppspec.c | 2 +-
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gcc/c-family/name-hint.h | 2 +-
gcc/c-family/stub-objc.c | 2 +-
gcc/c/ChangeLog | 28 +-
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gcc/c/c-convert.c | 2 +-
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gcc/c/c-parser.c | 59 +-
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gcc/c/c-typeck.c | 64 +-
gcc/c/config-lang.in | 2 +-
gcc/c/gccspec.c | 2 +-
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gcc/caller-save.c | 2 +-
gcc/calls.c | 2 +-
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gcc/ccmp.c | 2 +-
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gcc/cfg-flags.def | 2 +-
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gcc/cfgbuild.c | 3 +-
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gcc/cgraph.c | 6 +-
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gcc/cgraphunit.c | 4 +-
gcc/cif-code.def | 2 +-
gcc/collect-utils.c | 4 +-
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gcc/collect2-aix.c | 2 +-
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gcc/collect2.c | 45 +-
gcc/collect2.h | 2 +-
gcc/color-macros.h | 2 +-
gcc/combine-stack-adj.c | 2 +-
gcc/combine.c | 2 +-
gcc/common.md | 2 +-
gcc/common.opt | 6 +-
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gcc/testsuite/g++.old-deja/g++.law/visibility12.C | 7 +-
gcc/testsuite/g++.old-deja/g++.law/visibility4.C | 5 +-
gcc/testsuite/g++.old-deja/g++.law/visibility8.C | 5 +-
gcc/testsuite/g++.old-deja/g++.other/access4.C | 4 +-
gcc/testsuite/g++.old-deja/g++.robertl/README | 2 +-
gcc/testsuite/g++.old-deja/old-deja.exp | 2 +-
gcc/testsuite/g++.target/aarch64/aarch64.exp | 2 +-
.../g++.target/aarch64/sve/aarch64-sve.exp | 2 +-
gcc/testsuite/g++.target/aarch64/sve/abd_1.C | 38 +
.../aarch64/sve/acle/aarch64-sve-acle-asm.exp | 2 +-
.../aarch64/sve/acle/aarch64-sve-acle.exp | 2 +-
gcc/testsuite/g++.target/aarch64/sve/cond_abd_1.C | 60 +
gcc/testsuite/g++.target/aarch64/sve/cond_abd_2.C | 60 +
gcc/testsuite/g++.target/aarch64/sve/cond_abd_3.C | 49 +
gcc/testsuite/g++.target/aarch64/sve/cond_abd_4.C | 43 +
.../g++.target/aarch64/sve/cond_arith_1.C | 89 +
.../g++.target/aarch64/sve/cond_arith_2.C | 89 +
.../g++.target/aarch64/sve/cond_arith_3.C | 91 +
.../g++.target/aarch64/sve/cond_arith_4.C | 91 +
gcc/testsuite/g++.target/aarch64/sve/cond_bic_1.C | 40 +
gcc/testsuite/g++.target/aarch64/sve/cond_bic_2.C | 31 +
gcc/testsuite/g++.target/aarch64/sve/cond_bic_3.C | 36 +
gcc/testsuite/g++.target/aarch64/sve/cond_bic_4.C | 36 +
gcc/testsuite/g++.target/aarch64/sve/cond_mla_1.C | 33 +
gcc/testsuite/g++.target/aarch64/sve/cond_mla_2.C | 33 +
gcc/testsuite/g++.target/aarch64/sve/cond_mla_3.C | 33 +
gcc/testsuite/g++.target/aarch64/sve/cond_mla_4.C | 36 +
gcc/testsuite/g++.target/aarch64/sve/cond_mla_5.C | 33 +
gcc/testsuite/g++.target/aarch64/sve/cond_mls_1.C | 33 +
gcc/testsuite/g++.target/aarch64/sve/cond_mls_2.C | 33 +
gcc/testsuite/g++.target/aarch64/sve/cond_mls_3.C | 33 +
gcc/testsuite/g++.target/aarch64/sve/cond_mls_4.C | 36 +
gcc/testsuite/g++.target/aarch64/sve/cond_mls_5.C | 33 +
.../g++.target/aarch64/sve/cond_shift_1.C | 92 +
.../g++.target/aarch64/sve/cond_shift_2.C | 91 +
.../g++.target/aarch64/sve/cond_shift_3.C | 94 +
.../g++.target/aarch64/sve/cond_shift_4.C | 94 +
gcc/testsuite/g++.target/aarch64/sve/max_1.C | 73 +
gcc/testsuite/g++.target/aarch64/sve/min_1.C | 73 +
.../aarch64/sve2/acle/aarch64-sve2-acle-asm.exp | 4 +-
gcc/testsuite/g++.target/arm/arm.exp | 2 +-
gcc/testsuite/g++.target/arm/mve.exp | 2 +-
gcc/testsuite/g++.target/i386/avx512f-pr96891-1.C | 37 +
gcc/testsuite/g++.target/i386/i386.exp | 2 +-
gcc/testsuite/g++.target/i386/pr98847.C | 20 +
gcc/testsuite/g++.target/msp430/msp430.exp | 2 +-
gcc/testsuite/g++.target/nios2/nios2.exp | 2 +-
gcc/testsuite/g++.target/powerpc/powerpc.exp | 2 +-
gcc/testsuite/g++.target/riscv/riscv.exp | 2 +-
gcc/testsuite/g++.target/s390/pr98722.C | 12 +
gcc/testsuite/g++.target/s390/s390.exp | 2 +-
gcc/testsuite/g++.target/xtensa/xtensa.exp | 2 +-
gcc/testsuite/gcc.c-torture/compile/asmgoto-2.c | 1 +
gcc/testsuite/gcc.c-torture/compile/asmgoto-5.c | 1 +
gcc/testsuite/gcc.c-torture/compile/compile.exp | 2 +-
gcc/testsuite/gcc.c-torture/compile/pr97144.c | 24 +
gcc/testsuite/gcc.c-torture/compile/pr98629.c | 11 +
gcc/testsuite/gcc.c-torture/compile/pr98849.c | 60 +
.../gcc.c-torture/execute/builtins/builtins.exp | 2 +-
gcc/testsuite/gcc.c-torture/execute/execute.exp | 2 +-
gcc/testsuite/gcc.c-torture/execute/ieee/ieee.exp | 2 +-
gcc/testsuite/gcc.c-torture/execute/pr95731.c | 40 +
gcc/testsuite/gcc.c-torture/execute/pr98681.c | 18 +
gcc/testsuite/gcc.c-torture/execute/pr98727.c | 20 +
gcc/testsuite/gcc.c-torture/execute/pr98853-1.c | 21 +
gcc/testsuite/gcc.c-torture/execute/pr98853-2.c | 19 +
gcc/testsuite/gcc.c-torture/unsorted/unsorted.exp | 2 +-
gcc/testsuite/gcc.dg-selftests/dg-final.exp | 2 +-
gcc/testsuite/gcc.dg/README | 2 +-
gcc/testsuite/gcc.dg/Walloca-2.c | 6 +-
gcc/testsuite/gcc.dg/Wfree-nonheap-object-4.c | 107 +
gcc/testsuite/gcc.dg/Wstrict-overflow-25.c | 2 +-
gcc/testsuite/gcc.dg/Wvla-larger-than-4.c | 6 +-
gcc/testsuite/gcc.dg/analyzer/alloca-leak.c | 4 +-
gcc/testsuite/gcc.dg/analyzer/analyzer.exp | 2 +-
gcc/testsuite/gcc.dg/analyzer/attr-malloc-1.c | 75 +
gcc/testsuite/gcc.dg/analyzer/attr-malloc-2.c | 24 +
gcc/testsuite/gcc.dg/analyzer/attr-malloc-4.c | 21 +
gcc/testsuite/gcc.dg/analyzer/attr-malloc-5.c | 12 +
gcc/testsuite/gcc.dg/analyzer/attr-malloc-6.c | 228 +
.../analyzer/attr-malloc-CVE-2019-19078-usb-leak.c | 224 +
.../gcc.dg/analyzer/attr-malloc-misuses.c | 18 +
.../gcc.dg/analyzer/combined-conditionals-1.c | 55 +
gcc/testsuite/gcc.dg/analyzer/conditionals-3.c | 8 +-
gcc/testsuite/gcc.dg/analyzer/data-model-1.c | 9 +-
gcc/testsuite/gcc.dg/analyzer/feasibility-1.c | 26 +
gcc/testsuite/gcc.dg/analyzer/malloc-1.c | 3 +-
gcc/testsuite/gcc.dg/analyzer/malloc-paths-8.c | 7 +-
gcc/testsuite/gcc.dg/analyzer/params.c | 4 +-
.../analyzer/pr93355-localealias-feasibility-2.c | 31 +
.../analyzer/pr93355-localealias-feasibility-3.c | 64 +
gcc/testsuite/gcc.dg/analyzer/pr94851-1.c | 3 +-
gcc/testsuite/gcc.dg/analyzer/pr96651-2.c | 4 +-
gcc/testsuite/gcc.dg/analyzer/pr97072.c | 9 +
gcc/testsuite/gcc.dg/analyzer/pr97074.c | 32 +
gcc/testsuite/gcc.dg/analyzer/pr98073.c | 13 +
gcc/testsuite/gcc.dg/analyzer/pr98293.c | 2 +
gcc/testsuite/gcc.dg/analyzer/pr98564.c | 6 +
gcc/testsuite/gcc.dg/analyzer/pr98580-a.c | 9 +
gcc/testsuite/gcc.dg/analyzer/pr98580-b.c | 2 +
gcc/testsuite/gcc.dg/analyzer/pr98628.c | 19 +
gcc/testsuite/gcc.dg/analyzer/pr98918.c | 22 +
gcc/testsuite/gcc.dg/analyzer/sensitive-1.c | 5 +
gcc/testsuite/gcc.dg/analyzer/signal-4b.c | 18 +-
gcc/testsuite/gcc.dg/analyzer/sigsetjmp-5.c | 2 +-
gcc/testsuite/gcc.dg/analyzer/sigsetjmp-6.c | 2 +-
gcc/testsuite/gcc.dg/analyzer/single-field.c | 8 +-
.../gcc.dg/analyzer/torture/analyzer-torture.exp | 2 +-
.../gcc.dg/analyzer/torture/conditionals-2.c | 8 +-
gcc/testsuite/gcc.dg/array-quals-1.c | 40 +-
gcc/testsuite/gcc.dg/asan/asan.exp | 2 +-
gcc/testsuite/gcc.dg/asan/nested-1.c | 24 +
gcc/testsuite/gcc.dg/atomic/atomic.exp | 2 +-
gcc/testsuite/gcc.dg/autopar/autopar.exp | 2 +-
gcc/testsuite/gcc.dg/charset/charset.exp | 2 +-
gcc/testsuite/gcc.dg/compat/compat.exp | 2 +-
gcc/testsuite/gcc.dg/compat/struct-layout-1.exp | 2 +-
gcc/testsuite/gcc.dg/cpp/assembl2.S | 2 +-
gcc/testsuite/gcc.dg/cpp/cpp.exp | 2 +-
gcc/testsuite/gcc.dg/cpp/trad/trad.exp | 2 +-
gcc/testsuite/gcc.dg/cpp/ucs.c | 4 +-
gcc/testsuite/gcc.dg/debug/debug.exp | 2 +-
gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-float.c | 10 +-
gcc/testsuite/gcc.dg/debug/dwarf2/dwarf2.exp | 2 +-
gcc/testsuite/gcc.dg/debug/dwarf2/inline6.c | 2 +-
gcc/testsuite/gcc.dg/debug/dwarf2/pr41445-7.c | 7 +-
gcc/testsuite/gcc.dg/debug/pr97714.c | 11 +
gcc/testsuite/gcc.dg/dfp/dfp.exp | 2 +-
gcc/testsuite/gcc.dg/dg.exp | 2 +-
gcc/testsuite/gcc.dg/fixed-point/fixed-point.exp | 2 +-
gcc/testsuite/gcc.dg/format/format.exp | 2 +-
gcc/testsuite/gcc.dg/goacc-gomp/goacc-gomp.exp | 2 +-
gcc/testsuite/gcc.dg/goacc/goacc.exp | 2 +-
gcc/testsuite/gcc.dg/gomp/gomp.exp | 2 +-
gcc/testsuite/gcc.dg/gomp/simd-2.c | 3 +-
gcc/testsuite/gcc.dg/gomp/simd-3.c | 3 +-
gcc/testsuite/gcc.dg/gomp/task-detach-1.c | 20 +
gcc/testsuite/gcc.dg/graphite/graphite.exp | 2 +-
gcc/testsuite/gcc.dg/hwasan/hwasan.exp | 2 +-
gcc/testsuite/gcc.dg/ipa/ipa.exp | 2 +-
gcc/testsuite/gcc.dg/ipa/pr98222.c | 19 +
gcc/testsuite/gcc.dg/lto/lto.exp | 2 +-
gcc/testsuite/gcc.dg/noncompile/noncompile.exp | 2 +-
gcc/testsuite/gcc.dg/params/params.exp | 2 +-
gcc/testsuite/gcc.dg/pch/pch.exp | 2 +-
.../gcc.dg/plugin/diagnostic-test-inlining-3.c | 3 +-
...w-locus-GCC_EXTRA_DIAGNOSTIC_OUTPUT-fixits-v1.c | 71 +
...w-locus-GCC_EXTRA_DIAGNOSTIC_OUTPUT-fixits-v2.c | 71 +
gcc/testsuite/gcc.dg/plugin/gil-1.c | 4 +-
gcc/testsuite/gcc.dg/plugin/plugin.exp | 4 +-
gcc/testsuite/gcc.dg/pr69047.c | 4 +-
gcc/testsuite/gcc.dg/pr78973.c | 2 +-
gcc/testsuite/gcc.dg/pr90248.c | 73 +
gcc/testsuite/gcc.dg/pr95582.c | 19 +
gcc/testsuite/gcc.dg/pr96674.c | 40 +
gcc/testsuite/gcc.dg/pr97172.c | 50 +
gcc/testsuite/gcc.dg/pr98029.c | 21 +
gcc/testsuite/gcc.dg/pr98255.c | 49 +
gcc/testsuite/gcc.dg/pr98330.c | 7 +
gcc/testsuite/gcc.dg/pr98331.c | 18 +
gcc/testsuite/gcc.dg/pr98721-1.c | 14 +
gcc/testsuite/gcc.dg/pr98721-2.c | 8 +
gcc/testsuite/gcc.dg/pr98766.c | 12 +
gcc/testsuite/gcc.dg/pr98793.c | 38 +
gcc/testsuite/gcc.dg/pr98807.c | 35 +
gcc/testsuite/gcc.dg/rtl/rtl.exp | 2 +-
gcc/testsuite/gcc.dg/sancov/sancov.exp | 2 +-
.../gcc.dg/simulate-thread/simulate-thread.exp | 2 +-
gcc/testsuite/gcc.dg/special/mips-abi.exp | 2 +-
gcc/testsuite/gcc.dg/special/special.exp | 2 +-
gcc/testsuite/gcc.dg/sso/sso.exp | 2 +-
gcc/testsuite/gcc.dg/tls/tls.exp | 2 +-
gcc/testsuite/gcc.dg/tm/tm.exp | 2 +-
gcc/testsuite/gcc.dg/torture/ftrapv-2.c | 4 +-
gcc/testsuite/gcc.dg/torture/pr98640.c | 22 +
gcc/testsuite/gcc.dg/torture/pr98758.c | 13 +
gcc/testsuite/gcc.dg/torture/pr98773.c | 19 +
gcc/testsuite/gcc.dg/torture/pr98786.c | 23 +
.../gcc.dg/torture/stackalign/stackalign.exp | 2 +-
gcc/testsuite/gcc.dg/torture/tls/tls.exp | 2 +-
gcc/testsuite/gcc.dg/tree-prof/tree-prof.exp | 2 +-
.../gcc.dg/tree-ssa/builtin-sprintf-warn-20.c | 7 +-
gcc/testsuite/gcc.dg/tree-ssa/copy-sign-1.c | 2 +-
gcc/testsuite/gcc.dg/tree-ssa/pr47059.c | 45 +
gcc/testsuite/gcc.dg/tree-ssa/pr95731.c | 22 +
gcc/testsuite/gcc.dg/tree-ssa/pr95867.c | 14 +
gcc/testsuite/gcc.dg/tree-ssa/pr96239.c | 18 +
gcc/testsuite/gcc.dg/tree-ssa/pr96669-1.c | 59 +
gcc/testsuite/gcc.dg/tree-ssa/pr96669-2.c | 30 +
gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c | 51 +
gcc/testsuite/gcc.dg/tree-ssa/pr96671-2.c | 51 +
gcc/testsuite/gcc.dg/tree-ssa/pr96681.c | 35 +
gcc/testsuite/gcc.dg/tree-ssa/pr96688.c | 24 +
gcc/testsuite/gcc.dg/tree-ssa/pr96691.c | 21 +
gcc/testsuite/gcc.dg/tree-ssa/pr96782.c | 17 +
gcc/testsuite/gcc.dg/tree-ssa/pr96928.c | 38 +
gcc/testsuite/gcc.dg/tree-ssa/pr97260.c | 11 +
gcc/testsuite/gcc.dg/tree-ssa/pr98455.c | 19 +
gcc/testsuite/gcc.dg/tree-ssa/pr98513.c | 47 +
gcc/testsuite/gcc.dg/tree-ssa/reassoc-37.c | 2 +-
gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-54.c | 6 +-
gcc/testsuite/gcc.dg/tree-ssa/tree-ssa.exp | 2 +-
gcc/testsuite/gcc.dg/tsan/tsan.exp | 2 +-
gcc/testsuite/gcc.dg/ubsan/ubsan.exp | 2 +-
gcc/testsuite/gcc.dg/uninit-38.c | 87 +
gcc/testsuite/gcc.dg/uninit-39.c | 47 +
gcc/testsuite/gcc.dg/uninit-40.c | 50 +
gcc/testsuite/gcc.dg/uninit-pr98578.c | 110 +
gcc/testsuite/gcc.dg/vect/bb-slp-32.c | 1 +
gcc/testsuite/gcc.dg/vect/bb-slp-9.c | 2 +-
gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c | 20 -
gcc/testsuite/gcc.dg/vect/bb-slp-pr98516-1.c | 26 +
gcc/testsuite/gcc.dg/vect/bb-slp-pr98516-2.c | 36 +
gcc/testsuite/gcc.dg/vect/bb-slp-pr98544.c | 32 +
gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c | 15 +
gcc/testsuite/gcc.dg/vect/bb-slp-pr98854.c | 24 +
.../gcc.dg/vect/complex/complex-mla-template.c | 101 +
.../gcc.dg/vect/complex/complex-mls-template.c | 101 +
.../gcc.dg/vect/complex/complex-mul-template.c | 71 +
gcc/testsuite/gcc.dg/vect/complex/complex.exp | 2 +-
.../complex/fast-math-bb-slp-complex-mla-double.c | 9 +
.../complex/fast-math-bb-slp-complex-mla-float.c | 8 +
.../fast-math-bb-slp-complex-mla-half-float.c | 9 +
.../complex/fast-math-bb-slp-complex-mls-double.c | 9 +
.../complex/fast-math-bb-slp-complex-mls-float.c | 8 +
.../fast-math-bb-slp-complex-mls-half-float.c | 9 +
.../complex/fast-math-bb-slp-complex-mul-double.c | 9 +
.../complex/fast-math-bb-slp-complex-mul-float.c | 8 +
.../fast-math-bb-slp-complex-mul-half-float.c | 9 +
.../vect/complex/fast-math-complex-mla-double.c | 8 +
.../vect/complex/fast-math-complex-mla-float.c | 8 +
.../complex/fast-math-complex-mla-half-float.c | 8 +
.../vect/complex/fast-math-complex-mls-double.c | 8 +
.../vect/complex/fast-math-complex-mls-float.c | 8 +
.../complex/fast-math-complex-mls-half-float.c | 8 +
.../vect/complex/fast-math-complex-mul-double.c | 8 +
.../vect/complex/fast-math-complex-mul-float.c | 8 +
.../complex/fast-math-complex-mul-half-float.c | 8 +
.../vect/costmodel/i386/i386-costmodel-vect.exp | 2 +-
.../vect/costmodel/ppc/ppc-costmodel-vect.exp | 2 +-
.../costmodel/x86_64/x86_64-costmodel-vect.exp | 2 +-
gcc/testsuite/gcc.dg/vect/pr91403.c | 11 +
gcc/testsuite/gcc.dg/vect/pr92205.c | 2 +-
gcc/testsuite/gcc.dg/vect/pr98308.c | 16 +
gcc/testsuite/gcc.dg/vect/pr98560-1.c | 17 +
gcc/testsuite/gcc.dg/vect/pr98560-2.c | 17 +
gcc/testsuite/gcc.dg/vect/pr98674.c | 16 +
gcc/testsuite/gcc.dg/vect/pr98848.c | 18 +
gcc/testsuite/gcc.dg/vect/slp-11b.c | 12 +-
gcc/testsuite/gcc.dg/vect/slp-43.c | 4 +-
gcc/testsuite/gcc.dg/vect/slp-45.c | 2 +-
gcc/testsuite/gcc.dg/vect/slp-reduc-11.c | 20 +
gcc/testsuite/gcc.dg/vect/slp-reduc-3.c | 8 +-
gcc/testsuite/gcc.dg/vect/vect-reduc-in-order-4.c | 2 -
gcc/testsuite/gcc.dg/vect/vect.exp | 2 +-
gcc/testsuite/gcc.dg/vmx/vmx.exp | 2 +-
gcc/testsuite/gcc.dg/vxworks/vxworks.exp | 2 +-
gcc/testsuite/gcc.dg/weak/weak.exp | 2 +-
gcc/testsuite/gcc.misc-tests/acker1.exp | 2 +-
gcc/testsuite/gcc.misc-tests/arm-isr.exp | 2 +-
gcc/testsuite/gcc.misc-tests/bprob.exp | 2 +-
gcc/testsuite/gcc.misc-tests/dectest.exp | 2 +-
gcc/testsuite/gcc.misc-tests/dhry.exp | 2 +-
gcc/testsuite/gcc.misc-tests/gcov.exp | 2 +-
gcc/testsuite/gcc.misc-tests/godump.exp | 2 +-
gcc/testsuite/gcc.misc-tests/help.exp | 2 +-
gcc/testsuite/gcc.misc-tests/i386-prefetch.exp | 2 +-
gcc/testsuite/gcc.misc-tests/linkage.exp | 2 +-
gcc/testsuite/gcc.misc-tests/matrix1.exp | 2 +-
gcc/testsuite/gcc.misc-tests/mg-2.exp | 2 +-
gcc/testsuite/gcc.misc-tests/mg.exp | 2 +-
gcc/testsuite/gcc.misc-tests/options.exp | 2 +-
gcc/testsuite/gcc.misc-tests/output.exp | 2 +-
gcc/testsuite/gcc.misc-tests/outputs.exp | 48 +-
gcc/testsuite/gcc.misc-tests/sieve.exp | 2 +-
gcc/testsuite/gcc.misc-tests/sort2.exp | 2 +-
gcc/testsuite/gcc.src/maintainers.exp | 2 +-
.../gcc.target/aarch64/aapcs64/aapcs64.exp | 2 +-
gcc/testsuite/gcc.target/aarch64/aarch64.exp | 2 +-
gcc/testsuite/gcc.target/aarch64/acle/acle.exp | 2 +-
.../advsimd-intrinsics/advsimd-intrinsics.exp | 2 +-
.../aarch64/advsimd-intrinsics/arm-neon-ref.h | 67 -
.../aarch64/advsimd-intrinsics/binary_sat_op.inc | 43 +-
.../aarch64/advsimd-intrinsics/p64_p128.c | 46 +-
.../smlal-smlsl-mull-optimized.c | 45 +
.../aarch64/advsimd-intrinsics/unary_sat_op.inc | 21 +-
.../aarch64/advsimd-intrinsics/vmlXl_high.inc | 89 +
.../aarch64/advsimd-intrinsics/vmlXl_high_lane.inc | 71 +
.../advsimd-intrinsics/vmlXl_high_laneq.inc | 71 +
.../aarch64/advsimd-intrinsics/vmlXl_high_n.inc | 62 +
.../aarch64/advsimd-intrinsics/vmlal_high.c | 20 +
.../aarch64/advsimd-intrinsics/vmlal_high_lane.c | 16 +
.../aarch64/advsimd-intrinsics/vmlal_high_laneq.c | 16 +
.../aarch64/advsimd-intrinsics/vmlal_high_n.c | 16 +
.../aarch64/advsimd-intrinsics/vmlsl_high.c | 24 +
.../aarch64/advsimd-intrinsics/vmlsl_high_lane.c | 20 +
.../aarch64/advsimd-intrinsics/vmlsl_high_laneq.c | 20 +
.../aarch64/advsimd-intrinsics/vmlsl_high_n.c | 20 +
.../aarch64/advsimd-intrinsics/vmull_high.c | 78 +
.../aarch64/advsimd-intrinsics/vmull_high_lane.c | 69 +
.../aarch64/advsimd-intrinsics/vmull_high_laneq.c | 69 +
.../aarch64/advsimd-intrinsics/vmull_high_n.c | 61 +
.../gcc.target/aarch64/advsimd-intrinsics/vqabs.c | 29 +-
.../gcc.target/aarch64/advsimd-intrinsics/vqadd.c | 91 +-
.../aarch64/advsimd-intrinsics/vqdmlXl.inc | 17 +-
.../aarch64/advsimd-intrinsics/vqdmlXl_lane.inc | 21 +-
.../aarch64/advsimd-intrinsics/vqdmlXl_n.inc | 17 +-
.../aarch64/advsimd-intrinsics/vqdmlal.c | 9 -
.../aarch64/advsimd-intrinsics/vqdmlal_lane.c | 14 -
.../aarch64/advsimd-intrinsics/vqdmlal_n.c | 9 -
.../aarch64/advsimd-intrinsics/vqdmlsl.c | 9 -
.../aarch64/advsimd-intrinsics/vqdmlsl_lane.c | 14 -
.../aarch64/advsimd-intrinsics/vqdmlsl_n.c | 9 -
.../aarch64/advsimd-intrinsics/vqdmulh.c | 42 +-
.../aarch64/advsimd-intrinsics/vqdmulh_lane.c | 42 +-
.../aarch64/advsimd-intrinsics/vqdmulh_n.c | 42 +-
.../aarch64/advsimd-intrinsics/vqdmull.c | 30 +-
.../aarch64/advsimd-intrinsics/vqdmull_lane.c | 30 +-
.../aarch64/advsimd-intrinsics/vqdmull_n.c | 29 +-
.../gcc.target/aarch64/advsimd-intrinsics/vqmovn.c | 49 +-
.../aarch64/advsimd-intrinsics/vqmovun.c | 31 +-
.../gcc.target/aarch64/advsimd-intrinsics/vqneg.c | 29 +-
.../aarch64/advsimd-intrinsics/vqrdmlXh.inc | 42 +-
.../aarch64/advsimd-intrinsics/vqrdmlXh_lane.inc | 45 +-
.../aarch64/advsimd-intrinsics/vqrdmlah.c | 20 -
.../aarch64/advsimd-intrinsics/vqrdmlah_lane.c | 20 -
.../aarch64/advsimd-intrinsics/vqrdmlsh.c | 20 -
.../aarch64/advsimd-intrinsics/vqrdmlsh_lane.c | 20 -
.../aarch64/advsimd-intrinsics/vqrdmulh.c | 57 +-
.../aarch64/advsimd-intrinsics/vqrdmulh_lane.c | 65 +-
.../aarch64/advsimd-intrinsics/vqrdmulh_n.c | 65 +-
.../gcc.target/aarch64/advsimd-intrinsics/vqrshl.c | 521 +-
.../aarch64/advsimd-intrinsics/vqrshrn_n.c | 74 +-
.../aarch64/advsimd-intrinsics/vqrshrun_n.c | 72 +-
.../gcc.target/aarch64/advsimd-intrinsics/vqshl.c | 376 +-
.../aarch64/advsimd-intrinsics/vqshl_n.c | 117 +-
.../aarch64/advsimd-intrinsics/vqshlu_n.c | 118 +-
.../aarch64/advsimd-intrinsics/vqshrn_n.c | 75 +-
.../aarch64/advsimd-intrinsics/vqshrun_n.c | 46 +-
.../gcc.target/aarch64/advsimd-intrinsics/vqsub.c | 92 +-
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gcc/testsuite/gcc.target/aarch64/pr97701.c | 17 +
gcc/testsuite/gcc.target/aarch64/pr98603.c | 11 +
gcc/testsuite/gcc.target/aarch64/simd/simd.exp | 2 +-
gcc/testsuite/gcc.target/aarch64/simd/vaddlv_1.c | 56 +
.../gcc.target/aarch64/simd/vmovl_high_1.c | 32 +
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.../aarch64/sve/acle/aarch64-sve-acle-asm.exp | 2 +-
.../aarch64/sve/acle/aarch64-sve-acle.exp | 2 +-
.../gcc.target/aarch64/sve/acle/asm/prfb.c | 47 +-
.../gcc.target/aarch64/sve/acle/asm/prfd.c | 47 +-
.../gcc.target/aarch64/sve/acle/asm/prfh.c | 47 +-
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gcc/testsuite/gcc.target/aarch64/sve/adr_6.c | 43 +
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gcc/testsuite/gcc.target/aarch64/sve/cnot_2.c | 29 +
gcc/testsuite/gcc.target/aarch64/sve/cond_asrd_1.c | 32 +
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gcc/testsuite/gcc.target/aarch64/sve/cond_asrd_2.c | 35 +
.../gcc.target/aarch64/sve/cond_asrd_2_run.c | 26 +
gcc/testsuite/gcc.target/aarch64/sve/cond_asrd_3.c | 35 +
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gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_4.c | 32 +
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gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_5.c | 32 +
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gcc/testsuite/gcc.target/aarch64/sve/cond_cnot_6.c | 31 +
.../gcc.target/aarch64/sve/cond_cnot_6_run.c | 26 +
.../gcc.target/aarch64/sve/cond_unary_5.c | 49 +
.../gcc.target/aarch64/sve/cond_unary_5_run.c | 26 +
.../gcc.target/aarch64/sve/cond_unary_6.c | 53 +
.../gcc.target/aarch64/sve/cond_unary_6_run.c | 27 +
.../gcc.target/aarch64/sve/cond_unary_7.c | 48 +
.../gcc.target/aarch64/sve/cond_unary_7_run.c | 26 +
.../gcc.target/aarch64/sve/cond_unary_8.c | 50 +
.../gcc.target/aarch64/sve/cond_unary_8_run.c | 28 +
gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_5.c | 33 +
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gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_6.c | 33 +
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gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_7.c | 29 +
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gcc/testsuite/gcc.target/aarch64/sve/cond_uxt_8.c | 32 +
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gcc/testsuite/gcc.target/aarch64/sve/mls_2.c | 34 +
gcc/testsuite/gcc.target/aarch64/sve/mul_2.c | 52 +
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gcc/testsuite/gcc.target/aarch64/sve/pr98535.c | 18 +
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gcc/testsuite/gcc.target/aarch64/sve/shift_2.c | 81 +
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gcc/testsuite/gcc.target/arm/pr97969.c | 54 +
gcc/testsuite/gcc.target/arm/pr98636.c | 6 +
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gcc/testsuite/gcc.target/arm/simd/mve-vorn.c | 38 +
gcc/testsuite/gcc.target/arm/simd/mve-vshl.c | 62 +
gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 59 +
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gcc/testsuite/gcc.target/i386/avx512bw-pr96891-1.c | 75 +
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gcc/testsuite/gcc.target/i386/pr94802.c | 59 +
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gcc/testsuite/gcc.target/i386/pr95771.c | 67 +
gcc/testsuite/gcc.target/i386/pr95852-1.c | 266 +
gcc/testsuite/gcc.target/i386/pr95852-2.c | 266 +
gcc/testsuite/gcc.target/i386/pr95852-3.c | 266 +
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gcc/testsuite/gcc.target/i386/pr95905-1.c | 26 +
gcc/testsuite/gcc.target/i386/pr95905-2.c | 82 +
gcc/testsuite/gcc.target/i386/pr95905-3.c | 82 +
gcc/testsuite/gcc.target/i386/pr95905-4.c | 82 +
gcc/testsuite/gcc.target/i386/pr96271.c | 11 +
gcc/testsuite/gcc.target/i386/pr96938.c | 66 +
gcc/testsuite/gcc.target/i386/pr97510.c | 18 +
gcc/testsuite/gcc.target/i386/pr97684.c | 24 +
gcc/testsuite/gcc.target/i386/pr97978.c | 22 +
gcc/testsuite/gcc.target/i386/pr98334.c | 36 +
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gcc/testsuite/gcc.target/i386/pr98522.c | 39 +
gcc/testsuite/gcc.target/i386/pr98567-1.c | 31 +
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gcc/testsuite/gcc.target/i386/pr98585.c | 14 +
gcc/testsuite/gcc.target/i386/pr98603.c | 11 +
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gcc/testsuite/gcc.target/i386/pr98670.c | 16 +
gcc/testsuite/gcc.target/i386/pr98694.c | 41 +
gcc/testsuite/gcc.target/i386/pr98833.c | 9 +
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gcc/testsuite/gcc.target/i386/sse2-pr98461-2.c | 25 +
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.../gcc.target/powerpc/fold-vec-insert-char-p8.c | 17 +-
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gcc/testsuite/gcc.target/powerpc/pr79251.h | 36 +
gcc/testsuite/gcc.target/powerpc/pr79251.p8.c | 22 +
gcc/testsuite/gcc.target/powerpc/pr79251.p9.c | 22 +
gcc/testsuite/gcc.target/powerpc/pr88233.c | 2 +-
gcc/testsuite/gcc.target/powerpc/pr91903.c | 73 +
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gcc/testsuite/gcc.target/riscv/pr98777.c | 31 +
gcc/testsuite/gcc.target/riscv/predef-10.c | 43 +
gcc/testsuite/gcc.target/riscv/predef-11.c | 43 +
gcc/testsuite/gcc.target/riscv/predef-12.c | 43 +
gcc/testsuite/gcc.target/riscv/predef-13.c | 43 +
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libstdc++-v3/testsuite/27_io/fpos/11450.cc | 2 +-
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[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-Os-vs-Os_LTO updated (b66b4e658f -> e0bd9202fb)
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-Os-vs-Os_LTO
in repository toolchain/ci/binutils-gdb.
from b66b4e658f Fix pretty printer of main_type.flds_bnds.bounds
adds 3b47e132c4 Automatic date update in version.in
adds 0ede24f2c4 sim: common: add align_{up,down} to match gdb
adds e3b53295d5 PR27140, ppc32 segmentation fault in make_stub
adds 9898e882c5 gdb: fix typos in comments in target-float.c
adds a68494db84 Automatic date update in version.in
adds 90320e4095 PR27101, as: Reject (byte) .align 0x100000000
adds a7c23ac931 In libctf, make AC_CONFIG_MACRO_DIR consistent with ACLOCAL_AMFLAGS
adds e9cf3691bf PR26741, benign use after free in riscv_parse_prefixed_ext
adds 4c0e540e47 RISC-V: Fix the merged orders of Z* extension for linker.
adds dd933805d1 PR27102, gas: "section symbols are already global"
adds 5b4293ba3c PR26822, How to prevent a STT_FILE with absolute path in the [...]
adds dbb078f66e When displaying ARM private file flag bits, use a 0x prefix.
adds 098caef485 Refactor struct trad_frame_saved_regs
adds c5e71b3332 [gdb/testsuite] Don't require gold for gdb.base/morestack.exp
adds a754fbdfa2 gdb/testsuite: use clean_restart in gdb.server/solib-list.exp
adds 7b0ff8a22a gdb/testsuite: use build_executable in gdb.server/stop-reply [...]
adds 5169ae34bc gdb/testsuite: use clean_restart in gdb.server/ext-run.exp
adds d8387cc8b6 gdb/testsuite: use clean_restart in gdb.server/server-run.exp
adds 8dc558a072 gdb/testsuite: avoid reading files through the remote protoc [...]
adds 335709bc5a gdb: make "set debug timestamp" work nice with new debug printouts
adds e71daf80d3 gdb: use infrun_debug_printf in print_target_wait_results
adds 3ec3145c5d gdb: introduce scoped debug prints
adds e4ad960a57 [gdb/symtab] Remove superfluous end-of-sequence marker
adds cd6d537c48 elf: Allow mixed ordered/unordered inputs for non-relocatable link
adds dbed468bcb sim: common: rename sim_print_config
adds 19b1c38562 sim: common: add a version output helper w/copyright+license info
adds 2b667e3297 sim: common: use sim_config_print name
adds babd2ee15d sim: common: version: add build & homepage info when interactive
adds dfb856ba26 sim: update bug URI to https://
adds c68ea49f59 gdb: bfin: use align helper
adds 9353bb9ed6 Automatic date update in version.in
adds 9416af6e7d sim: stdlib.h for abs()
adds 3d52735bab sim: include stdlib.h for atoi()
adds 18b9872261 RISC-V: Ouput __global_pointer$ as dynamic symbol when gener [...]
adds de6a7ee4bd asan: heap buffer overflow in _bfd_vms_slurp_egsd
adds 40b119304e Re: elf: Allow mixed ordered/unordered inputs for non-reloca [...]
adds 5f8c2a1507 Update config.sub and config.guess
adds d750c713c9 Update libiberty with latest sources from gcc mainline
adds c8bad65eee is_relocatable_executable --exclude-libs failure
adds b281a04ff0 ld sysroot-prefix test fails
adds b5ff370e96 Fix TUI source window drawing
adds 1b6d4bb223 Redraw both spaces between line numbers and source code
adds 5519536196 Prevent flickering when redrawing the TUI source window
adds b09ad6eae9 libctf: do not print array declarators backwards
adds 57f97d0e6d libctf, ld: CTF dumper changes for consistency
adds 91e7ce2fd7 libctf, ld: more dumper improvements
adds ffeece6ac2 libctf, ld: prohibit getting the size or alignment of forwards
adds 37002871ac libctf, ld: dump enums: generally improve dump formatting
adds 1038406a8f libctf: rip out BFD_DEPENDENCIES / BFD_LIBADD
adds c59e30ed17 libctf: new testsuite
adds 9bc769718d libctf: new test of enum lookups with the _next iterator
adds abed0b0718 libctf: warn about information loss because of unreleased fo [...]
adds 6c3a38777b libctf, include: support unnamed structure members better
adds 8769046e5a libctf: remove outdated comment about parent dict importing
adds abe4ca69a1 libctf: fix lookups of pointers by name in parent dicts
adds 608a333d7d libctf: fix old ChangeLog typo
adds b4b6ea4680 libctf, ld: fix formatting of forwards to unions and enums
adds 70d3120f32 libctf, testsuite: don't run without a suitable compiler
adds 0814dbfbfc libctf, testsuite: adjust for real return type of ctf_member_count
adds 85dd67bd6d Automatic date update in version.in
adds 0c7f5bd08c sim: h8300: simplify testsuite runner
adds a2f8e947a8 sim: h8300: fix test mach markers
adds c004e77f7d sim: testsuite: delete unused Make-common.in file
adds 865288236d sim: fr30: delete unused testsuite
adds fbc09e7af7 RISC-V: Implement support for big endian targets.
adds f36ce378b4 RISC-V: Fix riscv gas/ld testsuites failures for big endian.
adds 286d2f2cd7 RISC-V: Mention -mbig-endian and -mlittle-endian in doc
adds 22206e847d gas APP macro tests
adds 73624512cf ld rgn-at10 and rgn-at11 test
adds 3677b72961 sparc-sun-solaris2 and sparc64-sun-solaris2 config
adds 85f55c2b75 sparc-elf ld test fails
adds 599c86c4a5 score-elf binutils-all/strip-13 fail
adds 4b186f88b8 gdbsupport: common-utils.h: fix typo in header
adds 3c55062cc1 gdb/testsuite: fix race in gdb.threads/signal-while-stepping [...]
adds b49180acf2 Fix fixed-point binary operation type handling
adds 1606216201 config.sub update broke powerpc-eabivle
adds 4018f4e0fc ld pr22471 test fails
adds f526791a6f Regen ld/po/BLD-POTFILES.in
adds e2ede46cb2 Automatic date update in version.in
adds 6987d5a1bb binutils/readelf.c: Correct grammar in comment
adds d4e57b87a3 bfin: Check bfd_link_hash_indirect
adds 2652cfad8d RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructio [...]
adds 1861f7cfbf sim: cris: fix C tests with newer toolchains
adds 9446bcf6be fix paths in ChangeLog
adds 4d4490b8d7 ld: xfail riscv64*-*-* for ld-scripts/empty-address-2 tests.
adds aa881ecde4 RISC-V: Add pause hint instruction.
adds 78e4948694 [gdb/build] Fix gdbserver build with -fsanitize=address
adds 17d60030ae Fix another path length problem opening files on Win32 systems.
adds d4813f1046 Fix regression in Ada aggregate assignment
adds 8e604ff077 xfail more cases of complaints about relocs in read-only sections
adds dc20061339 sh-pe ld XPASSes
adds 959d6a673e Fix regression in Ada do_full_match
adds 3b288c8e2e m68k: Require m68020up rather than m68000up for CHK.L instruction.
adds d1bcae833b ELF: Don't generate unused section symbols
adds 1b0927db3c Updated French translation for the opcodes/ subdirectory.
adds f478212851 libtool.m4: update GNU/Hurd test from upstream. In upstream [...]
adds e904f56d02 gdb/sim: add support for exporting memory map
adds bfc7d04afb sim: h8300: delete opcode caching
adds a39487c668 sim: cris: use -sim with C tests for cris-elf targets
adds e6c1dbbfe8 sim: cris: disable test that crashes the linker
adds 0f8e278da2 sim: ChangeLog: move arch-specific entries into the arch dir
adds 9a50f40e82 Automatic date update in version.in
adds f4cfa91741 sim: ppc: stub out sim_memory_map
adds e343681375 gdb/fortran: Correct the lval type for array elements of int [...]
adds 1940319c0e [gdb] Fix internal-error in process_event_stop_test
adds fb932b57cb Treat the AArch64 register id_aa64mmfr2_el1 as a core system [...]
adds e84c871648 Fix places in the AArch64 opcodes library code where a call [...]
adds 3c8c6de21d gdb: user variables with components of dynamic type
adds ed20522215 Updated Swedish translation for the opcodes/ subdirectory
adds d00f086803 gdb: add missing test for completion of invalid /FMT strings
adds 6abd4cf281 gdb: check for empty strings in get_standard_cache_dir/get_s [...]
adds 8fc48b7961 Pass void_context_p to parse_expression
adds 46f900c065 sim: require a C11 compiler
adds a7e906e8f5 Automatic date update in version.in
adds 6430704567 configure regen
adds aae7fcb8d7 POWER10: Add Return-Oriented Programming instructions
adds b1b29aa51a elf: Verify section size for mixed ordered/unordered inputs
adds ba9e922fa0 ld/x86-64: Also set LAM_U57 when setting LAM_U48
adds ce0be4070f sim: common: add missing stdlib.h for abort()
adds 055bc77a80 Add Changelog entries and NEWS entries for 2.36 branch
adds 573fe3fbc1 Change version number to 2.36.50 and regenerate files
adds be2c78856d Update release howto with 2.37 numbers
adds b5a4a01af4 sim: hw: rework code to avoid gcc warnings
adds f41464416a sim: pru: fix include ordering with sim-main.h
adds 0a94990bf6 ld/x86-64: Properly Handle -z lam-u48/lam-u57
adds bf470982f9 sim: enable -Werror by default for some arches
adds 50df264dae sim: clean up stale AC_PREREQ refs
adds f8cab0b995 sim: sh64: delete port
adds f074c07d8d sim: common: clean up asprintf includes a bit
adds 7eb99e5e27 sim: cr16/d10v: move storage out of header
adds a9fd212a24 sim: replace rindex with strrchr
adds 50ad1254d5 GCC: Pass --plugin to AR and RANLIB
adds a4966cd965 Binutils: Pass --plugin to AR and RANLIB
adds af019bfde9 Support the PGO build for binutils+gdb
adds 66beed0227 Fix erroneous agent expression test
adds bc167b6b3e Remove a use of print_expression
adds 54585eee2e Avoid crash in compile_to_object
adds 5834526f4b Automatic date update in version.in
adds 46b1518d4c Automatic date update in version.in
adds a8aa72b913 Updated translations for multiple subdirectories
adds 68ed285428 sim: clean up C11 header includes
adds 933306703a sim: rl78: move storage out of header
adds 90e123dd60 sim: common: fix printf formats
adds a0c38f0d70 sim: or1k: fix include ordering with sim-main.h
adds 5c1008a41f sim: call SIM_AC_OPTION_WARNINGS(no) in remaining ports
adds 9c70334dee sim: always call SIM_AC_OPTION_WARNINGS
adds c0f6e439cc Add support for more MIPS variants to the linker command line.
adds 82c70b08df aarch64: Remove support for CSRE
adds 10dadadc5b [gdb/testsuite] Fix gdb.arch/amd64-stap-three-arg-disp.S
adds 062eaacbac gdb: change jit_debug to a bool
adds eef401dce1 gdb: convert solib-aix to new-style debug macros
adds c6185dce03 gdb: convert aarch64 to new-style debug macros
adds 254c3783fe sim: tests: get common tests working again
adds eabdd87b2e Automatic date update in version.in
adds 03c02f3116 GCC: Check if AR works with --plugin and rc
adds 83b33c6cb9 Binutils: Check if AR works with --plugin and rc
adds 44124a4683 binuitils: Check if AR is usable for LTO build
adds f631b79abe sim: or1k: delete redundant SIM_AC_OPTION_INLINE call
adds f220ef633c sim: common: use #error properly
adds 68895f7d7e sim: README-HACKING: clean up stale run references
adds 5e9e2f41eb sim: or1k: clean up stale build entries
adds e998918e98 sim: or1k: fix mixing of code & decl warning
adds 7c654b719d gdb/fortran: add symbol base comparison operators
adds ce38f5edf1 gdb: fix debug dump of OP_BOOL expressions
adds 6d104cac0a Updated translations for some subdirectories
adds c2e9a4a3ed elf/x86-64: Adjust R_AMD64_DIR64/R_AMD64_DIR32 for PE/x86-64 inputs
adds 18bfb5057f [gdb/testsuite] Require is_amd64_regs_target in gdb.base/dis [...]
adds d546b61084 Implement a workaround for GNU mak jobserver
adds 5291fe3cd1 aarch64: Add support for bfloat16 in gdb.
adds b2f2ae0d6f gdb: remove pre_init_ui_hook from top.c
adds 3f94e58859 [gdb/testsuite] Add have_mpx in lib/gdb.exp
adds 16e9019ef7 gdb: move baud_rate and serial_parity declarations to serial.h
adds fe7a351a8e gdb: move read{now,never}_symbol_files declarations to symfile.h
adds 24a7f1b548 gdb: fix indentation in infrun.c
adds 3034143dc6 src-release: fix indentation
adds 4180301e81 Automatic date update in version.in
adds 62fe7512a7 sim: watch: fix pc watchpoints on little endian host systems
adds c54f3efdc2 sim: watch: fix range expression processing
adds 2ce40d1a51 Add SEH support to code generated by dlltool.
adds 8c4645b488 Remove sflag_info param from wild callback functions
adds b209b5a6b8 SHF_LINK_ORDER fixup_link_order in ld
adds 5347ed60c5 Regen Makefile.in for jobserver.m4 aclocal.m4 dependency
adds 844bf810cf x86: Don't generate GOT_symbol for PLT relocations
adds b634d11d61 ld: Check for ELF input before accessing ELF section data
adds 54ca900277 gdb: convert jit to new-style debug macros
adds 5e12f48ffb gdb: bool-ify file_is_auto_load_safe
adds db972fce46 gdb: bool-ify ext_lang_auto_load_enabled and friends
adds 5bf7e91b2b gdb: bool-ify users of file_is_auto_load_safe
adds 506195754c gdb: bool-ify maybe_add_script_{text,file}
adds fb0f5031bb gdb: turn arc_debug into a bool
adds d8d1feb424 gdb: convert arc to new-style debug macros
adds 4120e4885b Re: SHF_LINK_ORDER fixup_link_order in ld
adds 3eeabe12c3 Automatic date update in version.in
adds c9d220893e gdb: make the remote target track its own thread resume state
adds bd497355ea gdb: remove target_ops::commit_resume implementation in reco [...]
adds 8f66807b98 gdb: better handling of 'S' packets
adds d9b1deff13 sim: watch: add basic default handler that traps
adds 54780889e9 sim: h8300: drop separate eightbit memory buffer
adds adb0bd8fda gas: bfin: fix build time warnings
adds abad28152e gas: bfin: build lexer with -Werror
adds 271bea6acd ld: tests: add -msim when testing bfin targets
adds 7e0d77ef5f Fix an illegal memory access parsing a win32pstatus note wit [...]
adds 116d0cf103 [gdb/testsuite] Fix gdb.base/style.exp with -m32
adds 5fae2a2c66 [gdb/breakpoint] Handle .plt.sec in in_plt_section
adds 5a10699ff3 Updated translations for some subdirectories
adds 8ca9c7eb67 bfin: Skip non SEC_ALLOC section for R_BFIN_FUNCDESC
adds 58eadc4b69 Fix building gdb with gcc-4.x
adds c14dee84dd Update my email address (long overdue!)
adds 17e8913732 Add myself to gdb/MAINTAINERS
adds 5aa06b1b14 Automatic date update in version.in
adds 5fda40b28f gas: make [248]byte directives available everywhere
adds 3624a6c15c PR26539, memory leak in inflate.c
adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status
adds 7cf91a2481 sim: m32r: clean up redundant test coverage
adds 89bfc2a429 sim: frv: clean up redundant test coverage
adds 137d6efd8a sim: mips: delete empty stub test dir
adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness
adds bb3eddb5bd sim: testsuite: delete configure script
adds dcd709e056 RISC-V: Comments tidy and improvement.
adds b800637e76 RISC-V: Error and warning messages tidy.
adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...]
adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...]
adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32
adds 5a11fff005 gdb/tui: compare pointer to nullptr, not 0
adds e403a898b5 Automatic date update in version.in
adds 1368b914e9 sim: testsuite: flatten tree
adds eb6e6af8c1 PR26002 undefined symbol VER_NDX_GLOBAL vs. VER_NDX_LOCAL
adds ad92f33d38 Tidy inflateEnd calls
adds 68b007788a ld/x86: Add -z report-relative-reloc
adds 75a933f399 ld/elf/x86: Don't compare IFUNC address in the shared object
adds 514fca98df Automatic date update in version.in
adds edf0f284b1 PR binutils/23460: Increase the max number of open files to 20
adds d46153313b Automatic date update in version.in
adds 25294ff049 gold: Remove the circular IFUNC dependency in ifuncmain6pie
adds 994b251328 ld/elf: Ignore section symbols when matching linkonce with comdat
adds 44365e88c0 PR27198, segv in S_IS_WEAK
adds cecb191290 gdb: const-ify unpack_* functions in remote.c
adds e3b2741b16 gdb: const-ify remote_target::add_current_inferior_and_threa [...]
adds b5c8f22d28 gdb: move remote_target::start_remote variable to narrower scope
adds aa2838ccc5 gdb: const-ify hostio methods parameter in remote.c
adds d3d7d1ba3b [gdb/tdep] Handle si_addr_bnd in compat_siginfo_from_siginfo
adds 326adec374 PR26378, sections initialised only by linker scripts are alw [...]
adds 6a9ad81c44 gdb/riscv: use a single regset supply function for riscv fbs [...]
adds 705989f19a as: Automatically enable DWARF5 support
adds 02baa13385 gdb/testsuite: remove actual addresses from some test names
adds 4cfcd3b333 sim: common: modernize gennltvals.sh
adds 5e25901fcc sim: common: delete configure & Makefile
adds f89f33e57c sim: common: simplify version script
adds f0c1efa53d Automatic date update in version.in
adds 85e963f185 ld: Just xfail riscv little endian targets for compressed1d.d test.
adds 0e7620dcdc sim: bfin: delete accidental ADI copyright
adds a75a6a4164 [GOLD] powerpc assertion failure
adds 30845f113a PowerPC use_local_plt
adds 0c4e2c6c88 [gdb/testsuite] Fix gdb.arch/i386-mpx.exp with -m32
adds 1485212328 [gdb/testsuite] Fix gdb.base/step-over-syscall.exp with -m32
adds c98de297b3 libctf, ld: fix data symbol test with newer GCC
adds e05a3e5a49 libctf: lookup_by_name: do not return success for nonexisten [...]
adds 26503e2f5e libctf, create: fix ctf_type_add of structs with unnamed members
adds ccbe4c82d5 Use gdb::array_view for setting value bytes in trad-frame
adds c65ca138c4 sim: ppc: update version script usage
adds bdec2917b1 Convert some frame functions to use gdb::array_view.
adds a9a87d3525 trad-frame cleanups
adds 1c3b85ad28 use DISABLE_COPY_AND_ASSIGN in switch_thru_all_uis
adds 11321a0505 Automatic date update in version.in
adds 8bd10d6b16 PowerPC64 synthetic symbols
adds 4bd7c90276 PowerPC: Don't generate unused section symbols
adds 037e8112b9 [gdb/server] Don't overwrite fs/gs_base with -m32
adds 6f52fdf404 Fix a few stap parser issues and add a new test for probe ex [...]
adds 1402665c8f [gdb/testsuite] Skip gdb.rust/*.exp for target board unix/-m32
adds 7c794afd54 [gdb/testsuite] Fix gdb.python/py-format-string.exp with -m32
adds 6571ffc620 gdb/testsuite: add links for handled control sequences in li [...]
adds c3e96aa78f gdb/testsuite: rename _cur_x/_cur_y to _cur_col/_cur_row in [...]
adds 3f0781f389 Automatic date update in version.in
adds a6c11cbb14 gdb/remote.c: address conflicting enum and method name
adds 6bd434d6ca gdb: make some variables static
adds 17e593e966 gdb/dwarf: add some logging in dwarf2/read.c
adds de53369b2e gdb/dwarf: add assertion in maybe_queue_comp_unit
adds f9e9ba90b3 gdb/testsuite: use multi_line in gdb.base/skip.exp
adds d4dd4fca16 gdb: change debug_bfd_cache to bool
adds c78eec4424 mips XPASS pr26936
adds 498ff0328f PR27218, memory access violation in dwarf2dbg.c
adds be07043ea8 PR27221, 058430b4a1 warnings while assembling the Linux kernel
adds 7cb6d92a3f gdb: convert arm to new-style debug macros
adds 325d39e4e0 Add Python support for hardware breakpoints
adds a72d0f3d69 gdb/doc: reorder and group sections relating to aliases
adds 730af66356 gdb/testsuite: improve logging in lib/tuiterm.exp
adds 439706e6a9 gdb: use interruptible_select when connecting to a remote
adds 1e15fcac94 gdb: convert bfd-cache to new-style debug macros
adds d3abc0cee0 gdb: remove unused f77_array_offset_tbl from f-valprint.c
adds a59902a7c1 gdb: convert auto-load to new-style debug macros
adds d5d24e12f9 Fix build errors for armhf
adds cd211c75cb Handle additional connection error
adds e534c7e8c4 Automatic date update in version.in
adds c651f0a614 MAINTAINERS: Update my e-mail address
adds cc4bc93e52 gdb/doc: down case contents of @var
adds fe461d2f70 gdb/doc: move @menu to the end of the node
adds 5b7d941b90 gdb: add owner-related methods to struct type
adds 3062502019 gdb: remove TYPE_OBJFILE_OWNED macro
adds 344e9841d9 gdb: remove TYPE_OBJFILE macro
adds baf2b57f18 gdb: move set remote commands to remote.c
adds cda09ec9f9 gdb: move remote_debug to remote.{h,c}
adds 02349803fc gdb: change remote_debug to bool
adds 2189c31265 gdb: add remote_debug_printf
adds d8c4766d31 gdb/doc: don't rely on @menu item within the docs
adds e7b430724d gdb: don't print escape characters when a style is disabled
adds 9d2d8a16e1 gdb: add new version style
adds 0ac85db529 gdb/testsuite: eliminate gdb_suppress_tests mechanism
adds 705646c074 Fix expected output of gdb.base/line65535.exp with dwarf-5
adds e753591581 Automatic date update in version.in
adds 1af4c9c420 Disable bracketed paste mode in GDB tests
adds ef45cb65a7 Use readline's variant of Windows patch
adds d3ee35dbf7 Improve gdb_tilde_expand logic.
adds dd5ca05f47 gdb: fix regression in copy_type_recursive
adds c99d72de18 Automatic date update in version.in
adds 9f7f6cb8d2 Remove call to reset from compile_to_object
adds 18454c151f DWARF-5: Fix parsing DWARF-5 line number tables
adds 3637a558a5 Use std::vector for "registers_used" in compile feature
adds b10bae1875 Avoid crash when "compile" expression uses cooked register
adds 68fcee4fa7 PR27228, .reloc wrong symbol emitted for undefined local symbol
adds 9b351c9bc9 Minor updates to the 'how to make a release' document
adds eea133e655 gas: Add a testcase for PR gas/27228
adds 940d0202fd DWARF-5: Ignore empty range in DWARF-5 line number tables
adds 123b18bf62 Automatic date update in version.in
adds b8df69003d Update linker scripts with the names of new DWARF-5 debug sections.
adds 04de9f3e31 gdb/doc: move @menu blocks to the end of their enclosing @node
adds 9e42b97628 Add some more DWARF-5 sections
adds acd6125f01 Add test case for symbol menu for local enumerators
adds 191849105b Specially handle array contexts in Ada expression resolution
adds a625a8c9eb Fix fixed-point regression with recent GCC
adds f3bdc2dbb9 gdb/docs: add parentheses in Python examples using print
adds 9f6c202e57 [gdb/symtab] Handle DW_AT_ranges with DW_FORM_sec_off in par [...]
adds 01a01e0ab3 Automatic date update in version.in
adds d0021af39c [gdb/testsuite] Fix gdb.opt/solib-intra-step.exp with -m32
adds 4ca40594f9 [gdb/testsuite] Fix gdb.threads/killed-outside.exp with -m32
adds d56834cbfb arc: Log "pc" value in "arc_skip_prologue"
adds e37709f090 Fix thinko in objcopy's memory freeing code.
adds ac3571d941 Fix the date for the last entry in gdb/ChangeLog
adds d0cc52bdf2 gdb: Add default reggroups for ARC
adds 4287950e54 pr27228 testcase
adds 9886ff0319 gas byte test
adds a45ef9a30b gas testsuite tidy
adds 1c9c9b9b55 PR27226, ld.bfd contains huge .rodata section
adds c3ffb8f340 Segmentation fault i386-gen
adds 4cb1265b3f bfd: add elfcore_write_file_note
adds 4ef367bffd Use debug_prefixed_printf_cond in windows-nat.c
adds 1f583bc2fc nios2: Don't disable relaxation with --gdwarf-N
adds c22788d614 Automatic date update in version.in
adds 2eda57ef61 ld: Fix a typo in testsuite/ld-x86-64/bnd-plt-1.d
adds 67965ba289 Simplify the code at the end of objcopy's main() function.
adds f04ce15e83 ld: depend on libctf
adds bb3c2d4d94 Remove extra space after @pxref in gdb.texinfo
adds 807f647cac GDB: aarch64: Add ability to displaced step over a BR/BLR in [...]
adds 59b59f08f6 Avoid use after free with logging and debug redirect.
adds 07b8b9e7c5 Automatic date update in version.in
adds 22efa3d307 [gdb/testsuite] Fix ERROR in gdb.dwarf2/dw2-out-of-range-end [...]
adds 2f985dd1ac [gdb/testsuite] Fix gdb.ada/out_of_line_in_inlined.exp with [...]
adds def97fb945 PR27259, SHF_LINK_ORDER self-link
adds 2a7f6487d0 [gdb/breakpoints] Fix longjmp master breakpoint with separat [...]
adds 24cf63899b gdb: update comment for execute_command_to_string
adds 47918cca26 gdb/testsuite: unset XDG_CONFIG_HOME
adds 0318cca493 gold: Skip address size and segment selector for DWARF5
adds a7ad3cb1ff Fix binutils tools so that they can cope with the special /d [...]
adds 53e556e5b4 ld: Add a test for PR ld/27259
adds cc3edc5274 Improve windres's handling of pathnames containing special c [...]
adds 6ac373717c gdb: rename type::{arch,objfile} -> type::{arch_owner,objfil [...]
adds 8ee511afd8 gdb: rename get_type_arch to type::arch
adds c47b145e1a [gdb/testsuite] Fix g0 search in gdb.arch/i386-sse-stack-align.exp
adds cdeba395cf [gdb/testsuite] Fix gdb.arch/i386-gnu-cfi.exp
adds f237f998d1 gdb/tui: remove special handling of locator/status window
adds 0f93c3a25b gdb: remove unneeded switch_to_thread from thr_try_catch_cmd
adds 986dbd541a Automatic date update in version.in
adds c4566785ac PR27271, c6x-uclinux-ld segfaults linking ld-uClibc-1.0.37.so
adds 620ec3caae [gdb/testsuite] Fix gdb.opt/solib-intra-step.exp with -m32 a [...]
adds ebde6f2ddc [gdb/breakpoint] Fix stepping past non-stmt line-table entries
adds 6efcd6f329 Automatic date update in version.in
adds 008a02e36d sim: readd myself as a maintainer
adds 481fac96bd sim: common: sort nltvals.def
adds f4dd74915b sim: hw: replace fgets with getline
adds 88f68ee277 sim: m68hc11: stop making hardware conditional
adds 18d4b488f4 sim: profile: fix bucketing with 64-bit targets
adds d4e3adda12 sim: watchpoints: change sizeof_pc to sizeof(sim_cia)
adds ee64caae5b sim: m68hc11: include stdlib.h for prototypes
adds fb8d4e59af sim: m68hc11: tweak printf-style funcs
adds b9e016f517 sim: m68hc11: localize a few functions
adds 683b8d961e sim: m68hc11: fix printf size warnings
adds ca51543cf5 Automatic date update in version.in
adds 9a7ba4aa0e sim: common: change gennltvals helper to Python
adds 3c811346e9 sim: moxie: cleanup build warnings
adds 44b30b7f0e sim: v850: fix handling of SYS_times
adds 5f05936d9b sim: v850: cleanup build warnings
adds 5bc4f5ca15 sim: cgen-accfp: Fix pointer sign warnings
adds ba2f0de216 sim: bpf/or1k: fix CGEN_TRACE_EXTRACT name
adds bccec180ce sim: bpf: fix mainloop extract call
adds 6451541244 sim: cgen-trace: tweak printf call
adds 4ebf566ea5 Automatic date update in version.in
adds 7bba67ec7c PR27283 gas for alpha fails to build with gcc 11
adds 49daa38f31 Re: ld: Add a test for PR ld/27259
adds a5f92c6756 ldgram.y low_level_library_NAME_list
adds 82a1fd3a49 gdb: unify parts of the Linux and FreeBSD core dumping code
adds 40726f16a8 ld script expression parsing
adds fb6c220ebd ld --defsym
adds 72a51a0603 Small updates to the 'how to make a release' document follow [...]
adds 34c10233cd Wrong operand for SADDR (rl78)
adds c39c86378f [gdb/testsuite] Fix gdb.dwarf2/fission-reread.exp with .gdb_index
adds 1f568f9a0d Add Genode target support
adds 82e3e87da4 Automatic date update in version.in
adds 2bd3e4b8d2 [gdb/symtab] Fix assert in write_one_signatured_type
adds 9918bff7cf PR27311, ld.bfd (symbol from plugin): undefined reference
adds 5424d7ed94 readelf: Add 'R' and 'D' to "Key to Flags:"
adds a0c1eeba9b gdb/dwarf: change read_loclist_index complaints into errors
adds 5e4d9bbc4b gdb/dwarf: fix bound check in read_rnglist_index
adds 05787bad36 gdb/dwarf: add missing bound check to read_loclist_index
adds 0c800c6ebc gdb/dwarf: remove unnecessary check in read_{rng,loc}list_index
adds b1829e1bf2 gdb/dwarf: few fixes for handling DW_FORM_{rng,loc}listx
adds a1c4010369 gdb/dwarf: read correct rnglist/loclist header in read_{rng, [...]
adds 962effa790 gdb/testsuite: add .debug_rnglists tests
adds 6b0933da34 gdb/testsuite: DWARF assembler: add context parameters to _location
adds ecfda20dcc gdb/testsuite: add .debug_loclists tests
adds 2b0c7f41d1 gdb/dwarf: split dwarf2_cu::ranges_base in two
adds e57933dc9c gdb/dwarf: make read_{loc,rng}list_index return sect_offset
adds 9307efbe9e gdb/testsuite: add test for .debug_{rng,loc}lists section wi [...]
adds e0bd9202fb gdb/testsuite: use proc_with_prefix in gdb.base/scope.exp
No new revisions were added by this update.
Summary of changes:
ChangeLog | 164 +
Makefile.def | 5 +-
Makefile.in | 82 +-
Makefile.tpl | 63 +-
bfd/ChangeLog | 419 +
bfd/Makefile.in | 1 +
bfd/aclocal.m4 | 1 +
bfd/aix386-core.c | 1 +
bfd/aout-target.h | 1 +
bfd/bfd-in2.h | 17 +
bfd/bfdio.c | 23 +-
bfd/binary.c | 1 +
bfd/cisco-core.c | 2 +
bfd/coff-alpha.c | 1 +
bfd/coff-i386.c | 4 +-
bfd/coff-ia64.c | 1 +
bfd/coff-mips.c | 3 +
bfd/coff-rs6000.c | 2 +
bfd/coff-sh.c | 2 +
bfd/coff-tic30.c | 1 +
bfd/coff-tic54x.c | 26 +
bfd/coff-x86_64.c | 2 +
bfd/coff64-rs6000.c | 2 +
bfd/coffcode.h | 3 +
bfd/compress.c | 3 +-
bfd/config.bfd | 23 +-
bfd/configure | 87 +-
bfd/configure.ac | 4 +
bfd/doc/Makefile.in | 1 +
bfd/dwarf2.c | 5 +-
bfd/elf-bfd.h | 2 +
bfd/elf-linker-x86.h | 3 +
bfd/elf.c | 28 +-
bfd/elf32-arm.c | 4 +-
bfd/elf32-bfin.c | 245 +-
bfd/elf32-ft32.c | 3 +-
bfd/elf32-i386.c | 36 +
bfd/elf32-ppc.c | 55 +-
bfd/elf32-rl78.c | 2 +-
bfd/elf32-score.c | 10 +-
bfd/elf32-score7.c | 10 +-
bfd/elf64-ppc.c | 83 +-
bfd/elf64-x86-64.c | 33 +
bfd/elfcode.h | 8 +-
bfd/elflink.c | 272 +-
bfd/elfnn-aarch64.c | 4 +-
bfd/elfnn-riscv.c | 460 +-
bfd/elfxx-riscv.c | 60 +-
bfd/elfxx-riscv.h | 7 +-
bfd/elfxx-target.h | 6 +
bfd/elfxx-x86.c | 72 +-
bfd/elfxx-x86.h | 7 +
bfd/hppabsd-core.c | 1 +
bfd/hpux-core.c | 1 +
bfd/i386msdos.c | 1 +
bfd/ihex.c | 1 +
bfd/irix-core.c | 1 +
bfd/mach-o-target.c | 1 +
bfd/mmo.c | 1 +
bfd/netbsd-core.c | 1 +
bfd/osf-core.c | 1 +
bfd/pdp11.c | 1 +
bfd/pef.c | 2 +
bfd/plugin.c | 1 +
bfd/po/bfd.pot | 2574 +--
bfd/po/fr.po | 2666 +--
bfd/po/pt.po | 2681 ++--
bfd/po/sr.po | 2687 ++--
bfd/po/uk.po | 2666 +--
bfd/ppcboot.c | 1 +
bfd/ptrace-core.c | 1 +
bfd/reloc.c | 7 +
bfd/sco5-core.c | 1 +
bfd/som.c | 1 +
bfd/srec.c | 2 +
bfd/syms.c | 3 +
bfd/targets.c | 18 +
bfd/tekhex.c | 1 +
bfd/trad-core.c | 1 +
bfd/verilog.c | 1 +
bfd/version.h | 2 +-
bfd/version.m4 | 2 +-
bfd/vms-alpha.c | 4 +-
bfd/vms-lib.c | 1 +
bfd/wasm-module.c | 1 +
bfd/xsym.c | 1 +
binutils/BRANCHES | 1 +
binutils/ChangeLog | 138 +
binutils/MAINTAINERS | 8 +-
binutils/Makefile.in | 1 +
binutils/NEWS | 2 +
binutils/README-how-to-make-a-release | 104 +-
binutils/aclocal.m4 | 1 +
binutils/bucomm.c | 15 +
binutils/configure | 85 +-
binutils/configure.ac | 2 +
binutils/dlltool.c | 50 +-
binutils/doc/Makefile.in | 1 +
binutils/elfedit.c | 14 +
binutils/objcopy.c | 57 +-
binutils/po/binutils.pot | 3317 ++--
binutils/po/fr.po | 3826 +++--
binutils/po/pt.po | 3943 ++---
binutils/po/sr.po | 3845 +++--
binutils/po/sv.po | 3804 +++--
binutils/po/uk.po | 3840 +++--
binutils/readelf.c | 22 +-
binutils/testsuite/binutils-all/readelf.exp | 6 +-
binutils/testsuite/binutils-all/readelf.s-64 | 2 +-
.../{readelf.s-64 => readelf.s-64-unused} | 0
binutils/testsuite/binutils-all/readelf.ss | 5 +-
binutils/testsuite/binutils-all/readelf.ss-64 | 5 +-
.../{readelf.ss-64 => readelf.ss-64-unused} | 0
.../binutils-all/{readelf.ss => readelf.ss-unused} | 0
binutils/testsuite/binutils-all/retain1a.d | 2 +
binutils/testsuite/lib/binutils-common.exp | 31 +
binutils/windres.c | 31 +-
config.guess | 272 +-
config.sub | 638 +-
config/ChangeLog | 19 +
config/gcc-plugin.m4 | 40 +
config/jobserver.m4 | 24 +
configure | 246 +-
configure.ac | 84 +
cpu/ChangeLog | 4 +
elfcpp/ChangeLog | 4 +
gas/ChangeLog | 359 +
gas/Makefile.am | 4 +-
gas/Makefile.in | 5 +-
gas/NEWS | 10 +-
gas/aclocal.m4 | 1 +
gas/config/bfin-lex.l | 5 +-
gas/config/obj-elf.c | 11 +-
gas/config/tc-aarch64.c | 31 -
gas/config/tc-alpha.c | 2 +-
gas/config/tc-i386.c | 42 +-
gas/config/tc-nios2.c | 4 -
gas/config/tc-riscv.c | 569 +-
gas/config/tc-riscv.h | 8 +-
gas/configure | 85 +-
gas/configure.ac | 2 +
gas/configure.tgt | 8 +-
gas/doc/Makefile.in | 1 +
gas/doc/as.texi | 8 +-
gas/doc/c-aarch64.texi | 2 -
gas/doc/c-riscv.texi | 8 +
gas/dwarf2dbg.c | 33 +-
gas/po/fr.po | 7239 ++++-----
gas/po/gas.pot | 2131 +--
gas/po/uk.po | 7237 ++++-----
gas/read.c | 10 +-
gas/subsegs.c | 4 +
gas/symbols.c | 5 +-
gas/testsuite/gas/aarch64/csre-invalid.d | 3 -
gas/testsuite/gas/aarch64/csre-invalid.s | 6 -
gas/testsuite/gas/aarch64/csre.d | 29 -
gas/testsuite/gas/aarch64/csre_csr-invalid.d | 3 -
gas/testsuite/gas/aarch64/csre_csr-invalid.l | 2 -
gas/testsuite/gas/aarch64/csre_csr-invalid.s | 4 -
gas/testsuite/gas/aarch64/csre_csr.d | 10 -
gas/testsuite/gas/aarch64/csre_csr.s | 4 -
gas/testsuite/gas/all/byte.d | 4 -
gas/testsuite/gas/all/byte.l | 3 -
gas/testsuite/gas/all/byte.s | 2 -
gas/testsuite/gas/all/gas.exp | 5 -
gas/testsuite/gas/all/local-label-overflow.d | 5 +-
gas/testsuite/gas/all/none.d | 2 +-
gas/testsuite/gas/all/sleb128-2.d | 2 +-
gas/testsuite/gas/all/sleb128-4.d | 3 +-
gas/testsuite/gas/all/sleb128-5.d | 2 +-
gas/testsuite/gas/all/sleb128-7.d | 2 +-
gas/testsuite/gas/all/sleb128-9.d | 2 +-
gas/testsuite/gas/all/string.d | 2 +-
gas/testsuite/gas/cfi/cfi-label.d | 4 +-
gas/testsuite/gas/elf/bignums.d | 2 +-
gas/testsuite/gas/elf/dwarf-5-file0.d | 2 +-
gas/testsuite/gas/elf/dwarf2-20.d | 4 -
gas/testsuite/gas/elf/elf.exp | 12 +-
gas/testsuite/gas/elf/group0c.d | 2 +-
gas/testsuite/gas/elf/group1a.d | 2 +-
gas/testsuite/gas/elf/missing-build-notes.d | 2 +-
gas/testsuite/gas/elf/pr27228.d | 10 +
gas/testsuite/gas/elf/pr27228.s | 5 +
gas/testsuite/gas/elf/section-symbol-redef.d | 2 +-
gas/testsuite/gas/elf/section0.d | 2 +-
gas/testsuite/gas/elf/section1.d | 2 +-
gas/testsuite/gas/elf/section10.d | 2 +-
gas/testsuite/gas/elf/section11.d | 4 +-
gas/testsuite/gas/elf/section15.d | 2 +-
gas/testsuite/gas/elf/section2.e | 7 -
.../gas/elf/{section2.e => section2.e-unused} | 0
gas/testsuite/gas/elf/section4.d | 2 +-
gas/testsuite/gas/elf/section6.d | 2 +-
gas/testsuite/gas/elf/section7.d | 2 +-
gas/testsuite/gas/elf/symtab.d | 4 +-
gas/testsuite/gas/elf/symtab.s | 2 +-
gas/testsuite/gas/elf/symver.d | 4 -
gas/testsuite/gas/elf/warn-2.s | 7 -
gas/testsuite/gas/i386/i386.exp | 5 +
gas/testsuite/gas/i386/ilp32/elf/symver.d | 4 -
gas/testsuite/gas/i386/ilp32/x86-64-size-1.d | 24 +-
gas/testsuite/gas/i386/ilp32/x86-64-size-3.d | 16 +-
gas/testsuite/gas/i386/ilp32/x86-64-size-5.d | 12 +-
gas/testsuite/gas/i386/ilp32/x86-64-unwind.d | 6 +-
gas/testsuite/gas/i386/no-got.d | 17 +
gas/testsuite/gas/i386/no-got.s | 5 +
gas/testsuite/gas/i386/pr27198.d | 2 +
gas/testsuite/gas/i386/pr27198.err | 5 +
gas/testsuite/gas/i386/pr27198.s | 1 +
gas/testsuite/gas/i386/size-1.d | 24 +-
gas/testsuite/gas/i386/size-3.d | 16 +-
gas/testsuite/gas/i386/svr4.d | 3 -
gas/testsuite/gas/i386/x86-64-no-got.d | 17 +
gas/testsuite/gas/i386/x86-64-no-got.s | 5 +
gas/testsuite/gas/i386/x86-64-size-1.d | 24 +-
gas/testsuite/gas/i386/x86-64-size-3.d | 16 +-
gas/testsuite/gas/i386/x86-64-size-5.d | 12 +-
gas/testsuite/gas/i386/x86-64-unwind.d | 10 +-
gas/testsuite/gas/lns/lns-diag-1.l | 2 -
gas/testsuite/gas/m68hc11/indexed12.d | 4 -
gas/testsuite/gas/macros/app1.d | 1 +
gas/testsuite/gas/macros/app2.d | 1 +
gas/testsuite/gas/macros/app3.d | 1 +
gas/testsuite/gas/macros/app4.d | 1 +
gas/testsuite/gas/macros/irp.d | 2 +-
gas/testsuite/gas/macros/repeat.d | 2 +-
gas/testsuite/gas/macros/rept.d | 2 +-
gas/testsuite/gas/macros/test2.d | 2 +-
gas/testsuite/gas/macros/test3.d | 1 -
gas/testsuite/gas/macros/vararg.d | 2 +-
gas/testsuite/gas/nios2/relax.d | 25 +
gas/testsuite/gas/nios2/relax.s | 5 +
gas/testsuite/gas/ppc/power4.d | 1 -
gas/testsuite/gas/ppc/ppc.exp | 2 +
gas/testsuite/gas/ppc/rop-checks.d | 3 +
gas/testsuite/gas/ppc/rop-checks.l | 17 +
gas/testsuite/gas/ppc/rop-checks.s | 18 +
gas/testsuite/gas/ppc/rop.d | 27 +
gas/testsuite/gas/ppc/rop.s | 21 +
gas/testsuite/gas/ppc/test1elf32.d | 1 -
gas/testsuite/gas/ppc/test1elf64.d | 1 -
gas/testsuite/gas/riscv/bitmanip-insns-32.d | 37 +
gas/testsuite/gas/riscv/bitmanip-insns-64.d | 55 +
gas/testsuite/gas/riscv/bitmanip-insns.s | 58 +
gas/testsuite/gas/riscv/li32.d | 2 +-
gas/testsuite/gas/riscv/li64.d | 2 +-
gas/testsuite/gas/riscv/lla32.d | 2 +-
gas/testsuite/gas/riscv/lla64.d | 2 +-
gas/testsuite/gas/riscv/march-ok-g2.d | 2 +-
gas/testsuite/gas/riscv/march-ok-g2_p1.d | 2 +-
gas/testsuite/gas/riscv/march-ok-g2p0.d | 2 +-
gas/testsuite/gas/riscv/march-ok-i2p0.d | 2 +-
gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d | 2 +-
.../gas/riscv/march-ok-nse-with-version.d | 2 +-
gas/testsuite/gas/riscv/march-ok-two-nse.d | 2 +-
gas/testsuite/gas/riscv/pause.d | 10 +
gas/testsuite/gas/riscv/pause.s | 2 +
gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +-
.../gas/riscv/priv-reg-fail-read-only-01.l | 136 +-
.../gas/riscv/priv-reg-fail-read-only-02.l | 48 +-
gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +-
.../gas/riscv/priv-reg-fail-version-1p10.l | 48 +-
.../gas/riscv/priv-reg-fail-version-1p11.l | 46 +-
.../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +-
gas/testsuite/gas/sparc/sparc.exp | 34 +-
gas/write.c | 47 +-
gdb/ChangeLog | 1031 ++
gdb/MAINTAINERS | 5 +-
gdb/Makefile.in | 3 +
gdb/NEWS | 5 +
gdb/aarch64-linux-tdep.c | 16 +-
gdb/aarch64-tdep.c | 192 +-
gdb/ada-lang.c | 101 +-
gdb/ada-valprint.c | 2 +-
gdb/alpha-mdebug-tdep.c | 12 +-
gdb/alpha-tdep.c | 15 +-
gdb/amd64-fbsd-tdep.c | 2 +-
gdb/amd64-linux-tdep.c | 4 +-
gdb/amd64-obsd-tdep.c | 2 +-
gdb/arc-linux-nat.c | 16 +-
gdb/arc-linux-tdep.c | 47 +-
gdb/arc-newlib-tdep.c | 11 +-
gdb/arc-tdep.c | 182 +-
gdb/arc-tdep.h | 7 +-
gdb/arch/aarch64-insn.c | 9 +-
gdb/arch/aarch64-insn.h | 14 +
gdb/arm-linux-tdep.c | 2 +-
gdb/arm-tdep.c | 112 +-
gdb/auto-load.c | 214 +-
gdb/auto-load.h | 25 +-
gdb/avr-tdep.c | 39 +-
gdb/bfin-tdep.c | 6 +-
gdb/breakpoint.c | 348 +-
gdb/buildsym.c | 9 +-
gdb/c-lang.c | 8 +-
gdb/c-typeprint.c | 2 +-
gdb/c-valprint.c | 8 +-
gdb/cli/cli-cmds.c | 36 -
gdb/cli/cli-interp.c | 8 +
gdb/cli/cli-style.c | 17 +-
gdb/cli/cli-style.h | 6 +-
gdb/coffread.c | 4 +-
gdb/compile/compile-c-support.c | 8 +-
gdb/compile/compile-c-symbols.c | 13 +-
gdb/compile/compile-c-types.c | 12 +-
gdb/compile/compile-c.h | 2 +-
gdb/compile/compile-cplus-types.c | 6 +-
gdb/compile/compile-internal.h | 3 +-
gdb/compile/compile-loc2c.c | 30 +-
gdb/compile/compile.c | 16 +-
gdb/compile/compile.h | 4 +-
gdb/copyright.py | 2 +-
gdb/cp-valprint.c | 2 +-
gdb/cris-tdep.c | 58 +-
gdb/csky-tdep.c | 14 +-
gdb/debug.c | 4 +
gdb/doc/ChangeLog | 54 +
gdb/doc/gdb.texinfo | 490 +-
gdb/doc/python.texi | 22 +-
gdb/dwarf2/attribute.c | 5 +-
gdb/dwarf2/attribute.h | 1 +
gdb/dwarf2/die.h | 36 +-
gdb/dwarf2/index-write.c | 8 +
gdb/dwarf2/loc.c | 12 +-
gdb/dwarf2/loc.h | 2 +-
gdb/dwarf2/read.c | 340 +-
gdb/expprint.c | 9 +-
gdb/expression.h | 3 +-
gdb/extension-priv.h | 2 +-
gdb/extension.c | 7 +-
gdb/extension.h | 5 +-
gdb/f-array-walker.h | 4 +-
gdb/f-exp.y | 36 +-
gdb/f-lang.c | 12 +-
gdb/f-typeprint.c | 7 +-
gdb/f-valprint.c | 7 +-
gdb/fbsd-tdep.c | 135 +-
gdb/features/aarch64-fpu.c | 5 +
gdb/features/aarch64-fpu.xml | 2 +
gdb/findvar.c | 4 +-
gdb/frame-unwind.c | 2 +-
gdb/frame-unwind.h | 2 +-
gdb/frame.c | 20 +-
gdb/frame.h | 16 +-
gdb/frv-tdep.c | 11 +-
gdb/gcore.c | 136 +
gdb/gcore.h | 20 +
gdb/gdb_bfd.c | 70 +-
gdb/gdbarch.c | 2 +-
gdb/gdbcmd.h | 9 +-
gdb/gdbtypes.c | 124 +-
gdb/gdbtypes.h | 84 +-
gdb/gnu-v2-abi.c | 2 +-
gdb/gnu-v3-abi.c | 22 +-
gdb/go-valprint.c | 2 +-
gdb/guile/guile-internal.h | 5 +-
gdb/guile/scm-auto-load.c | 5 +-
gdb/guile/scm-pretty-print.c | 2 +-
gdb/guile/scm-type.c | 4 +-
gdb/guile/scm-value.c | 2 +-
gdb/hppa-linux-tdep.c | 20 +-
gdb/hppa-tdep.c | 66 +-
gdb/hppa-tdep.h | 4 +-
gdb/i386-fbsd-tdep.c | 16 +-
gdb/i386-gnu-tdep.c | 2 +-
gdb/i386-linux-tdep.c | 10 +-
gdb/i386-netbsd-tdep.c | 2 +-
gdb/i386-obsd-tdep.c | 2 +-
gdb/i386-tdep.c | 12 +-
gdb/i387-tdep.c | 6 +-
gdb/ia64-tdep.c | 6 +-
gdb/infcall.c | 2 +-
gdb/infrun.c | 82 +-
gdb/infrun.h | 10 +
gdb/jit.c | 80 +-
gdb/language.c | 4 +-
gdb/linux-nat.c | 2 +-
gdb/linux-tdep.c | 149 +-
gdb/linux-thread-db.c | 11 +-
gdb/lm32-tdep.c | 13 +-
gdb/m2-valprint.c | 4 +-
gdb/m32r-linux-tdep.c | 16 +-
gdb/m32r-tdep.c | 11 +-
gdb/m68hc11-tdep.c | 30 +-
gdb/m68k-linux-tdep.c | 2 +-
gdb/m68k-tdep.c | 6 +-
gdb/main.c | 17 +-
gdb/maint-test-options.c | 2 +-
gdb/mep-tdep.c | 2 +-
gdb/mi/mi-cmds.c | 5 +-
gdb/mips-tdep.c | 52 +-
gdb/moxie-tdep.c | 2 +-
gdb/nat/amd64-linux-siginfo.c | 13 +
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.../{sim => }/bfin/c_cactrl_iflush_pr_pp.s | 0
sim/testsuite/{sim => }/bfin/c_calla_ljump.s | 0
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.../{sim => }/bfin/c_cc_flag_ccmv_depend.S | 0
.../{sim => }/bfin/c_cc_flagdreg_mvbrsft.s | 0
.../{sim => }/bfin/c_cc_flagdreg_mvbrsft_s1.s | 0
.../{sim => }/bfin/c_cc_flagdreg_mvbrsft_sn.s | 0
.../{sim => }/bfin/c_cc_regmvlogi_mvbrsft.s | 0
.../{sim => }/bfin/c_cc_regmvlogi_mvbrsft_s1.s | 0
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.../{sim => }/bfin/c_compi2opd_dr_add_i7_n.s | 0
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.../{sim => }/bfin/c_dagmodik_lnz_imgebl.s | 0
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.../{sim => }/bfin/c_dagmodim_lnz_imgebl.s | 0
.../{sim => }/bfin/c_dagmodim_lnz_imltbl.s | 0
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.../{sim => }/bfin/c_dsp32mac_pair_a1a0_i.s | 0
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.../{sim => }/bfin/c_seq_ex2_raise_mmrj_mvpop.S | 0
.../{sim => }/bfin/c_seq_ex3_ls_brcc_mvp.S | 0
.../{sim => }/bfin/c_seq_ex3_ls_mmr_mvp.S | 0
.../{sim => }/bfin/c_seq_ex3_ls_mmrj_mvp.S | 0
.../{sim => }/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S | 0
.../{sim => }/bfin/c_seq_wb_cs_lsmmrj_mvp.S | 0
.../{sim => }/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S | 0
.../{sim => }/bfin/c_seq_wb_rti_lsmmrj_mvp.S | 0
.../{sim => }/bfin/c_seq_wb_rtn_lsmmrj_mvp.S | 0
.../{sim => }/bfin/c_seq_wb_rtx_lsmmrj_mvp.S | 0
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sim/testsuite/d10v-elf/ChangeLog | 139 -
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sim/testsuite/d10v-elf/t-ld-st.s | 32 -
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sim/testsuite/d10v-elf/t-macros.i | 233 -
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sim/testsuite/d10v-elf/t-rep.s | 45 -
sim/testsuite/d10v-elf/t-rie-xx.s | 12 -
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sim/testsuite/{sim => }/frv/fcku.cgs | 0
sim/testsuite/{sim => }/frv/fckue.cgs | 0
sim/testsuite/{sim => }/frv/fckug.cgs | 0
sim/testsuite/{sim => }/frv/fckuge.cgs | 0
sim/testsuite/{sim => }/frv/fckul.cgs | 0
sim/testsuite/{sim => }/frv/fckule.cgs | 0
sim/testsuite/{sim => }/frv/fcmpd.cgs | 0
sim/testsuite/{sim => }/frv/fcmps.cgs | 0
sim/testsuite/{sim => }/frv/fdabss.cgs | 0
sim/testsuite/{sim => }/frv/fdadds.cgs | 0
sim/testsuite/{sim => }/frv/fdcmps.cgs | 0
sim/testsuite/{sim => }/frv/fddivs.cgs | 0
sim/testsuite/{sim => }/frv/fditos.cgs | 0
sim/testsuite/{sim => }/frv/fdivd.cgs | 0
sim/testsuite/{sim => }/frv/fdivs.cgs | 0
sim/testsuite/{sim => }/frv/fdmadds.cgs | 0
sim/testsuite/{sim => }/frv/fdmas.cgs | 0
sim/testsuite/{sim => }/frv/fdmovs.cgs | 0
sim/testsuite/{sim => }/frv/fdmss.cgs | 0
sim/testsuite/{sim => }/frv/fdmulcs.cgs | 0
sim/testsuite/{sim => }/frv/fdmuls.cgs | 0
sim/testsuite/{sim => }/frv/fdnegs.cgs | 0
sim/testsuite/{sim => }/frv/fdsads.cgs | 0
sim/testsuite/{sim => }/frv/fdsqrts.cgs | 0
sim/testsuite/{sim => }/frv/fdstoi.cgs | 0
sim/testsuite/{sim => }/frv/fdsubs.cgs | 0
sim/testsuite/{sim => }/frv/fdtoi.cgs | 0
sim/testsuite/{sim => }/frv/fitod.cgs | 0
sim/testsuite/{sim => }/frv/fitos.cgs | 0
sim/testsuite/{sim => }/frv/fmad.cgs | 0
sim/testsuite/{sim => }/frv/fmaddd.cgs | 0
sim/testsuite/{sim => }/frv/fmadds.cgs | 0
sim/testsuite/{sim => }/frv/fmas.cgs | 0
sim/testsuite/{sim => }/frv/fmovd.cgs | 0
sim/testsuite/{sim => }/frv/fmovs.cgs | 0
sim/testsuite/{sim => }/frv/fmsd.cgs | 0
sim/testsuite/{sim => }/frv/fmss.cgs | 0
sim/testsuite/{sim => }/frv/fmsubd.cgs | 0
sim/testsuite/{sim => }/frv/fmsubs.cgs | 0
sim/testsuite/{sim => }/frv/fmuld.cgs | 0
sim/testsuite/{sim => }/frv/fmuls.cgs | 0
sim/testsuite/{sim => }/frv/fnegd.cgs | 0
sim/testsuite/{sim => }/frv/fnegs.cgs | 0
sim/testsuite/{sim => }/frv/fnop.cgs | 0
sim/testsuite/{sim => }/frv/fr400/addss.cgs | 0
sim/testsuite/{sim => }/frv/fr400/allinsn.exp | 0
sim/testsuite/{sim => }/frv/fr400/csdiv.cgs | 0
sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr400/masaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr400/maveh.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mclracc.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs | 0
sim/testsuite/{sim => }/frv/fr400/movgs.cgs | 0
sim/testsuite/{sim => }/frv/fr400/movsg.cgs | 0
sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr400/scutss.cgs | 0
sim/testsuite/{sim => }/frv/fr400/sdiv.cgs | 0
sim/testsuite/{sim => }/frv/fr400/sdivi.cgs | 0
sim/testsuite/{sim => }/frv/fr400/slass.cgs | 0
sim/testsuite/{sim => }/frv/fr400/smass.cgs | 0
sim/testsuite/{sim => }/frv/fr400/smsss.cgs | 0
sim/testsuite/{sim => }/frv/fr400/smu.cgs | 0
sim/testsuite/{sim => }/frv/fr400/subss.cgs | 0
sim/testsuite/{sim => }/frv/fr400/udiv.cgs | 0
sim/testsuite/{sim => }/frv/fr400/udivi.cgs | 0
sim/testsuite/{sim => }/frv/fr500/allinsn.exp | 0
sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs | 0
sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs | 0
sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs | 0
sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs | 0
sim/testsuite/{sim => }/frv/fr500/dcpl.cgs | 0
sim/testsuite/{sim => }/frv/fr500/dcul.cgs | 0
sim/testsuite/{sim => }/frv/fr500/mclracc.cgs | 0
sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs | 0
sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs | 0
sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs | 0
sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/allinsn.exp | 0
sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmaddhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmcpxiu.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmcpxru.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmmachs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmmachu.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmqaddhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmqaddhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmqmachs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmqmachu.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmqsubhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmqsubhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmsubhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/dcpl.cgs | 0
sim/testsuite/{sim => }/frv/fr550/dcul.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mabshs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/maddhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/maddhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/masaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mmachs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mmachu.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/msubhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/msubhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mtrap.cgs | 0
sim/testsuite/{sim => }/frv/fr550/udiv.cgs | 0
sim/testsuite/{sim => }/frv/fr550/udivi.cgs | 0
sim/testsuite/{sim => }/frv/fsqrtd.cgs | 0
sim/testsuite/{sim => }/frv/fsqrts.cgs | 0
sim/testsuite/{sim => }/frv/fstoi.cgs | 0
sim/testsuite/{sim => }/frv/fsubd.cgs | 0
sim/testsuite/{sim => }/frv/fsubs.cgs | 0
sim/testsuite/{sim => }/frv/fteq.cgs | 0
sim/testsuite/{sim => }/frv/ftge.cgs | 0
sim/testsuite/{sim => }/frv/ftgt.cgs | 0
sim/testsuite/{sim => }/frv/ftieq.cgs | 0
sim/testsuite/{sim => }/frv/ftige.cgs | 0
sim/testsuite/{sim => }/frv/ftigt.cgs | 0
sim/testsuite/{sim => }/frv/ftile.cgs | 0
sim/testsuite/{sim => }/frv/ftilg.cgs | 0
sim/testsuite/{sim => }/frv/ftilt.cgs | 0
sim/testsuite/{sim => }/frv/ftine.cgs | 0
sim/testsuite/{sim => }/frv/ftino.cgs | 0
sim/testsuite/{sim => }/frv/ftio.cgs | 0
sim/testsuite/{sim => }/frv/ftira.cgs | 0
sim/testsuite/{sim => }/frv/ftiu.cgs | 0
sim/testsuite/{sim => }/frv/ftiue.cgs | 0
sim/testsuite/{sim => }/frv/ftiug.cgs | 0
sim/testsuite/{sim => }/frv/ftiuge.cgs | 0
sim/testsuite/{sim => }/frv/ftiul.cgs | 0
sim/testsuite/{sim => }/frv/ftle.cgs | 0
sim/testsuite/{sim => }/frv/ftlg.cgs | 0
sim/testsuite/{sim => }/frv/ftlt.cgs | 0
sim/testsuite/{sim => }/frv/ftne.cgs | 0
sim/testsuite/{sim => }/frv/ftno.cgs | 0
sim/testsuite/{sim => }/frv/fto.cgs | 0
sim/testsuite/{sim => }/frv/ftra.cgs | 0
sim/testsuite/{sim => }/frv/ftu.cgs | 0
sim/testsuite/{sim => }/frv/ftue.cgs | 0
sim/testsuite/{sim => }/frv/ftug.cgs | 0
sim/testsuite/{sim => }/frv/ftuge.cgs | 0
sim/testsuite/{sim => }/frv/ftul.cgs | 0
sim/testsuite/{sim => }/frv/ftule.cgs | 0
sim/testsuite/frv/grloop.ms | 13 +
sim/testsuite/frv/hello.ms | 19 +
sim/testsuite/{sim => }/frv/icei.cgs | 0
sim/testsuite/{sim => }/frv/ici.cgs | 0
sim/testsuite/{sim => }/frv/icpl.cgs | 0
sim/testsuite/{sim => }/frv/icul.cgs | 0
sim/testsuite/{sim => }/frv/interrupts.exp | 0
.../{sim => }/frv/interrupts/Ipipe-fr400.cgs | 0
.../{sim => }/frv/interrupts/Ipipe-fr500.cgs | 0
.../{sim => }/frv/interrupts/badalign-fr550.cgs | 0
.../{sim => }/frv/interrupts/badalign.cgs | 0
.../{sim => }/frv/interrupts/compound-fr550.cgs | 0
.../{sim => }/frv/interrupts/compound.cgs | 0
.../frv/interrupts/data_store_error-fr550.cgs | 0
.../{sim => }/frv/interrupts/data_store_error.cgs | 0
.../frv/interrupts/fp_exception-fr550.cgs | 0
.../{sim => }/frv/interrupts/fp_exception.cgs | 0
sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs | 0
.../frv/interrupts/insn_access_error-fr550.cgs | 0
.../{sim => }/frv/interrupts/insn_access_error.cgs | 0
.../{sim => }/frv/interrupts/mp_exception.cgs | 0
.../frv/interrupts/privileged_instruction.cgs | 0
.../{sim => }/frv/interrupts/regalign.cgs | 0
sim/testsuite/{sim => }/frv/interrupts/reset.cgs | 0
.../{sim => }/frv/interrupts/shadow_regs.cgs | 0
sim/testsuite/{sim => }/frv/interrupts/timer.cgs | 0
sim/testsuite/{sim => }/frv/jmpil.cgs | 0
sim/testsuite/{sim => }/frv/jmpl.cgs | 0
sim/testsuite/{sim => }/frv/jmpl.pcgs | 0
sim/testsuite/{sim => }/frv/ld.cgs | 0
sim/testsuite/{sim => }/frv/ldbf.cgs | 0
sim/testsuite/{sim => }/frv/ldbfi.cgs | 0
sim/testsuite/{sim => }/frv/ldbfu.cgs | 0
sim/testsuite/{sim => }/frv/ldc.cgs | 0
sim/testsuite/{sim => }/frv/ldcu.cgs | 0
sim/testsuite/{sim => }/frv/ldd.cgs | 0
sim/testsuite/{sim => }/frv/lddc.cgs | 0
sim/testsuite/{sim => }/frv/lddcu.cgs | 0
sim/testsuite/{sim => }/frv/lddf.cgs | 0
sim/testsuite/{sim => }/frv/lddfi.cgs | 0
sim/testsuite/{sim => }/frv/lddfu.cgs | 0
sim/testsuite/{sim => }/frv/lddi.cgs | 0
sim/testsuite/{sim => }/frv/lddu.cgs | 0
sim/testsuite/{sim => }/frv/ldf.cgs | 0
sim/testsuite/{sim => }/frv/ldfi.cgs | 0
sim/testsuite/{sim => }/frv/ldfu.cgs | 0
sim/testsuite/{sim => }/frv/ldhf.cgs | 0
sim/testsuite/{sim => }/frv/ldhfi.cgs | 0
sim/testsuite/{sim => }/frv/ldhfu.cgs | 0
sim/testsuite/{sim => }/frv/ldi.cgs | 0
sim/testsuite/{sim => }/frv/ldq.cgs | 0
sim/testsuite/{sim => }/frv/ldqc.cgs | 0
sim/testsuite/{sim => }/frv/ldqcu.cgs | 0
sim/testsuite/{sim => }/frv/ldqf.cgs | 0
sim/testsuite/{sim => }/frv/ldqfi.cgs | 0
sim/testsuite/{sim => }/frv/ldqfu.cgs | 0
sim/testsuite/{sim => }/frv/ldqi.cgs | 0
sim/testsuite/{sim => }/frv/ldqu.cgs | 0
sim/testsuite/{sim => }/frv/ldsb.cgs | 0
sim/testsuite/{sim => }/frv/ldsbi.cgs | 0
sim/testsuite/{sim => }/frv/ldsbu.cgs | 0
sim/testsuite/{sim => }/frv/ldsh.cgs | 0
sim/testsuite/{sim => }/frv/ldshi.cgs | 0
sim/testsuite/{sim => }/frv/ldshu.cgs | 0
sim/testsuite/{sim => }/frv/ldu.cgs | 0
sim/testsuite/{sim => }/frv/ldub.cgs | 0
sim/testsuite/{sim => }/frv/ldubi.cgs | 0
sim/testsuite/{sim => }/frv/ldubu.cgs | 0
sim/testsuite/{sim => }/frv/lduh.cgs | 0
sim/testsuite/{sim => }/frv/lduhi.cgs | 0
sim/testsuite/{sim => }/frv/lduhu.cgs | 0
sim/testsuite/{sim => }/frv/lrbranch.pcgs | 0
sim/testsuite/{sim => }/frv/mabshs.cgs | 0
sim/testsuite/{sim => }/frv/maddhss.cgs | 0
sim/testsuite/{sim => }/frv/maddhus.cgs | 0
sim/testsuite/{sim => }/frv/mand.cgs | 0
sim/testsuite/{sim => }/frv/maveh.cgs | 0
sim/testsuite/{sim => }/frv/mbtoh.cgs | 0
sim/testsuite/{sim => }/frv/mbtohe.cgs | 0
sim/testsuite/{sim => }/frv/mclracc.cgs | 0
sim/testsuite/{sim => }/frv/mcmpsh.cgs | 0
sim/testsuite/{sim => }/frv/mcmpuh.cgs | 0
sim/testsuite/{sim => }/frv/mcop1.cgs | 0
sim/testsuite/{sim => }/frv/mcop2.cgs | 0
sim/testsuite/{sim => }/frv/mcplhi.cgs | 0
sim/testsuite/{sim => }/frv/mcpli.cgs | 0
sim/testsuite/{sim => }/frv/mcpxis.cgs | 0
sim/testsuite/{sim => }/frv/mcpxiu.cgs | 0
sim/testsuite/{sim => }/frv/mcpxrs.cgs | 0
sim/testsuite/{sim => }/frv/mcpxru.cgs | 0
sim/testsuite/{sim => }/frv/mcut.cgs | 0
sim/testsuite/{sim => }/frv/mcuti.cgs | 0
sim/testsuite/{sim => }/frv/mcutss.cgs | 0
sim/testsuite/{sim => }/frv/mcutssi.cgs | 0
sim/testsuite/{sim => }/frv/mdaddaccs.cgs | 0
sim/testsuite/{sim => }/frv/mdasaccs.cgs | 0
sim/testsuite/{sim => }/frv/mdcutssi.cgs | 0
sim/testsuite/{sim => }/frv/mdpackh.cgs | 0
sim/testsuite/{sim => }/frv/mdrotli.cgs | 0
sim/testsuite/{sim => }/frv/mdsubaccs.cgs | 0
sim/testsuite/{sim => }/frv/mdunpackh.cgs | 0
sim/testsuite/{sim => }/frv/membar.cgs | 0
sim/testsuite/{sim => }/frv/mexpdhd.cgs | 0
sim/testsuite/{sim => }/frv/mexpdhw.cgs | 0
sim/testsuite/{sim => }/frv/mhdseth.cgs | 0
sim/testsuite/{sim => }/frv/mhdsets.cgs | 0
sim/testsuite/{sim => }/frv/mhsethih.cgs | 0
sim/testsuite/{sim => }/frv/mhsethis.cgs | 0
sim/testsuite/{sim => }/frv/mhsetloh.cgs | 0
sim/testsuite/{sim => }/frv/mhsetlos.cgs | 0
sim/testsuite/{sim => }/frv/mhtob.cgs | 0
sim/testsuite/frv/misc.exp | 19 +
sim/testsuite/{sim => }/frv/mmachs.cgs | 0
sim/testsuite/{sim => }/frv/mmachu.cgs | 0
sim/testsuite/{sim => }/frv/mmrdhs.cgs | 0
sim/testsuite/{sim => }/frv/mmrdhu.cgs | 0
sim/testsuite/{sim => }/frv/mmulhs.cgs | 0
sim/testsuite/{sim => }/frv/mmulhu.cgs | 0
sim/testsuite/{sim => }/frv/mmulxhs.cgs | 0
sim/testsuite/{sim => }/frv/mmulxhu.cgs | 0
sim/testsuite/{sim => }/frv/mnop.cgs | 0
sim/testsuite/{sim => }/frv/mnot.cgs | 0
sim/testsuite/{sim => }/frv/mor.cgs | 0
sim/testsuite/{sim => }/frv/mov.cgs | 0
sim/testsuite/{sim => }/frv/movfg.cgs | 0
sim/testsuite/{sim => }/frv/movfgd.cgs | 0
sim/testsuite/{sim => }/frv/movfgq.cgs | 0
sim/testsuite/{sim => }/frv/movgf.cgs | 0
sim/testsuite/{sim => }/frv/movgfd.cgs | 0
sim/testsuite/{sim => }/frv/movgfq.cgs | 0
sim/testsuite/{sim => }/frv/movgs.cgs | 0
sim/testsuite/{sim => }/frv/movsg.cgs | 0
sim/testsuite/{sim => }/frv/mpackh.cgs | 0
sim/testsuite/{sim => }/frv/mqcpxis.cgs | 0
sim/testsuite/{sim => }/frv/mqcpxiu.cgs | 0
sim/testsuite/{sim => }/frv/mqcpxrs.cgs | 0
sim/testsuite/{sim => }/frv/mqcpxru.cgs | 0
sim/testsuite/{sim => }/frv/mqlclrhs.cgs | 0
sim/testsuite/{sim => }/frv/mqlmths.cgs | 0
sim/testsuite/{sim => }/frv/mqmachs.cgs | 0
sim/testsuite/{sim => }/frv/mqmachu.cgs | 0
sim/testsuite/{sim => }/frv/mqmacxhs.cgs | 0
sim/testsuite/{sim => }/frv/mqmulhs.cgs | 0
sim/testsuite/{sim => }/frv/mqmulhu.cgs | 0
sim/testsuite/{sim => }/frv/mqmulxhs.cgs | 0
sim/testsuite/{sim => }/frv/mqmulxhu.cgs | 0
sim/testsuite/{sim => }/frv/mqsaths.cgs | 0
sim/testsuite/{sim => }/frv/mqsllhi.cgs | 0
sim/testsuite/{sim => }/frv/mqsrahi.cgs | 0
sim/testsuite/{sim => }/frv/mqxmachs.cgs | 0
sim/testsuite/{sim => }/frv/mqxmacxhs.cgs | 0
sim/testsuite/{sim => }/frv/mrdacc.cgs | 0
sim/testsuite/{sim => }/frv/mrdaccg.cgs | 0
sim/testsuite/{sim => }/frv/mrotli.cgs | 0
sim/testsuite/{sim => }/frv/mrotri.cgs | 0
sim/testsuite/{sim => }/frv/msaths.cgs | 0
sim/testsuite/{sim => }/frv/msathu.cgs | 0
sim/testsuite/{sim => }/frv/msllhi.cgs | 0
sim/testsuite/{sim => }/frv/msrahi.cgs | 0
sim/testsuite/{sim => }/frv/msrlhi.cgs | 0
sim/testsuite/{sim => }/frv/msubhss.cgs | 0
sim/testsuite/{sim => }/frv/msubhus.cgs | 0
sim/testsuite/{sim => }/frv/mtrap.cgs | 0
sim/testsuite/{sim => }/frv/munpackh.cgs | 0
sim/testsuite/{sim => }/frv/mwcut.cgs | 0
sim/testsuite/{sim => }/frv/mwcuti.cgs | 0
sim/testsuite/{sim => }/frv/mwtacc.cgs | 0
sim/testsuite/{sim => }/frv/mwtaccg.cgs | 0
sim/testsuite/{sim => }/frv/mxor.cgs | 0
sim/testsuite/{sim => }/frv/nandcr.cgs | 0
sim/testsuite/{sim => }/frv/nandncr.cgs | 0
sim/testsuite/{sim => }/frv/nfadds.cgs | 0
sim/testsuite/{sim => }/frv/nfdadds.cgs | 0
sim/testsuite/{sim => }/frv/nfdcmps.cgs | 0
sim/testsuite/{sim => }/frv/nfddivs.cgs | 0
sim/testsuite/{sim => }/frv/nfditos.cgs | 0
sim/testsuite/{sim => }/frv/nfdivs.cgs | 0
sim/testsuite/{sim => }/frv/nfdmadds.cgs | 0
sim/testsuite/{sim => }/frv/nfdmas.cgs | 0
sim/testsuite/{sim => }/frv/nfdmss.cgs | 0
sim/testsuite/{sim => }/frv/nfdmulcs.cgs | 0
sim/testsuite/{sim => }/frv/nfdmuls.cgs | 0
sim/testsuite/{sim => }/frv/nfdsads.cgs | 0
sim/testsuite/{sim => }/frv/nfdsqrts.cgs | 0
sim/testsuite/{sim => }/frv/nfdstoi.cgs | 0
sim/testsuite/{sim => }/frv/nfdsubs.cgs | 0
sim/testsuite/{sim => }/frv/nfitos.cgs | 0
sim/testsuite/{sim => }/frv/nfmadds.cgs | 0
sim/testsuite/{sim => }/frv/nfmas.cgs | 0
sim/testsuite/{sim => }/frv/nfmss.cgs | 0
sim/testsuite/{sim => }/frv/nfmsubs.cgs | 0
sim/testsuite/{sim => }/frv/nfmuls.cgs | 0
sim/testsuite/{sim => }/frv/nfsqrts.cgs | 0
sim/testsuite/{sim => }/frv/nfstoi.cgs | 0
sim/testsuite/{sim => }/frv/nfsubs.cgs | 0
sim/testsuite/{sim => }/frv/nld.cgs | 0
sim/testsuite/{sim => }/frv/nldbf.cgs | 0
sim/testsuite/{sim => }/frv/nldbfi.cgs | 0
sim/testsuite/{sim => }/frv/nldbfu.cgs | 0
sim/testsuite/{sim => }/frv/nldd.cgs | 0
sim/testsuite/{sim => }/frv/nlddf.cgs | 0
sim/testsuite/{sim => }/frv/nlddfi.cgs | 0
sim/testsuite/{sim => }/frv/nlddfu.cgs | 0
sim/testsuite/{sim => }/frv/nlddi.cgs | 0
sim/testsuite/{sim => }/frv/nlddu.cgs | 0
sim/testsuite/{sim => }/frv/nldf.cgs | 0
sim/testsuite/{sim => }/frv/nldfi.cgs | 0
sim/testsuite/{sim => }/frv/nldfu.cgs | 0
sim/testsuite/{sim => }/frv/nldhf.cgs | 0
sim/testsuite/{sim => }/frv/nldhfi.cgs | 0
sim/testsuite/{sim => }/frv/nldhfu.cgs | 0
sim/testsuite/{sim => }/frv/nldi.cgs | 0
sim/testsuite/{sim => }/frv/nldq.cgs | 0
sim/testsuite/{sim => }/frv/nldqf.cgs | 0
sim/testsuite/{sim => }/frv/nldqfi.cgs | 0
sim/testsuite/{sim => }/frv/nldqfu.cgs | 0
sim/testsuite/{sim => }/frv/nldqu.cgs | 0
sim/testsuite/{sim => }/frv/nldsb.cgs | 0
sim/testsuite/{sim => }/frv/nldsbi.cgs | 0
sim/testsuite/{sim => }/frv/nldsbu.cgs | 0
sim/testsuite/{sim => }/frv/nldsh.cgs | 0
sim/testsuite/{sim => }/frv/nldshi.cgs | 0
sim/testsuite/{sim => }/frv/nldshu.cgs | 0
sim/testsuite/{sim => }/frv/nldu.cgs | 0
sim/testsuite/{sim => }/frv/nldub.cgs | 0
sim/testsuite/{sim => }/frv/nldubi.cgs | 0
sim/testsuite/{sim => }/frv/nldubu.cgs | 0
sim/testsuite/{sim => }/frv/nlduh.cgs | 0
sim/testsuite/{sim => }/frv/nlduhi.cgs | 0
sim/testsuite/{sim => }/frv/nlduhu.cgs | 0
sim/testsuite/{sim => }/frv/nop.cgs | 0
sim/testsuite/{sim => }/frv/norcr.cgs | 0
sim/testsuite/{sim => }/frv/norncr.cgs | 0
sim/testsuite/{sim => }/frv/not.cgs | 0
sim/testsuite/{sim => }/frv/notcr.cgs | 0
sim/testsuite/{sim => }/frv/nsdiv.cgs | 0
sim/testsuite/{sim => }/frv/nsdivi.cgs | 0
sim/testsuite/{sim => }/frv/nudiv.cgs | 0
sim/testsuite/{sim => }/frv/nudivi.cgs | 0
sim/testsuite/{sim => }/frv/or.cgs | 0
sim/testsuite/{sim => }/frv/orcc.cgs | 0
sim/testsuite/{sim => }/frv/orcr.cgs | 0
sim/testsuite/{sim => }/frv/ori.cgs | 0
sim/testsuite/{sim => }/frv/oricc.cgs | 0
sim/testsuite/{sim => }/frv/orncr.cgs | 0
sim/testsuite/{sim => }/frv/parallel.exp | 0
sim/testsuite/{sim => }/frv/ret.cgs | 0
sim/testsuite/{sim => }/frv/rett.cgs | 0
sim/testsuite/{sim => }/frv/scan.cgs | 0
sim/testsuite/{sim => }/frv/scani.cgs | 0
sim/testsuite/{sim => }/frv/sdiv.cgs | 0
sim/testsuite/{sim => }/frv/sdivi.cgs | 0
sim/testsuite/{sim => }/frv/sethi.cgs | 0
sim/testsuite/{sim => }/frv/sethilo.pcgs | 0
sim/testsuite/{sim => }/frv/setlo.cgs | 0
sim/testsuite/{sim => }/frv/setlos.cgs | 0
sim/testsuite/{sim => }/frv/sll.cgs | 0
sim/testsuite/{sim => }/frv/sllcc.cgs | 0
sim/testsuite/{sim => }/frv/slli.cgs | 0
sim/testsuite/{sim => }/frv/sllicc.cgs | 0
sim/testsuite/{sim => }/frv/smul.cgs | 0
sim/testsuite/{sim => }/frv/smulcc.cgs | 0
sim/testsuite/{sim => }/frv/smuli.cgs | 0
sim/testsuite/{sim => }/frv/smulicc.cgs | 0
sim/testsuite/{sim => }/frv/sra.cgs | 0
sim/testsuite/{sim => }/frv/sracc.cgs | 0
sim/testsuite/{sim => }/frv/srai.cgs | 0
sim/testsuite/{sim => }/frv/sraicc.cgs | 0
sim/testsuite/{sim => }/frv/srl.cgs | 0
sim/testsuite/{sim => }/frv/srlcc.cgs | 0
sim/testsuite/{sim => }/frv/srli.cgs | 0
sim/testsuite/{sim => }/frv/srlicc.cgs | 0
sim/testsuite/{sim => }/frv/st.cgs | 0
sim/testsuite/{sim => }/frv/stb.cgs | 0
sim/testsuite/{sim => }/frv/stbf.cgs | 0
sim/testsuite/{sim => }/frv/stbfi.cgs | 0
sim/testsuite/{sim => }/frv/stbfu.cgs | 0
sim/testsuite/{sim => }/frv/stbi.cgs | 0
sim/testsuite/{sim => }/frv/stbu.cgs | 0
sim/testsuite/{sim => }/frv/stc.cgs | 0
sim/testsuite/{sim => }/frv/stcu.cgs | 0
sim/testsuite/{sim => }/frv/std.cgs | 0
sim/testsuite/{sim => }/frv/std.pcgs | 0
sim/testsuite/{sim => }/frv/stdc.cgs | 0
sim/testsuite/{sim => }/frv/stdc.pcgs | 0
sim/testsuite/{sim => }/frv/stdcu.cgs | 0
sim/testsuite/{sim => }/frv/stdf.cgs | 0
sim/testsuite/{sim => }/frv/stdf.pcgs | 0
sim/testsuite/{sim => }/frv/stdfi.cgs | 0
sim/testsuite/{sim => }/frv/stdfu.cgs | 0
sim/testsuite/{sim => }/frv/stdi.cgs | 0
sim/testsuite/{sim => }/frv/stdu.cgs | 0
sim/testsuite/{sim => }/frv/stf.cgs | 0
sim/testsuite/{sim => }/frv/stfi.cgs | 0
sim/testsuite/{sim => }/frv/stfu.cgs | 0
sim/testsuite/{sim => }/frv/sth.cgs | 0
sim/testsuite/{sim => }/frv/sthf.cgs | 0
sim/testsuite/{sim => }/frv/sthfi.cgs | 0
sim/testsuite/{sim => }/frv/sthfu.cgs | 0
sim/testsuite/{sim => }/frv/sthi.cgs | 0
sim/testsuite/{sim => }/frv/sthu.cgs | 0
sim/testsuite/{sim => }/frv/sti.cgs | 0
sim/testsuite/{sim => }/frv/stq.cgs | 0
sim/testsuite/{sim => }/frv/stq.pcgs | 0
sim/testsuite/{sim => }/frv/stqc.cgs | 0
sim/testsuite/{sim => }/frv/stqc.pcgs | 0
sim/testsuite/{sim => }/frv/stqcu.cgs | 0
sim/testsuite/{sim => }/frv/stqf.cgs | 0
sim/testsuite/{sim => }/frv/stqf.pcgs | 0
sim/testsuite/{sim => }/frv/stqfi.cgs | 0
sim/testsuite/{sim => }/frv/stqfu.cgs | 0
sim/testsuite/{sim => }/frv/stqi.cgs | 0
sim/testsuite/{sim => }/frv/stqu.cgs | 0
sim/testsuite/{sim => }/frv/stu.cgs | 0
sim/testsuite/{sim => }/frv/sub.cgs | 0
sim/testsuite/{sim => }/frv/subcc.cgs | 0
sim/testsuite/{sim => }/frv/subi.cgs | 0
sim/testsuite/{sim => }/frv/subicc.cgs | 0
sim/testsuite/{sim => }/frv/subx.cgs | 0
sim/testsuite/{sim => }/frv/subxcc.cgs | 0
sim/testsuite/{sim => }/frv/subxi.cgs | 0
sim/testsuite/{sim => }/frv/subxicc.cgs | 0
sim/testsuite/{sim => }/frv/swap.cgs | 0
sim/testsuite/{sim => }/frv/swapi.cgs | 0
sim/testsuite/{sim => }/frv/tc.cgs | 0
sim/testsuite/{sim => }/frv/teq.cgs | 0
sim/testsuite/{sim => }/frv/testutils.inc | 0
sim/testsuite/{sim => }/frv/tge.cgs | 0
sim/testsuite/{sim => }/frv/tgt.cgs | 0
sim/testsuite/{sim => }/frv/thi.cgs | 0
sim/testsuite/{sim => }/frv/tic.cgs | 0
sim/testsuite/{sim => }/frv/tieq.cgs | 0
sim/testsuite/{sim => }/frv/tige.cgs | 0
sim/testsuite/{sim => }/frv/tigt.cgs | 0
sim/testsuite/{sim => }/frv/tihi.cgs | 0
sim/testsuite/{sim => }/frv/tile.cgs | 0
sim/testsuite/{sim => }/frv/tils.cgs | 0
sim/testsuite/{sim => }/frv/tilt.cgs | 0
sim/testsuite/{sim => }/frv/tin.cgs | 0
sim/testsuite/{sim => }/frv/tinc.cgs | 0
sim/testsuite/{sim => }/frv/tine.cgs | 0
sim/testsuite/{sim => }/frv/tino.cgs | 0
sim/testsuite/{sim => }/frv/tinv.cgs | 0
sim/testsuite/{sim => }/frv/tip.cgs | 0
sim/testsuite/{sim => }/frv/tira.cgs | 0
sim/testsuite/{sim => }/frv/tiv.cgs | 0
sim/testsuite/{sim => }/frv/tle.cgs | 0
sim/testsuite/{sim => }/frv/tls.cgs | 0
sim/testsuite/{sim => }/frv/tlt.cgs | 0
sim/testsuite/{sim => }/frv/tn.cgs | 0
sim/testsuite/{sim => }/frv/tnc.cgs | 0
sim/testsuite/{sim => }/frv/tne.cgs | 0
sim/testsuite/{sim => }/frv/tno.cgs | 0
sim/testsuite/{sim => }/frv/tnv.cgs | 0
sim/testsuite/{sim => }/frv/tp.cgs | 0
sim/testsuite/{sim => }/frv/tra.cgs | 0
sim/testsuite/{sim => }/frv/tv.cgs | 0
sim/testsuite/{sim => }/frv/udiv.cgs | 0
sim/testsuite/{sim => }/frv/udivi.cgs | 0
sim/testsuite/{sim => }/frv/umul.cgs | 0
sim/testsuite/{sim => }/frv/umulcc.cgs | 0
sim/testsuite/{sim => }/frv/umuli.cgs | 0
sim/testsuite/{sim => }/frv/umulicc.cgs | 0
sim/testsuite/{sim => }/frv/xor.cgs | 0
sim/testsuite/{sim => }/frv/xorcc.cgs | 0
sim/testsuite/{sim => }/frv/xorcr.cgs | 0
sim/testsuite/{sim => }/frv/xori.cgs | 0
sim/testsuite/{sim => }/frv/xoricc.cgs | 0
sim/testsuite/{sim => }/ft32/ChangeLog | 0
sim/testsuite/{sim => }/ft32/allinsn.exp | 0
sim/testsuite/{sim => }/ft32/basic.s | 0
sim/testsuite/{sim => }/ft32/testutils.inc | 0
sim/testsuite/h8300/ChangeLog | 107 +
sim/testsuite/{sim => }/h8300/addb.s | 0
sim/testsuite/{sim => }/h8300/addl.s | 0
sim/testsuite/{sim => }/h8300/adds.s | 0
sim/testsuite/{sim => }/h8300/addw.s | 0
sim/testsuite/{sim => }/h8300/addx.s | 0
sim/testsuite/h8300/allinsn.exp | 15 +
sim/testsuite/{sim => }/h8300/andb.s | 0
sim/testsuite/{sim => }/h8300/andl.s | 0
sim/testsuite/{sim => }/h8300/andw.s | 0
sim/testsuite/{sim => }/h8300/band.s | 0
sim/testsuite/{sim => }/h8300/bfld.s | 0
sim/testsuite/{sim => }/h8300/biand.s | 0
sim/testsuite/{sim => }/h8300/bra.s | 0
sim/testsuite/{sim => }/h8300/brabc.s | 0
sim/testsuite/{sim => }/h8300/bset.s | 0
sim/testsuite/{sim => }/h8300/cmpb.s | 0
sim/testsuite/{sim => }/h8300/cmpl.s | 0
sim/testsuite/{sim => }/h8300/cmpw.s | 0
sim/testsuite/{sim => }/h8300/daa.s | 0
sim/testsuite/{sim => }/h8300/das.s | 0
sim/testsuite/{sim => }/h8300/dec.s | 0
sim/testsuite/{sim => }/h8300/div.s | 0
sim/testsuite/{sim => }/h8300/extl.s | 0
sim/testsuite/{sim => }/h8300/extw.s | 0
sim/testsuite/{sim => }/h8300/inc.s | 0
sim/testsuite/{sim => }/h8300/jmp.s | 0
sim/testsuite/{sim => }/h8300/ldc.s | 0
sim/testsuite/{sim => }/h8300/ldm.s | 0
sim/testsuite/{sim => }/h8300/mac.s | 0
sim/testsuite/{sim => }/h8300/mova.s | 0
sim/testsuite/{sim => }/h8300/movb.s | 0
sim/testsuite/{sim => }/h8300/movl.s | 0
sim/testsuite/{sim => }/h8300/movmd.s | 0
sim/testsuite/{sim => }/h8300/movsd.s | 0
sim/testsuite/{sim => }/h8300/movw.s | 0
sim/testsuite/{sim => }/h8300/mul.s | 0
sim/testsuite/{sim => }/h8300/neg.s | 0
sim/testsuite/{sim => }/h8300/nop.s | 0
sim/testsuite/{sim => }/h8300/not.s | 0
sim/testsuite/{sim => }/h8300/orb.s | 0
sim/testsuite/{sim => }/h8300/orl.s | 0
sim/testsuite/{sim => }/h8300/orw.s | 0
sim/testsuite/h8300/rotl.s | 1212 ++
sim/testsuite/h8300/rotr.s | 1802 +++
sim/testsuite/h8300/rotxl.s | 167 +
sim/testsuite/h8300/rotxr.s | 2002 +++
sim/testsuite/h8300/shal.s | 167 +
sim/testsuite/h8300/shar.s | 2000 +++
sim/testsuite/h8300/shll.s | 375 +
sim/testsuite/h8300/shlr.s | 4085 +++++
sim/testsuite/{sim => }/h8300/stack.s | 0
sim/testsuite/{sim => }/h8300/stc.s | 0
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sim/testsuite/{sim => }/h8300/subs.s | 0
sim/testsuite/{sim => }/h8300/subw.s | 0
sim/testsuite/{sim => }/h8300/subx.s | 0
sim/testsuite/h8300/tas.s | 80 +
sim/testsuite/{sim => }/h8300/testutils.inc | 0
sim/testsuite/{sim => }/h8300/xorb.s | 0
sim/testsuite/{sim => }/h8300/xorl.s | 0
sim/testsuite/{sim => }/h8300/xorw.s | 0
sim/testsuite/{sim => }/iq2000/ChangeLog | 0
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sim/testsuite/{sim => }/iq2000/pass.s | 0
sim/testsuite/{sim => }/iq2000/testutils.inc | 0
sim/testsuite/lib/sim-defs.exp | 23 +-
sim/testsuite/{sim => }/lm32/ChangeLog | 0
sim/testsuite/{sim => }/lm32/allinsn.exp | 0
sim/testsuite/{sim => }/lm32/pass.s | 0
sim/testsuite/{sim => }/lm32/testutils.inc | 0
sim/testsuite/{sim => }/m32c/ChangeLog | 0
sim/testsuite/{sim => }/m32c/allinsn.exp | 0
sim/testsuite/{sim => }/m32c/blinky.s | 0
sim/testsuite/{sim => }/m32c/fail.s | 0
sim/testsuite/{sim => }/m32c/gloss.s | 0
sim/testsuite/{sim => }/m32c/pass.s | 0
sim/testsuite/{sim => }/m32c/sample.ld | 0
sim/testsuite/{sim => }/m32c/sample.s | 0
sim/testsuite/{sim => }/m32c/sample2.c | 0
sim/testsuite/{sim => }/m32c/testutils.inc | 0
sim/testsuite/m32r-elf/ChangeLog | 18 -
sim/testsuite/m32r-elf/Makefile.in | 156 -
sim/testsuite/m32r-elf/configure | 2984 ----
sim/testsuite/m32r-elf/configure.ac | 18 -
sim/testsuite/m32r-elf/exit47.s | 7 -
sim/testsuite/m32r-elf/hello.s | 17 -
sim/testsuite/m32r-elf/loop.s | 2 -
sim/testsuite/m32r/ChangeLog | 126 +
sim/testsuite/{sim => }/m32r/add.cgs | 0
sim/testsuite/{sim => }/m32r/add3.cgs | 0
sim/testsuite/{sim => }/m32r/addi.cgs | 0
sim/testsuite/{sim => }/m32r/addv.cgs | 0
sim/testsuite/{sim => }/m32r/addv3.cgs | 0
sim/testsuite/{sim => }/m32r/addx.cgs | 0
sim/testsuite/{sim => }/m32r/allinsn.exp | 0
sim/testsuite/{sim => }/m32r/and.cgs | 0
sim/testsuite/{sim => }/m32r/and3.cgs | 0
sim/testsuite/{sim => }/m32r/bc24.cgs | 0
sim/testsuite/{sim => }/m32r/bc8.cgs | 0
sim/testsuite/{sim => }/m32r/beq.cgs | 0
sim/testsuite/{sim => }/m32r/beqz.cgs | 0
sim/testsuite/{sim => }/m32r/bgez.cgs | 0
sim/testsuite/{sim => }/m32r/bgtz.cgs | 0
sim/testsuite/{sim => }/m32r/bl24.cgs | 0
sim/testsuite/{sim => }/m32r/bl8.cgs | 0
sim/testsuite/{sim => }/m32r/blez.cgs | 0
sim/testsuite/{sim => }/m32r/bltz.cgs | 0
sim/testsuite/{sim => }/m32r/bnc24.cgs | 0
sim/testsuite/{sim => }/m32r/bnc8.cgs | 0
sim/testsuite/{sim => }/m32r/bne.cgs | 0
sim/testsuite/{sim => }/m32r/bnez.cgs | 0
sim/testsuite/{sim => }/m32r/bra24.cgs | 0
sim/testsuite/{sim => }/m32r/bra8.cgs | 0
sim/testsuite/{sim => }/m32r/cmp.cgs | 0
sim/testsuite/{sim => }/m32r/cmpi.cgs | 0
sim/testsuite/{sim => }/m32r/cmpu.cgs | 0
sim/testsuite/{sim => }/m32r/cmpui.cgs | 0
sim/testsuite/{sim => }/m32r/div.cgs | 0
sim/testsuite/{sim => }/m32r/divu.cgs | 0
sim/testsuite/m32r/exit47.ms | 11 +
sim/testsuite/{sim => }/m32r/hello.ms | 0
sim/testsuite/{sim => }/m32r/hw-trap.ms | 0
sim/testsuite/{sim => }/m32r/jl.cgs | 0
sim/testsuite/{sim => }/m32r/jmp.cgs | 0
sim/testsuite/{sim => }/m32r/ld-d.cgs | 0
sim/testsuite/{sim => }/m32r/ld-plus.cgs | 0
sim/testsuite/{sim => }/m32r/ld.cgs | 0
sim/testsuite/{sim => }/m32r/ld24.cgs | 0
sim/testsuite/{sim => }/m32r/ldb-d.cgs | 0
sim/testsuite/{sim => }/m32r/ldb.cgs | 0
sim/testsuite/{sim => }/m32r/ldh-d.cgs | 0
sim/testsuite/{sim => }/m32r/ldh.cgs | 0
sim/testsuite/{sim => }/m32r/ldi16.cgs | 0
sim/testsuite/{sim => }/m32r/ldi8.cgs | 0
sim/testsuite/{sim => }/m32r/ldub-d.cgs | 0
sim/testsuite/{sim => }/m32r/ldub.cgs | 0
sim/testsuite/{sim => }/m32r/lduh-d.cgs | 0
sim/testsuite/{sim => }/m32r/lduh.cgs | 0
sim/testsuite/{sim => }/m32r/lock.cgs | 0
sim/testsuite/{sim => }/m32r/machi.cgs | 0
sim/testsuite/{sim => }/m32r/maclo.cgs | 0
sim/testsuite/{sim => }/m32r/macwhi.cgs | 0
sim/testsuite/{sim => }/m32r/macwlo.cgs | 0
sim/testsuite/{sim => }/m32r/misc.exp | 0
sim/testsuite/{sim => }/m32r/mul.cgs | 0
sim/testsuite/{sim => }/m32r/mulhi.cgs | 0
sim/testsuite/{sim => }/m32r/mullo.cgs | 0
sim/testsuite/{sim => }/m32r/mulwhi.cgs | 0
sim/testsuite/{sim => }/m32r/mulwlo.cgs | 0
sim/testsuite/{sim => }/m32r/mv.cgs | 0
sim/testsuite/{sim => }/m32r/mvfachi.cgs | 0
sim/testsuite/{sim => }/m32r/mvfaclo.cgs | 0
sim/testsuite/{sim => }/m32r/mvfacmi.cgs | 0
sim/testsuite/{sim => }/m32r/mvfc.cgs | 0
sim/testsuite/{sim => }/m32r/mvtachi.cgs | 0
sim/testsuite/{sim => }/m32r/mvtaclo.cgs | 0
sim/testsuite/{sim => }/m32r/mvtc.cgs | 0
sim/testsuite/{sim => }/m32r/neg.cgs | 0
sim/testsuite/{sim => }/m32r/nop.cgs | 0
sim/testsuite/{sim => }/m32r/not.cgs | 0
sim/testsuite/{sim => }/m32r/or.cgs | 0
sim/testsuite/{sim => }/m32r/or3.cgs | 0
sim/testsuite/{sim => }/m32r/rac.cgs | 0
sim/testsuite/{sim => }/m32r/rach.cgs | 0
sim/testsuite/{sim => }/m32r/rem.cgs | 0
sim/testsuite/{sim => }/m32r/remu.cgs | 0
sim/testsuite/{sim => }/m32r/rte.cgs | 0
sim/testsuite/{sim => }/m32r/seth.cgs | 0
sim/testsuite/{sim => }/m32r/sll.cgs | 0
sim/testsuite/{sim => }/m32r/sll3.cgs | 0
sim/testsuite/{sim => }/m32r/slli.cgs | 0
sim/testsuite/{sim => }/m32r/sra.cgs | 0
sim/testsuite/{sim => }/m32r/sra3.cgs | 0
sim/testsuite/{sim => }/m32r/srai.cgs | 0
sim/testsuite/{sim => }/m32r/srl.cgs | 0
sim/testsuite/{sim => }/m32r/srl3.cgs | 0
sim/testsuite/{sim => }/m32r/srli.cgs | 0
sim/testsuite/{sim => }/m32r/st-d.cgs | 0
sim/testsuite/{sim => }/m32r/st-minus.cgs | 0
sim/testsuite/{sim => }/m32r/st-plus.cgs | 0
sim/testsuite/{sim => }/m32r/st.cgs | 0
sim/testsuite/{sim => }/m32r/stb-d.cgs | 0
sim/testsuite/{sim => }/m32r/stb.cgs | 0
sim/testsuite/{sim => }/m32r/sth-d.cgs | 0
sim/testsuite/{sim => }/m32r/sth.cgs | 0
sim/testsuite/{sim => }/m32r/sub.cgs | 0
sim/testsuite/{sim => }/m32r/subv.cgs | 0
sim/testsuite/{sim => }/m32r/subx.cgs | 0
sim/testsuite/{sim => }/m32r/testutils.inc | 0
sim/testsuite/{sim => }/m32r/trap.cgs | 0
sim/testsuite/{sim => }/m32r/unlock.cgs | 0
sim/testsuite/{sim => }/m32r/uread16.ms | 0
sim/testsuite/{sim => }/m32r/uread32.ms | 0
sim/testsuite/{sim => }/m32r/uwrite16.ms | 0
sim/testsuite/{sim => }/m32r/uwrite32.ms | 0
sim/testsuite/{sim => }/m32r/xor.cgs | 0
sim/testsuite/{sim => }/m32r/xor3.cgs | 0
sim/testsuite/{sim => }/m68hc11/ChangeLog | 0
sim/testsuite/{sim => }/m68hc11/allinsn.exp | 0
sim/testsuite/{sim => }/m68hc11/pass.s | 0
sim/testsuite/{sim => }/m68hc11/testutils.inc | 0
sim/testsuite/{sim => }/mcore/ChangeLog | 0
sim/testsuite/{sim => }/mcore/allinsn.exp | 0
sim/testsuite/{sim => }/mcore/fail.s | 0
sim/testsuite/{sim => }/mcore/pass.s | 0
sim/testsuite/{sim => }/mcore/testutils.inc | 0
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sim/testsuite/sim/sh64/compact/movl1.cgs | 31 -
sim/testsuite/sim/sh64/compact/movl10.cgs | 34 -
sim/testsuite/sim/sh64/compact/movl11.cgs | 32 -
sim/testsuite/sim/sh64/compact/movl2.cgs | 43 -
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sim/testsuite/sim/sh64/compact/movl4.cgs | 38 -
sim/testsuite/sim/sh64/compact/movl5.cgs | 37 -
sim/testsuite/sim/sh64/compact/movl6.cgs | 25 -
sim/testsuite/sim/sh64/compact/movl7.cgs | 37 -
sim/testsuite/sim/sh64/compact/movl8.cgs | 24 -
sim/testsuite/sim/sh64/compact/movl9.cgs | 24 -
sim/testsuite/sim/sh64/compact/movt.cgs | 28 -
sim/testsuite/sim/sh64/compact/movw1.cgs | 29 -
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sim/testsuite/sim/sh64/compact/movw11.cgs | 35 -
sim/testsuite/sim/sh64/compact/movw2.cgs | 36 -
sim/testsuite/sim/sh64/compact/movw3.cgs | 31 -
sim/testsuite/sim/sh64/compact/movw4.cgs | 31 -
sim/testsuite/sim/sh64/compact/movw5.cgs | 32 -
sim/testsuite/sim/sh64/compact/movw6.cgs | 30 -
sim/testsuite/sim/sh64/compact/movw7.cgs | 36 -
sim/testsuite/sim/sh64/compact/movw8.cgs | 31 -
sim/testsuite/sim/sh64/compact/movw9.cgs | 33 -
sim/testsuite/sim/sh64/compact/mull.cgs | 64 -
sim/testsuite/sim/sh64/compact/mulsw.cgs | 91 -
sim/testsuite/sim/sh64/compact/muluw.cgs | 96 -
sim/testsuite/sim/sh64/compact/neg.cgs | 55 -
sim/testsuite/sim/sh64/compact/negc.cgs | 66 -
sim/testsuite/sim/sh64/compact/nop.cgs | 13 -
sim/testsuite/sim/sh64/compact/not.cgs | 47 -
sim/testsuite/sim/sh64/compact/ocbi.cgs | 14 -
sim/testsuite/sim/sh64/compact/ocbp.cgs | 15 -
sim/testsuite/sim/sh64/compact/ocbwb.cgs | 15 -
sim/testsuite/sim/sh64/compact/or.cgs | 43 -
sim/testsuite/sim/sh64/compact/orb.cgs | 24 -
sim/testsuite/sim/sh64/compact/ori.cgs | 40 -
sim/testsuite/sim/sh64/compact/pref.cgs | 15 -
sim/testsuite/sim/sh64/compact/rotcl.cgs | 121 -
sim/testsuite/sim/sh64/compact/rotcr.cgs | 103 -
sim/testsuite/sim/sh64/compact/rotl.cgs | 62 -
sim/testsuite/sim/sh64/compact/rotr.cgs | 55 -
sim/testsuite/sim/sh64/compact/rts.cgs | 24 -
sim/testsuite/sim/sh64/compact/sets.cgs | 13 -
sim/testsuite/sim/sh64/compact/sett.cgs | 16 -
sim/testsuite/sim/sh64/compact/shad.cgs | 58 -
sim/testsuite/sim/sh64/compact/shal.cgs | 57 -
sim/testsuite/sim/sh64/compact/shar.cgs | 40 -
sim/testsuite/sim/sh64/compact/shld.cgs | 48 -
sim/testsuite/sim/sh64/compact/shll.cgs | 57 -
sim/testsuite/sim/sh64/compact/shll16.cgs | 44 -
sim/testsuite/sim/sh64/compact/shll2.cgs | 40 -
sim/testsuite/sim/sh64/compact/shll8.cgs | 38 -
sim/testsuite/sim/sh64/compact/shlr.cgs | 33 -
sim/testsuite/sim/sh64/compact/shlr16.cgs | 14 -
sim/testsuite/sim/sh64/compact/shlr2.cgs | 14 -
sim/testsuite/sim/sh64/compact/shlr8.cgs | 14 -
sim/testsuite/sim/sh64/compact/stc-gbr.cgs | 21 -
sim/testsuite/sim/sh64/compact/stcl-gbr.cgs | 27 -
sim/testsuite/sim/sh64/compact/sts-fpscr.cgs | 23 -
sim/testsuite/sim/sh64/compact/sts-fpul.cgs | 14 -
sim/testsuite/sim/sh64/compact/sts-mach.cgs | 22 -
sim/testsuite/sim/sh64/compact/sts-macl.cgs | 21 -
sim/testsuite/sim/sh64/compact/sts-pr.cgs | 22 -
sim/testsuite/sim/sh64/compact/stsl-fpscr.cgs | 28 -
sim/testsuite/sim/sh64/compact/stsl-fpul.cgs | 27 -
sim/testsuite/sim/sh64/compact/stsl-mach.cgs | 42 -
sim/testsuite/sim/sh64/compact/stsl-macl.cgs | 42 -
sim/testsuite/sim/sh64/compact/stsl-pr.cgs | 42 -
sim/testsuite/sim/sh64/compact/sub.cgs | 68 -
sim/testsuite/sim/sh64/compact/subc.cgs | 109 -
sim/testsuite/sim/sh64/compact/subv.cgs | 55 -
sim/testsuite/sim/sh64/compact/swapb.cgs | 44 -
sim/testsuite/sim/sh64/compact/swapw.cgs | 43 -
sim/testsuite/sim/sh64/compact/tasb.cgs | 26 -
sim/testsuite/sim/sh64/compact/testutils.inc | 49 -
sim/testsuite/sim/sh64/compact/trapa.cgs | 13 -
sim/testsuite/sim/sh64/compact/tst.cgs | 62 -
sim/testsuite/sim/sh64/compact/tstb.cgs | 30 -
sim/testsuite/sim/sh64/compact/tsti.cgs | 32 -
sim/testsuite/sim/sh64/compact/xor.cgs | 70 -
sim/testsuite/sim/sh64/compact/xorb.cgs | 24 -
sim/testsuite/sim/sh64/compact/xori.cgs | 50 -
sim/testsuite/sim/sh64/compact/xtrct.cgs | 46 -
sim/testsuite/sim/sh64/interwork.exp | 20 -
sim/testsuite/sim/sh64/media.exp | 19 -
sim/testsuite/sim/sh64/media/ChangeLog | 102 -
sim/testsuite/sim/sh64/media/add.cgs | 47 -
sim/testsuite/sim/sh64/media/addi.cgs | 37 -
sim/testsuite/sim/sh64/media/addil.cgs | 49 -
sim/testsuite/sim/sh64/media/addl.cgs | 61 -
sim/testsuite/sim/sh64/media/addzl.cgs | 39 -
sim/testsuite/sim/sh64/media/alloco.cgs | 10 -
sim/testsuite/sim/sh64/media/and.cgs | 68 -
sim/testsuite/sim/sh64/media/andc.cgs | 50 -
sim/testsuite/sim/sh64/media/andi.cgs | 46 -
sim/testsuite/sim/sh64/media/beq.cgs | 52 -
sim/testsuite/sim/sh64/media/beqi.cgs | 40 -
sim/testsuite/sim/sh64/media/bge.cgs | 40 -
sim/testsuite/sim/sh64/media/bgeu.cgs | 47 -
sim/testsuite/sim/sh64/media/bgt.cgs | 32 -
sim/testsuite/sim/sh64/media/bgtu.cgs | 36 -
sim/testsuite/sim/sh64/media/blink.cgs | 17 -
sim/testsuite/sim/sh64/media/bne.cgs | 23 -
sim/testsuite/sim/sh64/media/bnei.cgs | 23 -
sim/testsuite/sim/sh64/media/brk.cgs | 11 -
sim/testsuite/sim/sh64/media/byterev.cgs | 67 -
sim/testsuite/sim/sh64/media/cmpeq.cgs | 42 -
sim/testsuite/sim/sh64/media/cmpgt.cgs | 43 -
sim/testsuite/sim/sh64/media/cmpgtu.cgs | 43 -
sim/testsuite/sim/sh64/media/cmveq.cgs | 32 -
sim/testsuite/sim/sh64/media/cmvne.cgs | 32 -
sim/testsuite/sim/sh64/media/fabsd.cgs | 39 -
sim/testsuite/sim/sh64/media/fabss.cgs | 39 -
sim/testsuite/sim/sh64/media/faddd.cgs | 33 -
sim/testsuite/sim/sh64/media/fadds.cgs | 34 -
sim/testsuite/sim/sh64/media/fcmpeqd.cgs | 36 -
sim/testsuite/sim/sh64/media/fcmpeqs.cgs | 36 -
sim/testsuite/sim/sh64/media/fcmpged.cgs | 46 -
sim/testsuite/sim/sh64/media/fcmpges.cgs | 46 -
sim/testsuite/sim/sh64/media/fcmpgtd.cgs | 36 -
sim/testsuite/sim/sh64/media/fcmpgts.cgs | 36 -
sim/testsuite/sim/sh64/media/fcmpund.cgs | 26 -
sim/testsuite/sim/sh64/media/fcmpuns.cgs | 26 -
sim/testsuite/sim/sh64/media/fcnvds.cgs | 27 -
sim/testsuite/sim/sh64/media/fcnvsd.cgs | 27 -
sim/testsuite/sim/sh64/media/fdivd.cgs | 39 -
sim/testsuite/sim/sh64/media/fdivs.cgs | 39 -
sim/testsuite/sim/sh64/media/fgetscr.cgs | 14 -
sim/testsuite/sim/sh64/media/fiprs.cgs | 42 -
sim/testsuite/sim/sh64/media/fldd.cgs | 13 -
sim/testsuite/sim/sh64/media/fldp.cgs | 16 -
sim/testsuite/sim/sh64/media/flds.cgs | 13 -
sim/testsuite/sim/sh64/media/fldxd.cgs | 16 -
sim/testsuite/sim/sh64/media/fldxp.cgs | 22 -
sim/testsuite/sim/sh64/media/fldxs.cgs | 16 -
sim/testsuite/sim/sh64/media/floatld.cgs | 12 -
sim/testsuite/sim/sh64/media/floatls.cgs | 12 -
sim/testsuite/sim/sh64/media/floatqd.cgs | 12 -
sim/testsuite/sim/sh64/media/floatqs.cgs | 12 -
sim/testsuite/sim/sh64/media/fmacs.cgs | 39 -
sim/testsuite/sim/sh64/media/fmovd.cgs | 24 -
sim/testsuite/sim/sh64/media/fmovdq.cgs | 23 -
sim/testsuite/sim/sh64/media/fmovls.cgs | 26 -
sim/testsuite/sim/sh64/media/fmovqd.cgs | 22 -
sim/testsuite/sim/sh64/media/fmovs.cgs | 24 -
sim/testsuite/sim/sh64/media/fmovsl.cgs | 21 -
sim/testsuite/sim/sh64/media/fmuld.cgs | 30 -
sim/testsuite/sim/sh64/media/fmuls.cgs | 31 -
sim/testsuite/sim/sh64/media/fnegd.cgs | 35 -
sim/testsuite/sim/sh64/media/fnegs.cgs | 35 -
sim/testsuite/sim/sh64/media/fputscr.cgs | 14 -
sim/testsuite/sim/sh64/media/fsqrtd.cgs | 27 -
sim/testsuite/sim/sh64/media/fsqrts.cgs | 27 -
sim/testsuite/sim/sh64/media/fstd.cgs | 34 -
sim/testsuite/sim/sh64/media/fstp.cgs | 14 -
sim/testsuite/sim/sh64/media/fsts.cgs | 34 -
sim/testsuite/sim/sh64/media/fstxd.cgs | 31 -
sim/testsuite/sim/sh64/media/fstxp.cgs | 14 -
sim/testsuite/sim/sh64/media/fstxs.cgs | 30 -
sim/testsuite/sim/sh64/media/fsubd.cgs | 36 -
sim/testsuite/sim/sh64/media/fsubs.cgs | 36 -
sim/testsuite/sim/sh64/media/ftrcdl.cgs | 26 -
sim/testsuite/sim/sh64/media/ftrcdq.cgs | 24 -
sim/testsuite/sim/sh64/media/ftrcsl.cgs | 26 -
sim/testsuite/sim/sh64/media/ftrcsq.cgs | 25 -
sim/testsuite/sim/sh64/media/ftrvs.cgs | 67 -
sim/testsuite/sim/sh64/media/getcfg.cgs | 10 -
sim/testsuite/sim/sh64/media/getcon.cgs | 29 -
sim/testsuite/sim/sh64/media/gettr.cgs | 48 -
sim/testsuite/sim/sh64/media/icbi.cgs | 10 -
sim/testsuite/sim/sh64/media/ldb.cgs | 21 -
sim/testsuite/sim/sh64/media/ldhil.cgs | 14 -
sim/testsuite/sim/sh64/media/ldhiq.cgs | 14 -
sim/testsuite/sim/sh64/media/ldl.cgs | 21 -
sim/testsuite/sim/sh64/media/ldlol.cgs | 14 -
sim/testsuite/sim/sh64/media/ldloq.cgs | 14 -
sim/testsuite/sim/sh64/media/ldq.cgs | 21 -
sim/testsuite/sim/sh64/media/ldub.cgs | 22 -
sim/testsuite/sim/sh64/media/lduw.cgs | 22 -
sim/testsuite/sim/sh64/media/ldw.cgs | 21 -
sim/testsuite/sim/sh64/media/ldxb.cgs | 28 -
sim/testsuite/sim/sh64/media/ldxl.cgs | 28 -
sim/testsuite/sim/sh64/media/ldxq.cgs | 28 -
sim/testsuite/sim/sh64/media/ldxub.cgs | 28 -
sim/testsuite/sim/sh64/media/ldxuw.cgs | 29 -
sim/testsuite/sim/sh64/media/ldxw.cgs | 29 -
sim/testsuite/sim/sh64/media/mabsl.cgs | 39 -
sim/testsuite/sim/sh64/media/mabsw.cgs | 38 -
sim/testsuite/sim/sh64/media/maddl.cgs | 29 -
sim/testsuite/sim/sh64/media/maddsl.cgs | 14 -
sim/testsuite/sim/sh64/media/maddsub.cgs | 14 -
sim/testsuite/sim/sh64/media/maddsw.cgs | 14 -
sim/testsuite/sim/sh64/media/maddw.cgs | 29 -
sim/testsuite/sim/sh64/media/mcmpeqb.cgs | 14 -
sim/testsuite/sim/sh64/media/mcmpeql.cgs | 14 -
sim/testsuite/sim/sh64/media/mcmpeqw.cgs | 14 -
sim/testsuite/sim/sh64/media/mcmpgtl.cgs | 14 -
sim/testsuite/sim/sh64/media/mcmpgtub.cgs | 14 -
sim/testsuite/sim/sh64/media/mcmpgtw.cgs | 14 -
sim/testsuite/sim/sh64/media/mcmv.cgs | 14 -
sim/testsuite/sim/sh64/media/mcnvslw.cgs | 14 -
sim/testsuite/sim/sh64/media/mcnvswb.cgs | 14 -
sim/testsuite/sim/sh64/media/mcnvswub.cgs | 14 -
sim/testsuite/sim/sh64/media/mextr1.cgs | 67 -
sim/testsuite/sim/sh64/media/mextr2.cgs | 67 -
sim/testsuite/sim/sh64/media/mextr3.cgs | 67 -
sim/testsuite/sim/sh64/media/mextr4.cgs | 67 -
sim/testsuite/sim/sh64/media/mextr5.cgs | 67 -
sim/testsuite/sim/sh64/media/mextr6.cgs | 67 -
sim/testsuite/sim/sh64/media/mextr7.cgs | 67 -
sim/testsuite/sim/sh64/media/mmacfxwl.cgs | 14 -
sim/testsuite/sim/sh64/media/mmacnfx-wl.cgs | 14 -
sim/testsuite/sim/sh64/media/mmulfxl.cgs | 14 -
sim/testsuite/sim/sh64/media/mmulfxrpw.cgs | 14 -
sim/testsuite/sim/sh64/media/mmulfxw.cgs | 14 -
sim/testsuite/sim/sh64/media/mmulhiwl.cgs | 14 -
sim/testsuite/sim/sh64/media/mmull.cgs | 14 -
sim/testsuite/sim/sh64/media/mmullowl.cgs | 14 -
sim/testsuite/sim/sh64/media/mmulsumwq.cgs | 14 -
sim/testsuite/sim/sh64/media/mmulw.cgs | 14 -
sim/testsuite/sim/sh64/media/movi.cgs | 29 -
sim/testsuite/sim/sh64/media/mpermw.cgs | 51 -
sim/testsuite/sim/sh64/media/msadubq.cgs | 14 -
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sim/testsuite/sim/sh64/media/mshaldsw.cgs | 14 -
sim/testsuite/sim/sh64/media/mshardl.cgs | 14 -
sim/testsuite/sim/sh64/media/mshardsq.cgs | 14 -
sim/testsuite/sim/sh64/media/mshardw.cgs | 14 -
sim/testsuite/sim/sh64/media/mshfhib.cgs | 14 -
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sim/testsuite/sim/sh64/media/mshfhiw.cgs | 14 -
sim/testsuite/sim/sh64/media/mshflob.cgs | 14 -
sim/testsuite/sim/sh64/media/mshflol.cgs | 14 -
sim/testsuite/sim/sh64/media/mshflow.cgs | 14 -
sim/testsuite/sim/sh64/media/mshlldl.cgs | 14 -
sim/testsuite/sim/sh64/media/mshlldw.cgs | 14 -
sim/testsuite/sim/sh64/media/mshlrdl.cgs | 14 -
sim/testsuite/sim/sh64/media/mshlrdw.cgs | 14 -
sim/testsuite/sim/sh64/media/msubl.cgs | 14 -
sim/testsuite/sim/sh64/media/msubsl.cgs | 14 -
sim/testsuite/sim/sh64/media/msubsub.cgs | 14 -
sim/testsuite/sim/sh64/media/msubsw.cgs | 14 -
sim/testsuite/sim/sh64/media/msubw.cgs | 14 -
sim/testsuite/sim/sh64/media/mulsl.cgs | 54 -
sim/testsuite/sim/sh64/media/mulul.cgs | 54 -
sim/testsuite/sim/sh64/media/nop.cgs | 10 -
sim/testsuite/sim/sh64/media/nsb.cgs | 66 -
sim/testsuite/sim/sh64/media/ocbi.cgs | 10 -
sim/testsuite/sim/sh64/media/ocbp.cgs | 10 -
sim/testsuite/sim/sh64/media/ocbwb.cgs | 10 -
sim/testsuite/sim/sh64/media/or.cgs | 44 -
sim/testsuite/sim/sh64/media/ori.cgs | 41 -
sim/testsuite/sim/sh64/media/prefi.cgs | 10 -
sim/testsuite/sim/sh64/media/pta.cgs | 26 -
sim/testsuite/sim/sh64/media/ptabs.cgs | 25 -
sim/testsuite/sim/sh64/media/ptb.cgs | 29 -
sim/testsuite/sim/sh64/media/ptrel.cgs | 22 -
sim/testsuite/sim/sh64/media/putcfg.cgs | 10 -
sim/testsuite/sim/sh64/media/putcon.cgs | 30 -
sim/testsuite/sim/sh64/media/rte.cgs | 11 -
sim/testsuite/sim/sh64/media/shard.cgs | 30 -
sim/testsuite/sim/sh64/media/shardl.cgs | 45 -
sim/testsuite/sim/sh64/media/shari.cgs | 28 -
sim/testsuite/sim/sh64/media/sharil.cgs | 45 -
sim/testsuite/sim/sh64/media/shlld.cgs | 36 -
sim/testsuite/sim/sh64/media/shlldl.cgs | 34 -
sim/testsuite/sim/sh64/media/shlli.cgs | 30 -
sim/testsuite/sim/sh64/media/shllil.cgs | 14 -
sim/testsuite/sim/sh64/media/shlrd.cgs | 30 -
sim/testsuite/sim/sh64/media/shlrdl.cgs | 37 -
sim/testsuite/sim/sh64/media/shlri.cgs | 28 -
sim/testsuite/sim/sh64/media/shlril.cgs | 14 -
sim/testsuite/sim/sh64/media/shori.cgs | 35 -
sim/testsuite/sim/sh64/media/sleep.cgs | 10 -
sim/testsuite/sim/sh64/media/stb.cgs | 26 -
sim/testsuite/sim/sh64/media/sthil.cgs | 55 -
sim/testsuite/sim/sh64/media/sthiq.cgs | 79 -
sim/testsuite/sim/sh64/media/stl.cgs | 26 -
sim/testsuite/sim/sh64/media/stlol.cgs | 14 -
sim/testsuite/sim/sh64/media/stloq.cgs | 14 -
sim/testsuite/sim/sh64/media/stq.cgs | 26 -
sim/testsuite/sim/sh64/media/stw.cgs | 26 -
sim/testsuite/sim/sh64/media/stxb.cgs | 29 -
sim/testsuite/sim/sh64/media/stxl.cgs | 29 -
sim/testsuite/sim/sh64/media/stxq.cgs | 29 -
sim/testsuite/sim/sh64/media/stxw.cgs | 29 -
sim/testsuite/sim/sh64/media/sub.cgs | 42 -
sim/testsuite/sim/sh64/media/subl.cgs | 38 -
sim/testsuite/sim/sh64/media/swapq.cgs | 36 -
sim/testsuite/sim/sh64/media/synci.cgs | 10 -
sim/testsuite/sim/sh64/media/synco.cgs | 10 -
sim/testsuite/sim/sh64/media/testutils.inc | 51 -
sim/testsuite/sim/sh64/media/trapa.cgs | 11 -
sim/testsuite/sim/sh64/media/xor.cgs | 54 -
sim/testsuite/sim/sh64/media/xori.cgs | 48 -
sim/testsuite/sim/sh64/misc/fr-dr.s | 22 -
sim/testsuite/{sim => }/v850/ChangeLog | 0
sim/testsuite/{sim => }/v850/allinsns.exp | 0
sim/testsuite/{sim => }/v850/bsh.cgs | 0
sim/testsuite/{sim => }/v850/div.cgs | 0
sim/testsuite/{sim => }/v850/divh.cgs | 0
sim/testsuite/{sim => }/v850/divh_3.cgs | 0
sim/testsuite/{sim => }/v850/divhu.cgs | 0
sim/testsuite/{sim => }/v850/divu.cgs | 0
sim/testsuite/{sim => }/v850/sar.cgs | 0
sim/testsuite/{sim => }/v850/satadd.cgs | 0
sim/testsuite/{sim => }/v850/satsub.cgs | 0
sim/testsuite/{sim => }/v850/satsubi.cgs | 0
sim/testsuite/{sim => }/v850/satsubr.cgs | 0
sim/testsuite/{sim => }/v850/shl.cgs | 0
sim/testsuite/{sim => }/v850/shr.cgs | 0
sim/testsuite/{sim => }/v850/testutils.cgs | 0
sim/testsuite/{sim => }/v850/testutils.inc | 0
sim/v850/ChangeLog | 38 +-
sim/v850/config.in | 6 -
sim/v850/configure | 340 +-
sim/v850/configure.ac | 1 -
sim/v850/interp.c | 10 -
sim/v850/simops.c | 14 +-
src-release.sh | 68 +-
zlib/ChangeLog.bin-gdb | 9 +
zlib/configure | 47 +-
4826 files changed, 84017 insertions(+), 165731 deletions(-)
copy binutils/testsuite/binutils-all/{readelf.s-64 => readelf.s-64-unused} (100%)
copy binutils/testsuite/binutils-all/{readelf.ss-64 => readelf.ss-64-unused} (100%)
copy binutils/testsuite/binutils-all/{readelf.ss => readelf.ss-unused} (100%)
create mode 100644 config/jobserver.m4
delete mode 100644 gas/testsuite/gas/aarch64/csre-invalid.d
delete mode 100644 gas/testsuite/gas/aarch64/csre-invalid.s
delete mode 100644 gas/testsuite/gas/aarch64/csre.d
delete mode 100644 gas/testsuite/gas/aarch64/csre_csr-invalid.d
delete mode 100644 gas/testsuite/gas/aarch64/csre_csr-invalid.l
delete mode 100644 gas/testsuite/gas/aarch64/csre_csr-invalid.s
delete mode 100644 gas/testsuite/gas/aarch64/csre_csr.d
delete mode 100644 gas/testsuite/gas/aarch64/csre_csr.s
delete mode 100644 gas/testsuite/gas/all/byte.d
delete mode 100644 gas/testsuite/gas/all/byte.l
delete mode 100644 gas/testsuite/gas/all/byte.s
create mode 100644 gas/testsuite/gas/elf/pr27228.d
create mode 100644 gas/testsuite/gas/elf/pr27228.s
copy gas/testsuite/gas/elf/{section2.e => section2.e-unused} (100%)
delete mode 100644 gas/testsuite/gas/elf/warn-2.s
create mode 100644 gas/testsuite/gas/i386/no-got.d
create mode 100644 gas/testsuite/gas/i386/no-got.s
create mode 100644 gas/testsuite/gas/i386/pr27198.d
create mode 100644 gas/testsuite/gas/i386/pr27198.err
create mode 100644 gas/testsuite/gas/i386/pr27198.s
create mode 100644 gas/testsuite/gas/i386/x86-64-no-got.d
create mode 100644 gas/testsuite/gas/i386/x86-64-no-got.s
create mode 100644 gas/testsuite/gas/nios2/relax.d
create mode 100644 gas/testsuite/gas/nios2/relax.s
create mode 100644 gas/testsuite/gas/ppc/rop-checks.d
create mode 100644 gas/testsuite/gas/ppc/rop-checks.l
create mode 100644 gas/testsuite/gas/ppc/rop-checks.s
create mode 100644 gas/testsuite/gas/ppc/rop.d
create mode 100644 gas/testsuite/gas/ppc/rop.s
create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-32.d
create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns-64.d
create mode 100644 gas/testsuite/gas/riscv/bitmanip-insns.s
create mode 100644 gas/testsuite/gas/riscv/pause.d
create mode 100644 gas/testsuite/gas/riscv/pause.s
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rename sim/testsuite/{sim => }/arm/umlal.cgs (100%)
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rename sim/testsuite/{sim => }/arm/xscale/blx.cgs (100%)
rename sim/testsuite/{sim => }/arm/xscale/mia.cgs (100%)
rename sim/testsuite/{sim => }/arm/xscale/miaph.cgs (100%)
rename sim/testsuite/{sim => }/arm/xscale/miaxy.cgs (100%)
rename sim/testsuite/{sim => }/arm/xscale/mra.cgs (100%)
rename sim/testsuite/{sim => }/arm/xscale/testutils.inc (100%)
rename sim/testsuite/{sim => }/arm/xscale/xscale.exp (100%)
rename sim/testsuite/{sim => }/avr/ChangeLog (100%)
rename sim/testsuite/{sim => }/avr/allinsn.exp (100%)
rename sim/testsuite/{sim => }/avr/pass.s (100%)
rename sim/testsuite/{sim => }/avr/testutils.inc (100%)
rename sim/testsuite/{sim => }/bfin/.gitignore (100%)
rename sim/testsuite/{sim => }/bfin/10272_small.s (100%)
rename sim/testsuite/{sim => }/bfin/10436.s (100%)
rename sim/testsuite/{sim => }/bfin/10622.s (100%)
rename sim/testsuite/{sim => }/bfin/10742.s (100%)
rename sim/testsuite/{sim => }/bfin/10799.s (100%)
rename sim/testsuite/{sim => }/bfin/11080.s (100%)
rename sim/testsuite/{sim => }/bfin/7641.s (100%)
create mode 100644 sim/testsuite/bfin/ChangeLog
rename sim/testsuite/{sim => }/bfin/PN_generator.s (100%)
rename sim/testsuite/{sim => }/bfin/a0.s (100%)
rename sim/testsuite/{sim => }/bfin/a0shift.S (100%)
rename sim/testsuite/{sim => }/bfin/a1.s (100%)
rename sim/testsuite/{sim => }/bfin/a10.s (100%)
rename sim/testsuite/{sim => }/bfin/a11.S (100%)
rename sim/testsuite/{sim => }/bfin/a12.s (100%)
rename sim/testsuite/{sim => }/bfin/a2.s (100%)
rename sim/testsuite/{sim => }/bfin/a20.S (100%)
rename sim/testsuite/{sim => }/bfin/a21.s (100%)
rename sim/testsuite/{sim => }/bfin/a22.s (100%)
rename sim/testsuite/{sim => }/bfin/a23.s (100%)
rename sim/testsuite/{sim => }/bfin/a24.s (100%)
rename sim/testsuite/{sim => }/bfin/a25.s (100%)
rename sim/testsuite/{sim => }/bfin/a26.s (100%)
rename sim/testsuite/{sim => }/bfin/a3.s (100%)
rename sim/testsuite/{sim => }/bfin/a30.s (100%)
rename sim/testsuite/{sim => }/bfin/a4.s (100%)
rename sim/testsuite/{sim => }/bfin/a5.s (100%)
rename sim/testsuite/{sim => }/bfin/a6.s (100%)
rename sim/testsuite/{sim => }/bfin/a7.s (100%)
rename sim/testsuite/{sim => }/bfin/a8.s (100%)
rename sim/testsuite/{sim => }/bfin/a9.s (100%)
rename sim/testsuite/{sim => }/bfin/abs-2.S (100%)
rename sim/testsuite/{sim => }/bfin/abs-3.S (100%)
rename sim/testsuite/{sim => }/bfin/abs-4.S (100%)
rename sim/testsuite/{sim => }/bfin/abs.S (100%)
rename sim/testsuite/{sim => }/bfin/abs_acc.s (100%)
rename sim/testsuite/{sim => }/bfin/acc-rot.s (100%)
rename sim/testsuite/{sim => }/bfin/acp5_19.s (100%)
rename sim/testsuite/{sim => }/bfin/acp5_4.s (100%)
rename sim/testsuite/{sim => }/bfin/add_imm7.s (100%)
rename sim/testsuite/{sim => }/bfin/add_shift.S (100%)
rename sim/testsuite/{sim => }/bfin/add_sub_acc.s (100%)
rename sim/testsuite/{sim => }/bfin/addsub_flags.S (100%)
rename sim/testsuite/{sim => }/bfin/algnbug1.s (100%)
rename sim/testsuite/{sim => }/bfin/algnbug2.s (100%)
rename sim/testsuite/{sim => }/bfin/allinsn.exp (100%)
rename sim/testsuite/{sim => }/bfin/argc.c (100%)
rename sim/testsuite/{sim => }/bfin/ashift.s (100%)
rename sim/testsuite/{sim => }/bfin/ashift_flags.s (100%)
rename sim/testsuite/{sim => }/bfin/ashift_left.s (100%)
rename sim/testsuite/{sim => }/bfin/b0.S (100%)
rename sim/testsuite/{sim => }/bfin/b1.s (100%)
rename sim/testsuite/{sim => }/bfin/b2.S (100%)
rename sim/testsuite/{sim => }/bfin/brcc.s (100%)
rename sim/testsuite/{sim => }/bfin/brevadd.s (100%)
rename sim/testsuite/{sim => }/bfin/byteop16m.s (100%)
rename sim/testsuite/{sim => }/bfin/byteop16p.s (100%)
rename sim/testsuite/{sim => }/bfin/byteop1p.s (100%)
rename sim/testsuite/{sim => }/bfin/byteop2p.s (100%)
rename sim/testsuite/{sim => }/bfin/byteop3p.s (100%)
rename sim/testsuite/{sim => }/bfin/byteunpack.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_arith_r_sft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_neg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_toggle.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_xb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_divq.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_divs.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_log_l_sft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_log_r_sft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_shadd_1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_shadd_2.s (100%)
rename sim/testsuite/{sim => }/bfin/c_br_preg_killed_ac.s (100%)
rename sim/testsuite/{sim => }/bfin/c_br_preg_killed_ex1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_br_preg_stall_ac.s (100%)
rename sim/testsuite/{sim => }/bfin/c_br_preg_stall_ex1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_bp1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_bp2.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_bp3.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_bp4.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brf_bp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_bp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_nbp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brf_fbkwd.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brf_nbp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brt_bp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brt_nbp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_kills_dhits.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_kills_dmiss.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr_pp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_calla_ljump.s (100%)
rename sim/testsuite/{sim => }/bfin/c_calla_subr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_ac.S (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_an.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_aq.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av0.S (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av1.S (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_az.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_flag_ccmv_depend.S (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft_s1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft_sn.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_s1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_sn.S (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_a0a1.S (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr_uu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3_uu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3_uu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr_uu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_pr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_pr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_and_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_minus_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_or_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_plus_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_xor_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_pr_plus_pr_sh1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_pr_plus_pr_sh2.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_add_i7_n.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_add_i7_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_eq_i7_n.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_eq_i7_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags.S (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags_2.S (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_n.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_n.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imgebl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imltbl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dagmodik_lz_inc_dec.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imgebl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imltbl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dagmodim_lz_inc_dec.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0_pm_a1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0a1s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_abs_a.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_neg_a.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_absabs.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_negneg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_abs.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_absabs.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_alhwx.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_awx.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop1ew.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop2.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop3.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_bytepack.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteunpack.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_disalnexcpt.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_max.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_maxmax.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_min.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_minmin.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_r_lh_a0pa1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_r_negneg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd12_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd12_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd20_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd20_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd12_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd12_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd20_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd20_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rlh_rnd.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rr_lph_a1a0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm_aa.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft_x.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft_x.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_saa.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sat_aa.S (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_search.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sgn.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_iuw32.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_ih.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_iu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_t.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_tu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_ih.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_iu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_t.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_tu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_iutsh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_ih.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_iu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_iutsh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_t.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_t.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_tu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_a0alr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align16.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align24.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_l.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_r.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expexp_r.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_ln.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_lp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rn.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_pack.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_r.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmax.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmaxvmax.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_a0alr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ippm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_ipp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_ipp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ippm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_ipp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_ipp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_except_illopcode.S (100%)
rename sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S (100%)
rename sim/testsuite/{sim => }/bfin/c_except_user_mode.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_disable.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_disable_enable.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_excpt.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_loopsetup_stld.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_nested.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_nmi.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_pending.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_pending_2.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_timer.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_timer_reload.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_timer_tcount.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_timer_tscale.S (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drlo.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_ibml.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_ibml.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_ibml.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_ibml.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_pibml.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_ppmm_hbx.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_mm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_pp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_mm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_pp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dr_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_st_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_hi.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_lo.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_h_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_lohi.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_hi.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_lo.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_lohi.s (100%)
rename sim/testsuite/{sim => }/bfin/c_linkage.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_alshft_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_arith_shft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_bitclr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_bitset.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_bittgl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_bittst.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft_astat.S (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft_astat.S (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_nbittst.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_bot.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_prelc.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_top.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_overlap.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_stld.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_prelc.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_topbotcntr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_mmr_interr_ctl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_mmr_loop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mmr_loop_user_except.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mmr_ppop_illegal_adr.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mmr_ppopm_illegal_adr.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mmr_timer.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mode_supervisor.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mode_user.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mode_user_superivsor.S (100%)
rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ld_ld.s (100%)
rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_2.s (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pcpr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_clisti_interr.S (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_csync_mmr.S (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_except_rtx.S (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_excpt.S (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pcpr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_nop.s (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_raise_rt_i_n.S (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_rts.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_neg_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_sft_2_1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_shadd_1_2.s (100%)
rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp_pair.s (100%)
rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_acc_acc.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_dag_lz_dep.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_dr_acc_acc.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dep_nostall.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_dr_imlb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_dr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dep_nostall.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dep_stall.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_imlb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dep_nostall.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dep_stall.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dr.s (100%)
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rename sim/testsuite/{sim => }/bfin/vec-abs-3.S (100%)
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rename sim/testsuite/{sim => }/bfin/vec-neg-2.S (100%)
rename sim/testsuite/{sim => }/bfin/vec-neg-3.S (100%)
rename sim/testsuite/{sim => }/bfin/vec-neg.S (100%)
rename sim/testsuite/{sim => }/bfin/vecadd.s (100%)
rename sim/testsuite/{sim => }/bfin/vit_max.s (100%)
rename sim/testsuite/{sim => }/bfin/vit_max2.s (100%)
rename sim/testsuite/{sim => }/bfin/viterbi2.s (100%)
rename sim/testsuite/{sim => }/bfin/wtf.s (100%)
rename sim/testsuite/{sim => }/bfin/x1.s (100%)
rename sim/testsuite/{sim => }/bfin/zcall.s (100%)
rename sim/testsuite/{sim => }/bfin/zeroflagrnd.s (100%)
create mode 100644 sim/testsuite/bpf/ChangeLog
rename sim/testsuite/{sim => }/bpf/allinsn.exp (100%)
rename sim/testsuite/{sim => }/bpf/alu.s (100%)
rename sim/testsuite/{sim => }/bpf/alu32.s (100%)
rename sim/testsuite/{sim => }/bpf/endbe.s (100%)
rename sim/testsuite/{sim => }/bpf/endle.s (100%)
rename sim/testsuite/{sim => }/bpf/jmp.s (100%)
rename sim/testsuite/{sim => }/bpf/jmp32.s (100%)
rename sim/testsuite/{sim => }/bpf/ldabs.s (100%)
rename sim/testsuite/{sim => }/bpf/mem.s (100%)
rename sim/testsuite/{sim => }/bpf/mov.s (100%)
rename sim/testsuite/{sim => }/bpf/testutils.inc (100%)
rename sim/testsuite/{sim => }/bpf/xadd.s (100%)
delete mode 100644 sim/testsuite/common/Make-common.in
delete mode 100755 sim/testsuite/configure
delete mode 100644 sim/testsuite/configure.ac
rename sim/testsuite/{sim => }/cr16/ChangeLog (100%)
rename sim/testsuite/{sim => }/cr16/addb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/addd.cgs (100%)
rename sim/testsuite/{sim => }/cr16/addi.cgs (100%)
rename sim/testsuite/{sim => }/cr16/addw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/allinsn.exp (100%)
rename sim/testsuite/{sim => }/cr16/andb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/andd.cgs (100%)
rename sim/testsuite/{sim => }/cr16/andw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/ashub.cgs (100%)
rename sim/testsuite/{sim => }/cr16/ashub_i.cgs (100%)
rename sim/testsuite/{sim => }/cr16/ashud.cgs (100%)
rename sim/testsuite/{sim => }/cr16/ashud_i.cgs (100%)
rename sim/testsuite/{sim => }/cr16/ashuw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/ashuw_i.cgs (100%)
rename sim/testsuite/{sim => }/cr16/bal1_24.cgs (100%)
rename sim/testsuite/{sim => }/cr16/bal2_24.cgs (100%)
rename sim/testsuite/{sim => }/cr16/bcc.cgs (100%)
rename sim/testsuite/{sim => }/cr16/bcs.cgs (100%)
rename sim/testsuite/{sim => }/cr16/beq.cgs (100%)
rename sim/testsuite/{sim => }/cr16/beq0b.cgs (100%)
rename sim/testsuite/{sim => }/cr16/beq0w.cgs (100%)
rename sim/testsuite/{sim => }/cr16/bge.cgs (100%)
rename sim/testsuite/{sim => }/cr16/bgt.cgs (100%)
rename sim/testsuite/{sim => }/cr16/bhi.cgs (100%)
rename sim/testsuite/{sim => }/cr16/bhs.cgs (100%)
rename sim/testsuite/{sim => }/cr16/bht.cgs (100%)
rename sim/testsuite/{sim => }/cr16/blo.cgs (100%)
rename sim/testsuite/{sim => }/cr16/bls.cgs (100%)
rename sim/testsuite/{sim => }/cr16/blt.cgs (100%)
rename sim/testsuite/{sim => }/cr16/bne.cgs (100%)
rename sim/testsuite/{sim => }/cr16/bne0b.cgs (100%)
rename sim/testsuite/{sim => }/cr16/bne0w.cgs (100%)
rename sim/testsuite/{sim => }/cr16/br.cgs (100%)
rename sim/testsuite/{sim => }/cr16/cbitb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/cbitw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/cmpb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/cmpb_i.cgs (100%)
rename sim/testsuite/{sim => }/cr16/cmpd.cgs (100%)
rename sim/testsuite/{sim => }/cr16/cmpd_i.cgs (100%)
rename sim/testsuite/{sim => }/cr16/cmpi.cgs (100%)
rename sim/testsuite/{sim => }/cr16/cmpw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/cmpw_i.cgs (100%)
rename sim/testsuite/{sim => }/cr16/excp.cgs (100%)
rename sim/testsuite/{sim => }/cr16/hello.ms (100%)
rename sim/testsuite/{sim => }/cr16/hw-trap.ms (100%)
rename sim/testsuite/{sim => }/cr16/jal.cgs (100%)
rename sim/testsuite/{sim => }/cr16/jcc.cgs (100%)
rename sim/testsuite/{sim => }/cr16/jcs.cgs (100%)
rename sim/testsuite/{sim => }/cr16/jeq.cgs (100%)
rename sim/testsuite/{sim => }/cr16/jfc.cgs (100%)
rename sim/testsuite/{sim => }/cr16/jfs.cgs (100%)
rename sim/testsuite/{sim => }/cr16/jge.cgs (100%)
rename sim/testsuite/{sim => }/cr16/jgt.cgs (100%)
rename sim/testsuite/{sim => }/cr16/jhi.cgs (100%)
rename sim/testsuite/{sim => }/cr16/jhs.cgs (100%)
rename sim/testsuite/{sim => }/cr16/jlo.cgs (100%)
rename sim/testsuite/{sim => }/cr16/jls.cgs (100%)
rename sim/testsuite/{sim => }/cr16/jlt.cgs (100%)
rename sim/testsuite/{sim => }/cr16/jne.cgs (100%)
rename sim/testsuite/{sim => }/cr16/jump.cgs (100%)
rename sim/testsuite/{sim => }/cr16/loadb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/loadd.cgs (100%)
rename sim/testsuite/{sim => }/cr16/loadm.cgs (100%)
rename sim/testsuite/{sim => }/cr16/loadmp.cgs (100%)
rename sim/testsuite/{sim => }/cr16/loadw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/lpr-spr.cgs (100%)
rename sim/testsuite/{sim => }/cr16/lprd-sprd.cgs (100%)
rename sim/testsuite/{sim => }/cr16/lshb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/lshb_i.cgs (100%)
rename sim/testsuite/{sim => }/cr16/lshd.cgs (100%)
rename sim/testsuite/{sim => }/cr16/lshd_i.cgs (100%)
rename sim/testsuite/{sim => }/cr16/lshw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/lshw_i.cgs (100%)
rename sim/testsuite/{sim => }/cr16/macqw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/macsw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/macuw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/misc.exp (100%)
rename sim/testsuite/{sim => }/cr16/movb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/movd.cgs (100%)
rename sim/testsuite/{sim => }/cr16/movw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/movxb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/movxw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/movzb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/movzw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/mulb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/mulsb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/mulsw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/muluw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/mulw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/nop.cgs (100%)
rename sim/testsuite/{sim => }/cr16/orb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/ord.cgs (100%)
rename sim/testsuite/{sim => }/cr16/orw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/pop1.cgs (100%)
rename sim/testsuite/{sim => }/cr16/pop2.cgs (100%)
rename sim/testsuite/{sim => }/cr16/pop3.cgs (100%)
rename sim/testsuite/{sim => }/cr16/popret1.cgs (100%)
rename sim/testsuite/{sim => }/cr16/popret2.cgs (100%)
rename sim/testsuite/{sim => }/cr16/popret3.cgs (100%)
rename sim/testsuite/{sim => }/cr16/push1.cgs (100%)
rename sim/testsuite/{sim => }/cr16/push2.cgs (100%)
rename sim/testsuite/{sim => }/cr16/push3.cgs (100%)
rename sim/testsuite/{sim => }/cr16/sbitb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/sbitw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/scc.cgs (100%)
rename sim/testsuite/{sim => }/cr16/scs.cgs (100%)
rename sim/testsuite/{sim => }/cr16/seq.cgs (100%)
rename sim/testsuite/{sim => }/cr16/sfc.cgs (100%)
rename sim/testsuite/{sim => }/cr16/sfs.cgs (100%)
rename sim/testsuite/{sim => }/cr16/sge.cgs (100%)
rename sim/testsuite/{sim => }/cr16/sgt.cgs (100%)
rename sim/testsuite/{sim => }/cr16/shi.cgs (100%)
rename sim/testsuite/{sim => }/cr16/shs.cgs (100%)
rename sim/testsuite/{sim => }/cr16/slo.cgs (100%)
rename sim/testsuite/{sim => }/cr16/sls.cgs (100%)
rename sim/testsuite/{sim => }/cr16/slt.cgs (100%)
rename sim/testsuite/{sim => }/cr16/sne.cgs (100%)
rename sim/testsuite/{sim => }/cr16/storb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/stord.cgs (100%)
rename sim/testsuite/{sim => }/cr16/storw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/subb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/subd.cgs (100%)
rename sim/testsuite/{sim => }/cr16/subi.cgs (100%)
rename sim/testsuite/{sim => }/cr16/subw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/tbit.cgs (100%)
rename sim/testsuite/{sim => }/cr16/tbitb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/tbitw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/testutils.inc (100%)
rename sim/testsuite/{sim => }/cr16/uread16.ms (100%)
rename sim/testsuite/{sim => }/cr16/uread32.ms (100%)
rename sim/testsuite/{sim => }/cr16/xorb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/xord.cgs (100%)
rename sim/testsuite/{sim => }/cr16/xorw.cgs (100%)
create mode 100644 sim/testsuite/cris/ChangeLog
rename sim/testsuite/{sim => }/cris/asm/abs.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addcpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addcv32c.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addcv32m.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addcv32r.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addi.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addiv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addoc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addom.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addoq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addqpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addswpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addxc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addxm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addxr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/andc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/andm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/andq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/andr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/asm.exp (100%)
rename sim/testsuite/{sim => }/cris/asm/asr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/ba.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/badarch1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bare1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bare2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bare3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bas.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bccb.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bdapc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bdapm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bdapq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bdapqpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/biap.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/boundc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/boundm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/boundmv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/boundr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/break.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/btst.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/ccr-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/ccs-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/clearfv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/clearfv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/clrjmp1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/cmpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/cmpm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/cmpq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/cmpr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/cmpxc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/cmpxm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/dflags.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/dip.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/dstep.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/fidxd.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/fidxi.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/ftagd.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/ftagi.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/halt.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io4.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io5.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io6.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io7.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io8.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io9.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/jsr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/jsrmv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/jumpmp.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/jumppv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/lapc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/lsl.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/lsr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/lz.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/mcp.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movdelsr1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movecpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movecr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movecrt10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movecrt32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movect10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movei.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movempc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movemr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movemrv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movemrv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movepcb.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movepcd.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movepcw.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moveq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moveqpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/mover.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverbpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverdpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverpcb.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverpcd.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverpcw.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverwpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movesmp.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movmp.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movmp8.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movpmv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movpmv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movppc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movpr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movprv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movprv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movrss.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movscpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movscr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movsm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movsmpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movsr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movsrpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movssr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movucpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movucr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movum.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movumpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movur.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movurpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/mstep.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/msteppc1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/msteppc2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/msteppc3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/mulv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/mulv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/mulx.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/neg.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/nonvcv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/nopv10t.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/nopv32t.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/nopv32t2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/nopv32t3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/nopv32t4.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/not.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/op3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/opterr1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/opterr2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/opterr3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/opterr4.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/opterr5.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/option1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/option2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/option3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/option4.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/orc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/orm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/orq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/orr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/pcplus.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/pid1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw11.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw12.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw13.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw14.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw15.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw16.ms (100%)
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create mode 100644 sim/testsuite/cris/hw/rv-n-cris/rvc.exp
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rename sim/testsuite/{sim => }/cris/hw/rv-n-cris/trivial4.r (100%)
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create mode 100644 sim/testsuite/d10v/t-sp.s
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create mode 100644 sim/testsuite/d10v/t-sub2w.s
create mode 100644 sim/testsuite/d10v/t-subi.s
create mode 100644 sim/testsuite/d10v/t-trap.s
delete mode 100644 sim/testsuite/frv-elf/ChangeLog
delete mode 100644 sim/testsuite/frv-elf/Makefile.in
delete mode 100644 sim/testsuite/frv-elf/cache.s
delete mode 100755 sim/testsuite/frv-elf/configure
delete mode 100644 sim/testsuite/frv-elf/configure.ac
delete mode 100644 sim/testsuite/frv-elf/exit47.s
delete mode 100644 sim/testsuite/frv-elf/grloop.s
delete mode 100644 sim/testsuite/frv-elf/hello.s
delete mode 100644 sim/testsuite/frv-elf/loop.s
create mode 100644 sim/testsuite/frv/ChangeLog
rename sim/testsuite/{sim => }/frv/add.cgs (100%)
rename sim/testsuite/{sim => }/frv/add.pcgs (100%)
rename sim/testsuite/{sim => }/frv/addcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/addi.cgs (100%)
rename sim/testsuite/{sim => }/frv/addicc.cgs (100%)
rename sim/testsuite/{sim => }/frv/addx.cgs (100%)
rename sim/testsuite/{sim => }/frv/addxcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/addxi.cgs (100%)
rename sim/testsuite/{sim => }/frv/addxicc.cgs (100%)
rename sim/testsuite/{sim => }/frv/allinsn.exp (100%)
rename sim/testsuite/{sim => }/frv/and.cgs (100%)
rename sim/testsuite/{sim => }/frv/andcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/andcr.cgs (100%)
rename sim/testsuite/{sim => }/frv/andi.cgs (100%)
rename sim/testsuite/{sim => }/frv/andicc.cgs (100%)
rename sim/testsuite/{sim => }/frv/andncr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bar.cgs (100%)
rename sim/testsuite/{sim => }/frv/bc.cgs (100%)
rename sim/testsuite/{sim => }/frv/bcclr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bceqlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bcgelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bcgtlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bchilr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bclelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bclr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bclslr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bcltlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bcnclr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bcnelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bcnlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bcnolr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bcnvlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bcplr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bcralr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bctrlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bcvlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/beq.cgs (100%)
rename sim/testsuite/{sim => }/frv/beqlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bge.cgs (100%)
rename sim/testsuite/{sim => }/frv/bgelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bgt.cgs (100%)
rename sim/testsuite/{sim => }/frv/bgtlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/bhilr.cgs (100%)
rename sim/testsuite/{sim => }/frv/ble.cgs (100%)
rename sim/testsuite/{sim => }/frv/blelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bls.cgs (100%)
rename sim/testsuite/{sim => }/frv/blslr.cgs (100%)
rename sim/testsuite/{sim => }/frv/blt.cgs (100%)
rename sim/testsuite/{sim => }/frv/bltlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bn.cgs (100%)
rename sim/testsuite/{sim => }/frv/bnc.cgs (100%)
rename sim/testsuite/{sim => }/frv/bnclr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bne.cgs (100%)
rename sim/testsuite/{sim => }/frv/bnelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bnlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bno.cgs (100%)
rename sim/testsuite/{sim => }/frv/bnolr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bnv.cgs (100%)
rename sim/testsuite/{sim => }/frv/bnvlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bp.cgs (100%)
rename sim/testsuite/{sim => }/frv/bplr.cgs (100%)
rename sim/testsuite/{sim => }/frv/bra.cgs (100%)
rename sim/testsuite/{sim => }/frv/bralr.cgs (100%)
rename sim/testsuite/{sim => }/frv/branch.pcgs (100%)
rename sim/testsuite/{sim => }/frv/break.cgs (100%)
rename sim/testsuite/{sim => }/frv/bv.cgs (100%)
rename sim/testsuite/{sim => }/frv/bvlr.cgs (100%)
create mode 100644 sim/testsuite/frv/cache.ms
rename sim/testsuite/{sim => }/frv/cadd.cgs (100%)
rename sim/testsuite/{sim => }/frv/caddcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/call.cgs (100%)
rename sim/testsuite/{sim => }/frv/call.pcgs (100%)
rename sim/testsuite/{sim => }/frv/callil.cgs (100%)
rename sim/testsuite/{sim => }/frv/calll.cgs (100%)
rename sim/testsuite/{sim => }/frv/cand.cgs (100%)
rename sim/testsuite/{sim => }/frv/candcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/ccalll.cgs (100%)
rename sim/testsuite/{sim => }/frv/cckc.cgs (100%)
rename sim/testsuite/{sim => }/frv/cckeq.cgs (100%)
rename sim/testsuite/{sim => }/frv/cckge.cgs (100%)
rename sim/testsuite/{sim => }/frv/cckgt.cgs (100%)
rename sim/testsuite/{sim => }/frv/cckhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/cckle.cgs (100%)
rename sim/testsuite/{sim => }/frv/cckls.cgs (100%)
rename sim/testsuite/{sim => }/frv/ccklt.cgs (100%)
rename sim/testsuite/{sim => }/frv/cckn.cgs (100%)
rename sim/testsuite/{sim => }/frv/ccknc.cgs (100%)
rename sim/testsuite/{sim => }/frv/cckne.cgs (100%)
rename sim/testsuite/{sim => }/frv/cckno.cgs (100%)
rename sim/testsuite/{sim => }/frv/ccknv.cgs (100%)
rename sim/testsuite/{sim => }/frv/cckp.cgs (100%)
rename sim/testsuite/{sim => }/frv/cckra.cgs (100%)
rename sim/testsuite/{sim => }/frv/cckv.cgs (100%)
rename sim/testsuite/{sim => }/frv/ccmp.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfabss.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfckeq.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfckge.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfckgt.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfckle.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfcklg.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfcklt.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfckne.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfckno.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfcko.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfckra.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfcku.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfckue.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfckug.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfckuge.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfckul.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfckule.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfcmps.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfdivs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfitos.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfmadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfmas.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfmovs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfmss.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfmsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfmuls.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfnegs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfsqrts.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfstoi.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cjmpl.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckc.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckeq.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckge.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckgt.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckle.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckls.cgs (100%)
rename sim/testsuite/{sim => }/frv/cklt.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckn.cgs (100%)
rename sim/testsuite/{sim => }/frv/cknc.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckne.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckno.cgs (100%)
rename sim/testsuite/{sim => }/frv/cknv.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckp.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckra.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckv.cgs (100%)
rename sim/testsuite/{sim => }/frv/cld.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldbf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldbfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldd.cgs (100%)
rename sim/testsuite/{sim => }/frv/clddf.cgs (100%)
rename sim/testsuite/{sim => }/frv/clddfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/clddu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldhf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldhfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldq.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldqu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldsb.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldsbu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldsh.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldshu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldub.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldubu.cgs (100%)
rename sim/testsuite/{sim => }/frv/clduh.cgs (100%)
rename sim/testsuite/{sim => }/frv/clduhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/clrfa.cgs (100%)
rename sim/testsuite/{sim => }/frv/clrfr.cgs (100%)
rename sim/testsuite/{sim => }/frv/clrga.cgs (100%)
rename sim/testsuite/{sim => }/frv/clrgr.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmaddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmaddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmand.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmbtoh.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmbtohe.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmcpxis.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmcpxiu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmcpxrs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmcpxru.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmexpdhd.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmexpdhw.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmhtob.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmmulhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmmulhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmnot.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmor.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmov.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmovfg.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmovfgd.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmovgf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmovgfd.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmp.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmpb.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmpba.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmpi.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmqmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmqmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmqmulhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmqmulhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmsubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmsubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmxor.cgs (100%)
rename sim/testsuite/{sim => }/frv/cnot.cgs (100%)
rename sim/testsuite/{sim => }/frv/commitfa.cgs (100%)
rename sim/testsuite/{sim => }/frv/commitfr.cgs (100%)
rename sim/testsuite/{sim => }/frv/commitga.cgs (100%)
rename sim/testsuite/{sim => }/frv/commitgr.cgs (100%)
rename sim/testsuite/{sim => }/frv/cop1.cgs (100%)
rename sim/testsuite/{sim => }/frv/cop2.cgs (100%)
rename sim/testsuite/{sim => }/frv/cor.cgs (100%)
rename sim/testsuite/{sim => }/frv/corcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/cscan.cgs (100%)
rename sim/testsuite/{sim => }/frv/csdiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/csll.cgs (100%)
rename sim/testsuite/{sim => }/frv/csllcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/csmul.cgs (100%)
rename sim/testsuite/{sim => }/frv/csmulcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/csra.cgs (100%)
rename sim/testsuite/{sim => }/frv/csracc.cgs (100%)
rename sim/testsuite/{sim => }/frv/csrl.cgs (100%)
rename sim/testsuite/{sim => }/frv/csrlcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/cst.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstb.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstbf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstbfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstbu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstd.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstdf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstdfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstdu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/csth.cgs (100%)
rename sim/testsuite/{sim => }/frv/csthf.cgs (100%)
rename sim/testsuite/{sim => }/frv/csthfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/csthu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstq.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstu.cgs (100%)
rename sim/testsuite/{sim => }/frv/csub.cgs (100%)
rename sim/testsuite/{sim => }/frv/csubcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/cswap.cgs (100%)
rename sim/testsuite/{sim => }/frv/cudiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/cxor.cgs (100%)
rename sim/testsuite/{sim => }/frv/cxorcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/dcef.cgs (100%)
rename sim/testsuite/{sim => }/frv/dcei.cgs (100%)
rename sim/testsuite/{sim => }/frv/dcf.cgs (100%)
rename sim/testsuite/{sim => }/frv/dci.cgs (100%)
create mode 100644 sim/testsuite/frv/exit47.ms
rename sim/testsuite/{sim => }/frv/fabsd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fabss.cgs (100%)
rename sim/testsuite/{sim => }/frv/faddd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbeq.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbeqlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbge.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbgelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbgt.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbgtlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fble.cgs (100%)
rename sim/testsuite/{sim => }/frv/fblelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fblg.cgs (100%)
rename sim/testsuite/{sim => }/frv/fblglr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fblt.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbltlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbne.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbnelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbno.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbnolr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbo.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbolr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbra.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbralr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbue.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbuelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbug.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbuge.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbugelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbuglr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbul.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbule.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbulelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbullr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbulr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbeqlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbgelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbgtlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcblelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcblglr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbltlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbnelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbnolr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbolr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbralr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbuelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbugelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbuglr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbulelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbullr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbulr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckeq.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckge.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckgt.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckle.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcklg.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcklt.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckne.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckno.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcko.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckra.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcku.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckue.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckug.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckuge.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckul.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckule.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcmpd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcmps.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdabss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdcmps.cgs (100%)
rename sim/testsuite/{sim => }/frv/fddivs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fditos.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdivd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdivs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdmadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdmas.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdmovs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdmss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdmulcs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdmuls.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdnegs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdsads.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdsqrts.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdstoi.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdtoi.cgs (100%)
rename sim/testsuite/{sim => }/frv/fitod.cgs (100%)
rename sim/testsuite/{sim => }/frv/fitos.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmad.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmaddd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmas.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmovd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmovs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmsd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmsubd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmuld.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmuls.cgs (100%)
rename sim/testsuite/{sim => }/frv/fnegd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fnegs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fnop.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/addss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/allinsn.exp (100%)
rename sim/testsuite/{sim => }/frv/fr400/csdiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/masaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/maveh.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mclracc.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/movgs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/movsg.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/scutss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/sdiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/sdivi.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/slass.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/smass.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/smsss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/smu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/subss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/udiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/udivi.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/allinsn.exp (100%)
rename sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/dcpl.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/dcul.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/mclracc.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/allinsn.exp (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmaddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmcpxiu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmcpxru.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmqaddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmqaddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmqmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmqmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmqsubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmqsubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmsubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/dcpl.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/dcul.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mabshs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/maddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/maddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/masaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/msubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/msubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mtrap.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/udiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/udivi.cgs (100%)
rename sim/testsuite/{sim => }/frv/fsqrtd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fsqrts.cgs (100%)
rename sim/testsuite/{sim => }/frv/fstoi.cgs (100%)
rename sim/testsuite/{sim => }/frv/fsubd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fteq.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftge.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftgt.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftieq.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftige.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftigt.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftile.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftilg.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftilt.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftine.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftino.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftio.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftira.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftiu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftiue.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftiug.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftiuge.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftiul.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftle.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftlg.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftlt.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftne.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftno.cgs (100%)
rename sim/testsuite/{sim => }/frv/fto.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftra.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftue.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftug.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftuge.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftul.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftule.cgs (100%)
create mode 100644 sim/testsuite/frv/grloop.ms
create mode 100644 sim/testsuite/frv/hello.ms
rename sim/testsuite/{sim => }/frv/icei.cgs (100%)
rename sim/testsuite/{sim => }/frv/ici.cgs (100%)
rename sim/testsuite/{sim => }/frv/icpl.cgs (100%)
rename sim/testsuite/{sim => }/frv/icul.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts.exp (100%)
rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr400.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr500.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/badalign-fr550.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/badalign.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/compound-fr550.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/compound.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/data_store_error-fr550.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/data_store_error.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/fp_exception-fr550.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/fp_exception.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error-fr550.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/mp_exception.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/privileged_instruction.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/regalign.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/reset.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/shadow_regs.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/timer.cgs (100%)
rename sim/testsuite/{sim => }/frv/jmpil.cgs (100%)
rename sim/testsuite/{sim => }/frv/jmpl.cgs (100%)
rename sim/testsuite/{sim => }/frv/jmpl.pcgs (100%)
rename sim/testsuite/{sim => }/frv/ld.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldbf.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldbfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldbfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldc.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldcu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldd.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddc.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddcu.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddf.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddi.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldf.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldhf.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldhfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldhfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldq.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqc.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqcu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqf.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldsb.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldsbi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldsbu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldsh.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldshi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldshu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldub.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldubi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldubu.cgs (100%)
rename sim/testsuite/{sim => }/frv/lduh.cgs (100%)
rename sim/testsuite/{sim => }/frv/lduhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/lduhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/lrbranch.pcgs (100%)
rename sim/testsuite/{sim => }/frv/mabshs.cgs (100%)
rename sim/testsuite/{sim => }/frv/maddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/maddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/mand.cgs (100%)
rename sim/testsuite/{sim => }/frv/maveh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mbtoh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mbtohe.cgs (100%)
rename sim/testsuite/{sim => }/frv/mclracc.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcmpsh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcmpuh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcop1.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcop2.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcplhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcpli.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcpxis.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcpxiu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcpxrs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcpxru.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcut.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcuti.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcutss.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcutssi.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdaddaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdasaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdcutssi.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdpackh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdrotli.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdsubaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdunpackh.cgs (100%)
rename sim/testsuite/{sim => }/frv/membar.cgs (100%)
rename sim/testsuite/{sim => }/frv/mexpdhd.cgs (100%)
rename sim/testsuite/{sim => }/frv/mexpdhw.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhdseth.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhdsets.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhsethih.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhsethis.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhsetloh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhsetlos.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhtob.cgs (100%)
create mode 100644 sim/testsuite/frv/misc.exp
rename sim/testsuite/{sim => }/frv/mmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmrdhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmrdhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmulhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmulhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmulxhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmulxhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mnop.cgs (100%)
rename sim/testsuite/{sim => }/frv/mnot.cgs (100%)
rename sim/testsuite/{sim => }/frv/mor.cgs (100%)
rename sim/testsuite/{sim => }/frv/mov.cgs (100%)
rename sim/testsuite/{sim => }/frv/movfg.cgs (100%)
rename sim/testsuite/{sim => }/frv/movfgd.cgs (100%)
rename sim/testsuite/{sim => }/frv/movfgq.cgs (100%)
rename sim/testsuite/{sim => }/frv/movgf.cgs (100%)
rename sim/testsuite/{sim => }/frv/movgfd.cgs (100%)
rename sim/testsuite/{sim => }/frv/movgfq.cgs (100%)
rename sim/testsuite/{sim => }/frv/movgs.cgs (100%)
rename sim/testsuite/{sim => }/frv/movsg.cgs (100%)
rename sim/testsuite/{sim => }/frv/mpackh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqcpxis.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqcpxiu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqcpxrs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqcpxru.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqlclrhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqlmths.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmacxhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmulhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmulhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmulxhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmulxhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqsaths.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqsllhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqsrahi.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqxmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqxmacxhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mrdacc.cgs (100%)
rename sim/testsuite/{sim => }/frv/mrdaccg.cgs (100%)
rename sim/testsuite/{sim => }/frv/mrotli.cgs (100%)
rename sim/testsuite/{sim => }/frv/mrotri.cgs (100%)
rename sim/testsuite/{sim => }/frv/msaths.cgs (100%)
rename sim/testsuite/{sim => }/frv/msathu.cgs (100%)
rename sim/testsuite/{sim => }/frv/msllhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/msrahi.cgs (100%)
rename sim/testsuite/{sim => }/frv/msrlhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/msubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/msubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/mtrap.cgs (100%)
rename sim/testsuite/{sim => }/frv/munpackh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mwcut.cgs (100%)
rename sim/testsuite/{sim => }/frv/mwcuti.cgs (100%)
rename sim/testsuite/{sim => }/frv/mwtacc.cgs (100%)
rename sim/testsuite/{sim => }/frv/mwtaccg.cgs (100%)
rename sim/testsuite/{sim => }/frv/mxor.cgs (100%)
rename sim/testsuite/{sim => }/frv/nandcr.cgs (100%)
rename sim/testsuite/{sim => }/frv/nandncr.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdcmps.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfddivs.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfditos.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdivs.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdmadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdmas.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdmss.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdmulcs.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdmuls.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdsads.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdsqrts.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdstoi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfitos.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfmadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfmas.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfmss.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfmsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfmuls.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfsqrts.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfstoi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/nld.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldbf.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldbfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldbfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldd.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlddf.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlddfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlddfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlddi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlddu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldf.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldhf.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldhfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldhfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldq.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldqf.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldqfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldqfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldqu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldsb.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldsbi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldsbu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldsh.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldshi.cgs (100%)
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rename sim/testsuite/{sim => }/frv/nldu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldub.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldubi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldubu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlduh.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlduhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlduhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nop.cgs (100%)
rename sim/testsuite/{sim => }/frv/norcr.cgs (100%)
rename sim/testsuite/{sim => }/frv/norncr.cgs (100%)
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rename sim/testsuite/{sim => }/frv/notcr.cgs (100%)
rename sim/testsuite/{sim => }/frv/nsdiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/nsdivi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nudiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/nudivi.cgs (100%)
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rename sim/testsuite/{sim => }/frv/orcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/orcr.cgs (100%)
rename sim/testsuite/{sim => }/frv/ori.cgs (100%)
rename sim/testsuite/{sim => }/frv/oricc.cgs (100%)
rename sim/testsuite/{sim => }/frv/orncr.cgs (100%)
rename sim/testsuite/{sim => }/frv/parallel.exp (100%)
rename sim/testsuite/{sim => }/frv/ret.cgs (100%)
rename sim/testsuite/{sim => }/frv/rett.cgs (100%)
rename sim/testsuite/{sim => }/frv/scan.cgs (100%)
rename sim/testsuite/{sim => }/frv/scani.cgs (100%)
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rename sim/testsuite/{sim => }/frv/sdivi.cgs (100%)
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rename sim/testsuite/{sim => }/frv/sethilo.pcgs (100%)
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rename sim/testsuite/{sim => }/frv/setlos.cgs (100%)
rename sim/testsuite/{sim => }/frv/sll.cgs (100%)
rename sim/testsuite/{sim => }/frv/sllcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/slli.cgs (100%)
rename sim/testsuite/{sim => }/frv/sllicc.cgs (100%)
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rename sim/testsuite/{sim => }/frv/smulcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/smuli.cgs (100%)
rename sim/testsuite/{sim => }/frv/smulicc.cgs (100%)
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rename sim/testsuite/{sim => }/frv/sracc.cgs (100%)
rename sim/testsuite/{sim => }/frv/srai.cgs (100%)
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rename sim/testsuite/{sim => }/frv/srl.cgs (100%)
rename sim/testsuite/{sim => }/frv/srlcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/srli.cgs (100%)
rename sim/testsuite/{sim => }/frv/srlicc.cgs (100%)
rename sim/testsuite/{sim => }/frv/st.cgs (100%)
rename sim/testsuite/{sim => }/frv/stb.cgs (100%)
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rename sim/testsuite/{sim => }/frv/stbfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/stbfu.cgs (100%)
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rename sim/testsuite/{sim => }/frv/stcu.cgs (100%)
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rename sim/testsuite/{sim => }/frv/stfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/stfu.cgs (100%)
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rename sim/testsuite/{sim => }/frv/stqc.pcgs (100%)
rename sim/testsuite/{sim => }/frv/stqcu.cgs (100%)
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rename sim/testsuite/{sim => }/frv/stqfi.cgs (100%)
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rename sim/testsuite/{sim => }/frv/subxi.cgs (100%)
rename sim/testsuite/{sim => }/frv/subxicc.cgs (100%)
rename sim/testsuite/{sim => }/frv/swap.cgs (100%)
rename sim/testsuite/{sim => }/frv/swapi.cgs (100%)
rename sim/testsuite/{sim => }/frv/tc.cgs (100%)
rename sim/testsuite/{sim => }/frv/teq.cgs (100%)
rename sim/testsuite/{sim => }/frv/testutils.inc (100%)
rename sim/testsuite/{sim => }/frv/tge.cgs (100%)
rename sim/testsuite/{sim => }/frv/tgt.cgs (100%)
rename sim/testsuite/{sim => }/frv/thi.cgs (100%)
rename sim/testsuite/{sim => }/frv/tic.cgs (100%)
rename sim/testsuite/{sim => }/frv/tieq.cgs (100%)
rename sim/testsuite/{sim => }/frv/tige.cgs (100%)
rename sim/testsuite/{sim => }/frv/tigt.cgs (100%)
rename sim/testsuite/{sim => }/frv/tihi.cgs (100%)
rename sim/testsuite/{sim => }/frv/tile.cgs (100%)
rename sim/testsuite/{sim => }/frv/tils.cgs (100%)
rename sim/testsuite/{sim => }/frv/tilt.cgs (100%)
rename sim/testsuite/{sim => }/frv/tin.cgs (100%)
rename sim/testsuite/{sim => }/frv/tinc.cgs (100%)
rename sim/testsuite/{sim => }/frv/tine.cgs (100%)
rename sim/testsuite/{sim => }/frv/tino.cgs (100%)
rename sim/testsuite/{sim => }/frv/tinv.cgs (100%)
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rename sim/testsuite/{sim => }/frv/tls.cgs (100%)
rename sim/testsuite/{sim => }/frv/tlt.cgs (100%)
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rename sim/testsuite/{sim => }/frv/tv.cgs (100%)
rename sim/testsuite/{sim => }/frv/udiv.cgs (100%)
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rename sim/testsuite/{sim => }/frv/umuli.cgs (100%)
rename sim/testsuite/{sim => }/frv/umulicc.cgs (100%)
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rename sim/testsuite/{sim => }/frv/xori.cgs (100%)
rename sim/testsuite/{sim => }/frv/xoricc.cgs (100%)
rename sim/testsuite/{sim => }/ft32/ChangeLog (100%)
rename sim/testsuite/{sim => }/ft32/allinsn.exp (100%)
rename sim/testsuite/{sim => }/ft32/basic.s (100%)
rename sim/testsuite/{sim => }/ft32/testutils.inc (100%)
create mode 100644 sim/testsuite/h8300/ChangeLog
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rename sim/testsuite/{sim => }/iq2000/ChangeLog (100%)
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rename sim/testsuite/{sim => }/iq2000/pass.s (100%)
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rename sim/testsuite/{sim => }/lm32/ChangeLog (100%)
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delete mode 100644 sim/testsuite/m32r-elf/ChangeLog
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delete mode 100644 sim/testsuite/m32r-elf/configure.ac
delete mode 100644 sim/testsuite/m32r-elf/exit47.s
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rename sim/testsuite/{sim => }/m32r/beqz.cgs (100%)
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create mode 100644 sim/testsuite/m32r/exit47.ms
rename sim/testsuite/{sim => }/m32r/hello.ms (100%)
rename sim/testsuite/{sim => }/m32r/hw-trap.ms (100%)
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rename sim/testsuite/{sim => }/v850/testutils.inc (100%)
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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-Os-vs-Os_LTO updated (e50f3878 -> abc37101)
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-Os-vs-Os_LTO
in repository toolchain/ci/base-artifacts.
discards e50f3878 2: update: gcc-ef370f933c03b95ff0e8ae86b3422d26fc5c49c6: 1
discards 5bd83c60 1: reset: gcc-eafe8ee7af13c39805ea09bbf5b4f9ab2a48304a: 1
discards aab3b4b6 0: update: binutils-glibc: 1
new abc37101 0: update: binutils-gcc-glibc: 1
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branch are not in the new version. This situation occurs
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containing something like this:
* -- * -- B -- O -- O -- O (e50f3878)
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N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-s [...]
You should already have received notification emails for all of the O
revisions, and so the following emails describe only the N revisions
from the common base, B.
Any revisions marked "omits" are not gone; other references still
refer to them. Any revisions marked "discards" are gone forever.
The 1 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
01-reset_artifacts/console.log | 129 +-
02-prepare_abe/console.log | 436 +-
03-build_abe-binutils/console.log | 11332 +-
04-build_abe-stage1/console.log | 20016 ++-
05-build_abe-linux/console.log | 192 -
05-clean_sysroot/console.log | 14 +
06-build_abe-glibc/console.log | 19680 ---
06-build_abe-linux/console.log | 1047 +
07-build_abe-glibc/console.log | 20149 +++
07-build_abe-stage2/console.log | 23022 ----
08-benchmark--Os_mthumb/benchmark-start.log | 1 -
08-build_abe-stage2/console.log | 19769 +++
09-benchmark--Os_LTO_mthumb/benchmark-start.log | 1 -
09-benchmark--Os_mthumb/benchmark-start.log | 1 +
.../benchmark.log | 45 +-
.../console.log | 230 +-
10-benchmark--Os_LTO_mthumb/benchmark-start.log | 1 +
.../benchmark.log | 42 +-
.../console.log | 177 +-
11-check_regression/console.log | 1232 -
11-check_regression/new-results-0.csv | 30 -
11-check_regression/new-results-1.csv | 31 -
11-check_regression/new-results-brief.csv | 30 -
11-check_regression/new-results-compare.csv | 30 -
11-check_regression/new-results-full.csv | 30 -
11-check_regression/new-results.csv | 30 -
11-check_regression/new-results.log | 7079 --
11-check_regression/new-results.regressions | 1 -
11-check_regression/ref-results-0.csv | 30 -
11-check_regression/ref-results-1.csv | 31 -
11-check_regression/ref-results-brief.csv | 30 -
11-check_regression/ref-results-compare.csv | 30 -
11-check_regression/ref-results-full.csv | 30 -
11-check_regression/ref-results.csv | 30 -
11-check_regression/ref-results.log | 7227 --
11-check_regression/ref-results.regressions | 1 -
11-check_regression/results-compare.csv | 30 -
{10-true => 11-true}/console.log | 0
12-check_regression/console.log | 179 +
.../extra-bisect-params | 0
12-check_regression/new-results-0.csv | 1 +
12-check_regression/new-results-1.csv | 1 +
12-check_regression/new-results-brief.csv | 1 +
12-check_regression/new-results-compare.csv | 1 +
12-check_regression/new-results-full.csv | 1 +
12-check_regression/new-results.csv | 1 +
12-check_regression/new-results.log | 3748 +
12-check_regression/ref-results-0.csv | 1 +
12-check_regression/ref-results-1.csv | 3 +
12-check_regression/ref-results-brief.csv | 2 +
12-check_regression/ref-results-compare.csv | 1 +
12-check_regression/ref-results-full.csv | 2 +
12-check_regression/ref-results.csv | 2 +
12-check_regression/ref-results.log | 3693 +
12-check_regression/results-compare.csv | 1 +
12-update_baseline/console.log | 3694 -
12-update_baseline/extra-bisect-params | 1 -
12-update_baseline/new-results-0.csv | 30 -
12-update_baseline/new-results-1.csv | 31 -
12-update_baseline/new-results-brief.csv | 30 -
12-update_baseline/new-results-compare.csv | 30 -
12-update_baseline/new-results-full.csv | 30 -
12-update_baseline/new-results.csv | 30 -
12-update_baseline/new-results.log | 7079 --
12-update_baseline/new-results.regressions | 1 -
12-update_baseline/ref-results-0.csv | 30 -
12-update_baseline/ref-results-1.csv | 30 -
12-update_baseline/ref-results-brief.csv | 30 -
12-update_baseline/ref-results-compare.csv | 30 -
12-update_baseline/ref-results-full.csv | 30 -
12-update_baseline/ref-results.csv | 30 -
12-update_baseline/ref-results.log | 7322 --
12-update_baseline/ref-results.regressions | 1 -
12-update_baseline/results-compare.csv | 30 -
12-update_baseline/results.regressions | 1 -
13-update_baseline/console.log | 531 +
.../extra-bisect-params | 0
13-update_baseline/new-results-0.csv | 1 +
13-update_baseline/new-results-1.csv | 1 +
13-update_baseline/new-results-brief.csv | 1 +
13-update_baseline/new-results-compare.csv | 1 +
13-update_baseline/new-results-full.csv | 1 +
13-update_baseline/new-results.csv | 1 +
13-update_baseline/new-results.log | 3748 +
13-update_baseline/ref-results-0.csv | 1 +
13-update_baseline/ref-results-1.csv | 1 +
13-update_baseline/ref-results-brief.csv | 1 +
13-update_baseline/ref-results-compare.csv | 1 +
13-update_baseline/ref-results-full.csv | 1 +
13-update_baseline/ref-results.csv | 1 +
13-update_baseline/ref-results.log | 3748 +
13-update_baseline/results-compare.csv | 1 +
console.log | 119647 +++++++++---------
jenkins/manifest.sh | 26 +-
results_id-1 | 2 +-
results_id-2 | 2 +-
96 files changed, 129603 insertions(+), 156458 deletions(-)
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rename {09-benchmark--Os_LTO_mthumb => 09-benchmark--Os_mthumb}/benchmark.log (69%)
rename {08-benchmark--Os_mthumb => 09-benchmark--Os_mthumb}/console.log (52%)
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rename {08-benchmark--Os_mthumb => 10-benchmark--Os_LTO_mthumb}/benchmark.log (77%)
rename {09-benchmark--Os_LTO_mthumb => 10-benchmark--Os_LTO_mthumb}/console.log (61%)
delete mode 100644 11-check_regression/console.log
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delete mode 100644 11-check_regression/results-compare.csv
rename {10-true => 11-true}/console.log (100%)
create mode 100644 12-check_regression/console.log
copy {11-check_regression => 12-check_regression}/extra-bisect-params (100%)
create mode 100644 12-check_regression/new-results-0.csv
create mode 100644 12-check_regression/new-results-1.csv
create mode 100644 12-check_regression/new-results-brief.csv
create mode 100644 12-check_regression/new-results-compare.csv
create mode 100644 12-check_regression/new-results-full.csv
create mode 100644 12-check_regression/new-results.csv
create mode 100644 12-check_regression/new-results.log
create mode 100644 12-check_regression/ref-results-0.csv
create mode 100644 12-check_regression/ref-results-1.csv
create mode 100644 12-check_regression/ref-results-brief.csv
create mode 100644 12-check_regression/ref-results-compare.csv
create mode 100644 12-check_regression/ref-results-full.csv
create mode 100644 12-check_regression/ref-results.csv
create mode 100644 12-check_regression/ref-results.log
create mode 100644 12-check_regression/results-compare.csv
delete mode 100644 12-update_baseline/console.log
delete mode 100644 12-update_baseline/extra-bisect-params
delete mode 100644 12-update_baseline/new-results-0.csv
delete mode 100644 12-update_baseline/new-results-1.csv
delete mode 100644 12-update_baseline/new-results-brief.csv
delete mode 100644 12-update_baseline/new-results-compare.csv
delete mode 100644 12-update_baseline/new-results-full.csv
delete mode 100644 12-update_baseline/new-results.csv
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delete mode 100644 12-update_baseline/results-compare.csv
delete mode 100644 12-update_baseline/results.regressions
create mode 100644 13-update_baseline/console.log
rename {11-check_regression => 13-update_baseline}/extra-bisect-params (100%)
create mode 100644 13-update_baseline/new-results-0.csv
create mode 100644 13-update_baseline/new-results-1.csv
create mode 100644 13-update_baseline/new-results-brief.csv
create mode 100644 13-update_baseline/new-results-compare.csv
create mode 100644 13-update_baseline/new-results-full.csv
create mode 100644 13-update_baseline/new-results.csv
create mode 100644 13-update_baseline/new-results.log
create mode 100644 13-update_baseline/ref-results-0.csv
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create mode 100644 13-update_baseline/ref-results-brief.csv
create mode 100644 13-update_baseline/ref-results-compare.csv
create mode 100644 13-update_baseline/ref-results-full.csv
create mode 100644 13-update_baseline/ref-results.csv
create mode 100644 13-update_baseline/ref-results.log
create mode 100644 13-update_baseline/results-compare.csv
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- 1
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[binutils-gdb] branch master updated (0e33957abf8 -> a71501e25ff)
by git＠git.linaro.org
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unknown user pushed a change to branch master
in repository binutils-gdb.
from 0e33957abf8 Automatic date update in version.in
new 2ab76a181f3 Fix attaching in non-stop mode (PR gdb/27055)
new 621cc310717 Fix "target extended-remote" + "maint set target-non-stop" [...]
new 92234eb192f Testcase for attaching in non-stop mode
new b0083dd72fc Fix a couple vStopped pending ack bugs
new 7e9cf1fe361 gdbserver: spurious SIGTRAP w/ detach while step-over in progress
new d758e62c0ec Factor out after-stop event handling code from stop_all_threads
new 9147506842a prepare_for_detach: don't release scoped_restore at the end
new 8ff531399b7 prepare_for_detach and ongoing displaced stepping
new e87f0fe8237 detach and breakpoint removal
new ac7d717c1eb detach with in-line step over in progress
new 408f66864a1 detach in all-stop with threads running
new a71501e25ff Testcase for detaching while stepping over breakpoint
The 12 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
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Summary of changes:
gdb/ChangeLog | 61 ++
gdb/infcmd.c | 13 +
gdb/infrun.c | 635 ++++++++++++---------
gdb/infrun.h | 4 +
gdb/linux-nat.c | 5 +
gdb/remote.c | 39 +-
gdb/target.c | 9 -
gdb/target.h | 7 +
gdb/testsuite/ChangeLog | 10 +
.../tids.c => gdb.threads/attach-non-stop.c} | 40 +-
gdb/testsuite/gdb.threads/attach-non-stop.exp | 148 +++++
gdb/testsuite/gdb.threads/detach-step-over.c | 112 ++++
gdb/testsuite/gdb.threads/detach-step-over.exp | 290 ++++++++++
gdbserver/ChangeLog | 10 +
gdbserver/linux-low.cc | 29 +-
gdbserver/server.cc | 9 +
16 files changed, 1117 insertions(+), 304 deletions(-)
copy gdb/testsuite/{gdb.multi/tids.c => gdb.threads/attach-non-stop.c} (64%)
create mode 100644 gdb/testsuite/gdb.threads/attach-non-stop.exp
create mode 100644 gdb/testsuite/gdb.threads/detach-step-over.c
create mode 100644 gdb/testsuite/gdb.threads/detach-step-over.exp
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[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_ubsan updated (0f42bb87222 -> a4f8e2fc771)
by git＠git.linaro.org
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_ubsan
in repository toolchain/ci/gcc.
from 0f42bb87222 PR fortran/86470 - ICE with OpenMP, class(*) allocatable
adds 96a85f8734a Daily bump.
adds 3976b2701b8 tree-optimization/97627 - Avoid computing niters for fake edges
adds 81fd2df5911 c++: Fix list-init of array of no-copy type [PR63707]
adds 506fcfdb125 c++: Avoid redundant copy in {} init [PR98642]
adds 85908100051 c++: Invisible refs are not restrict [PR97474]
adds 2127d2c3ee2 c++: [[no_unique_address]] in empty base [PR98463]
adds 8182cbe3fb2 c++: Fix up potential_constant_expression_1 FOR/WHILE_STMT [...]
adds 8e28ebfa5a3 on ARRAY_REFs sign-extend offsets only from sizetype's prec [...]
adds dd92986ea6d match.pd: Replace incorrect simplifications into copysign [ [...]
adds e5750f84715 c++: Fix up ubsan false positives on references [PR95693]
adds db9a3ce7b83 rs6000: Fix up __m64 typedef in mmintrin.h [PR97301]
adds c20cd1688ae fold: Fix up strn{case,}cmp folding [PR98771]
adds fb09d7242a2 aarch64: Tighten up checks for ubfix [PR98681]
adds 2a2c1e22c25 aarch64: Fix up *aarch64_bfxilsi_uxtw [PR98853]
adds cf93f94b349 c++: Fix up handling of register ... asm ("...") vars in te [...]
adds ea0e1eaa30f expand: Fix up find_bb_boundaries [PR98331]
adds 64dd326e97f Daily bump.
adds 739a5d45884 Daily bump.
adds b051aa35005 Add missing definition of SIZE_MAX
adds 86dae8a243a Daily bump.
adds 037a02be13d PR target/96307: Fix KASAN option checking.
adds 4311ae206da rtl-optimization/98863 - fix PRE/CPROP memory usage check
adds f426e4f6345 c++: cxx_eval_vec_init after zero-initialization [PR96282]
adds c616e86e8bc c++: Improve sorry for __builtin_has_attribute [PR98355]
adds a6de3b05735 Daily bump.
adds 38c2d9598b1 d: Fix junk in generated symbol on powerpc64-*-* [PR98921]
adds a4f8e2fc771 c++: Fix ICE from verify_ctor_sanity [PR98295]
No new revisions were added by this update.
Summary of changes:
contrib/ChangeLog | 5 +
gcc/ChangeLog | 83 +++++++++++++
gcc/DATESTAMP | 2 +-
gcc/cfgbuild.c | 1 +
gcc/config/aarch64/aarch64.c | 9 +-
gcc/config/aarch64/aarch64.md | 4 +-
gcc/config/rs6000/mmintrin.h | 3 +-
gcc/cp/ChangeLog | 77 ++++++++++++
gcc/cp/call.c | 6 +-
gcc/cp/constexpr.c | 133 +++++++++++++++++++--
gcc/cp/decl.c | 6 +
gcc/cp/init.c | 5 +-
gcc/cp/parser.c | 2 +-
gcc/cp/pt.c | 14 ++-
gcc/cp/tree.c | 10 +-
gcc/cp/typeck2.c | 32 +++--
gcc/d/dmd/dmangle.c | 29 +++--
gcc/d/dmd/root/outbuffer.c | 31 +++++
gcc/d/dmd/root/outbuffer.h | 1 +
gcc/fold-const-call.c | 22 ++--
gcc/fortran/ChangeLog | 9 ++
gcc/gcse.c | 11 +-
gcc/gimple-fold.c | 2 +-
gcc/match.pd | 46 +++----
gcc/system.h | 4 +
gcc/testsuite/ChangeLog | 111 +++++++++++++++++
gcc/testsuite/g++.dg/cpp0x/constexpr-98295.C | 11 ++
gcc/testsuite/g++.dg/cpp0x/constexpr-array26.C | 13 ++
gcc/testsuite/g++.dg/cpp0x/constexpr-array27.C | 13 ++
gcc/testsuite/g++.dg/cpp0x/initlist-array13.C | 16 +++
gcc/testsuite/g++.dg/cpp1y/constexpr-98672.C | 92 ++++++++++++++
gcc/testsuite/g++.dg/cpp1z/elide5.C | 15 +++
gcc/testsuite/g++.dg/cpp2a/constexpr-init18.C | 16 +++
gcc/testsuite/g++.dg/cpp2a/no_unique_address8.C | 11 ++
gcc/testsuite/g++.dg/ext/builtin-has-attribute2.C | 8 ++
gcc/testsuite/g++.dg/pr97627.C | 44 +++++++
gcc/testsuite/g++.dg/torture/pr97474.C | 28 +++++
gcc/testsuite/g++.dg/ubsan/pr95693.C | 26 ++++
gcc/testsuite/g++.target/i386/pr98847.C | 20 ++++
gcc/testsuite/gcc.c-torture/execute/pr98681.c | 18 +++
gcc/testsuite/gcc.c-torture/execute/pr98853-1.c | 21 ++++
gcc/testsuite/gcc.c-torture/execute/pr98853-2.c | 19 +++
gcc/testsuite/gcc.dg/pr90248.c | 73 +++++++++++
.../{gcc.target/riscv => gcc.dg}/pr91441.c | 1 +
.../{gcc.target/riscv => gcc.dg}/pr96260.c | 1 +
gcc/testsuite/gcc.dg/pr96307.c | 25 ++++
gcc/testsuite/gcc.dg/pr98255.c | 49 ++++++++
gcc/testsuite/gcc.dg/pr98331.c | 18 +++
gcc/testsuite/gcc.dg/tree-ssa/copy-sign-1.c | 2 +-
gcc/testsuite/lib/target-supports.exp | 11 ++
gcc/toplev.c | 1 -
gcc/tree-dfa.c | 6 +-
gcc/tree-ssa-loop-niter.c | 5 +
gcc/tree-ssa-sccvn.c | 2 +-
54 files changed, 1122 insertions(+), 101 deletions(-)
create mode 100644 gcc/testsuite/g++.dg/cpp0x/constexpr-98295.C
create mode 100644 gcc/testsuite/g++.dg/cpp0x/constexpr-array26.C
create mode 100644 gcc/testsuite/g++.dg/cpp0x/constexpr-array27.C
create mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist-array13.C
create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-98672.C
create mode 100644 gcc/testsuite/g++.dg/cpp1z/elide5.C
create mode 100644 gcc/testsuite/g++.dg/cpp2a/constexpr-init18.C
create mode 100644 gcc/testsuite/g++.dg/cpp2a/no_unique_address8.C
create mode 100644 gcc/testsuite/g++.dg/ext/builtin-has-attribute2.C
create mode 100644 gcc/testsuite/g++.dg/pr97627.C
create mode 100644 gcc/testsuite/g++.dg/torture/pr97474.C
create mode 100644 gcc/testsuite/g++.dg/ubsan/pr95693.C
create mode 100644 gcc/testsuite/g++.target/i386/pr98847.C
create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr98681.c
create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr98853-1.c
create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr98853-2.c
create mode 100644 gcc/testsuite/gcc.dg/pr90248.c
rename gcc/testsuite/{gcc.target/riscv => gcc.dg}/pr91441.c (85%)
rename gcc/testsuite/{gcc.target/riscv => gcc.dg}/pr96260.c (77%)
create mode 100644 gcc/testsuite/gcc.dg/pr96307.c
create mode 100644 gcc/testsuite/gcc.dg/pr98255.c
create mode 100644 gcc/testsuite/gcc.dg/pr98331.c
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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_ubsan updated (99a7aadb -> 68693a08)
by git＠git.linaro.org
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discards 99a7aadb 0: update: gcc-0f42bb8722204fb83dcd001cc4254ad25b969402: 1
new 68693a08 0: update: gcc-a4f8e2fc771bea21aaac44433e75510362e208c1: 1
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01-reset_artifacts/console.log | 20 +-
02-prepare_abe/console.log | 162 +-
04-build_abe-bootstrap_ubsan/console.log | 91412 ++++++++++++++--------------
05-check_regression/console.log | 2 +-
06-update_baseline/console.log | 4 +-
console.log | 91608 +++++++++++++++--------------
jenkins/manifest.sh | 10 +-
7 files changed, 91623 insertions(+), 91595 deletions(-)
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