Tcwg-commits December 2021

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[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_gnu_tk1/gnu-master-arm-spec2k6-O3 updated (f20f980c71 -> 268d812c19)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_gnu_tk1/gnu-master-arm-spec2k6-O3 in repository toolchain/ci/glibc. from f20f980c71 x86-64: Add vector acos/acosf implementation to libmvec adds cd0c333d2e elf: Remove unused NEED_DL_BASE_ADDR and _dl_base_addr adds 9702a7901e stdio: Implement %#m for vfprintf and related functions adds a4b4131355 Set default __TIMESIZE default to 64 adds 6e30181b4a math: Properly cast X_TLOSS to float [BZ #28713] adds 268d812c19 elf: Remove AArch64 from comment for AT_MINSIGSTKSZ No new revisions were added by this update. Summary of changes: NEWS | 3 + bits/timesize.h | 4 +- elf/dl-sysdep.c | 8 -- elf/elf.h | 3 +- manual/stdio.texi | 8 +- math/math-svid-compat.h | 2 + math/w_j0f_compat.c | 5 +- math/w_j1f_compat.c | 5 +- math/w_jnf_compat.c | 5 +- stdio-common/Makefile | 4 +- stdio-common/tst-sprintf-errno.c | 93 ++++++++++++++++++++++ stdio-common/vfprintf-internal.c | 25 ++++-- .../sysv/linux/arc => mach/hurd}/bits/timesize.h | 11 ++- .../unix/sysv/linux/arm/bits}/timesize.h | 8 +- .../unix/sysv/linux/csky/bits}/timesize.h | 8 +- .../unix/sysv/linux/hppa/bits}/timesize.h | 8 +- .../unix/sysv/linux/m68k/bits}/timesize.h | 8 +- .../unix/sysv/linux/microblaze/bits}/timesize.h | 8 +- .../unix/sysv/linux/mips/bits}/timesize.h | 12 +-- .../sysv/linux/{riscv => nios2}/bits/timesize.h | 10 +-- .../sysv/linux/powerpc/powerpc32/bits}/timesize.h | 8 +- .../unix/sysv/linux/s390/s390-32/bits}/timesize.h | 8 +- .../unix/sysv/linux/sh/bits}/timesize.h | 8 +- .../unix/sysv/linux/sparc/sparc32/bits}/timesize.h | 8 +- sysdeps/unix/sysv/linux/x86/bits/timesize.h | 2 + 25 files changed, 183 insertions(+), 89 deletions(-) create mode 100644 stdio-common/tst-sprintf-errno.c rename sysdeps/{unix/sysv/linux/arc => mach/hurd}/bits/timesize.h (74%) copy {bits => sysdeps/unix/sysv/linux/arm/bits}/timesize.h (81%) copy {bits => sysdeps/unix/sysv/linux/csky/bits}/timesize.h (81%) copy {bits => sysdeps/unix/sysv/linux/hppa/bits}/timesize.h (81%) copy {bits => sysdeps/unix/sysv/linux/m68k/bits}/timesize.h (81%) copy {bits => sysdeps/unix/sysv/linux/microblaze/bits}/timesize.h (81%) copy {bits => sysdeps/unix/sysv/linux/mips/bits}/timesize.h (79%) rename sysdeps/unix/sysv/linux/{riscv => nios2}/bits/timesize.h (77%) copy {bits => sysdeps/unix/sysv/linux/powerpc/powerpc32/bits}/timesize.h (81%) copy {bits => sysdeps/unix/sysv/linux/s390/s390-32/bits}/timesize.h (81%) copy {bits => sysdeps/unix/sysv/linux/sh/bits}/timesize.h (81%) copy {bits => sysdeps/unix/sysv/linux/sparc/sparc32/bits}/timesize.h (81%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_gnu_tk1/gnu-master-arm-spec2k6-O3 updated (9f9bc0bf0d6 -> 10ae9946dce)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_gnu_tk1/gnu-master-arm-spec2k6-O3 in repository toolchain/ci/gcc. from 9f9bc0bf0d6 Daily bump. adds 1a7ce857099 Combine vpcmpuw + zero_extend to vpcmpuw. adds 9ac0730c25b Fix typo in type verification. adds 61e53698a08 i386: Enable intrinsics that convert float and bf16 data to [...] adds ef26c151c14 x86: PR target/103773: Fix wrong-code with -Oz from pop to memory. adds 8f34344ec69 smuldi3_highpart.c: Replace long with long long for -mx32 adds 7d01da81b80 Daily bump. adds 9a4a29eaf23 Darwin: Define OBJECT_FORMAT_MACHO. adds 8381075ff3f Darwin: Check for that flag-reorder-and-partition. adds 19bf83a9a06 Darwin: Update rules for handling alignment of globals. adds 43dadcf3e7b Darwin: Amend a comment to be more inclusive [NFC]. adds 8f921393e33 i386: Add V2SFmode DIV insn pattern [PR95046, PR103797] adds ffb5418fb79 Daily bump. adds 4ae906e46c4 Fortran: simplify library code for integer-to-decimal conversion adds 10ae9946dce Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 84 ++++ gcc/DATESTAMP | 2 +- gcc/config.gcc | 14 + gcc/config/darwin.c | 24 +- gcc/config/darwin.h | 11 +- gcc/config/i386/avx512bf16intrin.h | 36 ++ gcc/config/i386/avx512bf16vlintrin.h | 63 +++ gcc/config/i386/i386.md | 62 ++- gcc/config/i386/mmx.md | 20 + gcc/config/i386/sse.md | 275 ++++++++++++ gcc/testsuite/ChangeLog | 42 ++ gcc/testsuite/gcc.dg/attr-aligned.c | 8 +- gcc/testsuite/gcc.dg/darwin-aligned-globals.c | 24 ++ gcc/testsuite/gcc.dg/darwin-comm-1.c | 5 + .../gcc.target/i386/avx512bf16-cvtsbh2ss-1.c | 15 + .../gcc.target/i386/avx512bf16-vcvtpbh2ps-1.c | 20 + .../gcc.target/i386/avx512bf16vl-cvtness2sbh-1.c | 14 + .../gcc.target/i386/avx512bf16vl-vcvtpbh2ps-1.c | 29 ++ .../gcc.target/i386/avx512bw-pr103750-1.c | 154 +++++++ .../gcc.target/i386/avx512bw-pr103750-2.c | 173 ++++++++ gcc/testsuite/gcc.target/i386/avx512f-pr103750-1.c | 426 ++++++++++++++++++ gcc/testsuite/gcc.target/i386/avx512f-pr103750-2.c | 478 +++++++++++++++++++++ .../gcc.target/i386/avx512fp16-pr103750-1.c | 58 +++ .../gcc.target/i386/avx512fp16-pr103750-2.c | 71 +++ gcc/testsuite/gcc.target/i386/pr103773-2.c | 19 + gcc/testsuite/gcc.target/i386/pr103773.c | 12 + gcc/testsuite/gcc.target/i386/pr89261.c | 3 +- gcc/testsuite/gcc.target/i386/pr95046-1.c | 11 +- gcc/testsuite/gcc.target/i386/smuldi3_highpart.c | 2 +- gcc/tree.c | 2 +- libgfortran/ChangeLog | 18 + libgfortran/io/write.c | 70 ++- libgfortran/libgfortran.h | 7 +- libgfortran/runtime/backtrace.c | 1 + libgfortran/runtime/error.c | 31 -- libgfortran/runtime/string.c | 39 +- 36 files changed, 2204 insertions(+), 119 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/darwin-aligned-globals.c create mode 100644 gcc/testsuite/gcc.dg/darwin-comm-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512bf16-cvtsbh2ss-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512bf16-vcvtpbh2ps-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512bf16vl-cvtness2sbh-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512bf16vl-vcvtpbh2ps-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512bw-pr103750-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512bw-pr103750-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-pr103750-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-pr103750-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-pr103750-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-pr103750-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr103773-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr103773.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk_gnu_tk1/gnu-master-arm-spec2k6-O3 updated (7898f55ba0 -> d16ce6240e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_gnu_tk1/gnu-master-arm-spec2k6-O3 in repository toolchain/ci/binutils-gdb. from 7898f55ba0 Automatic date update in version.in adds 391c90eea5 gdb: make use of SCOPE_EXIT to manage thread executing state adds b1718fcdd1 gdb: on x86-64 non-trivial C++ objects are returned in memory adds b622494ee3 gdb/remote: handle attach when stop packet lacks thread-id adds b6846ba57b gdb/testsuite: resolve some duplicate testnames in gdb.mi adds d20236e748 Automatic date update in version.in adds 5c3ffbc4dd RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implement [...] adds a63375ac33 RISC-V: Hypervisor ext: support Privileged Spec 1.12 adds b6a08665ff RISC-V: Rewrite the csr testcases. adds 34b965f7c0 Move gdb_bfd_errmsg to gdb_bfd.c adds 64b7cc507b Remove gdb_print_host_address adds 5436dda805 Automatic date update in version.in adds d16ce6240e Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/cpu-riscv.c | 1 + bfd/cpu-riscv.h | 1 + bfd/version.h | 2 +- gas/config/tc-riscv.c | 10 +- gas/testsuite/gas/riscv/csr-dw-regnums.d | 10 - gas/testsuite/gas/riscv/csr-dw-regnums.s | 10 - gas/testsuite/gas/riscv/csr-fail-nonexistent.d | 3 + ...g-fail-nonexistent.l => csr-fail-nonexistent.l} | 0 ...g-fail-nonexistent.s => csr-fail-nonexistent.s} | 0 ...pseudo-noalias.d => csr-insns-pseudo-noalias.d} | 2 +- .../{priv-reg-pseudo.d => csr-insns-pseudo.d} | 2 +- .../{priv-reg-pseudo.s => csr-insns-pseudo.s} | 0 gas/testsuite/gas/riscv/csr-insns-read-only.d | 3 + ...g-fail-read-only-02.l => csr-insns-read-only.l} | 0 ...g-fail-read-only-02.s => csr-insns-read-only.s} | 0 gas/testsuite/gas/riscv/csr-version-1p10.d | 573 +++++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p10.l | 309 +++++++++++ gas/testsuite/gas/riscv/csr-version-1p11.d | 573 +++++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p11.l | 307 +++++++++++ gas/testsuite/gas/riscv/csr-version-1p12.d | 573 +++++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p12.l | 255 +++++++++ gas/testsuite/gas/riscv/csr-version-1p9p1.d | 573 +++++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p9p1.l | 335 ++++++++++++ gas/testsuite/gas/riscv/{priv-reg.s => csr.s} | 74 ++- gas/testsuite/gas/riscv/h-ext-32.d | 30 ++ gas/testsuite/gas/riscv/h-ext-32.s | 21 + gas/testsuite/gas/riscv/h-ext-64.d | 33 ++ gas/testsuite/gas/riscv/h-ext-64.s | 24 + gas/testsuite/gas/riscv/priv-reg-fail-fext.d | 3 - gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 - .../gas/riscv/priv-reg-fail-nonexistent.d | 3 - .../gas/riscv/priv-reg-fail-read-only-01.d | 3 - .../gas/riscv/priv-reg-fail-read-only-01.l | 71 --- .../gas/riscv/priv-reg-fail-read-only-01.s | 269 ---------- .../gas/riscv/priv-reg-fail-read-only-02.d | 3 - gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d | 3 - gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 68 --- .../gas/riscv/priv-reg-fail-version-1p10.d | 11 - .../gas/riscv/priv-reg-fail-version-1p10.l | 25 - .../gas/riscv/priv-reg-fail-version-1p11.d | 11 - .../gas/riscv/priv-reg-fail-version-1p11.l | 24 - .../gas/riscv/priv-reg-fail-version-1p9p1.d | 12 - .../gas/riscv/priv-reg-fail-version-1p9p1.l | 28 - gas/testsuite/gas/riscv/priv-reg-fail-zkr.d | 3 - gas/testsuite/gas/riscv/priv-reg-fail-zkr.l | 4 - gas/testsuite/gas/riscv/priv-reg-version-1p10.d | 275 ---------- gas/testsuite/gas/riscv/priv-reg-version-1p11.d | 275 ---------- gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d | 275 ---------- gdb/amd64-tdep.c | 16 +- gdb/dummy-frame.c | 12 +- gdb/gdb_bfd.c | 30 ++ gdb/gdb_bfd.h | 7 + gdb/gdbtypes.c | 161 +++--- gdb/psymtab.c | 46 +- gdb/record-btrace.c | 24 +- gdb/record-full.c | 8 +- gdb/remote.c | 31 +- gdb/symmisc.c | 48 +- gdb/testsuite/gdb.cp/non-trivial-retval.cc | 19 +- gdb/testsuite/gdb.cp/non-trivial-retval.exp | 26 + gdb/testsuite/gdb.mi/mi-syn-frame.exp | 12 +- gdb/testsuite/gdb.mi/mi-var-child.exp | 10 +- gdb/testsuite/gdb.mi/mi-var-rtti.cc | 48 +- gdb/testsuite/gdb.mi/mi-watch.exp | 2 +- gdb/testsuite/gdb.mi/mi2-amd64-entry-value.exp | 236 +++++---- gdb/testsuite/gdb.mi/mi2-var-child.exp | 10 +- gdb/testsuite/gdb.server/ext-attach.exp | 98 ++-- gdb/utils.c | 36 -- gdb/utils.h | 14 - include/opcode/riscv-opc.h | 120 ++++- opcodes/riscv-opc.c | 21 + 71 files changed, 4259 insertions(+), 1872 deletions(-) create mode 100644 gas/testsuite/gas/riscv/csr-fail-nonexistent.d rename gas/testsuite/gas/riscv/{priv-reg-fail-nonexistent.l => csr-fail-nonexisten [...] rename gas/testsuite/gas/riscv/{priv-reg-fail-nonexistent.s => csr-fail-nonexisten [...] rename gas/testsuite/gas/riscv/{priv-reg-pseudo-noalias.d => csr-insns-pseudo-noal [...] rename gas/testsuite/gas/riscv/{priv-reg-pseudo.d => csr-insns-pseudo.d} (98%) rename gas/testsuite/gas/riscv/{priv-reg-pseudo.s => csr-insns-pseudo.s} (100%) create mode 100644 gas/testsuite/gas/riscv/csr-insns-read-only.d rename gas/testsuite/gas/riscv/{priv-reg-fail-read-only-02.l => csr-insns-read-onl [...] rename gas/testsuite/gas/riscv/{priv-reg-fail-read-only-02.s => csr-insns-read-onl [...] create mode 100644 gas/testsuite/gas/riscv/csr-version-1p10.d create mode 100644 gas/testsuite/gas/riscv/csr-version-1p10.l create mode 100644 gas/testsuite/gas/riscv/csr-version-1p11.d create mode 100644 gas/testsuite/gas/riscv/csr-version-1p11.l create mode 100644 gas/testsuite/gas/riscv/csr-version-1p12.d create mode 100644 gas/testsuite/gas/riscv/csr-version-1p12.l create mode 100644 gas/testsuite/gas/riscv/csr-version-1p9p1.d create mode 100644 gas/testsuite/gas/riscv/csr-version-1p9p1.l rename gas/testsuite/gas/riscv/{priv-reg.s => csr.s} (82%) create mode 100644 gas/testsuite/gas/riscv/h-ext-32.d create mode 100644 gas/testsuite/gas/riscv/h-ext-32.s create mode 100644 gas/testsuite/gas/riscv/h-ext-64.d create mode 100644 gas/testsuite/gas/riscv/h-ext-64.s delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-fext.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-fext.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-zkr.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-zkr.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p10.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p11.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_gnu_tk1/gnu-master-arm-spec2k6-O3 updated (d0e5dd78e -> 6f53c057f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_gnu_tk1/gnu-master-arm-spec2k6-O3 in repository toolchain/ci/base-artifacts. discards d0e5dd78e 0: update: binutils-gcc-linux-glibc: 1 new 6f53c057f 0: update: binutils-gcc-linux-glibc: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (d0e5dd78e) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk_gnu_tk1/gnu-master-a [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1552 -> 1568 bytes 02-prepare_abe/console.log.xz | Bin 2760 -> 2764 bytes 03-build_abe-binutils/console.log.xz | Bin 30856 -> 30268 bytes 04-build_abe-stage1/console.log.xz | Bin 92080 -> 91600 bytes 06-build_abe-linux/console.log.xz | Bin 9000 -> 8036 bytes 07-build_abe-glibc/console.log.xz | Bin 232632 -> 232312 bytes 08-build_abe-stage2/console.log.xz | Bin 208828 -> 205304 bytes 09-benchmark/benchmark-build.log | 64 +- 09-benchmark/benchmark.log | 62 +- 09-benchmark/console.log.xz | Bin 3104 -> 3108 bytes 10-check_regression/console.log.xz | Bin 7776 -> 7732 bytes 10-check_regression/results-0.csv | 3364 ++++----- 10-check_regression/results-1.csv | 3298 +++++---- 10-check_regression/results-brief.csv | 58 +- 10-check_regression/results-compare.csv | 132 +- 10-check_regression/results-full.csv | 3444 +++++---- 10-check_regression/results-perf-0.csv | 3364 ++++----- 10-check_regression/results-perf-1.csv | 3298 +++++---- 10-check_regression/results-vect-0.csv | 810 +-- 10-check_regression/results-vect-1.csv | 850 +-- 10-check_regression/results.csv | 240 +- 10-check_regression/results.log | 5410 +++++++------- 11-update_baseline/console.log | 7410 ++++++++++---------- 11-update_baseline/results-0.csv | 3364 ++++----- 11-update_baseline/results-1.csv | 3298 +++++---- 11-update_baseline/results-brief.csv | 58 +- 11-update_baseline/results-compare.csv | 132 +- 11-update_baseline/results-full.csv | 3444 +++++---- 11-update_baseline/results-perf-0.csv | 3364 ++++----- 11-update_baseline/results-perf-1.csv | 3298 +++++---- 11-update_baseline/results-vect-0.csv | 810 +-- 11-update_baseline/results-vect-1.csv | 850 +-- 11-update_baseline/results.csv | 240 +- 11-update_baseline/results.log | 5462 +++++++-------- .../top-artifacts/save-temps/400.perlbench.tar.xz | Bin 1445616 -> 1446488 bytes .../top-artifacts/save-temps/401.bzip2.tar.xz | Bin 111940 -> 111408 bytes .../top-artifacts/save-temps/403.gcc.tar.xz | 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12496720 -> 12797348 bytes jenkins/manifest.sh | 18 +- results_id | 2 +- save-temps/400.perlbench.tar.xz | Bin 1445616 -> 1446488 bytes save-temps/401.bzip2.tar.xz | Bin 111940 -> 111408 bytes save-temps/403.gcc.tar.xz | Bin 3946680 -> 3961044 bytes save-temps/410.bwaves.tar.xz | Bin 19120 -> 19132 bytes save-temps/416.gamess.tar.xz | Bin 5721208 -> 5744652 bytes save-temps/429.mcf.tar.xz | Bin 39664 -> 39660 bytes save-temps/433.milc.tar.xz | Bin 191932 -> 191272 bytes save-temps/434.zeusmp.tar.xz | Bin 220964 -> 220760 bytes save-temps/435.gromacs.tar.xz | Bin 1151164 -> 1152768 bytes save-temps/436.cactusADM.tar.xz | Bin 829120 -> 830760 bytes save-temps/437.leslie3d.tar.xz | Bin 63236 -> 63232 bytes save-temps/444.namd.tar.xz | Bin 221912 -> 221652 bytes save-temps/445.gobmk.tar.xz | Bin 1910448 -> 1920268 bytes save-temps/447.dealII.tar.xz | Bin 7163040 -> 7329488 bytes save-temps/450.soplex.tar.xz | Bin 807968 -> 805784 bytes save-temps/453.povray.tar.xz | Bin 1643304 -> 1640868 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2 years, 11 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_gnu_cross_build/master-arm updated (e2ae0d4a6b0b -> 438645193e59)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/linux. from e2ae0d4a6b0b Merge tag 'hwmon-for-v5.16-rc7' of git://git.kernel.org/pu [...] adds 2d5446da5ace pinctrl: mediatek: fix global-out-of-bounds issue adds 266423e60ea1 pinctrl: bcm2835: Change init order for gpio hogs adds b67210cc217f pinctrl: stm32: consider the GPIO offset to expose all the [...] adds 438645193e59 Merge tag 'pinctrl-v5.16-3' of git://git.kernel.org/pub/sc [...] No new revisions were added by this update. Summary of changes: drivers/pinctrl/bcm/pinctrl-bcm2835.c | 29 +++++++++++++----------- drivers/pinctrl/mediatek/pinctrl-mtk-common-v2.c | 8 +++++-- drivers/pinctrl/stm32/pinctrl-stm32.c | 8 +++---- 3 files changed, 26 insertions(+), 19 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_cross_build/master-arm updated (826c9e3ab -> c39fc7adc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/base-artifacts. discards 826c9e3ab 0: update: binutils-gcc-linux-glibc-gdb-qemu: 7 new c39fc7adc 0: update: binutils-gcc-linux-glibc-gdb-qemu: 7 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (826c9e3ab) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_cross_build/master-a [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1536 -> 1552 bytes 02-prepare_abe/console.log.xz | Bin 2772 -> 2776 bytes 04-build_abe-binutils/console.log.xz | Bin 30180 -> 30100 bytes 05-build_abe-stage1/console.log.xz | Bin 89836 -> 89628 bytes 07-build_abe-linux/console.log.xz | Bin 8924 -> 9104 bytes 08-build_abe-glibc/console.log.xz | Bin 231052 -> 231048 bytes 09-build_abe-stage2/console.log.xz | Bin 216244 -> 216872 bytes 10-build_abe-gdb/console.log.xz | Bin 37796 -> 37896 bytes 11-build_abe-qemu/console.log.xz | Bin 29988 -> 29932 bytes 12-check_regression/console.log.xz | Bin 416 -> 416 bytes 13-update_baseline/console.log | 10 +++++----- jenkins/manifest.sh | 8 ++++---- 12 files changed, 9 insertions(+), 9 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Os_LTO updated (0489e891199a -> dabfefa49057)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Os_LTO in repository toolchain/ci/llvm-project. from 0489e891199a [DAGCombiner] Avoid combining adjacent stores at -O0 to im [...] adds 4126b0866213 [NFC][sanitizer] Format a part of the file adds 4316859e6a1d [NFC][sanitizer] Format the test adds 9f3aca7eaefe [sanitizer] Support symbolize_inline_frames by addr2line adds e48b1c8a27f0 [ELF] Make Partition members unique_ptr and remove associa [...] adds 12779edd7118 [libc] Add performance tests for hypotf and hypot. adds ba6973c89b01 [ELF] Change nonnull pointer parameters to references adds 856550ca79ba [Sanitizer] Fix setbuffer() interceptor (it accept size, n [...] adds ba948c5a9c52 [ELF] Use SmallVector for some global variables (*Files an [...] adds f66d602c3f58 [clang-format] Fix wrong indentation after trailing requir [...] adds d39d2acfdd9f [DFSan] Make dfsan_read_origin_of_first_taint public. adds ad26b0b233d5 Revert "[ELF] Make Partition/InStruct members unique_ptr a [...] adds 8043beb8901c [JSONNodeDumper] Do not print mangled names for local vari [...] adds 1201a0f3955b [OpenMP] Fix incorrect type when casting from uintptr adds 510d0e493365 [IR] Add memory attributes for init.trampoline adds 55861c9681dd [IR] Use default attributes for trampoline intrinsics adds f8042492fe2a [DSE] Regenerate test checks (NFC) adds 58ad3428d1d4 [DSE] Add test for matrix store (NFC) adds 5d0be553fafe [ELF] Optimize copyLocalSymbols. NFC adds f9607d45f399 Revert "Revert "[DwarfDebug] Support emitting function-loc [...] adds 61312fd5aa1e [ELF] sortSections: delete unneeded outSecOff assignment adds 33319dde2a4f [ELF] LTO: skip expensive usedStartStop initialization if [...] adds 09669e6c5fa1 [CodeGen] Avoid pointer element type access when creating LValue adds 74ce7ff5dc5b [AMDGPU] Remove a TODO that was done by D98081 adds fcc0964ed43e Revert "[libc++] Remove unused headers from <filesystem>" adds 1d50cf98b56f [libc++] IWYU in <filesystem> tests adds 53f0538181fd [CodeGen] Use correct element type for store to sret adds 23f1cd9e6357 [libc++] Remove unused headers from <filesystem> adds 368318bcce66 [C++20] [Coroutines] Mark imported module as imported if n [...] adds 1e2c31c66be7 Revert "[C++20] [Coroutines] Mark imported module as impor [...] adds 2810c3403e42 [VE] Add VE support to update_llc_test_checks adds 86b001a94172 [C++20] [Modules] Mark imported module as imported if not [...] adds 3d36da77020b [VE] Add manuals to CompilerWriterInfo adds d2863088ab89 GlobalISel: Regen vector mir tests, add tests for vector a [...] adds 29f88b93fdbe [GlobalISel] Rework more/fewer elements for vectors adds 2c7dc13146ba [CGBuilder] Add CreateGEP() overload that accepts an Address adds bf2b5551f919 [CodeGen] Use CreateConstInBoundsGEP() in one more place adds 7977fd7cfc5b [OpenMP] Remove no-op cast (NFC) adds a3f50fb06dd4 [X86] isVectorShiftByScalarCheap - vXi8 select(shift(x,spl [...] adds a9486a40f7d1 [RISCV] Disable interleaving scalar loops in the loop vectorizer. adds 0ff20f2f4448 [InstSimplify] Fold logic AND to zero adds 71fc4bbdd200 [X86][SSE] Add ISD::ROTR support adds 0045d01af96f [SPIR-V] Add a toolchain for SPIR-V in clang adds fd3cde600ba6 AMDGPU/GlobalISel: Fix attempt to select non-legal instr i [...] adds e70ef6d9245e [AArch64] Add a tablegen pattern for SQXTN2. adds b7b260e19a74 [RISCV] Support strict FP conversion operations. adds dfb20d4d19ec [libc++][format] Improve ABI stability. adds 7704c503ecb8 [RISCV] Use positive 0.0 for the neutral element in fadd r [...] adds e8b24ee1153f [libc++][format][NFC] Remove some unneeded headers. adds ab3640aa0e83 [ASan] Moved optimized callbacks into a separate library. adds f766bc093c8c [Hexagon] Introduce Hexagon v69 ISA adds 4c8becbeee18 [Hexagon] Add Hexagon v69 builtins to clang adds d45a24799899 [AMDGPU] Don't remove VGPR to AGPR dead spills from frame info adds 4bf31659fac7 Revert "[ASan] Moved optimized callbacks into a separate l [...] adds 4374824ccf6e [ELF] --gc-sections: combine two iterations over inputSections adds 5410152827cc [Bazel] Add target for llvm-tli-checker adds 1d1b5efdef49 [Hexagon] Driver/preprocessor options for Hexagon v69 adds 3e52096809eb [libc][NFC] fix variable name adds 9fe0d67c9a72 [sanitizer] Check kArgVMax in SymbolizerProcess::GetArgV adds a7ebf2010ebb [NFC][sanitizer] Increase kArgVMax to 16 adds eafc64ed6325 [Driver][test] Remove unneeded -no-canonical-prefixes and [...] adds f103ee2e9e3f [sanitizer] Move internal_symbolizer "inline" option adds bf45624ba07f [ELF][PPC32] Support .got2 in an output section description adds be8180af5854 [clang][driver] Warn when '-mno-outline-atomics' is used w [...] adds 8f8c89f3cd74 [mlir] Remove spurious debug guard adds 6842f52a0bbf [libc++] [test] Flatten the directory structure a bit. NFC. adds a2a9a5c7d3d9 [libc++] [ranges] Fix bugs in ranges::empty(). adds 4191a93ea448 [libc++] [test] Eliminate `== true` and `== false`. NFC. adds 3042091168e9 [libc++] [ranges] Whitespace and namespace-style adjustmen [...] adds 937b00ab2cf0 [Polly][SchedOpt] Account for prevectorization of multiple [...] adds 313de31fbb75 [mlir][tosa] Split tosa-to-linalg named ops out of pass adds 10b3675aa950 [RISCV][VP] Lower mask vector VP AND/OR/XOR to RVV instructions adds 5fd328c45f6d [gn build] (manually) port f103ee2e9e3fc (sanitizer_symbol [...] adds 5d68dc184ef6 [Verifier] Iteratively traverse all indirect users. adds 7cd7b4d2f807 [sanitizer] Add common "demangle" flag adds 81378f7e56d9 Revert "[DwarfDebug] Support emitting function-local decla [...] adds ee4bbb50ae58 [gn build] (manually) port 7cd7b4d2f807 (sanitizer_symboli [...] adds 464cc4c920a1 [ELF] Remove stale comment which was duplicated in MarkLiv [...] adds a67c0fc1fbe8 [Hexagon] Revamp HVX flag verification in driver adds 60509623c46e [libc][obvious] Fix style of MPFRWrapper. adds 8a26ba6a02f1 Load binary by UUID from qProcessInfo packet fields adds 735fe1da6b97 Revert "[mlir][tosa] Split tosa-to-linalg named ops out of pass" adds 71b3bfde9cd2 [ASan] Moved optimized callbacks into a separate library. adds 417cd2e5c5e0 [ELF] SymbolTable: change some vector<Symbol *> to SmallVector adds a6114ff0cd69 [gn build] "port" 71b3bfde9cd2 adds 8ff42766d1ef [mlir] Use thread-pool's notion of thread count instead of [...] adds a2baf634a1d7 [ELF] Simplify SymbolTable::insert. NFC adds 41a64338cc84 [mlir] Add getNumThreads to MLIRContext adds 1abbbc7b2435 [ELF] scanVersionScript: remove unused variable adds 0a35211b3488 [RISCV] Don't allow vector types to be used with inline as [...] adds a79c567f6a9a [NFC] Remove tailing whitespaces in llvm/include/llvm/Fron [...] adds 1d285f2de0b7 [ELF] Simplify and optimize ObjFile<ELFT>::parseLazy adds f3d4e168dbc7 [C++20] Conform coroutine's comments in clang (NFC-ish) adds b05df0287baf Revert "[DWARF] Fix PR51087 Extraneous enum record in DWAR [...] adds 02478a26f269 [RISCV] Use DAG variable directly instead of DCI.DAG adds 097208dbf077 [C++20] [Coroutines] Allow promise_type to not define retu [...] adds 0d749e13f714 [ELF] Optimize symbol initialization and resolution adds dd903173c0fb [OpenMP] Avoid creating null pointer lvalue (NFC) adds 69ffc3cee900 [Attributor] Directly call areTypesABICompatible() hook adds cb31a5710421 [DebugInfo] Remove type-units-maybe-unused-types.ll test adds ae64c5a0fde5 [DSE][MemLoc] Handle intrinsics more generically adds ba2b34b1c7d4 [DSE] Simplify isGuaranteedLoopInvariant() (NFC) adds ea2d4c588137 [GlobalISel] Fix -Wunused-function in -DLLVM_ENABLE_ASSERT [...] adds 81d69e1bda9e [DSE] Call isRemovable() after getLocForWriteEx() (NFCI) adds 2b8a703858ea [DSE] Avoid calling isRemovable() on non-analyzable locati [...] adds 034e66e76c6f [DSE] Assert analyzable write in isRemovable() (NFC) adds 24c68ea1eb4f Reland "[X86][MS-InlineAsm] Use exact conditions to recogn [...] adds 72d220178560 [DSE] Rename getLocForWriteEx() to getLocForWrite() (NFC) adds 90095a0b65bd [DSE] Remove unnecessary check in getLocForWrite() (NFC) adds eb91d91b7a8e [DSE] Fix typo in recent commit adds 969a51ff3632 Revert "[ASan] Moved optimized callbacks into a separate l [...] adds 3b4c040cca9d [gn build] Port 969a51ff3632 adds bb84dd81590b [AArch64] Add a tablegen pattern for RADDHN/RADDHN2. adds c7a589a2c4e2 [Clang][OpenMP] Add the support for atomic compare in parser adds 159da567378a [X86] Enable v32i16 ISD::ROTL/ROTR lowering on AVX512BW targets adds 286237962ad3 InstCombine: Gracefully handle more allocas in the wrong a [...] adds 8020458c5dc2 [AMDGPU] Changing S_AND_B32 to V_AND_B32_e64 in the diverg [...] adds d5dc3964a741 [DFAJumpThreading] Determinator BB should precede switch-d [...] adds dc8f9fb196da [Docs] Minor fix in clang user manual adds 6c0eaefaf832 [MLIR][FlatAffineConstraints][NFC] Move some static functi [...] adds 27a0718ad0a4 Revert "[MLIR][FlatAffineConstraints][NFC] Move some stati [...] adds 8ea64d5585ec [clang-format] Fix short enums getting wrapped even when denied adds e1b6b5be462e [ELF] Avoid referencing SectionBase::repl after ICF adds e694180033d1 [ELF] Optimize --wrap to only check non-local symbols adds 5e3403bd2203 [ELF] parseLazy: skip local symbols adds a9e8b1ee7fd4 [mlir] Fully qualify default types used in parser code adds d63016a86548 [CMake] Revert -Wl,-O3 adds 2709fd1520bc [MLIR][LLVM] Add MemmoveOp to LLVM Dialect adds b5a0f0f397c7 [ELF] Add ELFFileBase::{elfShdrs,numELFShdrs} to avoid dup [...] adds 745420d3f4b0 [ELF] Cache global variable `target` in relocate* adds 40fae4d8fcbd [ELF] Optimize replaceCommonSymbols adds a8cbddc99411 [CodeGen] Fix a memory leak adds 9c0a4227a9ca Use Optional::getValueOr (NFC) adds 62e48ed10f9d Use isa instead of dyn_cast (NFC) adds 76f0f1cc5c52 Use {DenseSet,SetVector,SmallPtrSet}::contains (NFC) adds 3cfe375ae431 Use StringRef::contains (NFC) adds cde37a7e5a1f [ELF][test] Add tests for mixed GD-to-IE and IE, mixed TLS [...] adds 70912420bbc3 [ELF] Move TLS dynamic relocations to postScanRelocations adds 2d303e678152 Remove redundant return and continue statements (NFC) adds 34558b039b3b [StaticAnalyzer] Remove redundant declaration isStdSmartPtr (NFC) adds d86e2cc2e37c [NFC] Method for evaluation of FCmpInst for constant operands adds 5b2e611b734c [MLIR][FlatAffineConstraints][NFC] Move some static functi [...] adds 46cdcf087300 [lldb] Add support for UTF-8 unicode formatting adds 0c553cc1af2e [MLIR] Add forgotten directory Support to unittests cmake adds dd4f5d4ae577 [ELF] De-template handleTlsRelocation. NFC adds a00f480fe8ee [ELF] scanReloc: remove unused start parameter. NFC adds 2bddab25dba8 DebugInfo: Don't hash DIE offsets before they're computed adds dabfefa49057 Fix clang-tidy performance-move-const-arg in DLTI Dialect (NFC) No new revisions were added by this update. Summary of changes: clang-tools-extra/clang-doc/Mapper.cpp | 2 +- clang-tools-extra/clang-doc/Serialize.cpp | 6 +- .../abseil/DurationFactoryScaleCheck.cpp | 1 - .../clang-tidy/android/CloexecCheck.cpp | 2 +- .../bugprone/ReservedIdentifierCheck.cpp | 2 +- .../llvmlibc/ImplementationInNamespaceCheck.cpp | 1 - .../clang-tidy/modernize/LoopConvertCheck.cpp | 2 +- .../clang-tidy/modernize/RawStringLiteralCheck.cpp | 2 +- .../readability/BracesAroundStatementsCheck.cpp | 2 +- .../clang-tidy/readability/NamedParameterCheck.cpp | 2 +- clang/docs/UsersManual.rst | 54 + clang/include/clang/APINotes/Types.h | 10 +- clang/include/clang/AST/AbstractBasicReader.h | 2 +- clang/include/clang/AST/DeclTemplate.h | 11 +- clang/include/clang/AST/OpenMPClause.h | 41 + clang/include/clang/AST/RecursiveASTVisitor.h | 5 + .../clang/Analysis/Analyses/ThreadSafetyCommon.h | 2 +- clang/include/clang/Basic/BuiltinsHexagon.def | 10 +- clang/include/clang/Basic/BuiltinsHexagonDep.def | 147 + clang/include/clang/Basic/DiagnosticDriverKinds.td | 16 +- clang/include/clang/Basic/DiagnosticSemaKinds.td | 4 +- clang/include/clang/Driver/Options.td | 14 + clang/include/clang/Driver/Tool.h | 1 + clang/include/clang/Driver/ToolChain.h | 3 + clang/include/clang/Sema/Sema.h | 3 + clang/lib/AST/ASTContext.cpp | 2 +- clang/lib/AST/JSONNodeDumper.cpp | 17 +- clang/lib/AST/OpenMPClause.cpp | 6 + clang/lib/AST/StmtProfile.cpp | 2 + clang/lib/ASTMatchers/Dynamic/Marshallers.h | 1 - clang/lib/ASTMatchers/Dynamic/Parser.cpp | 2 +- clang/lib/Analysis/CFG.cpp | 2 - clang/lib/Basic/OpenMPKinds.cpp | 2 + clang/lib/Basic/Targets/Hexagon.cpp | 9 +- clang/lib/Basic/Targets/PPC.cpp | 5 +- clang/lib/CodeGen/CGBuilder.h | 15 + clang/lib/CodeGen/CGCall.cpp | 15 +- clang/lib/CodeGen/CGCoroutine.cpp | 4 + clang/lib/CodeGen/CGExpr.cpp | 3 +- clang/lib/CodeGen/CGExprCXX.cpp | 9 +- clang/lib/CodeGen/CGObjC.cpp | 8 +- clang/lib/CodeGen/CGOpenMPRuntime.cpp | 72 +- clang/lib/CodeGen/CGOpenMPRuntime.h | 8 +- clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp | 14 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 16 +- clang/lib/CodeGen/CodeGenAction.cpp | 1 - clang/lib/CodeGen/CodeGenFunction.cpp | 4 +- clang/lib/Driver/Driver.cpp | 36 +- clang/lib/Driver/ToolChain.cpp | 2 +- clang/lib/Driver/ToolChains/Clang.cpp | 22 +- clang/lib/Driver/ToolChains/Clang.h | 7 +- clang/lib/Driver/ToolChains/HIPAMD.cpp | 1 - clang/lib/Driver/ToolChains/Hexagon.cpp | 131 +- clang/lib/Driver/ToolChains/SPIRV.cpp | 25 +- clang/lib/Driver/ToolChains/SPIRV.h | 33 + clang/lib/Format/UnwrappedLineFormatter.cpp | 9 +- clang/lib/Format/UnwrappedLineParser.cpp | 3 +- clang/lib/Frontend/CompilerInstance.cpp | 12 +- clang/lib/Headers/hexagon_protos.h | 11 - clang/lib/Headers/hexagon_types.h | 32 - clang/lib/Headers/hvx_hexagon_protos.h | 814 +- clang/lib/Parse/ParseOpenMP.cpp | 1 + clang/lib/Sema/SemaCUDA.cpp | 1 - clang/lib/Sema/SemaCodeComplete.cpp | 1 - clang/lib/Sema/SemaCoroutine.cpp | 178 +- clang/lib/Sema/SemaExprCXX.cpp | 2 +- clang/lib/Sema/SemaModule.cpp | 9 +- clang/lib/Sema/SemaOpenMP.cpp | 39 +- clang/lib/Sema/SemaType.cpp | 1 - clang/lib/Sema/TreeTransform.h | 7 + clang/lib/Serialization/ASTReader.cpp | 5 + clang/lib/Serialization/ASTWriter.cpp | 2 + clang/lib/StaticAnalyzer/Checkers/SmartPtr.h | 2 - clang/test/AST/ast-dump-decl-json.c | 5 - clang/test/AST/ast-dump-decl-json.m | 16 - clang/test/AST/ast-dump-expr-json.c | 10 - clang/test/AST/ast-dump-expr-json.cpp | 18 - clang/test/AST/ast-dump-expr-json.m | 9 - clang/test/AST/ast-dump-funcs-json.cpp | 4 - clang/test/AST/ast-dump-if-json.cpp | 2 - clang/test/AST/ast-dump-stmt-json.c | 81 +- clang/test/AST/ast-dump-stmt-json.cpp | 29 - clang/test/AST/ast-dump-stmt-json.m | 4 - clang/test/AST/ast-dump-template-decls-json.cpp | 1 - clang/test/CodeGen/ms-inline-asm-functions.c | 2 +- clang/test/Driver/hexagon-hvx-ieee-fp.c | 25 + clang/test/Driver/hexagon-hvx-qfloat.c | 25 + clang/test/Driver/hexagon-hvx.c | 303 +- clang/test/Driver/hexagon-toolchain-elf.c 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33 +- .../format.arg/arg_t.compile.pass.cpp | 38 + .../{range.access.begin => }/begin.pass.cpp | 0 .../range.access/{range.prim => }/data.pass.cpp | 0 .../range.access/{range.prim => }/empty.pass.cpp | 40 +- .../{range.access.end => }/end.pass.cpp | 0 .../range.access.cbegin/cbegin.compile.pass.cpp | 1 - .../range.access.cend/cend.compile.pass.cpp | 1 - .../range.access/{range.prim => }/size.pass.cpp | 0 .../range.access/{range.prim => }/ssize.pass.cpp | 0 lld/COFF/Driver.cpp | 2 +- lld/ELF/CallGraphSort.cpp | 4 +- lld/ELF/DWARF.cpp | 3 +- lld/ELF/Driver.cpp | 40 +- lld/ELF/ICF.cpp | 16 + lld/ELF/InputFiles.cpp | 159 +- lld/ELF/InputFiles.h | 40 +- lld/ELF/InputSection.cpp | 77 +- lld/ELF/InputSection.h | 19 +- lld/ELF/LTO.cpp | 2 + lld/ELF/LinkerScript.cpp | 4 +- lld/ELF/MarkLive.cpp | 76 +- lld/ELF/OutputSections.cpp | 2 +- lld/ELF/OutputSections.h | 2 +- lld/ELF/Relocations.cpp | 138 +- lld/ELF/SymbolTable.cpp | 22 +- lld/ELF/SymbolTable.h | 17 +- lld/ELF/Symbols.cpp | 7 +- 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llvm/lib/CodeGen/AsmPrinter/DIEHash.h | 2 + llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 234 +- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h | 6 - llvm/lib/CodeGen/GlobalISel/CallLowering.cpp | 36 +- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 1119 +- llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 48 +- llvm/lib/CodeGen/GlobalISel/Utils.cpp | 15 + llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 5 +- llvm/lib/DebugInfo/DWARF/DWARFDie.cpp | 2 - llvm/lib/DebugInfo/DWARF/DWARFUnit.cpp | 2 +- llvm/lib/IR/ConstantFold.cpp | 42 +- llvm/lib/IR/Instructions.cpp | 44 +- llvm/lib/IR/Verifier.cpp | 17 +- llvm/lib/MC/MachObjectWriter.cpp | 4 +- llvm/lib/Support/RISCVISAInfo.cpp | 2 +- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 54 + llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp | 1 - llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 53 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 21 +- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 12 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 2 - llvm/lib/Target/AMDGPU/SIInstructions.td | 13 +- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 7 + llvm/lib/Target/AMDGPU/VOPInstructions.td | 12 + llvm/lib/Target/AVR/AVRInstrInfo.cpp | 2 - llvm/lib/Target/Hexagon/Hexagon.td | 55 +- llvm/lib/Target/Hexagon/HexagonDepArch.h | 34 +- llvm/lib/Target/Hexagon/HexagonDepArch.td | 2 + llvm/lib/Target/Hexagon/HexagonDepDecoders.inc | 1 + llvm/lib/Target/Hexagon/HexagonDepIICHVX.td | 1020 +- llvm/lib/Target/Hexagon/HexagonDepIICScalar.td | 768 ++ llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td | 14 + llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td | 1253 +- llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td | 293 +- llvm/lib/Target/Hexagon/HexagonDepMappings.td | 1 - llvm/lib/Target/Hexagon/HexagonInstrFormats.td | 7 +- llvm/lib/Target/Hexagon/HexagonPseudo.td | 11 + llvm/lib/Target/Hexagon/HexagonSchedule.td | 1 + llvm/lib/Target/Hexagon/HexagonScheduleV69.td | 40 + llvm/lib/Target/Hexagon/HexagonSubtarget.cpp | 72 +- llvm/lib/Target/Hexagon/HexagonSubtarget.h | 25 +- .../Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h | 5 +- .../Hexagon/MCTargetDesc/HexagonMCChecker.cpp | 38 +- .../Target/Hexagon/MCTargetDesc/HexagonMCChecker.h | 1 + .../Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp | 18 +- .../Hexagon/MCTargetDesc/HexagonMCInstrInfo.h | 4 +- .../Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp | 32 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 121 +- llvm/lib/Target/RISCV/RISCVISelLowering.h | 7 + llvm/lib/Target/RISCV/RISCVInstrInfoD.td | 28 +- llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 50 +- llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td | 32 +- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h | 4 +- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 3 +- llvm/lib/Target/X86/AsmParser/X86Operand.h | 7 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 115 +- llvm/lib/Transforms/IPO/AttributorAttributes.cpp | 34 +- .../Transforms/InstCombine/InstCombineCasts.cpp | 2 +- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 17 +- llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp | 58 +- .../lib/Transforms/Scalar/DeadStoreElimination.cpp | 151 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 4 +- .../CodeGen/AArch64/GlobalISel/arm64-fallback.ll | 8 - .../AArch64/GlobalISel/call-lowering-vectors.ll | 68 +- .../AArch64/GlobalISel/legalize-saddsat.mir | 258 +- .../AArch64/GlobalISel/legalize-shuffle-vector.mir | 211 +- .../AArch64/GlobalISel/legalize-ssubsat.mir | 258 +- llvm/test/CodeGen/AArch64/arm64-raddhn-combine.ll | 48 + llvm/test/CodeGen/AArch64/arm64-sqxtn2-combine.ll | 37 + llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll | 34 +- .../GlobalISel/artifact-combiner-extract.mir | 9 +- .../artifact-combiner-unmerge-values.mir | 2 +- .../AMDGPU/GlobalISel/artifact-combiner-zext.mir | 16 +- ...bug-legalization-artifact-combiner-dead-def.mir | 20 +- .../AMDGPU/GlobalISel/combine-fma-add-mul.ll | 176 +- .../CodeGen/AMDGPU/GlobalISel/function-returns.ll | 2029 +-- .../AMDGPU/GlobalISel/insertelement.large.ll | 12 +- .../AMDGPU/GlobalISel/inst-select-extract.mir | 153 - .../AMDGPU/GlobalISel/inst-select-fract.f64.mir | 6 +- .../AMDGPU/GlobalISel/inst-select-insert.mir | 39 - .../AMDGPU/GlobalISel/inst-select-insert.xfail.mir | 39 - .../GlobalISel/irtranslator-call-return-values.ll | 16 +- .../CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll | 194 +- .../GlobalISel/irtranslator-function-args.ll | 40 +- .../AMDGPU/GlobalISel/irtranslator-sibling-call.ll | 17 +- .../CodeGen/AMDGPU/GlobalISel/legalize-and.mir | 633 +- .../CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir | 5 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir | 104 +- .../CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir | 3449 ++--- .../AMDGPU/GlobalISel/legalize-concat-vectors.mir | 2 +- .../GlobalISel/legalize-extract-vector-elt.mir | 314 +- .../CodeGen/AMDGPU/GlobalISel/legalize-extract.mir | 218 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir | 55 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir | 16 +- .../AMDGPU/GlobalISel/legalize-fcanonicalize.mir | 8 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir | 8 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir | 3984 +++--- .../CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir | 270 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir | 588 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fma.mir | 994 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir | 1158 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir | 1158 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir | 16 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir | 8 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir | 140 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir | 1811 +-- .../CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir | 2448 ++-- .../CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir | 8 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir | 510 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir | 8 +- .../AMDGPU/GlobalISel/legalize-implicit-def.mir | 231 +- .../GlobalISel/legalize-insert-vector-elt.mir | 79 +- .../CodeGen/AMDGPU/GlobalISel/legalize-insert.mir | 578 +- .../AMDGPU/GlobalISel/legalize-intrinsic-round.mir | 1840 +-- .../AMDGPU/GlobalISel/legalize-inttoptr.mir | 2 +- .../legalize-llvm.amdgcn.image.load.2d.d16.ll | 2684 ++-- .../legalize-llvm.amdgcn.image.load.2d.ll | 2 +- .../legalize-llvm.amdgcn.image.store.2d.d16.ll | 690 +- .../legalize-llvm.amdgcn.s.buffer.load.mir | 175 +- .../GlobalISel/legalize-load-constant-32bit.mir | 2 +- .../AMDGPU/GlobalISel/legalize-load-constant.mir | 105 +- .../AMDGPU/GlobalISel/legalize-load-flat.mir | 110 +- .../AMDGPU/GlobalISel/legalize-load-global.mir | 1016 +- .../AMDGPU/GlobalISel/legalize-load-local.mir | 64 +- .../AMDGPU/GlobalISel/legalize-load-private.mir | 24 +- .../CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir | 216 +- .../test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir | 567 +- .../CodeGen/AMDGPU/GlobalISel/legalize-phi.mir | 1678 +-- .../CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir | 530 +- .../CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir | 1704 ++- .../CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir | 8 +- .../CodeGen/AMDGPU/GlobalISel/legalize-select.mir | 115 +- .../AMDGPU/GlobalISel/legalize-sext-inreg.mir | 10 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sext.mir | 5 +- .../CodeGen/AMDGPU/GlobalISel/legalize-shl.mir | 104 +- .../AMDGPU/GlobalISel/legalize-shuffle-vector.mir | 104 +- .../GlobalISel/legalize-shuffle-vector.s16.mir | 108 +- .../CodeGen/AMDGPU/GlobalISel/legalize-smax.mir | 622 +- .../CodeGen/AMDGPU/GlobalISel/legalize-smin.mir | 622 +- .../CodeGen/AMDGPU/GlobalISel/legalize-srem.mir | 8 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir | 1808 ++- .../CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir | 530 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir | 1704 ++- .../AMDGPU/GlobalISel/legalize-store-global.mir | 1192 +- .../CodeGen/AMDGPU/GlobalISel/legalize-store.mir | 16 +- .../CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir | 414 +- .../CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir | 1106 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/legalize-umax.mir | 632 +- .../CodeGen/AMDGPU/GlobalISel/legalize-umin.mir | 632 +- .../CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir | 1084 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir | 1436 +-- .../CodeGen/AMDGPU/GlobalISel/legalize-usube.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir | 456 +- .../CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir | 1054 +- .../GlobalISel/legalize-vector-args-gfx7.mir | 355 + .../GlobalISel/legalize-vector-args-gfx8-plus.mir | 477 + .../CodeGen/AMDGPU/GlobalISel/legalize-xor.mir | 277 +- .../CodeGen/AMDGPU/GlobalISel/legalize-zext.mir | 41 +- .../GlobalISel/llvm.amdgcn.image.load.1d.d16.ll | 27 +- .../AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll | 8119 ++++++------ .../CodeGen/AMDGPU/GlobalISel/load-constant.96.ll | 64 +- .../regbankselect-amdgcn.s.buffer.load.ll | 5042 ++++---- .../AMDGPU/GlobalISel/regbankselect-load.mir | 382 +- .../regbankselect-split-scalar-load-metadata.mir | 30 +- llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll | 946 +- llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll | 910 +- llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll | 509 +- .../AMDGPU/divergence-driven-trunc-to-i1.ll | 59 + llvm/test/CodeGen/AMDGPU/fp-min-max-atomics.ll | 33 +- llvm/test/CodeGen/AMDGPU/lds-atomic-fmin-fmax.ll | 188 +- llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir | 88 + llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll | 15 +- .../test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll | 4 +- .../test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll | 4 +- llvm/test/CodeGen/RISCV/double-convert-strict.ll | 850 ++ llvm/test/CodeGen/RISCV/float-convert-strict.ll | 719 ++ llvm/test/CodeGen/RISCV/half-convert-strict.ll | 712 + llvm/test/CodeGen/RISCV/inline-asm-invalid.ll | 12 + .../CodeGen/RISCV/rv64d-double-convert-strict.ll | 134 + .../CodeGen/RISCV/rv64f-float-convert-strict.ll | 134 + .../CodeGen/RISCV/rv64f-half-convert-strict.ll | 123 + .../CodeGen/RISCV/rvv/fixed-vectors-marith-vp.ll | 269 + .../RISCV/rvv/fixed-vectors-reduction-fp.ll | 17 + llvm/test/CodeGen/RISCV/rvv/marith-vp.ll | 437 + .../CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll | 14 + llvm/test/CodeGen/X86/funnel-shift-rot.ll | 6 +- llvm/test/CodeGen/X86/vector-fshl-rot-512.ll | 52 +- llvm/test/CodeGen/X86/vector-fshr-rot-128.ll | 130 +- llvm/test/CodeGen/X86/vector-fshr-rot-256.ll | 93 +- llvm/test/CodeGen/X86/vector-fshr-rot-512.ll | 166 +- llvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll | 6 +- llvm/test/CodeGen/X86/vector-rotate-512.ll | 28 +- llvm/test/DebugInfo/AMDGPU/variable-locations.ll | 31 +- llvm/test/DebugInfo/BPF/extern-void.ll | 3 +- .../Generic/cross-cu-linkonce-distinct.ll | 10 +- .../DebugInfo/Generic/debug-info-qualifiers.ll | 4 - .../DebugInfo/Generic/debug-names-linkage-name.ll | 2 +- llvm/test/DebugInfo/Generic/enum-types.ll | 6 +- .../Generic/incorrect-variable-debugloc.ll | 3 - llvm/test/DebugInfo/Generic/namespace.ll | 36 +- llvm/test/DebugInfo/Generic/varargs.ll | 12 +- .../MIR/AArch64/implicit-def-dead-scope.mir | 2 +- llvm/test/DebugInfo/NVPTX/debug-addr-class.ll | 154 +- llvm/test/DebugInfo/NVPTX/debug-info.ll | 12876 +++++++++---------- llvm/test/DebugInfo/NVPTX/debug-loc-offset.ll | 154 +- llvm/test/DebugInfo/PowerPC/strict-dwarf.ll | 4 +- .../DebugInfo/X86/2011-09-26-GlobalVarContext.ll | 12 +- .../test/DebugInfo/X86/DW_AT_calling-convention.ll | 8 +- llvm/test/DebugInfo/X86/align_cpp11.ll | 30 +- llvm/test/DebugInfo/X86/align_objc.ll | 13 +- llvm/test/DebugInfo/X86/arange-and-stub.ll | 2 +- .../X86/containing-type-extension-rust.ll | 1 - llvm/test/DebugInfo/X86/convert-loclist.ll | 2 +- llvm/test/DebugInfo/X86/debug-info-access.ll | 8 +- llvm/test/DebugInfo/X86/debug-info-blocks.ll | 8 +- .../test/DebugInfo/X86/debug-info-static-member.ll | 4 - llvm/test/DebugInfo/X86/debug-loc-offset.mir | 31 +- llvm/test/DebugInfo/X86/dwarf-aranges.ll | 12 +- llvm/test/DebugInfo/X86/dwarf-linkage-names.ll | 4 +- .../X86/dwarfdump-DIImportedEntity_elements.ll | 14 +- llvm/test/DebugInfo/X86/generate-odr-hash.ll | 18 +- llvm/test/DebugInfo/X86/gnu-public-names.ll | 43 +- .../DebugInfo/X86/lexical-block-file-inline.ll | 5 + llvm/test/DebugInfo/X86/linkage-name.ll | 2 +- llvm/test/DebugInfo/X86/namelist1.ll | 5 +- llvm/test/DebugInfo/X86/sret.ll | 4 +- llvm/test/DebugInfo/X86/subprogram-across-cus.ll | 6 +- llvm/test/DebugInfo/X86/template.ll | 33 +- llvm/test/DebugInfo/X86/tls.ll | 37 +- .../DebugInfo/X86/type-units-maybe-unused-types.ll | 133 - llvm/test/DebugInfo/X86/vla-global.ll | 3 - llvm/test/DebugInfo/attr-btf_tag.ll | 71 +- llvm/test/MC/WebAssembly/debug-info.ll | 22 +- llvm/test/MC/WebAssembly/debug-info64.ll | 22 +- llvm/test/MC/WebAssembly/dwarfdump.ll | 86 +- llvm/test/MC/WebAssembly/dwarfdump64.ll | 40 +- .../CodeGenPrepare/X86/vec-shift-inseltpoison.ll | 54 +- .../Transforms/CodeGenPrepare/X86/vec-shift.ll | 49 +- .../X86/x86-shuffle-sink-inseltpoison.ll | 36 +- .../CodeGenPrepare/X86/x86-shuffle-sink.ll | 36 +- .../dfa-jump-threading-analysis.ll | 14 +- .../DeadStoreElimination/invariant.start.ll | 29 +- .../test/Transforms/DeadStoreElimination/simple.ll | 16 +- .../stores-of-existing-values.ll | 24 + .../InstCombine/alloca-in-non-alloca-as.ll | 27 +- llvm/test/Transforms/InstSimplify/and.ll | 115 +- .../RISCV/unroll-in-loop-vectorizer.ll | 43 + .../CodeGen/GlobalISel/LegalizerHelperTest.cpp | 175 +- llvm/unittests/IR/VerifierTest.cpp | 14 +- llvm/utils/UpdateTestChecks/asm.py | 18 + .../gn/secondary/compiler-rt/lib/asan/BUILD.gn | 11 +- .../gn/secondary/compiler-rt/lib/tsan/rtl/BUILD.gn | 2 + mlir/include/mlir/Analysis/AffineStructures.h | 20 +- .../mlir/Analysis/Presburger/IntegerPolyhedron.h | 10 + mlir/include/mlir/Analysis/Presburger/Utils.h | 40 + mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 4 + mlir/include/mlir/IR/MLIRContext.h | 7 + mlir/include/mlir/Support/DebugAction.h | 3 +- mlir/lib/Analysis/AffineStructures.cpp | 231 +- mlir/lib/Analysis/Presburger/CMakeLists.txt | 2 + mlir/lib/Analysis/Presburger/IntegerPolyhedron.cpp | 54 + mlir/lib/Analysis/Presburger/Utils.cpp | 155 + mlir/lib/Dialect/DLTI/DLTI.cpp | 2 +- mlir/lib/IR/MLIRContext.cpp | 10 + mlir/lib/Transforms/Inliner.cpp | 11 +- .../Utils/GreedyPatternRewriteDriver.cpp | 5 - mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir | 8 + mlir/test/Transforms/inlining.mlir | 1 + mlir/tools/mlir-tblgen/OpFormatGen.cpp | 6 +- mlir/unittests/CMakeLists.txt | 1 + mlir/unittests/Support/CMakeLists.txt | 2 +- polly/include/polly/ScheduleTreeTransform.h | 33 + polly/lib/CodeGen/IslAst.cpp | 2 +- polly/lib/External/isl/isl_int_sioimath.h | 1 - polly/lib/Support/SCEVValidator.cpp | 2 +- polly/lib/Transform/ManualOptimizer.cpp | 1 - polly/lib/Transform/ScheduleOptimizer.cpp | 34 +- polly/lib/Transform/ScheduleTreeTransform.cpp | 29 - polly/lib/Transform/ScopInliner.cpp | 2 +- .../focaltech_test_detail_threshold-7bc17e.ll | 12 +- ...-gen-vivid_vbi_gen_sliced-before-llvmreduced.ll | 45 + utils/bazel/llvm-project-overlay/llvm/BUILD.bazel | 39 + 596 files changed, 58678 insertions(+), 47025 deletions(-) create mode 100644 clang/test/Driver/hexagon-hvx-ieee-fp.c create mode 100644 clang/test/Driver/hexagon-hvx-qfloat.c create mode 100644 clang/test/Driver/spirv-toolchain.cl create mode 100644 clang/test/Driver/unsupported-outline-atomics.c create mode 100644 compiler-rt/test/dfsan/origin_of_first_taint.c create mode 100644 compiler-rt/test/sanitizer_common/TestCases/symbolize_pc_demangle.cpp create mode 100644 libc/test/src/math/differential_testing/BinaryOpSingleOutputDiff.h create mode 100644 libc/test/src/math/differential_testing/hypot_perf.cpp create mode 100644 libc/test/src/math/differential_testing/hypotf_perf.cpp create mode 100644 libcxx/test/libcxx/utilities/format/format.arguments/format.arg [...] rename libcxx/test/std/ranges/range.access/{range.access.begin => }/begin.pass.cpp (100%) rename libcxx/test/std/ranges/range.access/{range.prim => }/data.pass.cpp (100%) rename libcxx/test/std/ranges/range.access/{range.prim => }/empty.pass.cpp (85%) rename libcxx/test/std/ranges/range.access/{range.access.end => }/end.pass.cpp (100%) delete mode 100644 libcxx/test/std/ranges/range.access/range.access.cbegin/cbegin. [...] delete mode 100644 libcxx/test/std/ranges/range.access/range.access.cend/cend.comp [...] rename libcxx/test/std/ranges/range.access/{range.prim => }/size.pass.cpp (100%) rename libcxx/test/std/ranges/range.access/{range.prim => }/ssize.pass.cpp (100%) create mode 100644 lld/test/ELF/linkerscript/ppc32-got2.s create mode 100644 lld/test/ELF/x86-64-tlsdesc-gd-mixed.s create mode 100644 llvm/lib/Target/Hexagon/HexagonScheduleV69.td create mode 100644 llvm/test/CodeGen/AArch64/arm64-raddhn-combine.ll create mode 100644 llvm/test/CodeGen/AArch64/arm64-sqxtn2-combine.ll delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.xfail.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir create mode 100644 llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll create mode 100644 llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir create mode 100644 llvm/test/CodeGen/RISCV/double-convert-strict.ll create mode 100644 llvm/test/CodeGen/RISCV/float-convert-strict.ll create mode 100644 llvm/test/CodeGen/RISCV/half-convert-strict.ll create mode 100644 llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll create mode 100644 llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll create mode 100644 llvm/test/CodeGen/RISCV/rv64f-half-convert-strict.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-marith-vp.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/marith-vp.ll delete mode 100644 llvm/test/DebugInfo/X86/type-units-maybe-unused-types.ll create mode 100644 llvm/test/Transforms/LoopVectorize/RISCV/unroll-in-loop-vectorizer.ll create mode 100644 mlir/include/mlir/Analysis/Presburger/Utils.h create mode 100644 mlir/lib/Analysis/Presburger/Utils.cpp create mode 100644 polly/test/ScheduleOptimizer/vivid-vbi-gen-vivid_vbi_gen_sliced [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Os_LTO updated (f20f980c71 -> 268d812c19)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Os_LTO in repository toolchain/ci/glibc. from f20f980c71 x86-64: Add vector acos/acosf implementation to libmvec adds cd0c333d2e elf: Remove unused NEED_DL_BASE_ADDR and _dl_base_addr adds 9702a7901e stdio: Implement %#m for vfprintf and related functions adds a4b4131355 Set default __TIMESIZE default to 64 adds 6e30181b4a math: Properly cast X_TLOSS to float [BZ #28713] adds 268d812c19 elf: Remove AArch64 from comment for AT_MINSIGSTKSZ No new revisions were added by this update. Summary of changes: NEWS | 3 + bits/timesize.h | 4 +- elf/dl-sysdep.c | 8 -- elf/elf.h | 3 +- manual/stdio.texi | 8 +- math/math-svid-compat.h | 2 + math/w_j0f_compat.c | 5 +- math/w_j1f_compat.c | 5 +- math/w_jnf_compat.c | 5 +- stdio-common/Makefile | 4 +- stdio-common/tst-sprintf-errno.c | 93 ++++++++++++++++++++++ stdio-common/vfprintf-internal.c | 25 ++++-- .../sysv/linux/arc => mach/hurd}/bits/timesize.h | 11 ++- .../unix/sysv/linux/arm/bits}/timesize.h | 8 +- .../unix/sysv/linux/csky/bits}/timesize.h | 8 +- .../unix/sysv/linux/hppa/bits}/timesize.h | 8 +- .../unix/sysv/linux/m68k/bits}/timesize.h | 8 +- .../unix/sysv/linux/microblaze/bits}/timesize.h | 8 +- .../unix/sysv/linux/mips/bits}/timesize.h | 12 +-- .../sysv/linux/{riscv => nios2}/bits/timesize.h | 10 +-- .../sysv/linux/powerpc/powerpc32/bits}/timesize.h | 8 +- .../unix/sysv/linux/s390/s390-32/bits}/timesize.h | 8 +- .../unix/sysv/linux/sh/bits}/timesize.h | 8 +- .../unix/sysv/linux/sparc/sparc32/bits}/timesize.h | 8 +- sysdeps/unix/sysv/linux/x86/bits/timesize.h | 2 + 25 files changed, 183 insertions(+), 89 deletions(-) create mode 100644 stdio-common/tst-sprintf-errno.c rename sysdeps/{unix/sysv/linux/arc => mach/hurd}/bits/timesize.h (74%) copy {bits => sysdeps/unix/sysv/linux/arm/bits}/timesize.h (81%) copy {bits => sysdeps/unix/sysv/linux/csky/bits}/timesize.h (81%) copy {bits => sysdeps/unix/sysv/linux/hppa/bits}/timesize.h (81%) copy {bits => sysdeps/unix/sysv/linux/m68k/bits}/timesize.h (81%) copy {bits => sysdeps/unix/sysv/linux/microblaze/bits}/timesize.h (81%) copy {bits => sysdeps/unix/sysv/linux/mips/bits}/timesize.h (79%) rename sysdeps/unix/sysv/linux/{riscv => nios2}/bits/timesize.h (77%) copy {bits => sysdeps/unix/sysv/linux/powerpc/powerpc32/bits}/timesize.h (81%) copy {bits => sysdeps/unix/sysv/linux/s390/s390-32/bits}/timesize.h (81%) copy {bits => sysdeps/unix/sysv/linux/sh/bits}/timesize.h (81%) copy {bits => sysdeps/unix/sysv/linux/sparc/sparc32/bits}/timesize.h (81%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Os_LTO updated (9f9bc0bf0d6 -> 10ae9946dce)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Os_LTO in repository toolchain/ci/gcc. from 9f9bc0bf0d6 Daily bump. adds 1a7ce857099 Combine vpcmpuw + zero_extend to vpcmpuw. adds 9ac0730c25b Fix typo in type verification. adds 61e53698a08 i386: Enable intrinsics that convert float and bf16 data to [...] adds ef26c151c14 x86: PR target/103773: Fix wrong-code with -Oz from pop to memory. adds 8f34344ec69 smuldi3_highpart.c: Replace long with long long for -mx32 adds 7d01da81b80 Daily bump. adds 9a4a29eaf23 Darwin: Define OBJECT_FORMAT_MACHO. adds 8381075ff3f Darwin: Check for that flag-reorder-and-partition. adds 19bf83a9a06 Darwin: Update rules for handling alignment of globals. adds 43dadcf3e7b Darwin: Amend a comment to be more inclusive [NFC]. adds 8f921393e33 i386: Add V2SFmode DIV insn pattern [PR95046, PR103797] adds ffb5418fb79 Daily bump. adds 4ae906e46c4 Fortran: simplify library code for integer-to-decimal conversion adds 10ae9946dce Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 84 ++++ gcc/DATESTAMP | 2 +- gcc/config.gcc | 14 + gcc/config/darwin.c | 24 +- gcc/config/darwin.h | 11 +- gcc/config/i386/avx512bf16intrin.h | 36 ++ gcc/config/i386/avx512bf16vlintrin.h | 63 +++ gcc/config/i386/i386.md | 62 ++- gcc/config/i386/mmx.md | 20 + gcc/config/i386/sse.md | 275 ++++++++++++ gcc/testsuite/ChangeLog | 42 ++ gcc/testsuite/gcc.dg/attr-aligned.c | 8 +- gcc/testsuite/gcc.dg/darwin-aligned-globals.c | 24 ++ gcc/testsuite/gcc.dg/darwin-comm-1.c | 5 + .../gcc.target/i386/avx512bf16-cvtsbh2ss-1.c | 15 + .../gcc.target/i386/avx512bf16-vcvtpbh2ps-1.c | 20 + .../gcc.target/i386/avx512bf16vl-cvtness2sbh-1.c | 14 + .../gcc.target/i386/avx512bf16vl-vcvtpbh2ps-1.c | 29 ++ .../gcc.target/i386/avx512bw-pr103750-1.c | 154 +++++++ .../gcc.target/i386/avx512bw-pr103750-2.c | 173 ++++++++ gcc/testsuite/gcc.target/i386/avx512f-pr103750-1.c | 426 ++++++++++++++++++ gcc/testsuite/gcc.target/i386/avx512f-pr103750-2.c | 478 +++++++++++++++++++++ .../gcc.target/i386/avx512fp16-pr103750-1.c | 58 +++ .../gcc.target/i386/avx512fp16-pr103750-2.c | 71 +++ gcc/testsuite/gcc.target/i386/pr103773-2.c | 19 + gcc/testsuite/gcc.target/i386/pr103773.c | 12 + gcc/testsuite/gcc.target/i386/pr89261.c | 3 +- gcc/testsuite/gcc.target/i386/pr95046-1.c | 11 +- gcc/testsuite/gcc.target/i386/smuldi3_highpart.c | 2 +- gcc/tree.c | 2 +- libgfortran/ChangeLog | 18 + libgfortran/io/write.c | 70 ++- libgfortran/libgfortran.h | 7 +- libgfortran/runtime/backtrace.c | 1 + libgfortran/runtime/error.c | 31 -- libgfortran/runtime/string.c | 39 +- 36 files changed, 2204 insertions(+), 119 deletions(-) create mode 100644 gcc/testsuite/gcc.dg/darwin-aligned-globals.c create mode 100644 gcc/testsuite/gcc.dg/darwin-comm-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512bf16-cvtsbh2ss-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512bf16-vcvtpbh2ps-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512bf16vl-cvtness2sbh-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512bf16vl-vcvtpbh2ps-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512bw-pr103750-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512bw-pr103750-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-pr103750-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-pr103750-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-pr103750-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-pr103750-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr103773-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr103773.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Os_LTO updated (7898f55ba0 -> d16ce6240e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_llvm_apm/llvm-master-arm-spec2k6-Os_LTO in repository toolchain/ci/binutils-gdb. from 7898f55ba0 Automatic date update in version.in adds 391c90eea5 gdb: make use of SCOPE_EXIT to manage thread executing state adds b1718fcdd1 gdb: on x86-64 non-trivial C++ objects are returned in memory adds b622494ee3 gdb/remote: handle attach when stop packet lacks thread-id adds b6846ba57b gdb/testsuite: resolve some duplicate testnames in gdb.mi adds d20236e748 Automatic date update in version.in adds 5c3ffbc4dd RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implement [...] adds a63375ac33 RISC-V: Hypervisor ext: support Privileged Spec 1.12 adds b6a08665ff RISC-V: Rewrite the csr testcases. adds 34b965f7c0 Move gdb_bfd_errmsg to gdb_bfd.c adds 64b7cc507b Remove gdb_print_host_address adds 5436dda805 Automatic date update in version.in adds d16ce6240e Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/cpu-riscv.c | 1 + bfd/cpu-riscv.h | 1 + bfd/version.h | 2 +- gas/config/tc-riscv.c | 10 +- gas/testsuite/gas/riscv/csr-dw-regnums.d | 10 - gas/testsuite/gas/riscv/csr-dw-regnums.s | 10 - gas/testsuite/gas/riscv/csr-fail-nonexistent.d | 3 + ...g-fail-nonexistent.l => csr-fail-nonexistent.l} | 0 ...g-fail-nonexistent.s => csr-fail-nonexistent.s} | 0 ...pseudo-noalias.d => csr-insns-pseudo-noalias.d} | 2 +- .../{priv-reg-pseudo.d => csr-insns-pseudo.d} | 2 +- .../{priv-reg-pseudo.s => csr-insns-pseudo.s} | 0 gas/testsuite/gas/riscv/csr-insns-read-only.d | 3 + ...g-fail-read-only-02.l => csr-insns-read-only.l} | 0 ...g-fail-read-only-02.s => csr-insns-read-only.s} | 0 gas/testsuite/gas/riscv/csr-version-1p10.d | 573 +++++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p10.l | 309 +++++++++++ gas/testsuite/gas/riscv/csr-version-1p11.d | 573 +++++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p11.l | 307 +++++++++++ gas/testsuite/gas/riscv/csr-version-1p12.d | 573 +++++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p12.l | 255 +++++++++ gas/testsuite/gas/riscv/csr-version-1p9p1.d | 573 +++++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p9p1.l | 335 ++++++++++++ gas/testsuite/gas/riscv/{priv-reg.s => csr.s} | 74 ++- gas/testsuite/gas/riscv/h-ext-32.d | 30 ++ gas/testsuite/gas/riscv/h-ext-32.s | 21 + gas/testsuite/gas/riscv/h-ext-64.d | 33 ++ gas/testsuite/gas/riscv/h-ext-64.s | 24 + gas/testsuite/gas/riscv/priv-reg-fail-fext.d | 3 - gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 - .../gas/riscv/priv-reg-fail-nonexistent.d | 3 - .../gas/riscv/priv-reg-fail-read-only-01.d | 3 - .../gas/riscv/priv-reg-fail-read-only-01.l | 71 --- .../gas/riscv/priv-reg-fail-read-only-01.s | 269 ---------- .../gas/riscv/priv-reg-fail-read-only-02.d | 3 - gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d | 3 - gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 68 --- .../gas/riscv/priv-reg-fail-version-1p10.d | 11 - .../gas/riscv/priv-reg-fail-version-1p10.l | 25 - .../gas/riscv/priv-reg-fail-version-1p11.d | 11 - .../gas/riscv/priv-reg-fail-version-1p11.l | 24 - .../gas/riscv/priv-reg-fail-version-1p9p1.d | 12 - .../gas/riscv/priv-reg-fail-version-1p9p1.l | 28 - gas/testsuite/gas/riscv/priv-reg-fail-zkr.d | 3 - gas/testsuite/gas/riscv/priv-reg-fail-zkr.l | 4 - gas/testsuite/gas/riscv/priv-reg-version-1p10.d | 275 ---------- gas/testsuite/gas/riscv/priv-reg-version-1p11.d | 275 ---------- gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d | 275 ---------- gdb/amd64-tdep.c | 16 +- gdb/dummy-frame.c | 12 +- gdb/gdb_bfd.c | 30 ++ gdb/gdb_bfd.h | 7 + gdb/gdbtypes.c | 161 +++--- gdb/psymtab.c | 46 +- gdb/record-btrace.c | 24 +- gdb/record-full.c | 8 +- gdb/remote.c | 31 +- gdb/symmisc.c | 48 +- gdb/testsuite/gdb.cp/non-trivial-retval.cc | 19 +- gdb/testsuite/gdb.cp/non-trivial-retval.exp | 26 + gdb/testsuite/gdb.mi/mi-syn-frame.exp | 12 +- gdb/testsuite/gdb.mi/mi-var-child.exp | 10 +- gdb/testsuite/gdb.mi/mi-var-rtti.cc | 48 +- gdb/testsuite/gdb.mi/mi-watch.exp | 2 +- gdb/testsuite/gdb.mi/mi2-amd64-entry-value.exp | 236 +++++---- gdb/testsuite/gdb.mi/mi2-var-child.exp | 10 +- gdb/testsuite/gdb.server/ext-attach.exp | 98 ++-- gdb/utils.c | 36 -- gdb/utils.h | 14 - include/opcode/riscv-opc.h | 120 ++++- opcodes/riscv-opc.c | 21 + 71 files changed, 4259 insertions(+), 1872 deletions(-) create mode 100644 gas/testsuite/gas/riscv/csr-fail-nonexistent.d rename gas/testsuite/gas/riscv/{priv-reg-fail-nonexistent.l => csr-fail-nonexisten [...] rename gas/testsuite/gas/riscv/{priv-reg-fail-nonexistent.s => csr-fail-nonexisten [...] rename gas/testsuite/gas/riscv/{priv-reg-pseudo-noalias.d => csr-insns-pseudo-noal [...] rename gas/testsuite/gas/riscv/{priv-reg-pseudo.d => csr-insns-pseudo.d} (98%) rename gas/testsuite/gas/riscv/{priv-reg-pseudo.s => csr-insns-pseudo.s} (100%) create mode 100644 gas/testsuite/gas/riscv/csr-insns-read-only.d rename gas/testsuite/gas/riscv/{priv-reg-fail-read-only-02.l => csr-insns-read-onl [...] rename gas/testsuite/gas/riscv/{priv-reg-fail-read-only-02.s => csr-insns-read-onl [...] create mode 100644 gas/testsuite/gas/riscv/csr-version-1p10.d create mode 100644 gas/testsuite/gas/riscv/csr-version-1p10.l create mode 100644 gas/testsuite/gas/riscv/csr-version-1p11.d create mode 100644 gas/testsuite/gas/riscv/csr-version-1p11.l create mode 100644 gas/testsuite/gas/riscv/csr-version-1p12.d create mode 100644 gas/testsuite/gas/riscv/csr-version-1p12.l create mode 100644 gas/testsuite/gas/riscv/csr-version-1p9p1.d create mode 100644 gas/testsuite/gas/riscv/csr-version-1p9p1.l rename gas/testsuite/gas/riscv/{priv-reg.s => csr.s} (82%) create mode 100644 gas/testsuite/gas/riscv/h-ext-32.d create mode 100644 gas/testsuite/gas/riscv/h-ext-32.s create mode 100644 gas/testsuite/gas/riscv/h-ext-64.d create mode 100644 gas/testsuite/gas/riscv/h-ext-64.s delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-fext.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-fext.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-zkr.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-zkr.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p10.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p11.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

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Tcwg-commits December 2021