Tcwg-commits December 2021

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15423 discussions

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu_cross_build/master-arm updated (500d3f0a302 -> e078de24eae)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/gcc. from 500d3f0a302 RISC-V: fixed testcase riscv/pr103302.c adds e078de24eae testsuite: Avoid unwanted vecorization [PR95046] No new revisions were added by this update. Summary of changes: gcc/testsuite/gfortran.dg/extract_recip_1.f | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu_cross_build/master-arm updated (5e2061291 -> 7261f4222)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu_cross_build/master-arm in repository toolchain/ci/base-artifacts. discards 5e2061291 0: update: binutils-gcc-linux-glibc-gdb-qemu: 7 new 7261f4222 0: update: binutils-gcc-linux-glibc-gdb-qemu: 7 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (5e2061291) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu_cross_build/master-a [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1536 -> 1536 bytes 02-prepare_abe/console.log.xz | Bin 2780 -> 2772 bytes 04-build_abe-binutils/console.log.xz | Bin 30240 -> 30004 bytes 05-build_abe-stage1/console.log.xz | Bin 90428 -> 90384 bytes 07-build_abe-linux/console.log.xz | Bin 8592 -> 8600 bytes 08-build_abe-glibc/console.log.xz | Bin 230036 -> 231320 bytes 09-build_abe-stage2/console.log.xz | Bin 216564 -> 217904 bytes 10-build_abe-gdb/console.log.xz | Bin 37752 -> 37756 bytes 11-build_abe-qemu/console.log.xz | Bin 29956 -> 29988 bytes 12-check_regression/console.log.xz | Bin 416 -> 416 bytes 13-update_baseline/console.log | 2 +- jenkins/manifest.sh | 14 +++++++------- 12 files changed, 8 insertions(+), 8 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig updated (6f016a2f79 -> 89f3bfa326)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig in repository toolchain/ci/qemu. from 6f016a2f79 Merge tag 'pull-block-2021-12-22' of https://gitlab.com/hrei [...] adds be16b8bf9f nbd: allow reconnect on open, with corresponding new options adds 169b9a94ed nbd/client-connection: nbd_co_establish_connection(): return [...] adds 9e14491af4 nbd/client-connection: improve error message of cancelled attempt adds c34ec5137d iotests.py: add qemu_tool_popen() adds 94a781f220 iotests.py: add and use qemu_io_wrap_args() adds 75c90eeeaf iotests.py: add qemu_io_popen() adds ab7f7e67a7 iotests: add nbd-reconnect-on-open test adds 1bd88c4542 Merge tag 'pull-nbd-2021-12-22-v2' of https://src.openvz.org [...] adds 3d2f73ef75 build: use "meson test" as the test harness adds f18155a207 Merge tag 'for-upstream-mtest' of https://gitlab.com/bonzini [...] adds 05bfd4db08 target/hppa: Fix deposit assert from trans_shrpw_imm adds 89f3bfa326 Merge tag 'pull-pa-20211223' of https://gitlab.com/rth7680/q [...] No new revisions were added by this update. Summary of changes: Makefile | 3 +- block/nbd.c | 45 ++- meson.build | 5 +- nbd/client-connection.c | 57 +++- qapi/block-core.json | 9 +- scripts/mtest2make.py | 112 +++--- scripts/tap-driver.pl | 379 --------------------- scripts/tap-merge.pl | 111 ------ target/hppa/translate.c | 19 +- tests/fp/meson.build | 2 +- tests/qemu-iotests/iotests.py | 37 +- tests/qemu-iotests/tests/nbd-reconnect-on-open | 71 ++++ tests/qemu-iotests/tests/nbd-reconnect-on-open.out | 11 + 13 files changed, 262 insertions(+), 599 deletions(-) delete mode 100755 scripts/tap-driver.pl delete mode 100755 scripts/tap-merge.pl create mode 100755 tests/qemu-iotests/tests/nbd-reconnect-on-open create mode 100644 tests/qemu-iotests/tests/nbd-reconnect-on-open.out -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig updated (368318bcce66 -> ba89c6d50569)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig in repository toolchain/ci/llvm-project. from 368318bcce66 [C++20] [Coroutines] Mark imported module as imported if n [...] adds 1e2c31c66be7 Revert "[C++20] [Coroutines] Mark imported module as impor [...] adds 2810c3403e42 [VE] Add VE support to update_llc_test_checks adds 86b001a94172 [C++20] [Modules] Mark imported module as imported if not [...] adds 3d36da77020b [VE] Add manuals to CompilerWriterInfo adds d2863088ab89 GlobalISel: Regen vector mir tests, add tests for vector a [...] adds 29f88b93fdbe [GlobalISel] Rework more/fewer elements for vectors adds 2c7dc13146ba [CGBuilder] Add CreateGEP() overload that accepts an Address adds bf2b5551f919 [CodeGen] Use CreateConstInBoundsGEP() in one more place adds 7977fd7cfc5b [OpenMP] Remove no-op cast (NFC) adds a3f50fb06dd4 [X86] isVectorShiftByScalarCheap - vXi8 select(shift(x,spl [...] adds a9486a40f7d1 [RISCV] Disable interleaving scalar loops in the loop vectorizer. adds 0ff20f2f4448 [InstSimplify] Fold logic AND to zero adds 71fc4bbdd200 [X86][SSE] Add ISD::ROTR support adds 0045d01af96f [SPIR-V] Add a toolchain for SPIR-V in clang adds fd3cde600ba6 AMDGPU/GlobalISel: Fix attempt to select non-legal instr i [...] adds e70ef6d9245e [AArch64] Add a tablegen pattern for SQXTN2. adds b7b260e19a74 [RISCV] Support strict FP conversion operations. adds dfb20d4d19ec [libc++][format] Improve ABI stability. adds 7704c503ecb8 [RISCV] Use positive 0.0 for the neutral element in fadd r [...] adds e8b24ee1153f [libc++][format][NFC] Remove some unneeded headers. adds ab3640aa0e83 [ASan] Moved optimized callbacks into a separate library. adds f766bc093c8c [Hexagon] Introduce Hexagon v69 ISA adds 4c8becbeee18 [Hexagon] Add Hexagon v69 builtins to clang adds d45a24799899 [AMDGPU] Don't remove VGPR to AGPR dead spills from frame info adds 4bf31659fac7 Revert "[ASan] Moved optimized callbacks into a separate l [...] adds 4374824ccf6e [ELF] --gc-sections: combine two iterations over inputSections adds 5410152827cc [Bazel] Add target for llvm-tli-checker adds 1d1b5efdef49 [Hexagon] Driver/preprocessor options for Hexagon v69 adds 3e52096809eb [libc][NFC] fix variable name adds 9fe0d67c9a72 [sanitizer] Check kArgVMax in SymbolizerProcess::GetArgV adds a7ebf2010ebb [NFC][sanitizer] Increase kArgVMax to 16 adds eafc64ed6325 [Driver][test] Remove unneeded -no-canonical-prefixes and [...] adds f103ee2e9e3f [sanitizer] Move internal_symbolizer "inline" option adds bf45624ba07f [ELF][PPC32] Support .got2 in an output section description adds be8180af5854 [clang][driver] Warn when '-mno-outline-atomics' is used w [...] adds 8f8c89f3cd74 [mlir] Remove spurious debug guard adds 6842f52a0bbf [libc++] [test] Flatten the directory structure a bit. NFC. adds a2a9a5c7d3d9 [libc++] [ranges] Fix bugs in ranges::empty(). adds 4191a93ea448 [libc++] [test] Eliminate `== true` and `== false`. NFC. adds 3042091168e9 [libc++] [ranges] Whitespace and namespace-style adjustmen [...] adds 937b00ab2cf0 [Polly][SchedOpt] Account for prevectorization of multiple [...] adds 313de31fbb75 [mlir][tosa] Split tosa-to-linalg named ops out of pass adds 10b3675aa950 [RISCV][VP] Lower mask vector VP AND/OR/XOR to RVV instructions adds 5fd328c45f6d [gn build] (manually) port f103ee2e9e3fc (sanitizer_symbol [...] adds 5d68dc184ef6 [Verifier] Iteratively traverse all indirect users. adds 7cd7b4d2f807 [sanitizer] Add common "demangle" flag adds 81378f7e56d9 Revert "[DwarfDebug] Support emitting function-local decla [...] adds ee4bbb50ae58 [gn build] (manually) port 7cd7b4d2f807 (sanitizer_symboli [...] adds 464cc4c920a1 [ELF] Remove stale comment which was duplicated in MarkLiv [...] adds a67c0fc1fbe8 [Hexagon] Revamp HVX flag verification in driver adds 60509623c46e [libc][obvious] Fix style of MPFRWrapper. adds 8a26ba6a02f1 Load binary by UUID from qProcessInfo packet fields adds 735fe1da6b97 Revert "[mlir][tosa] Split tosa-to-linalg named ops out of pass" adds 71b3bfde9cd2 [ASan] Moved optimized callbacks into a separate library. adds 417cd2e5c5e0 [ELF] SymbolTable: change some vector<Symbol *> to SmallVector adds a6114ff0cd69 [gn build] "port" 71b3bfde9cd2 adds 8ff42766d1ef [mlir] Use thread-pool's notion of thread count instead of [...] adds a2baf634a1d7 [ELF] Simplify SymbolTable::insert. NFC adds 41a64338cc84 [mlir] Add getNumThreads to MLIRContext adds 1abbbc7b2435 [ELF] scanVersionScript: remove unused variable adds 0a35211b3488 [RISCV] Don't allow vector types to be used with inline as [...] adds a79c567f6a9a [NFC] Remove tailing whitespaces in llvm/include/llvm/Fron [...] adds 1d285f2de0b7 [ELF] Simplify and optimize ObjFile<ELFT>::parseLazy adds f3d4e168dbc7 [C++20] Conform coroutine's comments in clang (NFC-ish) adds b05df0287baf Revert "[DWARF] Fix PR51087 Extraneous enum record in DWAR [...] adds 02478a26f269 [RISCV] Use DAG variable directly instead of DCI.DAG adds 097208dbf077 [C++20] [Coroutines] Allow promise_type to not define retu [...] adds 0d749e13f714 [ELF] Optimize symbol initialization and resolution adds dd903173c0fb [OpenMP] Avoid creating null pointer lvalue (NFC) adds 69ffc3cee900 [Attributor] Directly call areTypesABICompatible() hook adds cb31a5710421 [DebugInfo] Remove type-units-maybe-unused-types.ll test adds ae64c5a0fde5 [DSE][MemLoc] Handle intrinsics more generically adds ba2b34b1c7d4 [DSE] Simplify isGuaranteedLoopInvariant() (NFC) adds ea2d4c588137 [GlobalISel] Fix -Wunused-function in -DLLVM_ENABLE_ASSERT [...] adds 81d69e1bda9e [DSE] Call isRemovable() after getLocForWriteEx() (NFCI) adds 2b8a703858ea [DSE] Avoid calling isRemovable() on non-analyzable locati [...] adds 034e66e76c6f [DSE] Assert analyzable write in isRemovable() (NFC) adds 24c68ea1eb4f Reland "[X86][MS-InlineAsm] Use exact conditions to recogn [...] adds 72d220178560 [DSE] Rename getLocForWriteEx() to getLocForWrite() (NFC) adds 90095a0b65bd [DSE] Remove unnecessary check in getLocForWrite() (NFC) adds eb91d91b7a8e [DSE] Fix typo in recent commit adds 969a51ff3632 Revert "[ASan] Moved optimized callbacks into a separate l [...] adds 3b4c040cca9d [gn build] Port 969a51ff3632 adds bb84dd81590b [AArch64] Add a tablegen pattern for RADDHN/RADDHN2. adds c7a589a2c4e2 [Clang][OpenMP] Add the support for atomic compare in parser adds 159da567378a [X86] Enable v32i16 ISD::ROTL/ROTR lowering on AVX512BW targets adds 286237962ad3 InstCombine: Gracefully handle more allocas in the wrong a [...] adds 8020458c5dc2 [AMDGPU] Changing S_AND_B32 to V_AND_B32_e64 in the diverg [...] adds d5dc3964a741 [DFAJumpThreading] Determinator BB should precede switch-d [...] adds dc8f9fb196da [Docs] Minor fix in clang user manual adds 6c0eaefaf832 [MLIR][FlatAffineConstraints][NFC] Move some static functi [...] adds 27a0718ad0a4 Revert "[MLIR][FlatAffineConstraints][NFC] Move some stati [...] adds 8ea64d5585ec [clang-format] Fix short enums getting wrapped even when denied adds e1b6b5be462e [ELF] Avoid referencing SectionBase::repl after ICF adds e694180033d1 [ELF] Optimize --wrap to only check non-local symbols adds 5e3403bd2203 [ELF] parseLazy: skip local symbols adds a9e8b1ee7fd4 [mlir] Fully qualify default types used in parser code adds d63016a86548 [CMake] Revert -Wl,-O3 adds 2709fd1520bc [MLIR][LLVM] Add MemmoveOp to LLVM Dialect adds b5a0f0f397c7 [ELF] Add ELFFileBase::{elfShdrs,numELFShdrs} to avoid dup [...] adds 745420d3f4b0 [ELF] Cache global variable `target` in relocate* adds 40fae4d8fcbd [ELF] Optimize replaceCommonSymbols adds a8cbddc99411 [CodeGen] Fix a memory leak adds 9c0a4227a9ca Use Optional::getValueOr (NFC) adds 62e48ed10f9d Use isa instead of dyn_cast (NFC) adds 76f0f1cc5c52 Use {DenseSet,SetVector,SmallPtrSet}::contains (NFC) adds 3cfe375ae431 Use StringRef::contains (NFC) adds cde37a7e5a1f [ELF][test] Add tests for mixed GD-to-IE and IE, mixed TLS [...] adds 70912420bbc3 [ELF] Move TLS dynamic relocations to postScanRelocations adds 2d303e678152 Remove redundant return and continue statements (NFC) adds 34558b039b3b [StaticAnalyzer] Remove redundant declaration isStdSmartPtr (NFC) adds d86e2cc2e37c [NFC] Method for evaluation of FCmpInst for constant operands adds 5b2e611b734c [MLIR][FlatAffineConstraints][NFC] Move some static functi [...] adds 46cdcf087300 [lldb] Add support for UTF-8 unicode formatting adds 0c553cc1af2e [MLIR] Add forgotten directory Support to unittests cmake adds dd4f5d4ae577 [ELF] De-template handleTlsRelocation. NFC adds a00f480fe8ee [ELF] scanReloc: remove unused start parameter. NFC adds 2bddab25dba8 DebugInfo: Don't hash DIE offsets before they're computed adds dabfefa49057 Fix clang-tidy performance-move-const-arg in DLTI Dialect (NFC) adds d5e310b15435 [ELF][test] Make some TLS tests less sensitive to addresses adds 2c8ebab32ead [ELF] sortSymTabSymbols: change vector to SmallVector adds 20b4704da315 [ELF] reportRangeError: mention symbol name for non-STT_SE [...] adds aabe901d57d6 [ELF] Remove one redundant computeBinding adds 2132906836cf Revert "[MLIR] Add forgotten directory Support to unittest [...] adds fc15fc57e615 [Orc] Remove a redundant declaration (NFC) adds 7006d34ce753 Ensure newlines at the end of files (NFC) adds 0542d15211cb Remove redundant string initialization (NFC) adds bf7f3dd74ee3 [ELF] Move outSecOff addition from InputSection::writeTo t [...] adds 511726c64d3b [LV] Move getStepVector out of ILV (NFC). adds 10316a6f94d4 [ELF] Change InputSectionDescription members from vector t [...] adds 31cfb3f4f644 [clang] Remove redundant calls to c_str() (NFC) adds a1c2ee01470e [ELF] LinkerScript/OutputSection: change other std::vector [...] adds e7774f499bb2 Use static_assert instead of assert (NFC) adds 213896bc5aea [ELF] Remove unused InputSection::getOffsetInFile adds 469144ffa37f [ELF] De-template InputSectionBase::getEnclosingFunction adds 7924b3814f40 [ELF] Add Symbol::hasVersionSuffix adds 70a98008eaf7 [RISCV] Reduce repetitive codes in flw, fsw adds e9262edf0d11 [ELF] SymbolTable::symbols: don't filter out PlaceholderKind adds 64038ef8c3fe [ELF] ScriptParser: change std::vector to SmallVector new 6441536c27cf [libcxx] [Coroutines] Support noop_coroutine for GCC new 5d47e7d76895 [RISCV] Convert whole register copies as the source define [...] new ec501f15a8b8 [clang][CodeGen] Remove the signed version of createExpression new e90c8c042214 [ELF] Optimize basic block section bytesDropped/jumpInstrMods new 315554e873a5 [ELF] Unify sizeof(InputSection) limits for _WIN32 and others new b07292f77a1e [ELF] Serialize deleteFallThruJmpInsn to fix concurrency issue new 0a5788ab5746 [Target] Use range-based for loops (NFC) new 66c550f8de67 [ELF] Delete unused LazyObjKind new abc388ed3cf0 [ELF] Move excludeLibs/redirectSymbols/replaceCommonSymbol [...] new 7c3cf4c2c068 [Inline][X86] Avoid inlining if it would create ABI-incomp [...] new b5fef6dbfd6b [OpenCL] Allow optional __generic in __remove_address_spac [...] new 4fe5cfe53e86 [MLIR] Add forgotten directory Support to unittests cmake new 21aa4d5d5ef9 [NFC] [Coroutines] Add a test for icmp use of coro.suspend [...] new 2e630eabd329 [LV] Sink BTC creation to actual use (NFC). new 1f07a4a5699b [CodeGen] Avoid more pointer element type accesses new ca4d2c368d1a Revert "[NFC] [Coroutines] Add a test for icmp use of coro [...] new 508e39afe012 GlobalISel: remove redundant line added in D114198. NFC new daf32b13d700 [IndVars] Support opaque pointers in LFTR new 948ae472a610 [MCA][X86] Add AVX512 vector move instruction test coverage new 3e6586113157 [CodeGen] Avoid one more pointer element type access new 29475e02865b [X86] Add scheduler classes for zmm vector reg-reg move in [...] new 1ef3f83ef242 [NFC] [Coroutines] Add tests to address the problem for co [...] new ba89c6d50569 Fix forward for "signed version of createExpression" The 23 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang-tools-extra/clang-doc/Mapper.cpp | 2 +- clang-tools-extra/clang-doc/Serialize.cpp | 6 +- .../abseil/DurationFactoryScaleCheck.cpp | 1 - .../clang-tidy/android/CloexecCheck.cpp | 2 +- .../bugprone/ReservedIdentifierCheck.cpp | 2 +- .../clang-tidy/cert/LimitedRandomnessCheck.cpp | 2 +- .../llvmlibc/ImplementationInNamespaceCheck.cpp | 1 - .../clang-tidy/modernize/LoopConvertCheck.cpp | 2 +- .../clang-tidy/modernize/RawStringLiteralCheck.cpp | 2 +- .../readability/BracesAroundStatementsCheck.cpp | 2 +- .../clang-tidy/readability/NamedParameterCheck.cpp | 2 +- clang/docs/UsersManual.rst | 54 + clang/include/clang/APINotes/Types.h | 10 +- clang/include/clang/AST/AbstractBasicReader.h | 2 +- clang/include/clang/AST/DeclTemplate.h | 11 +- clang/include/clang/AST/OpenMPClause.h | 41 + clang/include/clang/AST/RecursiveASTVisitor.h | 5 + .../clang/Analysis/Analyses/ThreadSafetyCommon.h | 2 +- clang/include/clang/Basic/BuiltinsHexagon.def | 10 +- clang/include/clang/Basic/BuiltinsHexagonDep.def | 147 + clang/include/clang/Basic/DiagnosticDriverKinds.td | 16 +- clang/include/clang/Basic/DiagnosticSemaKinds.td | 4 +- clang/include/clang/Driver/Options.td | 14 + clang/include/clang/Driver/Tool.h | 1 + clang/include/clang/Driver/ToolChain.h | 3 + clang/include/clang/Sema/Sema.h | 3 + clang/lib/AST/ASTContext.cpp | 2 +- clang/lib/AST/OpenMPClause.cpp | 6 + clang/lib/AST/StmtProfile.cpp | 2 + clang/lib/ASTMatchers/Dynamic/Marshallers.h | 1 - clang/lib/ASTMatchers/Dynamic/Parser.cpp | 2 +- clang/lib/Analysis/CFG.cpp | 2 - clang/lib/Basic/OpenMPKinds.cpp | 2 + clang/lib/Basic/Targets/Hexagon.cpp | 9 +- clang/lib/Basic/Targets/M68k.cpp | 2 +- clang/lib/Basic/Targets/PPC.cpp | 5 +- clang/lib/Basic/Targets/PPC.h | 2 +- clang/lib/CodeGen/CGBuilder.h | 15 + clang/lib/CodeGen/CGClass.cpp | 4 +- clang/lib/CodeGen/CGCoroutine.cpp | 4 + clang/lib/CodeGen/CGDebugInfo.cpp | 12 +- clang/lib/CodeGen/CGDebugInfo.h | 2 +- clang/lib/CodeGen/CGDecl.cpp | 6 +- clang/lib/CodeGen/CGExprAgg.cpp | 9 +- clang/lib/CodeGen/CGExprCXX.cpp | 9 +- clang/lib/CodeGen/CGObjC.cpp | 8 +- clang/lib/CodeGen/CGOpenMPRuntime.cpp | 78 +- clang/lib/CodeGen/CGOpenMPRuntime.h | 8 +- clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp | 14 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 13 +- clang/lib/CodeGen/CodeGenAction.cpp | 1 - clang/lib/CodeGen/CodeGenFunction.h | 5 +- clang/lib/CodeGen/ItaniumCXXABI.cpp | 4 +- clang/lib/Driver/Driver.cpp | 36 +- clang/lib/Driver/ToolChain.cpp | 2 +- clang/lib/Driver/ToolChains/Clang.cpp | 22 +- clang/lib/Driver/ToolChains/Clang.h | 7 +- clang/lib/Driver/ToolChains/CommonArgs.cpp | 16 +- clang/lib/Driver/ToolChains/HIPAMD.cpp | 1 - clang/lib/Driver/ToolChains/Hexagon.cpp | 131 +- clang/lib/Driver/ToolChains/SPIRV.cpp | 25 +- clang/lib/Driver/ToolChains/SPIRV.h | 33 + clang/lib/Format/NamespaceEndCommentsFixer.cpp | 4 +- clang/lib/Format/UnwrappedLineFormatter.cpp | 9 +- clang/lib/Format/UnwrappedLineParser.cpp | 1 - clang/lib/Frontend/CompilerInstance.cpp | 12 +- clang/lib/Frontend/InitHeaderSearch.cpp | 2 +- clang/lib/Headers/hexagon_protos.h | 11 - clang/lib/Headers/hexagon_types.h | 32 - clang/lib/Headers/hvx_hexagon_protos.h | 814 +- clang/lib/Headers/opencl-c-base.h | 2 + clang/lib/Parse/ParseOpenMP.cpp | 1 + clang/lib/Sema/SemaCUDA.cpp | 1 - clang/lib/Sema/SemaCodeComplete.cpp | 1 - clang/lib/Sema/SemaCoroutine.cpp | 178 +- clang/lib/Sema/SemaExprCXX.cpp | 2 +- clang/lib/Sema/SemaOpenMP.cpp | 39 +- clang/lib/Sema/SemaType.cpp | 1 - clang/lib/Sema/TreeTransform.h | 7 + clang/lib/Serialization/ASTReader.cpp | 5 + clang/lib/Serialization/ASTWriter.cpp | 2 + .../StaticAnalyzer/Checkers/ReturnValueChecker.cpp | 2 +- clang/lib/StaticAnalyzer/Checkers/SmartPtr.h | 2 - clang/test/CodeGen/ms-inline-asm-functions.c | 2 +- clang/test/Driver/hexagon-hvx-ieee-fp.c | 25 + clang/test/Driver/hexagon-hvx-qfloat.c | 25 + clang/test/Driver/hexagon-hvx.c | 303 +- clang/test/Driver/hexagon-toolchain-elf.c | 16 + clang/test/Driver/hexagon-vectorize.c | 2 +- clang/test/Driver/spirv-toolchain.cl | 65 + clang/test/Driver/unsupported-outline-atomics.c | 15 + clang/test/Misc/target-invalid-cpu-note.c | 2 +- clang/test/OpenMP/atomic_messages.cpp | 29 +- clang/test/Preprocessor/hexagon-predefines.c | 11 + clang/test/SemaCXX/coroutines-exp-namespace.cpp | 13 - clang/test/SemaCXX/coroutines.cpp | 29 +- .../remove-address-space.clcpp | 8 +- .../tools/clang-fuzzer/handle-llvm/handle_llvm.cpp | 2 - .../clang-nvlink-wrapper/ClangNvlinkWrapper.cpp | 2 +- clang/tools/clang-scan-deps/ClangScanDeps.cpp | 2 +- clang/tools/driver/driver.cpp | 2 +- clang/tools/libclang/CIndex.cpp | 2 + clang/unittests/Format/FormatTest.cpp | 15 + clang/utils/TableGen/NeonEmitter.cpp | 2 +- .../sanitizer_common_interface_posix.inc | 2 + .../lib/sanitizer_common/sanitizer_flags.inc | 1 + .../sanitizer_symbolizer_internal.h | 2 +- .../sanitizer_symbolizer_libcdep.cpp | 4 + .../sanitizer_common/sanitizer_symbolizer_mac.cpp | 1 + .../sanitizer_symbolizer_posix_libcdep.cpp | 20 +- .../symbolizer/sanitizer_symbolize.cpp | 36 +- .../symbolizer/scripts/build_symbolizer.sh | 2 + .../symbolizer/scripts/global_symbols.txt | 2 + compiler-rt/lib/sanitizer_common/weak_symbols.txt | 2 + .../TestCases/symbolize_pc_demangle.cpp | 30 + flang/lib/Semantics/check-omp-structure.cpp | 1 + libc/src/math/generic/logf.cpp | 6 +- libc/test/src/math/RIntTest.h | 28 +- libc/test/src/math/RoundToIntegerTest.h | 18 +- libc/utils/MPFRWrapper/MPFRUtils.cpp | 392 +- libc/utils/MPFRWrapper/MPFRUtils.h | 149 +- libcxx/docs/Status/Cxx2bIssues.csv | 2 +- libcxx/include/__coroutine/noop_coroutine_handle.h | 30 +- libcxx/include/__format/format_arg.h | 17 +- libcxx/include/__format/format_context.h | 3 +- libcxx/include/__format/formatter_string.h | 1 - libcxx/include/__ranges/access.h | 94 +- libcxx/include/__ranges/data.h | 5 +- libcxx/include/__ranges/empty.h | 14 +- libcxx/include/__ranges/size.h | 16 +- libcxx/src/chrono_system_time_init.h | 2 +- .../src/experimental/memory_resource_init_helper.h | 2 +- libcxx/src/iostream_init.h | 2 +- .../format.arg/arg_t.compile.pass.cpp | 38 + .../coroutine.handle.noop/noop_coroutine.pass.cpp | 23 +- .../{range.access.begin => }/begin.pass.cpp | 0 .../range.access/{range.prim => }/data.pass.cpp | 0 .../range.access/{range.prim => }/empty.pass.cpp | 40 +- .../{range.access.end => }/end.pass.cpp | 0 .../range.access.cbegin/cbegin.compile.pass.cpp | 1 - .../range.access.cend/cend.compile.pass.cpp | 1 - .../range.access/{range.prim => }/size.pass.cpp | 0 .../range.access/{range.prim => }/ssize.pass.cpp | 0 lld/COFF/Driver.cpp | 2 +- lld/ELF/AArch64ErrataFix.cpp | 2 +- lld/ELF/ARMErrataFix.cpp | 2 +- lld/ELF/Arch/X86_64.cpp | 3 +- lld/ELF/CallGraphSort.cpp | 4 +- lld/ELF/Config.h | 4 +- lld/ELF/DWARF.cpp | 3 +- lld/ELF/Driver.cpp | 73 +- lld/ELF/ICF.cpp | 16 + lld/ELF/InputFiles.cpp | 139 +- lld/ELF/InputFiles.h | 29 +- lld/ELF/InputSection.cpp | 114 +- lld/ELF/InputSection.h | 35 +- lld/ELF/LTO.cpp | 2 + lld/ELF/LinkerScript.cpp | 45 +- lld/ELF/LinkerScript.h | 34 +- lld/ELF/MarkLive.cpp | 76 +- lld/ELF/OutputSections.cpp | 12 +- lld/ELF/OutputSections.h | 10 +- lld/ELF/Relocations.cpp | 142 +- lld/ELF/Relocations.h | 2 +- lld/ELF/ScriptParser.cpp | 54 +- lld/ELF/SymbolTable.cpp | 31 +- lld/ELF/SymbolTable.h | 22 +- lld/ELF/Symbols.cpp | 14 +- lld/ELF/Symbols.h | 26 +- lld/ELF/SyntheticSections.cpp | 27 +- lld/ELF/SyntheticSections.h | 2 +- lld/ELF/Thunks.cpp | 5 +- lld/ELF/Writer.cpp | 54 +- lld/test/ELF/aarch64-movw-error.s | 6 +- lld/test/ELF/aarch64-tls-le.s | 24 +- lld/test/ELF/aarch64-tlsdesc-zrel.s | 18 +- lld/test/ELF/arm-adr-err-long.s | 2 +- lld/test/ELF/empty-ver2.s | 2 +- lld/test/ELF/i386-tls-dynamic.s | 22 +- lld/test/ELF/i386-tls-opt.s | 36 +- lld/test/ELF/i386-tlsdesc-gd.s | 20 +- lld/test/ELF/linkerscript/ppc32-got2.s | 59 + lld/test/ELF/ppc32-relocatable-got2.s | 10 +- lld/test/ELF/riscv-tls-ld.s | 34 +- lld/test/ELF/x86-64-tls-ie.s | 37 +- lld/test/ELF/x86-64-tlsdesc-gd-mixed.s | 25 + lld/test/ELF/x86-64-tlsdesc-gd.s | 20 +- lld/test/wasm/debuginfo.test | 32 +- lldb/docs/lldb-gdb-remote.txt | 3 + lldb/include/lldb/Core/ValueObject.h | 2 +- lldb/include/lldb/Target/LanguageRuntime.h | 2 +- lldb/include/lldb/Utility/RangeMap.h | 1 - lldb/source/Commands/CommandCompletions.cpp | 2 +- lldb/source/Core/IOHandlerCursesGUI.cpp | 15 +- lldb/source/Expression/IRExecutionUnit.cpp | 2 - lldb/source/Expression/IRMemoryMap.cpp | 4 - .../source/Host/posix/ProcessLauncherPosixFork.cpp | 1 - lldb/source/Interpreter/CommandInterpreter.cpp | 3 - .../Disassembler/LLVMC/DisassemblerLLVMC.cpp | 2 +- .../MacOSX-DYLD/DynamicLoaderMacOSXDYLD.cpp | 1 - .../Clang/ASTResultSynthesizer.cpp | 2 +- .../ExpressionParser/Clang/ClangASTImporter.cpp | 4 +- .../ExpressionParser/Clang/ClangASTSource.cpp | 2 - .../ExpressionParser/Clang/ClangASTSource.h | 2 +- .../Clang/ClangExpressionDeclMap.cpp | 2 - .../ExpressionParser/Clang/IRDynamicChecks.cpp | 2 +- .../Plugins/ExpressionParser/Clang/IRForTarget.cpp | 2 +- .../Instruction/MIPS/EmulateInstructionMIPS.cpp | 2 +- .../MIPS64/EmulateInstructionMIPS64.cpp | 2 +- .../InstrumentationRuntimeMainThreadChecker.cpp | 6 +- .../TSan/InstrumentationRuntimeTSan.cpp | 6 +- .../ObjC/AppleObjCRuntime/AppleObjCDeclVendor.cpp | 3 - .../Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp | 2 +- .../ObjectFile/Minidump/MinidumpFileBuilder.cpp | 2 +- .../gdb-server/PlatformRemoteGDBServer.cpp | 2 +- .../Plugins/Process/Linux/NativeProcessLinux.cpp | 2 +- .../gdb-remote/GDBRemoteCommunicationClient.cpp | 36 + .../gdb-remote/GDBRemoteCommunicationClient.h | 6 + .../Process/gdb-remote/ProcessGDBRemote.cpp | 88 + lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h | 2 +- .../Plugins/SymbolFile/NativePDB/PdbAstBuilder.cpp | 6 +- .../SymbolFile/NativePDB/SymbolFileNativePDB.cpp | 2 +- .../Plugins/SymbolFile/PDB/SymbolFilePDB.cpp | 3 +- .../ctf/CommandObjectThreadTraceExportCTF.cpp | 3 +- .../Plugins/TypeSystem/Clang/TypeSystemClang.cpp | 3 + lldb/source/Symbol/SymbolFile.cpp | 4 +- lldb/source/Target/RegisterContextUnwind.cpp | 2 +- lldb/source/Target/ThreadPlanStack.cpp | 1 - lldb/source/Target/UnwindLLDB.cpp | 1 - .../builtin-formats/TestBuiltinFormats.py | 6 +- llvm/bindings/go/llvm/dibuilder.go | 6 +- llvm/bindings/ocaml/debuginfo/debuginfo_ocaml.c | 2 +- llvm/cmake/modules/AddLLVM.cmake | 8 - llvm/docs/CompilerWriterInfo.rst | 6 + .../OrcV2CBindingsVeryLazy.c | 1 - llvm/include/llvm-c/DebugInfo.h | 4 +- llvm/include/llvm/CodeGen/DIE.h | 12 +- .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 52 +- .../llvm/CodeGen/GlobalISel/LegalizerInfo.h | 38 +- .../llvm/CodeGen/GlobalISel/MachineIRBuilder.h | 28 + llvm/include/llvm/CodeGen/GlobalISel/Utils.h | 5 + llvm/include/llvm/ExecutionEngine/Orc/DebugUtils.h | 3 - llvm/include/llvm/Frontend/OpenMP/OMP.td | 4 +- llvm/include/llvm/IR/DIBuilder.h | 1 - llvm/include/llvm/IR/Instructions.h | 9 + llvm/include/llvm/IR/IntrinsicsHexagonDep.td | 538 +- llvm/lib/Analysis/InstructionSimplify.cpp | 9 + llvm/lib/Analysis/MemoryLocation.cpp | 14 - llvm/lib/CodeGen/AsmPrinter/ByteStreamer.h | 21 +- llvm/lib/CodeGen/AsmPrinter/DIEHash.cpp | 12 + llvm/lib/CodeGen/AsmPrinter/DIEHash.h | 2 + llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp | 132 +- llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h | 41 +- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 290 +- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.h | 18 +- llvm/lib/CodeGen/AsmPrinter/DwarfFile.h | 7 +- llvm/lib/CodeGen/AsmPrinter/DwarfUnit.cpp | 2 +- llvm/lib/CodeGen/AsmPrinter/DwarfUnit.h | 2 +- llvm/lib/CodeGen/GlobalISel/CallLowering.cpp | 36 +- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 1118 +- llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 48 +- llvm/lib/CodeGen/GlobalISel/Utils.cpp | 15 + llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 5 +- llvm/lib/DebugInfo/DWARF/DWARFDebugAbbrev.cpp | 2 +- llvm/lib/DebugInfo/DWARF/DWARFDie.cpp | 2 - llvm/lib/DebugInfo/DWARF/DWARFUnit.cpp | 2 +- llvm/lib/IR/ConstantFold.cpp | 42 +- llvm/lib/IR/DIBuilder.cpp | 6 - llvm/lib/IR/DebugInfo.cpp | 8 +- llvm/lib/IR/Instructions.cpp | 44 +- llvm/lib/IR/Verifier.cpp | 17 +- llvm/lib/MC/MachObjectWriter.cpp | 4 +- llvm/lib/Support/RISCVISAInfo.cpp | 2 +- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 54 + llvm/lib/Target/AMDGPU/AMDGPUCombinerHelper.cpp | 1 - llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 53 +- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 21 +- llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 12 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 2 - llvm/lib/Target/AMDGPU/SIInstructions.td | 12 +- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 2 +- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 7 + llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 6 +- llvm/lib/Target/AMDGPU/VOPInstructions.td | 12 + llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp | 3 +- .../lib/Target/ARM/MCTargetDesc/ARMELFStreamer.cpp | 6 +- .../Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp | 4 +- llvm/lib/Target/ARM/Thumb2SizeReduction.cpp | 5 +- llvm/lib/Target/AVR/AVRInstrInfo.cpp | 2 - llvm/lib/Target/Hexagon/BitTracker.cpp | 4 +- llvm/lib/Target/Hexagon/Hexagon.td | 55 +- llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp | 7 +- llvm/lib/Target/Hexagon/HexagonCFGOptimizer.cpp | 19 +- .../lib/Target/Hexagon/HexagonConstPropagation.cpp | 8 +- llvm/lib/Target/Hexagon/HexagonDepArch.h | 34 +- llvm/lib/Target/Hexagon/HexagonDepArch.td | 2 + llvm/lib/Target/Hexagon/HexagonDepDecoders.inc | 1 + llvm/lib/Target/Hexagon/HexagonDepIICHVX.td | 1020 +- llvm/lib/Target/Hexagon/HexagonDepIICScalar.td | 768 ++ llvm/lib/Target/Hexagon/HexagonDepInstrFormats.td | 14 + llvm/lib/Target/Hexagon/HexagonDepInstrInfo.td | 1253 +- llvm/lib/Target/Hexagon/HexagonDepMapAsm2Intrin.td | 293 +- llvm/lib/Target/Hexagon/HexagonDepMappings.td | 1 - llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp | 20 +- llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp | 11 +- llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp | 4 +- llvm/lib/Target/Hexagon/HexagonInstrFormats.td | 7 +- llvm/lib/Target/Hexagon/HexagonPseudo.td | 11 + llvm/lib/Target/Hexagon/HexagonSchedule.td | 1 + llvm/lib/Target/Hexagon/HexagonScheduleV69.td | 40 + llvm/lib/Target/Hexagon/HexagonSubtarget.cpp | 72 +- llvm/lib/Target/Hexagon/HexagonSubtarget.h | 25 +- .../Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h | 5 +- .../Hexagon/MCTargetDesc/HexagonMCChecker.cpp | 38 +- .../Target/Hexagon/MCTargetDesc/HexagonMCChecker.h | 1 + .../Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp | 18 +- .../Hexagon/MCTargetDesc/HexagonMCInstrInfo.h | 4 +- .../Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp | 32 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 123 +- llvm/lib/Target/RISCV/RISCVISelLowering.h | 7 + llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 5 +- llvm/lib/Target/RISCV/RISCVInstrInfoD.td | 41 +- llvm/lib/Target/RISCV/RISCVInstrInfoF.td | 78 +- llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td | 44 +- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h | 4 +- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 3 +- llvm/lib/Target/X86/AsmParser/X86Operand.h | 7 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 115 +- llvm/lib/Target/X86/X86SchedBroadwell.td | 2 + llvm/lib/Target/X86/X86SchedHaswell.td | 2 + llvm/lib/Target/X86/X86SchedIceLake.td | 2 + llvm/lib/Target/X86/X86SchedSandyBridge.td | 2 + llvm/lib/Target/X86/X86SchedSkylakeClient.td | 2 + llvm/lib/Target/X86/X86SchedSkylakeServer.td | 2 + llvm/lib/Target/X86/X86Schedule.td | 10 +- llvm/lib/Target/X86/X86ScheduleAtom.td | 2 + llvm/lib/Target/X86/X86ScheduleBdVer2.td | 2 + llvm/lib/Target/X86/X86ScheduleBtVer2.td | 2 + llvm/lib/Target/X86/X86ScheduleSLM.td | 2 + llvm/lib/Target/X86/X86ScheduleZnver1.td | 2 + llvm/lib/Target/X86/X86ScheduleZnver2.td | 2 + llvm/lib/Target/X86/X86ScheduleZnver3.td | 2 + llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 42 +- llvm/lib/Transforms/IPO/AttributorAttributes.cpp | 34 +- .../Transforms/InstCombine/InstCombineCasts.cpp | 2 +- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 17 +- llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp | 58 +- .../lib/Transforms/Scalar/DeadStoreElimination.cpp | 151 +- llvm/lib/Transforms/Scalar/IndVarSimplify.cpp | 9 +- .../Transforms/Utils/SampleProfileInference.cpp | 7 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 153 +- .../CodeGen/AArch64/GlobalISel/arm64-fallback.ll | 8 - .../AArch64/GlobalISel/call-lowering-vectors.ll | 68 +- .../AArch64/GlobalISel/legalize-saddsat.mir | 258 +- .../AArch64/GlobalISel/legalize-shuffle-vector.mir | 211 +- .../AArch64/GlobalISel/legalize-ssubsat.mir | 258 +- llvm/test/CodeGen/AArch64/arm64-raddhn-combine.ll | 48 + llvm/test/CodeGen/AArch64/arm64-sqxtn2-combine.ll | 37 + llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll | 34 +- .../GlobalISel/artifact-combiner-extract.mir | 9 +- .../artifact-combiner-unmerge-values.mir | 2 +- .../AMDGPU/GlobalISel/artifact-combiner-zext.mir | 16 +- ...bug-legalization-artifact-combiner-dead-def.mir | 20 +- .../AMDGPU/GlobalISel/combine-fma-add-mul.ll | 176 +- .../CodeGen/AMDGPU/GlobalISel/function-returns.ll | 2029 +-- .../AMDGPU/GlobalISel/insertelement.large.ll | 12 +- .../AMDGPU/GlobalISel/inst-select-extract.mir | 153 - .../AMDGPU/GlobalISel/inst-select-fract.f64.mir | 6 +- .../AMDGPU/GlobalISel/inst-select-insert.mir | 39 - .../AMDGPU/GlobalISel/inst-select-insert.xfail.mir | 39 - .../GlobalISel/irtranslator-call-return-values.ll | 16 +- .../CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll | 194 +- .../GlobalISel/irtranslator-function-args.ll | 40 +- .../AMDGPU/GlobalISel/irtranslator-sibling-call.ll | 17 +- .../CodeGen/AMDGPU/GlobalISel/legalize-and.mir | 633 +- .../CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir | 5 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir | 104 +- .../CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir | 3449 ++--- .../AMDGPU/GlobalISel/legalize-concat-vectors.mir | 2 +- .../GlobalISel/legalize-extract-vector-elt.mir | 314 +- .../CodeGen/AMDGPU/GlobalISel/legalize-extract.mir | 218 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir | 55 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir | 16 +- .../AMDGPU/GlobalISel/legalize-fcanonicalize.mir | 8 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir | 8 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir | 3984 +++--- .../CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir | 270 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir | 588 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fma.mir | 994 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir | 1158 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir | 1158 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir | 16 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir | 8 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/legalize-freeze.mir | 140 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir | 1811 +-- .../CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir | 2448 ++-- .../CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir | 8 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir | 510 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir | 8 +- .../AMDGPU/GlobalISel/legalize-implicit-def.mir | 231 +- .../GlobalISel/legalize-insert-vector-elt.mir | 79 +- .../CodeGen/AMDGPU/GlobalISel/legalize-insert.mir | 578 +- .../AMDGPU/GlobalISel/legalize-intrinsic-round.mir | 1840 +-- .../AMDGPU/GlobalISel/legalize-inttoptr.mir | 2 +- .../legalize-llvm.amdgcn.image.load.2d.d16.ll | 2684 ++-- .../legalize-llvm.amdgcn.image.load.2d.ll | 2 +- .../legalize-llvm.amdgcn.image.store.2d.d16.ll | 690 +- .../legalize-llvm.amdgcn.s.buffer.load.mir | 175 +- .../GlobalISel/legalize-load-constant-32bit.mir | 2 +- .../AMDGPU/GlobalISel/legalize-load-constant.mir | 105 +- .../AMDGPU/GlobalISel/legalize-load-flat.mir | 110 +- .../AMDGPU/GlobalISel/legalize-load-global.mir | 1016 +- .../AMDGPU/GlobalISel/legalize-load-local.mir | 64 +- .../AMDGPU/GlobalISel/legalize-load-private.mir | 24 +- .../CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir | 216 +- .../test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir | 567 +- .../CodeGen/AMDGPU/GlobalISel/legalize-phi.mir | 1678 +-- .../CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir | 530 +- .../CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir | 1704 ++- .../CodeGen/AMDGPU/GlobalISel/legalize-sbfx.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir | 8 +- .../CodeGen/AMDGPU/GlobalISel/legalize-select.mir | 115 +- .../AMDGPU/GlobalISel/legalize-sext-inreg.mir | 10 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sext.mir | 5 +- .../CodeGen/AMDGPU/GlobalISel/legalize-shl.mir | 104 +- .../AMDGPU/GlobalISel/legalize-shuffle-vector.mir | 104 +- .../GlobalISel/legalize-shuffle-vector.s16.mir | 108 +- .../CodeGen/AMDGPU/GlobalISel/legalize-smax.mir | 622 +- .../CodeGen/AMDGPU/GlobalISel/legalize-smin.mir | 622 +- .../CodeGen/AMDGPU/GlobalISel/legalize-srem.mir | 8 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir | 1808 ++- .../CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir | 530 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir | 1704 ++- .../AMDGPU/GlobalISel/legalize-store-global.mir | 1192 +- .../CodeGen/AMDGPU/GlobalISel/legalize-store.mir | 16 +- .../CodeGen/AMDGPU/GlobalISel/legalize-trunc.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir | 414 +- .../CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir | 1106 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir | 6 +- .../CodeGen/AMDGPU/GlobalISel/legalize-umax.mir | 632 +- .../CodeGen/AMDGPU/GlobalISel/legalize-umin.mir | 632 +- .../CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir | 1084 +- .../CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir | 1436 +-- .../CodeGen/AMDGPU/GlobalISel/legalize-usube.mir | 2 +- .../CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir | 456 +- .../CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir | 1054 +- .../GlobalISel/legalize-vector-args-gfx7.mir | 355 + .../GlobalISel/legalize-vector-args-gfx8-plus.mir | 477 + .../CodeGen/AMDGPU/GlobalISel/legalize-xor.mir | 277 +- .../CodeGen/AMDGPU/GlobalISel/legalize-zext.mir | 41 +- .../GlobalISel/llvm.amdgcn.image.load.1d.d16.ll | 27 +- .../AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll | 8119 ++++++------ .../CodeGen/AMDGPU/GlobalISel/load-constant.96.ll | 64 +- .../regbankselect-amdgcn.s.buffer.load.ll | 5042 ++++---- .../AMDGPU/GlobalISel/regbankselect-load.mir | 382 +- .../regbankselect-split-scalar-load-metadata.mir | 30 +- llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll | 946 +- llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll | 910 +- llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll | 509 +- .../AMDGPU/divergence-driven-trunc-to-i1.ll | 59 + llvm/test/CodeGen/AMDGPU/fp-min-max-atomics.ll | 33 +- llvm/test/CodeGen/AMDGPU/lds-atomic-fmin-fmax.ll | 188 +- llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir | 88 + llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll | 15 +- .../test/CodeGen/ARM/2011-01-19-MergedGlobalDbg.ll | 4 +- .../test/CodeGen/ARM/2011-08-02-MergedGlobalDbg.ll | 4 +- llvm/test/CodeGen/RISCV/double-convert-strict.ll | 850 ++ llvm/test/CodeGen/RISCV/float-convert-strict.ll | 719 ++ llvm/test/CodeGen/RISCV/half-convert-strict.ll | 712 + llvm/test/CodeGen/RISCV/inline-asm-invalid.ll | 12 + .../CodeGen/RISCV/rv64d-double-convert-strict.ll | 134 + .../CodeGen/RISCV/rv64f-float-convert-strict.ll | 134 + .../CodeGen/RISCV/rv64f-half-convert-strict.ll | 123 + .../CodeGen/RISCV/rvv/fixed-vectors-marith-vp.ll | 269 + .../RISCV/rvv/fixed-vectors-reduction-fp.ll | 17 + llvm/test/CodeGen/RISCV/rvv/marith-vp.ll | 437 + llvm/test/CodeGen/RISCV/rvv/vmv-copy.mir | 16 +- .../CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll | 14 + llvm/test/CodeGen/X86/funnel-shift-rot.ll | 6 +- llvm/test/CodeGen/X86/vector-fshl-rot-512.ll | 52 +- llvm/test/CodeGen/X86/vector-fshr-rot-128.ll | 130 +- llvm/test/CodeGen/X86/vector-fshr-rot-256.ll | 93 +- llvm/test/CodeGen/X86/vector-fshr-rot-512.ll | 166 +- llvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll | 6 +- llvm/test/CodeGen/X86/vector-rotate-512.ll | 28 +- llvm/test/DebugInfo/AMDGPU/variable-locations.ll | 31 +- llvm/test/DebugInfo/BPF/extern-void.ll | 3 +- .../Generic/cross-cu-linkonce-distinct.ll | 10 +- .../DebugInfo/Generic/debug-info-qualifiers.ll | 4 - .../DebugInfo/Generic/debug-names-linkage-name.ll | 2 +- llvm/test/DebugInfo/Generic/enum-types.ll | 6 +- .../Generic/import-inlined-declaration.ll | 72 - .../DebugInfo/Generic/imported-name-inlined.ll | 10 +- .../Generic/incorrect-variable-debugloc.ll | 3 - llvm/test/DebugInfo/Generic/inlined-local-type.ll | 125 - llvm/test/DebugInfo/Generic/inlined-static-var.ll | 92 - .../test/DebugInfo/Generic/lexical_block_static.ll | 141 - llvm/test/DebugInfo/Generic/lexical_block_types.ll | 421 - llvm/test/DebugInfo/Generic/namespace.ll | 51 +- llvm/test/DebugInfo/Generic/varargs.ll | 12 +- .../MIR/AArch64/implicit-def-dead-scope.mir | 2 +- llvm/test/DebugInfo/NVPTX/debug-addr-class.ll | 154 +- llvm/test/DebugInfo/NVPTX/debug-info.ll | 12876 +++++++++---------- llvm/test/DebugInfo/NVPTX/debug-loc-offset.ll | 154 +- llvm/test/DebugInfo/PowerPC/strict-dwarf.ll | 4 +- .../DebugInfo/X86/2011-09-26-GlobalVarContext.ll | 12 +- .../test/DebugInfo/X86/DW_AT_calling-convention.ll | 8 +- llvm/test/DebugInfo/X86/align_cpp11.ll | 30 +- llvm/test/DebugInfo/X86/align_objc.ll | 13 +- llvm/test/DebugInfo/X86/arange-and-stub.ll | 2 +- .../X86/containing-type-extension-rust.ll | 1 - llvm/test/DebugInfo/X86/convert-loclist.ll | 2 +- llvm/test/DebugInfo/X86/debug-info-access.ll | 8 +- llvm/test/DebugInfo/X86/debug-info-blocks.ll | 8 +- .../test/DebugInfo/X86/debug-info-static-member.ll | 4 - llvm/test/DebugInfo/X86/debug-loc-offset.mir | 31 +- llvm/test/DebugInfo/X86/dwarf-aranges.ll | 12 +- llvm/test/DebugInfo/X86/dwarf-linkage-names.ll | 4 +- .../X86/dwarfdump-DIImportedEntity_elements.ll | 14 +- llvm/test/DebugInfo/X86/generate-odr-hash.ll | 18 +- llvm/test/DebugInfo/X86/gnu-public-names.ll | 43 +- .../DebugInfo/X86/lexical-block-file-inline.ll | 5 + llvm/test/DebugInfo/X86/linkage-name.ll | 2 +- llvm/test/DebugInfo/X86/namelist1.ll | 5 +- llvm/test/DebugInfo/X86/sret.ll | 4 +- llvm/test/DebugInfo/X86/subprogram-across-cus.ll | 6 +- llvm/test/DebugInfo/X86/template.ll | 33 +- llvm/test/DebugInfo/X86/tls.ll | 37 +- .../DebugInfo/X86/type-units-maybe-unused-types.ll | 133 - llvm/test/DebugInfo/X86/vla-global.ll | 3 - llvm/test/DebugInfo/attr-btf_tag.ll | 71 +- llvm/test/MC/WebAssembly/debug-info.ll | 22 +- llvm/test/MC/WebAssembly/debug-info64.ll | 22 +- llvm/test/MC/WebAssembly/dwarfdump.ll | 86 +- llvm/test/MC/WebAssembly/dwarfdump64.ll | 40 +- .../CodeGenPrepare/X86/vec-shift-inseltpoison.ll | 54 +- .../Transforms/CodeGenPrepare/X86/vec-shift.ll | 49 +- .../X86/x86-shuffle-sink-inseltpoison.ll | 36 +- .../CodeGenPrepare/X86/x86-shuffle-sink.ll | 36 +- .../Transforms/Coroutines/coro-split-musttail4.ll | 65 + .../Transforms/Coroutines/coro-split-musttail5.ll | 62 + .../dfa-jump-threading-analysis.ll | 14 +- .../DeadStoreElimination/invariant.start.ll | 10 +- .../test/Transforms/DeadStoreElimination/simple.ll | 5 +- .../stores-of-existing-values.ll | 24 + .../IndVarSimplify/lftr-opaque-pointers.ll | 42 + .../Inline/X86/call-abi-compatibility.ll | 14 +- .../InstCombine/alloca-in-non-alloca-as.ll | 27 +- llvm/test/Transforms/InstSimplify/and.ll | 115 +- .../RISCV/unroll-in-loop-vectorizer.ll | 43 + .../tools/llvm-mca/X86/Generic/resources-avx512.s | 202 +- .../llvm-mca/X86/Generic/resources-avx512bw.s | 52 +- .../llvm-mca/X86/Generic/resources-avx512bwvl.s | 102 +- .../llvm-mca/X86/Generic/resources-avx512vl.s | 402 +- .../llvm-mca/X86/IceLakeServer/resources-avx512.s | 202 +- .../X86/IceLakeServer/resources-avx512bw.s | 52 +- .../X86/IceLakeServer/resources-avx512bwvl.s | 102 +- .../X86/IceLakeServer/resources-avx512vl.s | 402 +- .../llvm-mca/X86/SkylakeServer/resources-avx512.s | 202 +- .../X86/SkylakeServer/resources-avx512bw.s | 52 +- .../X86/SkylakeServer/resources-avx512bwvl.s | 102 +- .../X86/SkylakeServer/resources-avx512vl.s | 402 +- .../CodeGen/GlobalISel/LegalizerHelperTest.cpp | 175 +- llvm/unittests/IR/VerifierTest.cpp | 14 +- llvm/utils/UpdateTestChecks/asm.py | 18 + .../gn/secondary/compiler-rt/lib/asan/BUILD.gn | 11 +- .../gn/secondary/compiler-rt/lib/tsan/rtl/BUILD.gn | 2 + mlir/include/mlir/Analysis/AffineStructures.h | 20 +- .../mlir/Analysis/Presburger/IntegerPolyhedron.h | 10 + mlir/include/mlir/Analysis/Presburger/Utils.h | 40 + mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 4 + mlir/include/mlir/IR/MLIRContext.h | 7 + mlir/include/mlir/Support/DebugAction.h | 3 +- mlir/lib/Analysis/AffineStructures.cpp | 231 +- mlir/lib/Analysis/Presburger/CMakeLists.txt | 2 + mlir/lib/Analysis/Presburger/IntegerPolyhedron.cpp | 54 + mlir/lib/Analysis/Presburger/Utils.cpp | 155 + mlir/lib/Dialect/DLTI/DLTI.cpp | 2 +- mlir/lib/IR/MLIRContext.cpp | 10 + mlir/lib/Transforms/Inliner.cpp | 11 +- .../Utils/GreedyPatternRewriteDriver.cpp | 5 - mlir/test/Target/LLVMIR/llvmir-intrinsics.mlir | 8 + mlir/test/Transforms/inlining.mlir | 1 + mlir/tools/mlir-tblgen/OpFormatGen.cpp | 6 +- mlir/unittests/CMakeLists.txt | 1 + mlir/unittests/Support/CMakeLists.txt | 2 +- polly/include/polly/ScheduleTreeTransform.h | 33 + polly/lib/CodeGen/IslAst.cpp | 2 +- polly/lib/CodeGen/IslExprBuilder.cpp | 4 +- polly/lib/External/isl/isl_int_sioimath.h | 1 - polly/lib/Support/SCEVValidator.cpp | 2 +- polly/lib/Transform/ManualOptimizer.cpp | 1 - polly/lib/Transform/ScheduleOptimizer.cpp | 34 +- polly/lib/Transform/ScheduleTreeTransform.cpp | 29 - polly/lib/Transform/ScopInliner.cpp | 2 +- .../focaltech_test_detail_threshold-7bc17e.ll | 12 +- ...-gen-vivid_vbi_gen_sliced-before-llvmreduced.ll | 45 + third-party/benchmark/src/CMakeLists.txt | 2 +- utils/bazel/llvm-project-overlay/llvm/BUILD.bazel | 39 + 601 files changed, 56771 insertions(+), 43760 deletions(-) create mode 100644 clang/test/Driver/hexagon-hvx-ieee-fp.c create mode 100644 clang/test/Driver/hexagon-hvx-qfloat.c create mode 100644 clang/test/Driver/spirv-toolchain.cl create mode 100644 clang/test/Driver/unsupported-outline-atomics.c rename clang/test/{CodeGenOpenCLCXX => SemaOpenCLCXX}/remove-address-space.clcpp (75%) create mode 100644 compiler-rt/test/sanitizer_common/TestCases/symbolize_pc_demangle.cpp create mode 100644 libcxx/test/libcxx/utilities/format/format.arguments/format.arg [...] rename libcxx/test/std/ranges/range.access/{range.access.begin => }/begin.pass.cpp (100%) rename libcxx/test/std/ranges/range.access/{range.prim => }/data.pass.cpp (100%) rename libcxx/test/std/ranges/range.access/{range.prim => }/empty.pass.cpp (85%) rename libcxx/test/std/ranges/range.access/{range.access.end => }/end.pass.cpp (100%) delete mode 100644 libcxx/test/std/ranges/range.access/range.access.cbegin/cbegin. [...] delete mode 100644 libcxx/test/std/ranges/range.access/range.access.cend/cend.comp [...] rename libcxx/test/std/ranges/range.access/{range.prim => }/size.pass.cpp (100%) rename libcxx/test/std/ranges/range.access/{range.prim => }/ssize.pass.cpp (100%) create mode 100644 lld/test/ELF/linkerscript/ppc32-got2.s create mode 100644 lld/test/ELF/x86-64-tlsdesc-gd-mixed.s create mode 100644 llvm/lib/Target/Hexagon/HexagonScheduleV69.td create mode 100644 llvm/test/CodeGen/AArch64/arm64-raddhn-combine.ll create mode 100644 llvm/test/CodeGen/AArch64/arm64-sqxtn2-combine.ll delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.xfail.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx7.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-vector-args-gfx8-plus.mir create mode 100644 llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll create mode 100644 llvm/test/CodeGen/AMDGPU/same-slot-agpr-sgpr.mir create mode 100644 llvm/test/CodeGen/RISCV/double-convert-strict.ll create mode 100644 llvm/test/CodeGen/RISCV/float-convert-strict.ll create mode 100644 llvm/test/CodeGen/RISCV/half-convert-strict.ll create mode 100644 llvm/test/CodeGen/RISCV/rv64d-double-convert-strict.ll create mode 100644 llvm/test/CodeGen/RISCV/rv64f-float-convert-strict.ll create mode 100644 llvm/test/CodeGen/RISCV/rv64f-half-convert-strict.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/fixed-vectors-marith-vp.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/marith-vp.ll delete mode 100644 llvm/test/DebugInfo/Generic/import-inlined-declaration.ll delete mode 100644 llvm/test/DebugInfo/Generic/inlined-local-type.ll delete mode 100644 llvm/test/DebugInfo/Generic/inlined-static-var.ll delete mode 100644 llvm/test/DebugInfo/Generic/lexical_block_static.ll delete mode 100644 llvm/test/DebugInfo/Generic/lexical_block_types.ll delete mode 100644 llvm/test/DebugInfo/X86/type-units-maybe-unused-types.ll create mode 100644 llvm/test/Transforms/Coroutines/coro-split-musttail4.ll create mode 100644 llvm/test/Transforms/Coroutines/coro-split-musttail5.ll create mode 100644 llvm/test/Transforms/IndVarSimplify/lftr-opaque-pointers.ll create mode 100644 llvm/test/Transforms/LoopVectorize/RISCV/unroll-in-loop-vectorizer.ll create mode 100644 mlir/include/mlir/Analysis/Presburger/Utils.h create mode 100644 mlir/lib/Analysis/Presburger/Utils.cpp create mode 100644 polly/test/ScheduleOptimizer/vivid-vbi-gen-vivid_vbi_gen_sliced [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig updated (b622494ee3 -> 67093b6e1a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig in repository toolchain/ci/binutils-gdb. from b622494ee3 gdb/remote: handle attach when stop packet lacks thread-id adds b6846ba57b gdb/testsuite: resolve some duplicate testnames in gdb.mi adds d20236e748 Automatic date update in version.in adds 5c3ffbc4dd RISC-V: Hypervisor ext: drop Privileged Spec 1.9.1 implement [...] adds a63375ac33 RISC-V: Hypervisor ext: support Privileged Spec 1.12 adds b6a08665ff RISC-V: Rewrite the csr testcases. adds 34b965f7c0 Move gdb_bfd_errmsg to gdb_bfd.c adds 64b7cc507b Remove gdb_print_host_address adds 5436dda805 Automatic date update in version.in adds d16ce6240e Automatic date update in version.in adds 67093b6e1a Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/cpu-riscv.c | 1 + bfd/cpu-riscv.h | 1 + bfd/version.h | 2 +- gas/config/tc-riscv.c | 10 +- gas/testsuite/gas/riscv/csr-dw-regnums.d | 10 - gas/testsuite/gas/riscv/csr-dw-regnums.s | 10 - gas/testsuite/gas/riscv/csr-fail-nonexistent.d | 3 + ...g-fail-nonexistent.l => csr-fail-nonexistent.l} | 0 ...g-fail-nonexistent.s => csr-fail-nonexistent.s} | 0 ...pseudo-noalias.d => csr-insns-pseudo-noalias.d} | 2 +- .../{priv-reg-pseudo.d => csr-insns-pseudo.d} | 2 +- .../{priv-reg-pseudo.s => csr-insns-pseudo.s} | 0 gas/testsuite/gas/riscv/csr-insns-read-only.d | 3 + ...g-fail-read-only-02.l => csr-insns-read-only.l} | 0 ...g-fail-read-only-02.s => csr-insns-read-only.s} | 0 gas/testsuite/gas/riscv/csr-version-1p10.d | 573 +++++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p10.l | 309 +++++++++++ gas/testsuite/gas/riscv/csr-version-1p11.d | 573 +++++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p11.l | 307 +++++++++++ gas/testsuite/gas/riscv/csr-version-1p12.d | 573 +++++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p12.l | 255 +++++++++ gas/testsuite/gas/riscv/csr-version-1p9p1.d | 573 +++++++++++++++++++++ gas/testsuite/gas/riscv/csr-version-1p9p1.l | 335 ++++++++++++ gas/testsuite/gas/riscv/{priv-reg.s => csr.s} | 74 ++- gas/testsuite/gas/riscv/h-ext-32.d | 30 ++ gas/testsuite/gas/riscv/h-ext-32.s | 21 + gas/testsuite/gas/riscv/h-ext-64.d | 33 ++ gas/testsuite/gas/riscv/h-ext-64.s | 24 + gas/testsuite/gas/riscv/priv-reg-fail-fext.d | 3 - gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 - .../gas/riscv/priv-reg-fail-nonexistent.d | 3 - .../gas/riscv/priv-reg-fail-read-only-01.d | 3 - .../gas/riscv/priv-reg-fail-read-only-01.l | 71 --- .../gas/riscv/priv-reg-fail-read-only-01.s | 269 ---------- .../gas/riscv/priv-reg-fail-read-only-02.d | 3 - gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d | 3 - gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 68 --- .../gas/riscv/priv-reg-fail-version-1p10.d | 11 - .../gas/riscv/priv-reg-fail-version-1p10.l | 25 - .../gas/riscv/priv-reg-fail-version-1p11.d | 11 - .../gas/riscv/priv-reg-fail-version-1p11.l | 24 - .../gas/riscv/priv-reg-fail-version-1p9p1.d | 12 - .../gas/riscv/priv-reg-fail-version-1p9p1.l | 28 - gas/testsuite/gas/riscv/priv-reg-fail-zkr.d | 3 - gas/testsuite/gas/riscv/priv-reg-fail-zkr.l | 4 - gas/testsuite/gas/riscv/priv-reg-version-1p10.d | 275 ---------- gas/testsuite/gas/riscv/priv-reg-version-1p11.d | 275 ---------- gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d | 275 ---------- gdb/dummy-frame.c | 12 +- gdb/gdb_bfd.c | 30 ++ gdb/gdb_bfd.h | 7 + gdb/gdbtypes.c | 161 +++--- gdb/psymtab.c | 46 +- gdb/symmisc.c | 48 +- gdb/testsuite/gdb.mi/mi-syn-frame.exp | 12 +- gdb/testsuite/gdb.mi/mi-var-child.exp | 10 +- gdb/testsuite/gdb.mi/mi-var-rtti.cc | 48 +- gdb/testsuite/gdb.mi/mi-watch.exp | 2 +- gdb/testsuite/gdb.mi/mi2-amd64-entry-value.exp | 236 +++++---- gdb/testsuite/gdb.mi/mi2-var-child.exp | 10 +- gdb/utils.c | 36 -- gdb/utils.h | 14 - include/opcode/riscv-opc.h | 120 ++++- opcodes/riscv-opc.c | 21 + 64 files changed, 4116 insertions(+), 1793 deletions(-) create mode 100644 gas/testsuite/gas/riscv/csr-fail-nonexistent.d rename gas/testsuite/gas/riscv/{priv-reg-fail-nonexistent.l => csr-fail-nonexisten [...] rename gas/testsuite/gas/riscv/{priv-reg-fail-nonexistent.s => csr-fail-nonexisten [...] rename gas/testsuite/gas/riscv/{priv-reg-pseudo-noalias.d => csr-insns-pseudo-noal [...] rename gas/testsuite/gas/riscv/{priv-reg-pseudo.d => csr-insns-pseudo.d} (98%) rename gas/testsuite/gas/riscv/{priv-reg-pseudo.s => csr-insns-pseudo.s} (100%) create mode 100644 gas/testsuite/gas/riscv/csr-insns-read-only.d rename gas/testsuite/gas/riscv/{priv-reg-fail-read-only-02.l => csr-insns-read-onl [...] rename gas/testsuite/gas/riscv/{priv-reg-fail-read-only-02.s => csr-insns-read-onl [...] create mode 100644 gas/testsuite/gas/riscv/csr-version-1p10.d create mode 100644 gas/testsuite/gas/riscv/csr-version-1p10.l create mode 100644 gas/testsuite/gas/riscv/csr-version-1p11.d create mode 100644 gas/testsuite/gas/riscv/csr-version-1p11.l create mode 100644 gas/testsuite/gas/riscv/csr-version-1p12.d create mode 100644 gas/testsuite/gas/riscv/csr-version-1p12.l create mode 100644 gas/testsuite/gas/riscv/csr-version-1p9p1.d create mode 100644 gas/testsuite/gas/riscv/csr-version-1p9p1.l rename gas/testsuite/gas/riscv/{priv-reg.s => csr.s} (82%) create mode 100644 gas/testsuite/gas/riscv/h-ext-32.d create mode 100644 gas/testsuite/gas/riscv/h-ext-32.s create mode 100644 gas/testsuite/gas/riscv/h-ext-64.d create mode 100644 gas/testsuite/gas/riscv/h-ext-64.s delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-fext.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-fext.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-nonexistent.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-01.s delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-read-only-02.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p10.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p11.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-version-1p9p1.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-zkr.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-fail-zkr.l delete mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p10.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p11.d delete mode 100644 gas/testsuite/gas/riscv/priv-reg-version-1p9p1.d -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig updated (c20a94483 -> 187d0fad2)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards c20a94483 2: update: binutils-llvm-linux-qemu: 20154 new 187d0fad2 2: update: binutils-llvm-linux-qemu: 20154 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (c20a94483) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1600 -> 1564 bytes 02-prepare_abe/console.log.xz | Bin 2776 -> 2768 bytes 03-build_abe-binutils/console.log.xz | Bin 31612 -> 30308 bytes 04-build_llvm/console.log.xz | Bin 59760 -> 59936 bytes 05-build_abe-qemu/console.log.xz | Bin 30096 -> 30732 bytes 06-build_linux/console.log.xz | Bin 3932 -> 3888 bytes 08-check_regression/console.log.xz | Bin 480 -> 480 bytes 09-update_baseline/console.log | 60 +++++++++++++++++------------------ jenkins/manifest.sh | 16 +++++----- 9 files changed, 38 insertions(+), 38 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_ubsan updated (9525c26bf19 -> e078de24eae)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_ubsan in repository toolchain/ci/gcc. from 9525c26bf19 Fortran: speed up decimal output of integers adds d87483015d4 i386: Check AX input in any_mul_highpart peepholes adds ad6091d1b89 Daily bump. adds 500d3f0a302 RISC-V: fixed testcase riscv/pr103302.c adds e078de24eae testsuite: Avoid unwanted vecorization [PR95046] No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 6 +++++ gcc/DATESTAMP | 2 +- gcc/config/i386/i386.md | 10 +++++--- gcc/testsuite/ChangeLog | 10 ++++++++ gcc/testsuite/gcc.target/i386/pr103785.c | 38 +++++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/pr103302.c | 2 +- gcc/testsuite/gfortran.dg/extract_recip_1.f | 2 +- libgfortran/ChangeLog | 7 ++++++ 8 files changed, 71 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr103785.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_ubsan updated (d16ce6240e -> 67093b6e1a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_ubsan in repository toolchain/ci/binutils-gdb. from d16ce6240e Automatic date update in version.in adds 67093b6e1a Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_ubsan updated (c61f1670e -> b14aeb37d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gcc_bootstrap/master-aarch64-bootstrap_ubsan in repository toolchain/ci/base-artifacts. discards c61f1670e 0: update: binutils-gcc: 2 new b14aeb37d 0: update: binutils-gcc: 2 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (c61f1670e) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gcc_bootstrap/master-aar [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log.xz | Bin 1516 -> 1576 bytes 02-prepare_abe/console.log.xz | Bin 2752 -> 2772 bytes 04-build_abe-binutils/console.log.xz | Bin 37444 -> 39048 bytes 05-build_abe-bootstrap_ubsan/console.log.xz | Bin 319568 -> 318476 bytes 06-check_regression/console.log.xz | Bin 420 -> 416 bytes 07-update_baseline/console.log | 36 ---------------------------- jenkins/manifest.sh | 12 +++++----- 7 files changed, 6 insertions(+), 42 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

[gcc] branch master updated (e078de24eae -> 9407058a430)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from e078de24eae testsuite: Avoid unwanted vecorization [PR95046] new 9407058a430 ix86: Don't use the 'm' constraint for x86_64_general_operand The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/i386/constraints.md | 10 + gcc/config/i386/i386.md | 67 +-- gcc/testsuite/gcc.target/i386/pr103762-1a.c | 647 ++++++++++++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr103762-1b.c | 7 + gcc/testsuite/gcc.target/i386/pr103762-1c.c | 7 + 5 files changed, 706 insertions(+), 32 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr103762-1a.c create mode 100644 gcc/testsuite/gcc.target/i386/pr103762-1b.c create mode 100644 gcc/testsuite/gcc.target/i386/pr103762-1c.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

2 years, 11 months

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