Tcwg-commits January 2021

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9360 discussions

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig updated (41192db338 -> e551455f1e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig in repository toolchain/ci/qemu. from 41192db338 Merge remote-tracking branch 'remotes/ehabkost-gl/tags/machi [...] adds 593621f36b readline: Fix possible array index out of bounds in readline [...] adds e551455f1e Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/b [...] No new revisions were added by this update. Summary of changes: util/readline.c | 3 +++ 1 file changed, 3 insertions(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig updated (8837f82e4ba -> 15af33a8806)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig in repository toolchain/ci/gcc. from 8837f82e4ba tree-optimization/98291 - allow SLP more vectorization of r [...] adds ff6b4062479 avr.exp: convert Dos newlines to Unix ones adds a40718b5fc8 Convert 2 files to utf8. adds 0926259f9fc tree-optimization/98393 - properly init matches when failing SLP adds ba15b0fa0df aarch64: Use the MUL VL form of SVE PRF[BHWD] adds b41e6dd50f3 aarch64: Improve vcombine codegen [PR89057] adds 13b80a7d1b9 tree-optimization/98282 - classify V_C_E<constant> as nary adds 7f2b7317566 docs: Fix wording describing the hwaddress sanitizer adds 39bd65faee3 tree-optimization/98464 - replace loop info with avail at uses adds 24cd9afe617 loop-niter: Recognize popcount idioms even with char, short [...] adds 9e79d76a16c tree-optimization/98308 - set vector type for mask of masked load adds 6bbc196c64d [libcody] Windows absdir fix adds 6288183377a [libcody] Remove some std::move [PR 98368] adds aa204d51185 vect, aarch64: Fix alignment units for IFN_MASK* [PR95401] adds a5469584f61 c++: Add stdlib module test cases adds f262a351887 MAINTAINERS: Update my email address. adds a000eb5918e C: Add test for incorrect warning for assignment of certain [...] new 7e73f511573 Daily bump. new 15af33a8806 analyzer: fix ICE with -fsanitize=undefined [PR98293] The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: ChangeLog | 4 + MAINTAINERS | 2 +- c++tools/ChangeLog | 5 + c++tools/resolver.cc | 4 +- contrib/ChangeLog | 19 +++ gcc/ChangeLog | 84 +++++++++++ gcc/DATESTAMP | 2 +- gcc/analyzer/store.cc | 19 ++- gcc/config/aarch64/aarch64-simd.md | 15 +- gcc/config/aarch64/aarch64-sve-builtins.cc | 2 +- gcc/config/aarch64/aarch64.c | 17 ++- gcc/doc/invoke.texi | 4 +- gcc/fortran/ChangeLog | 4 + gcc/gimple-fold.c | 2 +- gcc/testsuite/ChangeLog | 127 +++++++++++++++++ gcc/testsuite/README | 2 +- gcc/testsuite/g++.dg/modules/binding-1_a.H | 4 + gcc/testsuite/g++.dg/modules/binding-1_b.H | 4 + gcc/testsuite/g++.dg/modules/binding-1_c.C | 7 + gcc/testsuite/g++.dg/modules/binding-2.H | 9 ++ gcc/testsuite/g++.dg/modules/builtin-3_a.C | 44 ++++++ gcc/testsuite/g++.dg/modules/global-2_a.C | 22 +++ gcc/testsuite/g++.dg/modules/global-2_b.C | 10 ++ gcc/testsuite/g++.dg/modules/global-3_a.C | 16 +++ gcc/testsuite/g++.dg/modules/global-3_b.C | 9 ++ gcc/testsuite/g++.dg/modules/hello-1_a.C | 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gcc/testsuite/g++.dg/modules/xtreme-header-1_b.C | 4 + gcc/testsuite/g++.dg/modules/xtreme-header-1_c.C | 3 + gcc/testsuite/g++.dg/modules/xtreme-header-2.h | 14 ++ gcc/testsuite/g++.dg/modules/xtreme-header-2_a.H | 4 + gcc/testsuite/g++.dg/modules/xtreme-header-2_b.C | 4 + gcc/testsuite/g++.dg/modules/xtreme-header-2_c.C | 3 + gcc/testsuite/g++.dg/modules/xtreme-header-3.h | 21 +++ gcc/testsuite/g++.dg/modules/xtreme-header-3_a.H | 4 + gcc/testsuite/g++.dg/modules/xtreme-header-3_b.C | 4 + gcc/testsuite/g++.dg/modules/xtreme-header-3_c.C | 3 + gcc/testsuite/g++.dg/modules/xtreme-header-4.h | 17 +++ gcc/testsuite/g++.dg/modules/xtreme-header-4_a.H | 4 + gcc/testsuite/g++.dg/modules/xtreme-header-4_b.C | 4 + gcc/testsuite/g++.dg/modules/xtreme-header-4_c.C | 3 + gcc/testsuite/g++.dg/modules/xtreme-header-5.h | 22 +++ gcc/testsuite/g++.dg/modules/xtreme-header-5_a.H | 4 + gcc/testsuite/g++.dg/modules/xtreme-header-5_b.C | 4 + gcc/testsuite/g++.dg/modules/xtreme-header-5_c.C | 3 + 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.../gcc.target/aarch64/sve/acle/asm/prfd.c | 47 +++++-- .../gcc.target/aarch64/sve/acle/asm/prfh.c | 47 +++++-- .../gcc.target/aarch64/sve/acle/asm/prfw.c | 47 +++++-- gcc/testsuite/gcc.target/avr/avr.exp | 80 +++++------ gcc/testsuite/gcc.target/i386/pr95771.c | 67 +++++++++ gcc/tree-ssa-loop-niter.c | 45 ++++-- gcc/tree-ssa-sccvn.c | 26 +++- gcc/tree-vect-slp.c | 1 + gcc/tree-vect-stmts.c | 25 +++- libcody/ChangeLog | 9 ++ libcody/client.cc | 3 +- libcody/resolver.cc | 4 +- libiberty/ChangeLog | 4 + libiberty/strverscmp.c | 2 +- 96 files changed, 1641 insertions(+), 145 deletions(-) create mode 100644 gcc/testsuite/g++.dg/modules/binding-1_a.H create mode 100644 gcc/testsuite/g++.dg/modules/binding-1_b.H create mode 100644 gcc/testsuite/g++.dg/modules/binding-1_c.C create mode 100644 gcc/testsuite/g++.dg/modules/binding-2.H create mode 100644 gcc/testsuite/g++.dg/modules/builtin-3_a.C create mode 100644 gcc/testsuite/g++.dg/modules/global-2_a.C create mode 100644 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gcc/testsuite/g++.dg/modules/xtreme-header-3_b.C create mode 100644 gcc/testsuite/g++.dg/modules/xtreme-header-3_c.C create mode 100644 gcc/testsuite/g++.dg/modules/xtreme-header-4.h create mode 100644 gcc/testsuite/g++.dg/modules/xtreme-header-4_a.H create mode 100644 gcc/testsuite/g++.dg/modules/xtreme-header-4_b.C create mode 100644 gcc/testsuite/g++.dg/modules/xtreme-header-4_c.C create mode 100644 gcc/testsuite/g++.dg/modules/xtreme-header-5.h create mode 100644 gcc/testsuite/g++.dg/modules/xtreme-header-5_a.H create mode 100644 gcc/testsuite/g++.dg/modules/xtreme-header-5_b.C create mode 100644 gcc/testsuite/g++.dg/modules/xtreme-header-5_c.C create mode 100644 gcc/testsuite/g++.dg/modules/xtreme-header-6.h create mode 100644 gcc/testsuite/g++.dg/modules/xtreme-header-6_a.H create mode 100644 gcc/testsuite/g++.dg/modules/xtreme-header-6_b.C create mode 100644 gcc/testsuite/g++.dg/modules/xtreme-header-6_c.C create mode 100644 gcc/testsuite/g++.dg/modules/xtreme-header.h create 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3 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig updated (5b4293ba3c -> 9353bb9ed6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig in repository toolchain/ci/binutils-gdb. from 5b4293ba3c PR26822, How to prevent a STT_FILE with absolute path in the [...] adds dbb078f66e When displaying ARM private file flag bits, use a 0x prefix. adds 098caef485 Refactor struct trad_frame_saved_regs adds c5e71b3332 [gdb/testsuite] Don't require gold for gdb.base/morestack.exp adds a754fbdfa2 gdb/testsuite: use clean_restart in gdb.server/solib-list.exp adds 7b0ff8a22a gdb/testsuite: use build_executable in gdb.server/stop-reply [...] adds 5169ae34bc gdb/testsuite: use clean_restart in gdb.server/ext-run.exp adds d8387cc8b6 gdb/testsuite: use clean_restart in gdb.server/server-run.exp adds 8dc558a072 gdb/testsuite: avoid reading files through the remote protoc [...] adds 335709bc5a gdb: make "set debug timestamp" work nice with new debug printouts adds e71daf80d3 gdb: use infrun_debug_printf in print_target_wait_results adds 3ec3145c5d gdb: introduce scoped debug prints adds e4ad960a57 [gdb/symtab] Remove superfluous end-of-sequence marker adds cd6d537c48 elf: Allow mixed ordered/unordered inputs for non-relocatable link adds dbed468bcb sim: common: rename sim_print_config adds 19b1c38562 sim: common: add a version output helper w/copyright+license info adds 2b667e3297 sim: common: use sim_config_print name adds babd2ee15d sim: common: version: add build & homepage info when interactive adds dfb856ba26 sim: update bug URI to https:// adds c68ea49f59 gdb: bfin: use align helper new 9353bb9ed6 Automatic date update in version.in The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: bfd/ChangeLog | 21 +++ bfd/bfd-in2.h | 7 +- bfd/elf32-arm.c | 4 +- bfd/elflink.c | 83 +++++++--- bfd/elfnn-aarch64.c | 4 +- bfd/section.c | 7 +- bfd/version.h | 2 +- gas/ChangeLog | 6 + gas/config/obj-elf.c | 4 +- gdb/ChangeLog | 97 ++++++++++++ gdb/aarch64-tdep.c | 47 +++--- gdb/alpha-mdebug-tdep.c | 8 +- gdb/alpha-tdep.c | 7 +- gdb/arc-tdep.c | 11 +- gdb/arm-tdep.c | 62 ++++---- gdb/avr-tdep.c | 33 ++-- gdb/bfin-tdep.c | 6 +- gdb/buildsym.c | 9 +- gdb/cris-tdep.c | 47 +++--- gdb/csky-tdep.c | 10 +- gdb/debug.c | 4 + gdb/frame-unwind.c | 2 +- gdb/frame-unwind.h | 2 +- gdb/frv-tdep.c | 9 +- gdb/hppa-linux-tdep.c | 20 +-- gdb/hppa-tdep.c | 40 ++--- gdb/hppa-tdep.h | 4 +- gdb/infrun.c | 45 +++--- gdb/infrun.h | 10 ++ gdb/lm32-tdep.c | 9 +- gdb/m32r-linux-tdep.c | 6 +- gdb/m32r-tdep.c | 7 +- gdb/m68hc11-tdep.c | 26 ++-- gdb/mips-tdep.c | 16 +- gdb/moxie-tdep.c | 2 +- gdb/riscv-tdep.c | 5 +- gdb/rs6000-tdep.c | 27 ++-- gdb/s390-linux-tdep.c | 18 +-- gdb/s390-tdep.c | 18 +-- gdb/score-tdep.c | 26 ++-- gdb/sparc-netbsd-tdep.c | 36 ++--- gdb/sparc-sol2-tdep.c | 14 +- gdb/sparc64-fbsd-tdep.c | 24 +-- gdb/sparc64-netbsd-tdep.c | 30 ++-- gdb/sparc64-obsd-tdep.c | 10 +- gdb/sparc64-sol2-tdep.c | 18 +-- gdb/testsuite/ChangeLog | 51 ++++++ gdb/testsuite/gdb.base/morestack.c | 5 +- gdb/testsuite/gdb.base/morestack.exp | 8 +- gdb/testsuite/gdb.base/ui-redirect.exp | 9 +- .../gdb.dwarf2/dw2-out-of-range-end-of-seq.exp | 94 +++++++++++ gdb/testsuite/gdb.server/abspath.exp | 13 +- .../gdb.server/connect-without-multi-process.exp | 12 +- gdb/testsuite/gdb.server/exit-multiple-threads.exp | 12 +- gdb/testsuite/gdb.server/ext-attach.exp | 12 +- gdb/testsuite/gdb.server/ext-restart.exp | 12 +- gdb/testsuite/gdb.server/ext-run.exp | 18 ++- gdb/testsuite/gdb.server/ext-wrapper.exp | 12 +- gdb/testsuite/gdb.server/multi-ui-errors.exp | 12 +- gdb/testsuite/gdb.server/no-thread-db.exp | 10 +- gdb/testsuite/gdb.server/reconnect-ctrl-c.exp | 13 +- .../gdb.server/run-without-local-binary.exp | 7 + gdb/testsuite/gdb.server/server-kill.exp | 11 +- gdb/testsuite/gdb.server/server-run.exp | 13 +- gdb/testsuite/gdb.server/solib-list.exp | 14 +- gdb/testsuite/gdb.server/stop-reply-no-thread.exp | 14 +- gdb/testsuite/gdb.server/sysroot.exp | 54 ++++--- gdb/testsuite/gdb.server/wrapper.exp | 12 +- gdb/testsuite/gdb.threads/ia64-sigill.exp | 16 +- gdb/testsuite/gdb.threads/stepi-random-signal.exp | 5 +- gdb/testsuite/gdb.threads/watchthreads-reorder.exp | 7 +- gdb/tilegx-tdep.c | 19 ++- gdb/trad-frame.c | 84 +++++----- gdb/trad-frame.h | 173 ++++++++++++++++----- gdb/utils.c | 34 ++-- gdb/v850-tdep.c | 9 +- gdb/vax-tdep.c | 12 +- gdbserver/ChangeLog | 4 + gdbserver/debug.cc | 4 + gdbsupport/ChangeLog | 8 + gdbsupport/common-debug.cc | 2 +- gdbsupport/common-debug.h | 81 +++++++++- ld/ChangeLog | 19 +++ ld/ldlang.c | 4 +- ld/testsuite/ld-elf/pr26256-1.s | 20 +++ ld/testsuite/ld-elf/pr26256-1.t | 13 ++ ld/testsuite/ld-elf/pr26256-1a.d | 7 + ld/testsuite/ld-elf/pr26256-1b.d | 7 + ld/testsuite/ld-elf/pr26256-2.s | 32 ++++ ld/testsuite/ld-elf/pr26256-2.t | 9 ++ ld/testsuite/ld-elf/pr26256-2a.d | 20 +++ ld/testsuite/ld-elf/pr26256-2b-alt.d | 21 +++ ld/testsuite/ld-elf/pr26256-2b.d | 22 +++ ld/testsuite/ld-elf/pr26256-3.s | 27 ++++ ld/testsuite/ld-elf/pr26256-3a.d | 11 ++ ld/testsuite/ld-elf/pr26256-3a.t | 17 ++ ld/testsuite/ld-elf/pr26256-3b.d | 12 ++ ld/testsuite/ld-elf/pr26256-3b.t | 16 ++ sim/aarch64/ChangeLog | 4 + sim/aarch64/configure | 2 +- sim/arm/ChangeLog | 4 + sim/arm/configure | 2 +- sim/avr/ChangeLog | 4 + sim/avr/configure | 2 +- sim/bfin/configure | 2 +- sim/bpf/configure | 2 +- sim/common/ChangeLog | 22 +++ sim/common/acinclude.m4 | 2 +- sim/common/sim-config.c | 2 +- sim/common/sim-config.h | 2 +- sim/common/sim-options.c | 37 ++++- sim/common/sim-options.h | 4 + sim/cr16/ChangeLog | 4 + sim/cr16/configure | 2 +- sim/cris/ChangeLog | 4 + sim/cris/configure | 2 +- sim/d10v/ChangeLog | 4 + sim/d10v/configure | 2 +- sim/erc32/ChangeLog | 4 + sim/erc32/configure | 2 +- sim/frv/ChangeLog | 4 + sim/frv/configure | 2 +- sim/ft32/ChangeLog | 4 + sim/ft32/configure | 2 +- sim/h8300/ChangeLog | 4 + sim/h8300/configure | 2 +- sim/igen/ChangeLog | 4 + sim/iq2000/ChangeLog | 4 + sim/iq2000/configure | 2 +- sim/lm32/ChangeLog | 4 + sim/lm32/configure | 2 +- sim/m32c/ChangeLog | 4 + sim/m32c/configure | 2 +- sim/m32r/ChangeLog | 4 + sim/m32r/configure | 2 +- sim/m68hc11/ChangeLog | 4 + sim/m68hc11/configure | 2 +- sim/mcore/ChangeLog | 4 + sim/mcore/configure | 2 +- sim/microblaze/ChangeLog | 4 + sim/microblaze/configure | 2 +- sim/mips/ChangeLog | 4 + sim/mips/configure | 2 +- sim/mn10300/ChangeLog | 4 + sim/mn10300/configure | 2 +- sim/moxie/ChangeLog | 4 + sim/moxie/configure | 2 +- sim/msp430/ChangeLog | 4 + sim/msp430/configure | 2 +- sim/or1k/configure | 2 +- sim/ppc/ChangeLog | 5 + sim/ppc/configure | 2 +- sim/ppc/configure.ac | 2 +- sim/pru/ChangeLog | 4 + sim/pru/configure | 2 +- sim/rl78/ChangeLog | 4 + sim/rl78/configure | 2 +- sim/rx/ChangeLog | 4 + sim/rx/configure | 2 +- sim/sh/ChangeLog | 4 + sim/sh/configure | 2 +- sim/sh64/ChangeLog | 4 + sim/sh64/configure | 2 +- sim/testsuite/ChangeLog | 4 + sim/v850/ChangeLog | 4 + sim/v850/configure | 2 +- 166 files changed, 1691 insertions(+), 599 deletions(-) create mode 100644 gdb/testsuite/gdb.dwarf2/dw2-out-of-range-end-of-seq.exp create mode 100644 ld/testsuite/ld-elf/pr26256-1.s create mode 100644 ld/testsuite/ld-elf/pr26256-1.t create mode 100644 ld/testsuite/ld-elf/pr26256-1a.d create mode 100644 ld/testsuite/ld-elf/pr26256-1b.d create mode 100644 ld/testsuite/ld-elf/pr26256-2.s create mode 100644 ld/testsuite/ld-elf/pr26256-2.t create mode 100644 ld/testsuite/ld-elf/pr26256-2a.d create mode 100644 ld/testsuite/ld-elf/pr26256-2b-alt.d create mode 100644 ld/testsuite/ld-elf/pr26256-2b.d create mode 100644 ld/testsuite/ld-elf/pr26256-3.s create mode 100644 ld/testsuite/ld-elf/pr26256-3a.d create mode 100644 ld/testsuite/ld-elf/pr26256-3a.t create mode 100644 ld/testsuite/ld-elf/pr26256-3b.d create mode 100644 ld/testsuite/ld-elf/pr26256-3b.t -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig updated (a4ff044af -> 9a7efbe70)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig in repository toolchain/ci/base-artifacts. discards a4ff044af 0: update: binutils-gcc-linux-qemu: boot new 9a7efbe70 0: update: binutils-gcc-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (a4ff044af) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-lt [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 157 +- 02-prepare_abe/console.log | 418 +- 03-build_abe-binutils/console.log | 11570 +++++---- 04-build_abe-stage1/console.log | 20541 +++++++-------- 05-build_linux/console.log | 782 +- 06-build_abe-qemu/console.log | 6716 +++-- 07-boot_linux/console.log | 496 +- 08-check_regression/console.log | 18 +- 08-check_regression/results.regressions | 2 +- 09-update_baseline/console.log | 22 +- 09-update_baseline/results.regressions | 2 +- console.log | 40742 +++++++++++++++--------------- jenkins/manifest.sh | 18 +- 13 files changed, 40706 insertions(+), 40778 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig updated (41192db338 -> e551455f1e)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig in repository toolchain/ci/qemu. from 41192db338 Merge remote-tracking branch 'remotes/ehabkost-gl/tags/machi [...] adds 593621f36b readline: Fix possible array index out of bounds in readline [...] adds e551455f1e Merge remote-tracking branch 'remotes/stefanha-gitlab/tags/b [...] No new revisions were added by this update. Summary of changes: util/readline.c | 3 +++ 1 file changed, 3 insertions(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig updated (01f0d162d67 -> c4f12a07a44)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig in repository toolchain/ci/llvm-project. from 01f0d162d67 Moving UniqueInternalLinkageNamesPass to the start of IR pi [...] adds 7c8b8063b66 [SimplifyCFG][AMDGPU] AMDGPUUnifyDivergentExitNodes: Simpli [...] adds 19ab1817b61 [llvm-reduce] Fix removal of unused llvm intrinsics declarations adds 5799fc79c3f [llvm-reduce] Refactor global variable delta pass adds eda50309f59 [NFC][SimplifyCFG] Add test for switch creation where we fa [...] adds 6a3a8d17eba [SimplifyCFG] FoldValueComparisonIntoPredecessors(): fine-t [...] adds a0013934b6a [NFC][SimplifyCFG] Add another test for switch creation whe [...] adds 5fa241a6571 [SimplifyCFG] FoldValueComparisonIntoPredecessors(): fine-t [...] adds 835bdd17761 [gn build] Port 5799fc79c3f adds a554cd6ae5b [RuntimeDyld] Fix dangling reference in RuntimeDyldELF. adds fe9976c02c0 Revert "[sanitizer] Define SANITIZER_GLIBC to refine SANITI [...] adds f5f7ff8d0fa [dsymutil][DWARFLinker][NFC] Refactor usages of UniquingStr [...] adds d9c0b128e35 [SCEV] Simplify trunc to zero based on known bits adds c5a7e75eb6b Update *-inseltpoison.ll tests at Transforms/InstCombine/X8 [...] adds 1fc992bd864 [Scalarizer] Use poison as insertelement's placeholder adds 578c5a0c6e7 [ArgPromotion] Add test with dead GEP when promoting. adds 2139958b534 [InstSimplify] Return poison if insertelement touches out o [...] adds 858b99d774f [InstSimplify] Regenerate test checks (NFC) adds 49c2d703d34 [X86] Make deinterleave8bitStride3 use unary CreateShuffleVector adds c6ad00d7098 [InstSimplify] Return poison for out of bounds extractelement adds f094d65beaa [InstSimplify] Fix addo/subo with undef (PR43188) adds 985f899bf2c [Target] Use llvm::append_range (NFC) adds 0e219b6443b [Target] Construct SmallVector with iterator ranges (NFC) adds ba82c0b3157 [llvm] Call *(Set|Map)::erase directly (NFC) adds 766cf7f32e4 [InstSimplify] Fold division by zero to poison adds edb52c626b5 [LoopUnswitch] Precommit initial partial unswitching test cases. adds 3715c99be9d [InstSimplify] Fold nnan/ninf violation to poison adds 4fc908025fd [NFC][SimplifyCFG] Add a test where we fail to preserve Dom [...] adds 70935b9595a [NFC][SimplifyCFG] SimplifyTerminatorOnSelect(): pull out O [...] adds a7684940f0e [SimplifyCFG] SimplifyTerminatorOnSelect(): fix/tune DomTre [...] adds 98cd1c33e3c [NFC][SimplifyCFG] Hoist 'original' DomTree verification fr [...] adds 59810c51e76 [clang-tidy] Fix windows tests adds 6988f7a6f4a [compiler-rt] [Sanitizers] Extend ThreadDescriptorSize() fo [...] adds 6280bc1cc34 [Flang][openmp][5.0] Add task_reduction clause. adds 05e6ac4eb81 [IROutliner] Removing a duplicate addition, causing overest [...] adds 5c951623bc8 [IROutliner] Refactoring errors in the cost model from past [...] adds f6515b05205 [PowerPC] Do not fold `cmp(d|w)` and `subf` instruction to [...] adds 09b3f3f22cb [benchmark] Fixed a build error when using CMake 3.15.1 + NDK-R20 adds 94257d12cb2 [RISCV] Remove unused method isUImm5NonZero() from RISCVAsm [...] adds a65092040ad [SVE] Fix inline assembly parsing crash adds 74e7cb26b9a [VE] Remove VA.needsCustom checks adds e43b3d1f5e0 Revert "[Sema] Fix deleted function problem in implicitly m [...] adds e0905553b42 [ArgPromotion] Delay dead GEP removal until doPromotion. adds 685c8b537af [AARCH64] Improve accumulator forwarding for Cortex-A57 model adds c287f90ccd3 [VE] Change default CPU name to "generic" adds 6c89f6fae49 [AArch64] Attempt to fix Mac tests with a more specific tri [...] adds 975b64b2937 [docs] Release notes for IsDecl in DIModule. adds 42652c1d6e2 [Sparc] Fixes for the internal assembler adds 901cc9b6f30 [ARM] Extend lowering for i64 reductions adds 23b41986527 [Support] Add KnownBits::icmp helpers. adds d38a0258a5f [AArch64] Add patterns for FMCLA*_indexed. adds 060cfd97954 [AArch64][SVE]Add cost model for masked gather and scatter [...] adds 4d7cb6da9fc [Sparc] SparcMCExpr::printVariantKind - fix Wcovered-switch [...] adds 82a29a62aba [OpenMP] Add definition/interface for target memory routines adds 9f8c0d15c7f DeclCXX - Fix getAs<> null-dereference static analyzer warn [...] adds e9f401d8a26 [IR] CallBase::getBundleOpInfoForOperand - ensure Current i [...] adds ed936aad781 [InterleavedAccess] Return correct 'modified' status. adds e2d3d501ef8 [RISCV][NFC] Add additional cmov tests adds c367258b5cc [SimplifyCFG] Enabled hoisting late in LTO pipeline. adds c55b609b777 [Hexagon] Fix bad SDNodeXForm adds 76bfbb74d38 [libomptarget][amdgpu] Call into deviceRTL instead of ockl adds f7463ca3cc5 [ProfileData] GCOVFile::readGCNO - silence undefined pointe [...] adds fe5d51a4897 [OpenMP] Add using bit flags to select Libomptarget Information adds dd6bb367d19 [LoopDeletion] Break backedge of loops when known not taken adds 7c63aac7bd4 Revert "[LoopDeletion] Break backedge of loops when known n [...] adds d8938c8bb54 CodeGen: Use Register adds 6976812129b [InstCombine] add tests for ashr+icmp; NFC adds dc9ac0e8207 [RISCV] Replace i32 with XLenVT in (add AddrFI, simm12) ise [...] adds b8f22f9d300 [NewPM][AMDGPU] Run InternalizePass when -amdgpu-internaliz [...] adds 848e8f938fd [llvm] Construct SmallVector with iterator ranges (NFC) adds 0edbc90ec56 [DebugInfo] Use llvm::append_range (NFC) adds eb198f4c3ce [llvm] Use llvm::any_of (NFC) adds a5f863e0765 [NewPM][AMDGPU] Port amdgpu-propagate-attributes-early/late adds e1833e7493a [NewPM][AMDGPU] Port amdgpu-unify-metadata adds 9a17bff4f71 [LoopNest] Allow empty basic blocks without loops adds 4034f9273ed Switching Clang UniqueInternalLinkageNamesPass scheduling t [...] adds 4d0aad96e43 [flang][openmp] Make Reduction clause part of OmpClause adds fe597efc30b [RISCV] Remove unused method RISCVInstPrinter::printSImm5Pl [...] adds fd323a897c6 [NewPM][AMDGPU] Port amdgpu-printf-runtime-binding adds 4e838ba9ea2 [NewPM][AMDGPU] Port amdgpu-always-inline adds 191552344bb [NewPM][AMDGPU] Make amdgpu-aa work with NewPM adds de6d43f16cb Revert "[LoopNest] Allow empty basic blocks without loops" adds 92be640bd7d [FPEnv][AMDGPU] Disable FSUB(-0,X)->FNEG(X) DAGCombine when [...] adds 58b6c5d932a [LoopUtils] reorder logic for creating reduction; NFC adds 97669575241 [LoopUtils] reduce code for creatng reduction; NFC adds aa169033892 [test] Pin backedge-id-bug-xfail.ll to legacy PM adds 8e293fe6ad0 [NewPM][AMDGPU] Pass TargetMachine to AMDGPUSimplifyLibCallsPass adds abbef2fd46d [ValueTracking] isGuaranteedNotToBePoison should return tru [...] adds efc82c4ad2b [NFC, Refactor] Modernize StorageClass from Specifiers.h to [...] adds 36263a7cccc [LoopUtils] remove redundant opcode parameter; NFC adds 2fd11e0b1ef Revert "[NFC, Refactor] Modernize StorageClass from Specifi [...] adds f67d3dbdb93 [clang] - Also look for devtoolset-10 adds b4f519bddda [NFCI] DwarfEHPrepare: update DomTree in non-permissive mod [...] adds 3fb57222c4c [NFCI] SimplifyCFG: switch to non-permissive DomTree update [...] adds ed9de61cc3e [SimplifyCFGPass] mergeEmptyReturnBlocks(): switch to non-p [...] adds a8604e3d5b7 [SimplifyCFG] simplifyIndirectBr(): switch to non-permissiv [...] adds 110b3d7855e [SimplifyCFG] SimplifyEqualityComparisonWithOnlyPredecessor [...] adds 32c47ebef18 [SimplifyCFG] SimplifyCondBranchToTwoReturns(): switch to n [...] new e30fbbe9a53 [JumpThreading][NewPM] Skip when target has divergent CF new c4f12a07a44 [WebAssembly] Remove old SDT_WebAssemblyCalls (NFC) The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../cppcoreguidelines-macro-usage-custom.cpp | 7 +- ...eadability-identifier-naming-ignored-regexp.cpp | 13 +- clang/lib/AST/DeclCXX.cpp | 6 +- clang/lib/CodeGen/BackendUtil.cpp | 6 +- clang/lib/CodeGen/CGOpenMPRuntimeAMDGCN.cpp | 7 +- clang/lib/Driver/ToolChains/Gnu.cpp | 1 + clang/lib/Sema/SemaInit.cpp | 67 +-- clang/lib/Sema/SemaStmt.cpp | 36 +- .../CXX/class/class.init/class.copy.elision/p3.cpp | 50 -- clang/test/OpenMP/amdgcn_target_codegen.cpp | 10 +- compiler-rt/cmake/Modules/AddCompilerRT.cmake | 1 - compiler-rt/lib/asan/asan_interceptors.h | 6 +- compiler-rt/lib/asan/tests/asan_test.cpp | 4 +- .../lib/interception/interception_linux.cpp | 6 +- compiler-rt/lib/interception/interception_linux.h | 6 +- compiler-rt/lib/msan/tests/msan_test.cpp | 36 +- .../sanitizer_common_interceptors_ioctl.inc | 6 +- .../sanitizer_common/sanitizer_linux_libcdep.cpp | 15 +- .../lib/sanitizer_common/sanitizer_platform.h | 11 - .../sanitizer_platform_interceptors.h | 90 ++-- .../sanitizer_platform_limits_posix.cpp | 75 ++- .../sanitizer_platform_limits_posix.h | 2 - .../lib/tsan/rtl/tsan_interceptors_posix.cpp | 8 +- flang/include/flang/Parser/parse-tree.h | 2 +- flang/lib/Parser/openmp-parsers.cpp | 9 +- flang/lib/Parser/unparse.cpp | 4 +- flang/lib/Semantics/check-omp-structure.cpp | 3 +- flang/lib/Semantics/check-omp-structure.h | 3 +- flang/test/Semantics/omp-clause-validity01.f90 | 6 +- llvm/docs/ReleaseNotes.rst | 6 + llvm/include/llvm/Analysis/IVDescriptors.h | 9 +- llvm/include/llvm/Analysis/TargetTransformInfo.h | 11 +- .../llvm/Analysis/TargetTransformInfoImpl.h | 5 +- llvm/include/llvm/CodeGen/BasicTTIImpl.h | 6 +- llvm/include/llvm/CodeGen/LiveInterval.h | 7 +- llvm/include/llvm/CodeGen/MachineFrameInfo.h | 7 +- llvm/include/llvm/DWARFLinker/DWARFLinker.h | 2 - .../llvm/DWARFLinker/DWARFLinkerCompileUnit.h | 21 - .../llvm/DWARFLinker/DWARFLinkerDeclContext.h | 31 +- llvm/include/llvm/DebugInfo/CodeView/TypeRecord.h | 2 +- llvm/include/llvm/Frontend/OpenMP/OMP.td | 3 +- llvm/include/llvm/IR/DebugInfoMetadata.h | 5 +- llvm/include/llvm/IR/Metadata.h | 3 +- llvm/include/llvm/IR/PredIteratorCache.h | 2 +- llvm/include/llvm/Support/KnownBits.h | 31 ++ llvm/include/llvm/Transforms/Utils/LoopUtils.h | 3 +- llvm/lib/Analysis/AssumptionCache.cpp | 4 +- llvm/lib/Analysis/IVDescriptors.cpp | 5 +- llvm/lib/Analysis/InstructionSimplify.cpp | 54 +- llvm/lib/Analysis/ScalarEvolution.cpp | 21 +- llvm/lib/Analysis/TargetTransformInfo.cpp | 4 + llvm/lib/Analysis/ValueTracking.cpp | 2 +- llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp | 11 +- llvm/lib/CodeGen/CodeGenPrepare.cpp | 4 +- llvm/lib/CodeGen/DwarfEHPrepare.cpp | 2 +- llvm/lib/CodeGen/InterleavedAccessPass.cpp | 25 +- llvm/lib/CodeGen/MachineSink.cpp | 6 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 21 +- llvm/lib/DWARFLinker/DWARFLinker.cpp | 57 +-- llvm/lib/DWARFLinker/DWARFLinkerDeclContext.cpp | 80 +-- llvm/lib/DebugInfo/DWARF/DWARFDie.cpp | 3 +- llvm/lib/DebugInfo/MSF/MSFBuilder.cpp | 6 +- llvm/lib/DebugInfo/PDB/Native/NamedStreamMap.cpp | 2 +- llvm/lib/DebugInfo/PDB/Native/SymbolCache.cpp | 3 +- llvm/lib/DebugInfo/PDB/Native/TpiStreamBuilder.cpp | 2 +- .../ExecutionEngine/Orc/TargetProcessControl.cpp | 8 +- .../ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp | 15 +- llvm/lib/IR/Constants.cpp | 2 +- llvm/lib/IR/Instructions.cpp | 2 +- llvm/lib/IR/Verifier.cpp | 4 +- llvm/lib/Passes/PassBuilder.cpp | 10 +- llvm/lib/ProfileData/GCOV.cpp | 2 +- llvm/lib/Support/KnownBits.cpp | 69 +++ llvm/lib/Support/SourceMgr.cpp | 2 +- llvm/lib/TableGen/Record.cpp | 4 +- llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp | 3 +- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 2 +- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 21 + llvm/lib/Target/AArch64/AArch64SchedA57.td | 61 ++- llvm/lib/Target/AArch64/AArch64SchedA57WriteRes.td | 19 + .../Target/AArch64/AArch64TargetTransformInfo.cpp | 20 + .../Target/AArch64/AArch64TargetTransformInfo.h | 11 + llvm/lib/Target/AMDGPU/AMDGPU.h | 40 ++ llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp | 2 + llvm/lib/Target/AMDGPU/AMDGPUAliasAnalysis.h | 7 +- llvm/lib/Target/AMDGPU/AMDGPUAlwaysInlinePass.cpp | 20 +- .../Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp | 2 +- llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp | 2 +- .../Target/AMDGPU/AMDGPUPrintfRuntimeBinding.cpp | 77 ++- .../Target/AMDGPU/AMDGPUPropagateAttributes.cpp | 19 + llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 70 ++- llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h | 1 + .../AMDGPU/AMDGPUUnifyDivergentExitNodes.cpp | 8 +- llvm/lib/Target/AMDGPU/AMDGPUUnifyMetadata.cpp | 59 +-- llvm/lib/Target/AMDGPU/R600MachineScheduler.cpp | 2 +- llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 3 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 4 +- llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 3 +- llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp | 3 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 2 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 56 ++- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 3 +- llvm/lib/Target/BPF/BPFAdjustOpt.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonCommonGEP.cpp | 4 +- llvm/lib/Target/Hexagon/HexagonPatterns.td | 2 +- llvm/lib/Target/Hexagon/HexagonVectorCombine.cpp | 2 +- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp | 8 + llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 12 +- .../Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp | 9 - .../Target/RISCV/MCTargetDesc/RISCVInstPrinter.h | 2 - llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfo.td | 8 +- llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 1 - llvm/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp | 158 +++++- .../Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp | 30 +- .../Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp | 52 +- llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.cpp | 73 +-- llvm/lib/Target/Sparc/MCTargetDesc/SparcMCExpr.h | 1 + llvm/lib/Target/Sparc/SparcAsmPrinter.cpp | 2 +- llvm/lib/Target/Sparc/SparcISelLowering.cpp | 6 +- llvm/lib/Target/Sparc/SparcInstr64Bit.td | 6 +- llvm/lib/Target/Sparc/SparcInstrFormats.td | 4 +- llvm/lib/Target/Sparc/SparcInstrInfo.td | 25 +- llvm/lib/Target/VE/MCTargetDesc/VEMCTargetDesc.cpp | 2 +- llvm/lib/Target/VE/VE.td | 2 +- llvm/lib/Target/VE/VEISelLowering.cpp | 15 +- llvm/lib/Target/VE/VESubtarget.cpp | 2 +- .../lib/Target/WebAssembly/WebAssemblyInstrInfo.td | 2 - .../WebAssembly/WebAssemblyLateEHPrepare.cpp | 6 +- .../WebAssemblyLowerEmscriptenEHSjLj.cpp | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 3 +- llvm/lib/Target/X86/X86InstrInfo.cpp | 2 +- llvm/lib/Target/X86/X86InterleavedAccess.cpp | 19 +- llvm/lib/Target/XCore/XCoreLowerThreadLocal.cpp | 6 +- llvm/lib/Transforms/IPO/ArgumentPromotion.cpp | 18 +- llvm/lib/Transforms/IPO/IROutliner.cpp | 8 +- llvm/lib/Transforms/IPO/PassManagerBuilder.cpp | 6 +- llvm/lib/Transforms/Scalar/GVN.cpp | 7 +- llvm/lib/Transforms/Scalar/GVNSink.cpp | 4 +- llvm/lib/Transforms/Scalar/JumpThreading.cpp | 4 + llvm/lib/Transforms/Scalar/Scalarizer.cpp | 4 +- llvm/lib/Transforms/Scalar/SimplifyCFGPass.cpp | 7 +- llvm/lib/Transforms/Utils/LoopUtils.cpp | 112 ++--- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 159 +++--- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 6 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 6 +- llvm/lib/Transforms/Vectorize/VPlan.cpp | 2 +- .../AArch64/sve-getIntrinsicInstrCost-gather.ll | 37 ++ .../AArch64/sve-getIntrinsicInstrCost-scatter.ll | 40 ++ .../Analysis/ScalarEvolution/trunc-simplify.ll | 22 + .../AArch64/inline-asm-constraints-bad-sve.ll | 9 + llvm/test/CodeGen/AArch64/neon-vcmla.ll | 95 ++++ llvm/test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll | 2 + llvm/test/CodeGen/AMDGPU/clamp-modifier.ll | 2 +- llvm/test/CodeGen/AMDGPU/clamp.ll | 4 +- llvm/test/CodeGen/AMDGPU/fdiv32-to-rcp-folding.ll | 8 +- llvm/test/CodeGen/AMDGPU/fma-combine.ll | 4 +- llvm/test/CodeGen/AMDGPU/fneg-combines.ll | 42 +- .../force-alwaysinline-lds-global-address.ll | 2 + llvm/test/CodeGen/AMDGPU/fpext-free.ll | 2 +- llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll | 4 +- llvm/test/CodeGen/AMDGPU/internalize.ll | 4 +- llvm/test/CodeGen/AMDGPU/known-never-snan.ll | 2 +- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fmad.ftz.ll | 4 +- .../CodeGen/AMDGPU/llvm.amdgcn.wavefrontsize.ll | 1 + llvm/test/CodeGen/AMDGPU/mad-combine.ll | 6 +- llvm/test/CodeGen/AMDGPU/mad-mix.ll | 8 +- llvm/test/CodeGen/AMDGPU/opencl-printf.ll | 1 + .../CodeGen/AMDGPU/propagate-attributes-clone.ll | 2 + .../propagate-attributes-flat-work-group-size.ll | 1 + .../AMDGPU/propagate-attributes-single-set.ll | 1 + llvm/test/CodeGen/AMDGPU/rcp-pattern.ll | 4 +- llvm/test/CodeGen/AMDGPU/rsq.ll | 2 +- llvm/test/CodeGen/AMDGPU/unify-metadata.ll | 1 + llvm/test/CodeGen/AMDGPU/v_mac.ll | 6 +- llvm/test/CodeGen/AMDGPU/v_mac_f16.ll | 12 +- .../CodeGen/Hexagon/isel-splat-vector-neg-i8.ll | 16 + llvm/test/CodeGen/PowerPC/pr47830.ll | 5 +- llvm/test/CodeGen/RISCV/rv32Zbt.ll | 560 +++++++++++++++++---- llvm/test/CodeGen/RISCV/rv64Zbt.ll | 260 +++++++++- llvm/test/CodeGen/RISCV/vararg.ll | 48 +- llvm/test/CodeGen/Thumb2/mve-vecreduce-add.ll | 122 +---- llvm/test/CodeGen/Thumb2/mve-vecreduce-addpred.ll | 200 +------- llvm/test/CodeGen/Thumb2/mve-vecreduce-mla.ll | 298 +---------- llvm/test/CodeGen/Thumb2/mve-vecreduce-mlapred.ll | 534 ++------------------ llvm/test/CodeGen/VE/Scalar/cpu.ll | 5 + llvm/test/MC/Sparc/sparc-asm-errors.s | 6 + llvm/test/MC/Sparc/sparc-ctrl-instructions.s | 7 + llvm/test/MC/Sparc/sparc-relocations.s | 4 + llvm/test/Reduce/Inputs/remove-global-vars.py | 18 - llvm/test/Reduce/remove-global-vars.ll | 37 +- llvm/test/Reduce/remove-unused-declarations.ll | 21 + .../aggregate-promote-dead-gep.ll | 34 ++ .../ArgumentPromotion/dead-gep-no-promotion.ll | 30 ++ llvm/test/Transforms/IROutliner/opt-remarks.ll | 108 +++- llvm/test/Transforms/IROutliner/outlining-calls.ll | 2 +- .../outlining-compatible-and-attribute-transfer.ll | 2 +- .../outlining-compatible-or-attribute-transfer.ll | 2 +- .../Transforms/IROutliner/outlining-cost-model.ll | 8 + .../IROutliner/outlining-different-constants.ll | 2 +- .../IROutliner/outlining-different-structure.ll | 2 +- .../IROutliner/outlining-isomorphic-predicates.ll | 2 +- .../InstCombine/X86/x86-pack-inseltpoison.ll | 114 ++--- .../InstCombine/X86/x86-pshufb-inseltpoison.ll | 42 +- .../InstCombine/X86/x86-sse4a-inseltpoison.ll | 32 +- .../X86/x86-vector-shifts-inseltpoison.ll | 236 ++++----- .../InstCombine/X86/x86-vpermil-inseltpoison.ll | 48 +- .../Transforms/InstCombine/add-shl-sdiv-to-srem.ll | 2 +- llvm/test/Transforms/InstCombine/div.ll | 48 +- .../InstCombine/extractelement-inseltpoison.ll | 4 +- llvm/test/Transforms/InstCombine/extractelement.ll | 4 +- .../Transforms/InstCombine/icmp-div-constant.ll | 11 +- llvm/test/Transforms/InstCombine/icmp-shr.ll | 419 +++++++++++++-- .../InstCombine/inselt-binop-inseltpoison.ll | 8 +- llvm/test/Transforms/InstCombine/inselt-binop.ll | 8 +- .../InstCombine/out-of-bounds-indexes.ll | 2 +- llvm/test/Transforms/InstCombine/rem.ll | 2 +- .../sdiv-exact-by-negative-power-of-two.ll | 2 +- .../InstCombine/sdiv-exact-by-power-of-two.ll | 2 +- llvm/test/Transforms/InstCombine/shift.ll | 2 +- llvm/test/Transforms/InstCombine/vector-udiv.ll | 2 +- llvm/test/Transforms/InstCombine/vector-urem.ll | 4 +- .../vector_insertelt_shuffle-inseltpoison.ll | 6 +- .../InstCombine/vector_insertelt_shuffle.ll | 6 +- llvm/test/Transforms/InstCombine/with_overflow.ll | 2 +- .../InstSimplify/2011-09-05-InsertExtractValue.ll | 40 +- llvm/test/Transforms/InstSimplify/call.ll | 32 +- llvm/test/Transforms/InstSimplify/div.ll | 13 +- .../Transforms/InstSimplify/extract-element.ll | 10 +- llvm/test/Transforms/InstSimplify/fp-nan.ll | 20 +- .../Transforms/InstSimplify/fp-undef-poison.ll | 24 +- llvm/test/Transforms/InstSimplify/insertelement.ll | 10 +- llvm/test/Transforms/InstSimplify/rem.ll | 9 +- llvm/test/Transforms/InstSimplify/undef.ll | 91 ++-- .../Transforms/InstSimplify/vscale-inseltpoison.ll | 4 +- llvm/test/Transforms/InstSimplify/vscale.ll | 9 +- .../X86/interleave-load-extract-shuffle-changes.ll | 58 +++ .../X86/interleavedLoad-inseltpoison.ll | 30 +- .../InterleavedAccess/X86/interleavedLoad.ll | 30 +- .../X86/interleavedStore-inseltpoison.ll | 12 +- .../InterleavedAccess/X86/interleavedStore.ll | 12 +- .../JumpThreading/divergent-target-test.ll | 2 + .../Transforms/LoopUnswitch/partial-unswitch.ll | 461 +++++++++++++++++ .../dont-fold-tail-for-assumed-divisible-TC.ll | 65 +-- .../X86/alternate-int-inseltpoison.ll | 2 +- .../Transforms/Scalarizer/basic-inseltpoison.ll | 10 +- llvm/test/Transforms/Scalarizer/basic.ll | 10 +- .../Scalarizer/constant-insertelement.ll | 2 +- llvm/test/Transforms/Scalarizer/intrinsics.ll | 20 +- .../Scalarizer/order-bug-inseltpoison.ll | 2 +- llvm/test/Transforms/Scalarizer/order-bug.ll | 2 +- llvm/test/Transforms/Scalarizer/scatter-order.ll | 6 +- .../Scalarizer/variable-extractelement.ll | 2 +- .../Scalarizer/variable-insertelement.ll | 6 +- ...Predecessors-domtree-preservation-edgecase-2.ll | 80 +++ ...toPredecessors-domtree-preservation-edgecase.ll | 49 ++ ...inatorOnSelect-domtree-preservation-edgecase.ll | 58 +++ .../StructurizeCFG/AMDGPU/backedge-id-bug-xfail.ll | 2 +- .../tools/llvm-mca/AArch64/Cortex/forwarding-A57.s | 501 ++++++++++++++++++ llvm/tools/llvm-readobj/ELFDumper.cpp | 5 +- llvm/tools/llvm-reduce/CMakeLists.txt | 1 + llvm/tools/llvm-reduce/DeltaManager.h | 2 + llvm/tools/llvm-reduce/deltas/ReduceFunctions.cpp | 8 +- ...balVars.cpp => ReduceGlobalVarInitializers.cpp} | 41 +- ...eGlobalVars.h => ReduceGlobalVarInitializers.h} | 7 +- llvm/tools/llvm-reduce/deltas/ReduceGlobalVars.cpp | 13 +- llvm/tools/llvm-reduce/deltas/ReduceGlobalVars.h | 2 +- llvm/tools/opt/opt.cpp | 12 +- llvm/unittests/Analysis/ValueTrackingTest.cpp | 4 + llvm/unittests/Support/KnownBitsTest.cpp | 87 ++++ llvm/utils/TableGen/AsmMatcherEmitter.cpp | 5 +- llvm/utils/TableGen/GICombinerEmitter.cpp | 8 +- llvm/utils/benchmark/include/benchmark/benchmark.h | 2 +- .../gn/secondary/llvm/tools/llvm-reduce/BUILD.gn | 1 + .../deviceRTLs/amdgcn/src/amdgcn_interface.h | 2 + .../deviceRTLs/amdgcn/src/target_impl.hip | 6 +- openmp/libomptarget/include/Debug.h | 44 +- openmp/libomptarget/include/SourceInfo.h | 9 +- openmp/libomptarget/plugins/cuda/src/rtl.cpp | 28 +- openmp/libomptarget/src/device.cpp | 23 +- openmp/libomptarget/src/interface.cpp | 42 +- openmp/libomptarget/src/private.h | 63 ++- openmp/libomptarget/test/offloading/info.c | 35 +- openmp/runtime/src/include/omp.h.var | 18 + openmp/runtime/src/include/omp_lib.f90.var | 97 ++++ openmp/runtime/src/include/omp_lib.h.var | 107 ++++ 286 files changed, 5414 insertions(+), 3022 deletions(-) delete mode 100644 clang/test/CXX/class/class.init/class.copy.elision/p3.cpp create mode 100644 llvm/test/Analysis/CostModel/AArch64/sve-getIntrinsicInstrCost- [...] create mode 100644 llvm/test/Analysis/CostModel/AArch64/sve-getIntrinsicInstrCost- [...] create mode 100644 llvm/test/CodeGen/Hexagon/isel-splat-vector-neg-i8.ll create mode 100644 llvm/test/CodeGen/VE/Scalar/cpu.ll delete mode 100755 llvm/test/Reduce/Inputs/remove-global-vars.py create mode 100644 llvm/test/Reduce/remove-unused-declarations.ll create mode 100644 llvm/test/Transforms/ArgumentPromotion/aggregate-promote-dead-gep.ll create mode 100644 llvm/test/Transforms/ArgumentPromotion/dead-gep-no-promotion.ll create mode 100644 llvm/test/Transforms/InterleavedAccess/X86/interleave-load-extr [...] create mode 100644 llvm/test/Transforms/LoopUnswitch/partial-unswitch.ll create mode 100644 llvm/test/Transforms/SimplifyCFG/FoldValueComparisonIntoPredece [...] create mode 100644 llvm/test/Transforms/SimplifyCFG/FoldValueComparisonIntoPredece [...] create mode 100644 llvm/test/Transforms/SimplifyCFG/SimplifyTerminatorOnSelect-dom [...] create mode 100644 llvm/test/tools/llvm-mca/AArch64/Cortex/forwarding-A57.s copy llvm/tools/llvm-reduce/deltas/{ReduceGlobalVars.cpp => ReduceGlobalVarInitial [...] copy llvm/tools/llvm-reduce/deltas/{ReduceGlobalVars.h => ReduceGlobalVarInitializ [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig updated (8fe371b11 -> 7b034351e)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig in repository toolchain/ci/base-artifacts. discards 8fe371b11 0: update: qemu-41192db338588051f21501abc13743e62b0a5605: boot new 7b034351e 0: update: llvm-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (8fe371b11) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 16 +- 02-prepare_abe/console.log | 256 +- 03-build_llvm/console.log | 13636 ++++++++++++------------ 04-build_linux/console.log | 577 +- 05-build_abe-qemu/console.log | 6675 ++++++------ 06-boot_linux/console.log | 492 +- 07-check_regression/console.log | 4 +- 08-update_baseline/console.log | 10 +- console.log | 21666 +++++++++++++++++++------------------- jenkins/manifest.sh | 18 +- 10 files changed, 22045 insertions(+), 21305 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[binutils-gdb] branch master updated (9353bb9ed6e -> 3d52735bab7)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 9353bb9ed6e Automatic date update in version.in new 9416af6e7d5 sim: stdlib.h for abs() new 3d52735bab7 sim: include stdlib.h for atoi() The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: sim/arm/ChangeLog | 8 ++++++++ sim/arm/iwmmxt.c | 1 + sim/arm/wrapper.c | 1 + sim/bfin/ChangeLog | 8 ++++++++ sim/bfin/dv-bfin_dma.c | 2 ++ sim/bfin/machs.c | 2 ++ sim/igen/ChangeLog | 4 ++++ sim/igen/gen-icache.c | 1 + sim/igen/igen.c | 3 +-- sim/ppc/ChangeLog | 4 ++++ sim/ppc/gen-icache.c | 1 + sim/ppc/igen.c | 3 +-- sim/testsuite/sim/bfin/ChangeLog | 4 ++++ sim/testsuite/sim/bfin/mdma-skel.h | 1 + 14 files changed, 39 insertions(+), 4 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig updated (f262a351887 -> a000eb5918e)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig in repository toolchain/ci/gcc. from f262a351887 MAINTAINERS: Update my email address. new a000eb5918e C: Add test for incorrect warning for assignment of certain [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/testsuite/gcc.dg/pr98029.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 gcc/testsuite/gcc.dg/pr98029.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig updated (e4ad960a57 -> c68ea49f59)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig in repository toolchain/ci/binutils-gdb. from e4ad960a57 [gdb/symtab] Remove superfluous end-of-sequence marker adds cd6d537c48 elf: Allow mixed ordered/unordered inputs for non-relocatable link new dbed468bcb sim: common: rename sim_print_config new 19b1c38562 sim: common: add a version output helper w/copyright+license info new 2b667e3297 sim: common: use sim_config_print name new babd2ee15d sim: common: version: add build & homepage info when interactive new dfb856ba26 sim: update bug URI to https:// new c68ea49f59 gdb: bfin: use align helper The 6 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: bfd/ChangeLog | 15 +++++++ bfd/bfd-in2.h | 7 ++- bfd/elflink.c | 83 +++++++++++++++++++++++++++--------- bfd/section.c | 7 ++- gas/ChangeLog | 6 +++ gas/config/obj-elf.c | 4 +- gdb/ChangeLog | 5 +++ gdb/bfin-tdep.c | 6 +-- ld/ChangeLog | 19 +++++++++ ld/ldlang.c | 4 +- ld/testsuite/ld-elf/pr26256-1.s | 20 +++++++++ ld/testsuite/ld-elf/pr26256-1.t | 13 ++++++ ld/testsuite/ld-elf/pr26256-1a.d | 7 +++ ld/testsuite/ld-elf/pr26256-1b.d | 7 +++ ld/testsuite/ld-elf/pr26256-2.s | 32 ++++++++++++++ ld/testsuite/ld-elf/pr26256-2.t | 9 ++++ ld/testsuite/ld-elf/pr26256-2a.d | 20 +++++++++ ld/testsuite/ld-elf/pr26256-2b-alt.d | 21 +++++++++ ld/testsuite/ld-elf/pr26256-2b.d | 22 ++++++++++ ld/testsuite/ld-elf/pr26256-3.s | 27 ++++++++++++ ld/testsuite/ld-elf/pr26256-3a.d | 11 +++++ ld/testsuite/ld-elf/pr26256-3a.t | 17 ++++++++ ld/testsuite/ld-elf/pr26256-3b.d | 12 ++++++ ld/testsuite/ld-elf/pr26256-3b.t | 16 +++++++ sim/aarch64/ChangeLog | 4 ++ sim/aarch64/configure | 2 +- sim/arm/ChangeLog | 4 ++ sim/arm/configure | 2 +- sim/avr/ChangeLog | 4 ++ sim/avr/configure | 2 +- sim/bfin/configure | 2 +- sim/bpf/configure | 2 +- sim/common/ChangeLog | 22 ++++++++++ sim/common/acinclude.m4 | 2 +- sim/common/sim-config.c | 2 +- sim/common/sim-config.h | 2 +- sim/common/sim-options.c | 37 +++++++++++++++- sim/common/sim-options.h | 4 ++ sim/cr16/ChangeLog | 4 ++ sim/cr16/configure | 2 +- sim/cris/ChangeLog | 4 ++ sim/cris/configure | 2 +- sim/d10v/ChangeLog | 4 ++ sim/d10v/configure | 2 +- sim/erc32/ChangeLog | 4 ++ sim/erc32/configure | 2 +- sim/frv/ChangeLog | 4 ++ sim/frv/configure | 2 +- sim/ft32/ChangeLog | 4 ++ sim/ft32/configure | 2 +- sim/h8300/ChangeLog | 4 ++ sim/h8300/configure | 2 +- sim/igen/ChangeLog | 4 ++ sim/iq2000/ChangeLog | 4 ++ sim/iq2000/configure | 2 +- sim/lm32/ChangeLog | 4 ++ sim/lm32/configure | 2 +- sim/m32c/ChangeLog | 4 ++ sim/m32c/configure | 2 +- sim/m32r/ChangeLog | 4 ++ sim/m32r/configure | 2 +- sim/m68hc11/ChangeLog | 4 ++ sim/m68hc11/configure | 2 +- sim/mcore/ChangeLog | 4 ++ sim/mcore/configure | 2 +- sim/microblaze/ChangeLog | 4 ++ sim/microblaze/configure | 2 +- sim/mips/ChangeLog | 4 ++ sim/mips/configure | 2 +- sim/mn10300/ChangeLog | 4 ++ sim/mn10300/configure | 2 +- sim/moxie/ChangeLog | 4 ++ sim/moxie/configure | 2 +- sim/msp430/ChangeLog | 4 ++ sim/msp430/configure | 2 +- sim/or1k/configure | 2 +- sim/ppc/ChangeLog | 5 +++ sim/ppc/configure | 2 +- sim/ppc/configure.ac | 2 +- sim/pru/ChangeLog | 4 ++ sim/pru/configure | 2 +- sim/rl78/ChangeLog | 4 ++ sim/rl78/configure | 2 +- sim/rx/ChangeLog | 4 ++ sim/rx/configure | 2 +- sim/sh/ChangeLog | 4 ++ sim/sh/configure | 2 +- sim/sh64/ChangeLog | 4 ++ sim/sh64/configure | 2 +- sim/testsuite/ChangeLog | 4 ++ sim/v850/ChangeLog | 4 ++ sim/v850/configure | 2 +- 92 files changed, 580 insertions(+), 64 deletions(-) create mode 100644 ld/testsuite/ld-elf/pr26256-1.s create mode 100644 ld/testsuite/ld-elf/pr26256-1.t create mode 100644 ld/testsuite/ld-elf/pr26256-1a.d create mode 100644 ld/testsuite/ld-elf/pr26256-1b.d create mode 100644 ld/testsuite/ld-elf/pr26256-2.s create mode 100644 ld/testsuite/ld-elf/pr26256-2.t create mode 100644 ld/testsuite/ld-elf/pr26256-2a.d create mode 100644 ld/testsuite/ld-elf/pr26256-2b-alt.d create mode 100644 ld/testsuite/ld-elf/pr26256-2b.d create mode 100644 ld/testsuite/ld-elf/pr26256-3.s create mode 100644 ld/testsuite/ld-elf/pr26256-3a.d create mode 100644 ld/testsuite/ld-elf/pr26256-3a.t create mode 100644 ld/testsuite/ld-elf/pr26256-3b.d create mode 100644 ld/testsuite/ld-elf/pr26256-3b.t -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

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Tcwg-commits January 2021