Tcwg-commits January 2021

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-next-allnoconfig updated (f4a8139a -> d285b28f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-next-allnoconfig in repository toolchain/ci/base-artifacts. discards f4a8139a 0: update: llvm-linux-qemu: boot new d285b28f 0: update: llvm-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (f4a8139a) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 175 +- 02-prepare_abe/console.log | 438 +- 03-build_llvm/console.log | 13229 +++++++++++++------------- 04-build_linux/console.log | 658 +- 05-build_abe-qemu/console.log | 4469 ++++----- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 2 +- console.log | 18973 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 9 files changed, 18988 insertions(+), 18966 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig updated (7b09f12773 -> b3f846c59d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig in repository toolchain/ci/qemu. from 7b09f12773 Merge remote-tracking branch 'remotes/pmaydell/tags/pull-tar [...] adds b115ea3a0d gitlab-ci.yml: Add openSUSE Leap 15.2 for gitlab CI/CD adds 661465c2e0 qtest/libqtest: fix heap-buffer-overflow in qtest_cb_for_eve [...] adds 124bd3e0a8 util/oslib-win32: Fix _aligned_malloc() arguments order adds 22ec0c696f fuzz: accelerate non-crash detection adds 7b339f287f fuzz: double the IOs to remove for every loop adds e72203abec fuzz: split write operand using binary approach adds 247ab240c2 fuzz: remove IO commands iteratively adds 9d20f2af53 fuzz: set bits in operand of write/out to zero adds dd21ed0edf fuzz: add minimization options adds 4cc5752303 fuzz: heuristic split write based on past IOs adds 4d306e59cb bsd-user: regenerate FreeBSD's system call numbers adds ea1ab4cf2c bsd-user: move strace OS/arch dependent code to host/arch dirs adds f6eb4a0841 bsd-user: Update strace.list for FreeBSD's latest syscalls adds 333168efe5 tests/acceptance: Fix race conditions in s390x tests & skip [...] adds b677001d70 fuzz: map all BARs and enable PCI devices adds b3f846c59d Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull- [...] No new revisions were added by this update. Summary of changes: .gitlab-ci.d/containers.yml | 5 + .gitlab-ci.yml | 31 ++ bsd-user/arm/target_arch_sysarch.h | 78 +++ bsd-user/arm/target_syscall.h | 36 ++ bsd-user/{signal.c => freebsd/os-strace.h} | 17 +- bsd-user/freebsd/strace.list | 65 ++- bsd-user/freebsd/syscall_nr.h | 695 ++++++++++++++------------ bsd-user/i386/target_arch_sysarch.h | 77 +++ bsd-user/i386/target_syscall.h | 19 + bsd-user/mips/target_arch_sysarch.h | 69 +++ bsd-user/mips/target_syscall.h | 52 ++ bsd-user/mips64/target_arch_sysarch.h | 69 +++ bsd-user/mips64/target_syscall.h | 53 ++ bsd-user/netbsd/os-strace.h | 1 + bsd-user/openbsd/os-strace.h | 1 + bsd-user/sparc/target_arch_sysarch.h | 52 ++ bsd-user/sparc/target_syscall.h | 24 +- bsd-user/sparc64/target_arch_sysarch.h | 52 ++ bsd-user/sparc64/target_syscall.h | 24 +- bsd-user/strace.c | 11 + bsd-user/x86_64/target_arch_sysarch.h | 76 +++ bsd-user/x86_64/target_syscall.h | 21 +- meson.build | 1 + scripts/oss-fuzz/minimize_qtest_trace.py | 260 ++++++++-- tests/acceptance/machine_s390_ccw_virtio.py | 14 +- tests/docker/dockerfiles/opensuse-leap.docker | 55 ++ tests/qtest/fuzz/generic_fuzz.c | 24 + tests/qtest/libqtest.c | 2 +- util/oslib-win32.c | 2 +- 29 files changed, 1500 insertions(+), 386 deletions(-) create mode 100644 bsd-user/arm/target_arch_sysarch.h create mode 100644 bsd-user/arm/target_syscall.h copy bsd-user/{signal.c => freebsd/os-strace.h} (60%) create mode 100644 bsd-user/i386/target_arch_sysarch.h create mode 100644 bsd-user/mips/target_arch_sysarch.h create mode 100644 bsd-user/mips/target_syscall.h create mode 100644 bsd-user/mips64/target_arch_sysarch.h create mode 100644 bsd-user/mips64/target_syscall.h create mode 100644 bsd-user/netbsd/os-strace.h create mode 100644 bsd-user/openbsd/os-strace.h create mode 100644 bsd-user/sparc/target_arch_sysarch.h create mode 100644 bsd-user/sparc64/target_arch_sysarch.h create mode 100644 bsd-user/x86_64/target_arch_sysarch.h create mode 100644 tests/docker/dockerfiles/opensuse-leap.docker -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig updated (407b1e65a46 -> a81c68ae6be)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig in repository toolchain/ci/llvm-project. from 407b1e65a46 [StringExtras] Add a helper class for comma-separated lists adds 02bc320545d CGDebugInfo: Delete unused DIFile* parameter adds 4739dd67e7a [LoopDeletion] Break backedge of outermost loops when known [...] adds d43a264a5dd Revert "[X86][SSE] Fold unpack(hop(),hop()) -> permute(hop())" adds 7539c75bb43 [DAGCombine] Remove the check for unsafe-fp-math when we ar [...] adds 5cf73dca77e [RISCV] Convert most of the information about RVV Pseudos i [...] adds 7f69860243e [LoopUnroll] Fix a crash adds ffa67873a3f [PowerPC] Add variants of 64-bit vector types for vec_sel. adds dcac2da1063 [IR Parser] Fix a crash handling zero width integer attributes. adds 6215c1b778f CGDebugInfo: Delete redundant test adds b8d28420885 CGDebugInfo: Delete unneeded UnwrapTypeForDebugInfo adds a40767ec885 [MLIR][SPIRV] Add (de-)serialization support for SpecConsta [...] adds 5e476061deb [NFC][AsmPrinter] Make comments for spill/reload more precise. adds 7b11f564dcf [JITLink] Rename PostAllocationPasses to PreFixupPasses. adds 131ce834e4b [RISCV] Clear isCodeGenOnly flag on VMSGE(U) pseudo instruc [...] adds af339f89a14 Remove redundant casts. adds cddd3faf5de [CSKY] Add visibility macro to fix link error adds ee27c767bd2 [clang-format] Skip UTF8 Byte Order Mark while sorting includes adds 0c8b748f321 [ARM] Additional trunc cost tests. NFC adds 7473940bae0 [clang-format] turn on formatting after "clang-format on" w [...] adds 89878e8c966 [clang-format] Find main include after block ended with #pr [...] adds dcefcd51e01 [ARM] Update trunc costs adds b7ccaca5370 [NFC] Remove min/max functions from InstructionCost adds 97100646d1b Reapply "[clang][cli] Port DiagnosticOpts to new option par [...] adds 40abeb11f45 [NFC][InstructionCost] Change LoopVectorizationCostModel::g [...] adds 8165a034203 [ARM] Add debug messages for the load store optimizer. NFC adds 1677c86124e [clangd] Add metrics for go-to-implementation. adds c5be0e0cc0e [X86] Fix tile register spill issue. adds 675be651062 Require chained analyses in BasicAA and AAResults to be transitive adds c37f68a8885 [SVE][CodeGen] Fix legalisation of floating-point masked gathers adds 41bf338dd1e Revert rGd43a264a5dd3 "Revert "[X86][SSE] Fold unpack(hop() [...] adds 59632292663 [X86][SSE] Add missing SSE test coverage for permute(hop,ho [...] adds b72ca799823 [VE] Support intrinsic to isnert/extract_subreg of v512i1 adds d02de139324 [VE] Support additional VMRGW and VMV intrinsic instructions adds c74751d4b5b [obj2yaml] - Fix the crash in getUniquedSectionName(). adds 8ea72b38873 [clang][AArch64][SVE] Avoid going through memory for coerce [...] adds a6db7cf1ce7 [llvm-readelf/obj] - Index phdrs and relocations from 0 whe [...] adds a94497a3429 [VPlan] Move initial quote emission from ::print to ::dumpB [...] adds a5b484c4d41 [obj2yaml][test] - Improve and fix section-group.yaml test. adds d36e879c21c [lldb] Disable PipeTest.OpenAsReader on windows adds 8112a2598ce [X86][SSE] Add 'vectorized sum' test patterns adds 2e17d9c0ee7 [ARM] Add uses for locals introduced for debug messages. NFC. adds 6dcf9207df1 [AMDGPU] Fix a urem combine test to test what it was supposed to adds 4fe7b16ae3f [mlir] Remove unnecessary llvm.mlir.cast in AsyncToLLVM lowering. adds 4c372a35cd8 [mlir] Make GpuAsyncRegion pass depend on async dialect. adds 8298ec2d629 [flang][driver] Copy input files into a temp dir when testing adds df86f15f0c5 [mlir][linalg] Support parsing attributes in named op spec adds 55225471d98 [mlir][linalg] Support permutation when lowering to loop nests adds 007358239de [DAGCombiner] Use getVectorElementCount inside visitINSERT_ [...] adds c163aae45ef [attributes] Add a facility for enforcing a Trusted Comput [...] adds eb0371e403a [VPlan] Unify value/recipe printing after VPDef transition. adds 419ef38a502 Revert "[attributes] Add a facility for enforcing a Truste [...] adds d59ddba7772 [mlir] Fix gpu-to-llvm lowering for gpu.alloc with dynamic sizes. adds a46982a2551 [X86] Add nounwind to lzcnt-cmp tests adds a0f82749f4f [X86] Extend lzcnt-cmp tests to test on non-lzcnt targets adds dbd5fa1e75d [ARM] Update existing test case with +pauth targets adds a2dbf3443af [clangd] Fix -check mode doesn't respect any tidy configs. adds 97517055128 [OpenMPOpt][WIP] Expand parallel region merging adds 31732e6f52c [clangd] Remove ScratchFS from tests adds e5eb5c8a7f3 NFC: Use -LABEL more adds c161775decd [FastISel] Flush local value map on every instruction adds 4214ca96145 [X86][AVX] Attempt to fold vpermf128(op(x,i),op(y,i)) -> op [...] adds 9c0dc0b2c1c [mlir][Linalg] Fold init_tensor -> linalg.tensor_reshape. adds c15b0e2229e [Clang][Docs] Fix ambiguity in clang-offload-bundler docs adds 7200d2cf089 [NFC] Disallow unused prefixes in CodeGen/PowerPC tests. adds 3d693bd0bd7 [mlir][vector] Add memory effects to transfer_read transfer [...] adds c4486cfd556 [mlir][Linalg] Fix reshape fusion to reshape the outs inste [...] adds be179b9946f [FastISel] NFC: Remove obsolete -fast-isel-sink-local-value [...] adds ac2224c0228 [ELF] --exclude-libs: localize defined libcall symbols refe [...] adds 171771e0780 [SystemZ] Minor NFC fix in SchedModels. adds 1f9c29228ce [FastISel] NFC: Clean up unnecessary bookkeeping adds 072714b9619 [X86] Regenerate vector-constrained-fp-intrinsics.ll tests adds 35c9baa11e4 [attributes] Add a facility for enforcing a Trusted Comput [...] adds a90214760d0 [Hexagon] Custom-widen SETCC's operands adds bcec0f27a2c [AMDGPU] Deduplicate VOP tablegen asm & ins adds 74628c43053 [mlir] Add Python bindings for AffineExpr adds e79bd0b4f25 [mlir] More Python bindings for AffineMap adds 547e3eef14a [mlir] Expose MemRef layout in Python bindings adds 47567ca5fac [flang][openxx][NFC] Remove duplicated function to check re [...] adds d8c6d24359f -funique-internal-linkage-names appends a hex md5hash suffi [...] adds 43a830ed941 Introduce new quiet mode and new option handling for -print [...] adds 5464baaae8c Fix minor build issue (NFC) adds 1027a22ccd7 [SystemZ][z/OS] Fix Permission denied pattern matching adds 195728c75aa [mlir] Add structural conversion to async dialect lowering. adds 37b41bd0879 [RISCV] Add scalable vector fcmp ISel patterns adds 30a7d430e86 [libc++] Turn off auto-formatting of generated files. NFC. adds 72f1f084670 [NFC][AMDGPU] Clarify memory model support for volatile adds 20741773013 [mlir][ODS] Add a C++ abstraction for OpBuilders adds 948be58258d [mlir][TypeDefGen] Add support for adding builders when gen [...] adds d79642b3db1 [mlir][IR][NFC] Move the definitions of Complex/Function/In [...] adds d3ff24cbf87 [ADT] Add makeIntrusiveRefCnt helper function adds 8ad998a6115 [tools] Mark output of tools as text if it is really text adds 05e90cefeb4 [NFC] Disallow unused prefixes under llvm/test/CodeGen adds c1ae378205d [mlir][vector] Add side-effect information to different loa [...] adds 53c866c286a Enable python bindings for tensor, shape and linalg dialects. adds cceb1bfcbbc [mlir][CAPI] Introduce standard source layout for mlir-c di [...] adds 110775809ad Revert "[mlir][linalg] Support parsing attributes in named [...] adds 288f3fc5dfe [InstCombine] reduce icmp(ashr X, C1), C2 to sign-bit test adds 32c073acb32 [GlobalISel] Map extractelt to G_EXTRACT_VECTOR_ELT adds aefeb5f136e [libc][NFC] Make __support/common.h an in tree header. adds 9b222b108a2 [c++20] Don't consider string literal operator templates fo [...] adds f4cec703ec8 Add an assert to CGDebugInfo::getTypeOrNull adds 7989684a2e4 [RISCV] Add scalable vector fadd/fsub/fmul/fdiv ISel patterns adds 046612d29d7 [mlir][vector] verify memref of vector memory ops adds a808d89d355 [PredicateInfo] Add test for one unknown condition in and/or (NFC) adds 00f773cf424 [SCCP] Fix misclassified conditions in test (NFC) adds b88c8f1aab5 CGDebugInfo: Delete unused parameters adds 32bcfcda4e2 Rename debug linkage name with -funique-internal-linkage-names new a81c68ae6be [OpenMP] Take elf_common.c as a interface library The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang-tools-extra/clangd/XRefs.cpp | 11 + clang-tools-extra/clangd/tool/Check.cpp | 1 + .../unittests/GlobalCompilationDatabaseTests.cpp | 75 +- clang/docs/ClangOffloadBundler.rst | 4 +- clang/include/clang/Basic/Attr.td | 16 + clang/include/clang/Basic/AttrDocs.td | 25 + clang/include/clang/Basic/DiagnosticOptions.h | 12 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 7 + clang/include/clang/Driver/Options.td | 112 +- clang/include/clang/Sema/Sema.h | 5 + clang/lib/CodeGen/CGCall.cpp | 15 + clang/lib/CodeGen/CGDebugInfo.cpp | 24 +- clang/lib/CodeGen/CGDebugInfo.h | 11 +- clang/lib/CodeGen/CodeGenFunction.cpp | 3 +- clang/lib/Format/Format.cpp | 16 +- clang/lib/Frontend/CompilerInvocation.cpp | 165 +- clang/lib/Headers/altivec.h | 40 + clang/lib/Sema/SemaChecking.cpp | 38 + clang/lib/Sema/SemaDecl.cpp | 4 + clang/lib/Sema/SemaDeclAttr.cpp | 77 + clang/lib/Sema/SemaLookup.cpp | 7 + ...sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp | 7 +- clang/test/CodeGen/attr-arm-sve-vector-bits-call.c | 93 +- clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c | 27 +- .../CodeGen/attr-arm-sve-vector-bits-codegen.c | 27 +- clang/test/CodeGen/builtins-ppc-vsx.c | 60 + .../test/CodeGen/unique-internal-linkage-names.cpp | 20 +- ...pragma-attribute-supported-attributes-list.test | 2 + clang/test/Sema/attr-enforce-tcb-errors.cpp | 80 + clang/test/Sema/attr-enforce-tcb.c | 65 + clang/test/Sema/attr-enforce-tcb.cpp | 70 + clang/test/SemaCXX/cxx2a-user-defined-literals.cpp | 29 + clang/unittests/Format/SortIncludesTest.cpp | 112 + .../unittests/Frontend/CompilerInvocationTest.cpp | 15 + flang/lib/Semantics/check-directive-structure.h | 15 +- flang/lib/Semantics/check-omp-structure.cpp | 3 +- flang/test/Frontend/multiple-input-files.f90 | 10 +- flang/test/Semantics/omp-device-constructs.f90 | 2 +- libc/src/__support/CMakeLists.txt | 10 +- libc/src/__support/{common.h.def => common.h} | 18 +- .../algorithm.version.pass.cpp | 2 + .../support.limits.general/any.version.pass.cpp | 2 + .../support.limits.general/array.version.pass.cpp | 2 + .../support.limits.general/atomic.version.pass.cpp | 2 + .../barrier.version.pass.cpp | 2 + .../support.limits.general/bit.version.pass.cpp | 2 + .../support.limits.general/chrono.version.pass.cpp | 2 + .../support.limits.general/cmath.version.pass.cpp | 2 + .../compare.version.pass.cpp | 2 + .../complex.version.pass.cpp | 2 + .../concepts.version.pass.cpp | 2 + .../cstddef.version.pass.cpp | 2 + .../support.limits.general/deque.version.pass.cpp | 2 + .../exception.version.pass.cpp | 2 + .../execution.version.pass.cpp | 2 + .../filesystem.version.pass.cpp | 2 + .../forward_list.version.pass.cpp | 2 + .../functional.version.pass.cpp | 2 + .../iomanip.version.pass.cpp | 2 + .../istream.version.pass.cpp | 2 + .../iterator.version.pass.cpp | 2 + .../support.limits.general/latch.version.pass.cpp | 2 + .../support.limits.general/limits.version.pass.cpp | 2 + .../support.limits.general/list.version.pass.cpp | 2 + .../support.limits.general/locale.version.pass.cpp | 2 + .../support.limits.general/map.version.pass.cpp | 2 + .../support.limits.general/memory.version.pass.cpp | 2 + .../support.limits.general/mutex.version.pass.cpp | 2 + .../support.limits.general/new.version.pass.cpp | 2 + .../numbers.version.pass.cpp | 2 + .../numeric.version.pass.cpp | 2 + .../optional.version.pass.cpp | 2 + .../ostream.version.pass.cpp | 2 + .../support.limits.general/regex.version.pass.cpp | 2 + .../scoped_allocator.version.pass.cpp | 2 + .../semaphore.version.pass.cpp | 2 + .../support.limits.general/set.version.pass.cpp | 2 + .../shared_mutex.version.pass.cpp | 2 + .../support.limits.general/span.version.pass.cpp | 2 + .../support.limits.general/string.version.pass.cpp | 2 + .../string_view.version.pass.cpp | 2 + .../support.limits.general/thread.version.pass.cpp | 2 + .../support.limits.general/tuple.version.pass.cpp | 2 + .../type_traits.version.pass.cpp | 2 + .../unordered_map.version.pass.cpp | 2 + .../unordered_set.version.pass.cpp | 2 + .../utility.version.pass.cpp | 2 + .../variant.version.pass.cpp | 2 + .../support.limits.general/vector.version.pass.cpp | 2 + .../version.version.pass.cpp | 2 + .../generate_feature_test_macro_components.py | 2 + lld/ELF/Driver.cpp | 11 +- lld/test/ELF/lto/exclude-libs-libcall.ll | 28 + lld/test/wasm/debug-removed-fn.ll | 2 +- .../Shell/SymbolFile/NativePDB/disassembly.cpp | 4 +- lldb/test/Shell/SymbolFile/NativePDB/load-pdb.cpp | 2 +- lldb/unittests/Host/PipeTest.cpp | 3 + llvm/docs/AMDGPUUsage.rst | 48 +- llvm/include/llvm/ADT/IntrusiveRefCntPtr.h | 6 + llvm/include/llvm/CodeGen/FastISel.h | 25 +- .../include/llvm/ExecutionEngine/JITLink/JITLink.h | 4 +- llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h | 5 +- llvm/include/llvm/IR/DebugInfoMetadata.h | 4 + llvm/include/llvm/IR/IntrinsicsVE.td | 18 + llvm/include/llvm/Option/OptParser.td | 1 + .../include/llvm/Passes/StandardInstrumentations.h | 14 +- llvm/include/llvm/Support/InstructionCost.h | 8 - .../llvm/Target/GlobalISel/SelectionDAGCompat.td | 2 +- llvm/include/llvm/Transforms/Utils/LoopUtils.h | 6 + llvm/lib/Analysis/AliasAnalysis.cpp | 4 +- llvm/lib/Analysis/BasicAliasAnalysis.cpp | 6 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 17 +- llvm/lib/CodeGen/InlineSpiller.cpp | 42 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 14 +- llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 246 +- llvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp | 2 +- .../lib/ExecutionEngine/JITLink/JITLinkGeneric.cpp | 2 +- llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp | 2 +- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 21 +- llvm/lib/Passes/StandardInstrumentations.cpp | 52 +- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 11 +- llvm/lib/Target/AArch64/AArch64InstrGISel.td | 2 + llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 14 + llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 3 +- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 195 +- llvm/lib/Target/AMDGPU/VOP3Instructions.td | 1 + llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 104 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 13 + llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonISelLowering.h | 1 + llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 87 +- .../Target/Hexagon/HexagonLoopIdiomRecognition.cpp | 1 - llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 65 +- llvm/lib/Target/RISCV/RISCVInstrFormats.td | 18 + llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 22 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 137 +- llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td | 119 + llvm/lib/Target/RISCV/RISCVMCInstLower.cpp | 18 +- llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h | 43 +- llvm/lib/Target/SystemZ/SystemZScheduleZ13.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZ14.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZ15.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZ196.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td | 2 +- llvm/lib/Target/VE/VEInstrIntrinsicVL.td | 31 + llvm/lib/Target/X86/X86ISelLowering.cpp | 47 +- llvm/lib/Transforms/IPO/OpenMPOpt.cpp | 208 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 15 + llvm/lib/Transforms/Scalar/GVNHoist.cpp | 1 - llvm/lib/Transforms/Scalar/LoopDeletion.cpp | 51 + llvm/lib/Transforms/Utils/LoopUnroll.cpp | 105 +- llvm/lib/Transforms/Utils/LoopUtils.cpp | 32 + .../Utils/UniqueInternalLinkageNames.cpp | 20 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 55 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 2 +- llvm/lib/Transforms/Vectorize/VPlan.cpp | 72 +- llvm/lib/Transforms/Vectorize/VPlan.h | 16 +- llvm/lib/Transforms/Vectorize/VPlanSLP.cpp | 4 +- llvm/lib/Transforms/Vectorize/VPlanValue.h | 11 +- llvm/test/Analysis/CostModel/ARM/arith-overflow.ll | 48 +- llvm/test/Analysis/CostModel/ARM/cast.ll | 110 +- .../CostModel/ARM/mve-gather-scatter-cost.ll | 6 +- llvm/test/CodeGen/AArch64/arm64-abi_align.ll | 8 +- llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll | 15 +- llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll | 6 +- .../CodeGen/AArch64/arm64-fast-isel-intrinsic.ll | 4 +- llvm/test/CodeGen/AArch64/arm64-fast-isel.ll | 21 +- .../AArch64/arm64-patchpoint-webkit_jscc.ll | 18 +- llvm/test/CodeGen/AArch64/cfguard-checks.ll | 4 +- .../AArch64/dag-combine-insert-subvector.ll | 28 + llvm/test/CodeGen/AArch64/elf-globals-static.ll | 10 + llvm/test/CodeGen/AArch64/large-stack.ll | 3 +- .../CodeGen/AArch64/sve-masked-gather-legalize.ll | 106 + llvm/test/CodeGen/AArch64/swifterror.ll | 8 +- .../AMDGPU/GlobalISel/combine-urem-pow-2.mir | 8 +- llvm/test/CodeGen/AMDGPU/fneg-combines.ll | 2 +- llvm/test/CodeGen/AMDGPU/frem.ll | 6 +- llvm/test/CodeGen/AMDGPU/lit.local.cfg | 10 - llvm/test/CodeGen/ARM/fast-isel-call.ll | 72 +- llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll | 14 +- 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llvm/test/CodeGen/X86/fast-isel-select.ll | 8 +- llvm/test/CodeGen/X86/horizontal-shuffle-2.ll | 266 +- ...zontal-shuffle-2.ll => horizontal-shuffle-3.ll} | 119 - llvm/test/CodeGen/X86/horizontal-sum.ll | 1189 +++++++++ llvm/test/CodeGen/X86/inreg.ll | 4 +- llvm/test/CodeGen/X86/lit.local.cfg | 8 - llvm/test/CodeGen/X86/lvi-hardening-loads.ll | 2 +- llvm/test/CodeGen/X86/lzcnt-cmp.ll | 192 +- llvm/test/CodeGen/X86/membarrier.ll | 2 +- llvm/test/CodeGen/X86/pr32241.ll | 10 +- llvm/test/CodeGen/X86/pr32256.ll | 4 +- llvm/test/CodeGen/X86/pr32284.ll | 16 +- llvm/test/CodeGen/X86/pr32340.ll | 52 +- llvm/test/CodeGen/X86/pr32345.ll | 8 +- llvm/test/CodeGen/X86/pr32484.ll | 2 +- llvm/test/CodeGen/X86/pr44749.ll | 2 - llvm/test/CodeGen/X86/sink-local-value.ll | 2 +- llvm/test/CodeGen/X86/sqrt-fastmath-mir.ll | 36 +- llvm/test/CodeGen/X86/sqrt-fastmath.ll | 8 +- llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll | 16 +- .../X86/vector-constrained-fp-intrinsics.ll | 766 +++--- llvm/test/CodeGen/X86/vector-trunc.ll | 8 +- llvm/test/CodeGen/X86/volatile.ll | 38 +- llvm/test/CodeGen/{X86 => }/lit.local.cfg | 3 - llvm/test/DebugInfo/COFF/lines-bb-start.ll | 1 - llvm/test/DebugInfo/Mips/delay-slot.ll | 3 +- llvm/test/DebugInfo/X86/fission-ranges.ll | 24 +- llvm/test/DebugInfo/X86/prologue-stack.ll | 2 +- .../AArch64/armv8.3a-signed-pointer.txt | 2 + llvm/test/Other/change-printer.ll | 151 ++ .../Transforms/IndVarSimplify/exit_value_test2.ll | 6 +- llvm/test/Transforms/InstCombine/icmp-shr.ll | 78 +- llvm/test/Transforms/LoopDeletion/update-scev.ll | 3 +- llvm/test/Transforms/LoopDeletion/zero-btc.ll | 86 +- .../Transforms/LoopUnroll/unroll-after-peel.ll | 48 + .../Transforms/LoopVectorize/vplan-printing.ll | 4 +- .../Transforms/OpenMP/parallel_region_merging.ll | 1955 ++++++++++++-- llvm/test/Transforms/SCCP/conditions-ranges.ll | 48 +- .../unique-internal-linkage-names.ll | 50 + .../unique_symbol_names.ll | 4 +- .../unique-internal-linkage-names.ll | 24 - .../Transforms/Util/PredicateInfo/testandor.ll | 74 + llvm/test/tools/llvm-elfabi/fail-file-write.test | 2 +- llvm/test/tools/llvm-profdata/csprof-dump.test | 2 +- llvm/test/tools/llvm-profdata/instr-remap.test | 2 +- llvm/test/tools/llvm-readobj/ELF/gnu-notes.test | 8 +- .../llvm-readobj/ELF/note-core-ntfile-bad.test | 8 +- .../tools/llvm-readobj/ELF/relocation-errors.test | 8 +- llvm/test/tools/llvm-readobj/ELF/relocations.test | 8 +- llvm/test/tools/llvm-readobj/ELF/stack-sizes.test | 30 +- llvm/test/tools/obj2yaml/ELF/section-group.yaml | 67 +- llvm/test/tools/obj2yaml/ELF/symbol.yaml | 41 + llvm/tools/llvm-link/llvm-link.cpp | 3 +- llvm/tools/llvm-profdata/llvm-profdata.cpp | 4 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 13 +- llvm/tools/obj2yaml/elf2yaml.cpp | 29 +- llvm/unittests/ADT/IntrusiveRefCntPtrTest.cpp | 16 + llvm/unittests/Support/InstructionCostTest.cpp | 4 +- llvm/unittests/Transforms/Vectorize/VPlanTest.cpp | 72 +- llvm/utils/TableGen/GlobalISelEmitter.cpp | 2 + llvm/utils/TableGen/OptParserEmitter.cpp | 12 +- mlir/cmake/modules/AddMLIRPythonExtension.cmake | 26 +- mlir/docs/OpDefinitions.md | 165 ++ mlir/include/mlir-c/AffineExpr.h | 23 +- mlir/include/mlir-c/AffineMap.h | 16 +- mlir/include/mlir-c/Bindings/Python/Interop.h | 21 + mlir/include/mlir-c/BuiltinTypes.h | 8 +- mlir/include/mlir-c/Dialect/Linalg.h | 25 + mlir/include/mlir-c/Dialect/SCF.h | 25 + mlir/include/mlir-c/Dialect/Shape.h | 25 + .../{StandardDialect.h => Dialect/Standard.h} | 22 +- mlir/include/mlir-c/Dialect/Tensor.h | 25 + mlir/include/mlir-c/Registration.h | 55 +- mlir/include/mlir/CAPI/Registration.h | 40 + .../mlir/Conversion/AsyncToLLVM/AsyncToLLVM.h | 16 + .../StandardToLLVM/ConvertStandardToLLVM.h | 2 +- mlir/include/mlir/Dialect/ArmSVE/ArmSVE.td | 2 +- mlir/include/mlir/Dialect/GPU/Passes.td | 1 + mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td | 8 + mlir/include/mlir/Dialect/Linalg/Passes.td | 22 +- .../mlir/Dialect/Linalg/Transforms/Transforms.h | 58 +- mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td | 4 +- mlir/include/mlir/Dialect/Vector/VectorOps.td | 18 +- mlir/include/mlir/IR/BuiltinTypes.h | 219 +- mlir/include/mlir/IR/BuiltinTypes.td | 240 ++ mlir/include/mlir/IR/OpBase.td | 82 + mlir/include/mlir/TableGen/Builder.h | 85 + mlir/include/mlir/TableGen/Operator.h | 7 + mlir/include/mlir/TableGen/TypeDef.h | 43 +- mlir/lib/Bindings/Python/CMakeLists.txt | 20 +- mlir/lib/Bindings/Python/IRModules.cpp | 579 ++++- mlir/lib/Bindings/Python/IRModules.h | 29 + mlir/lib/Bindings/Python/LinalgOps.td | 16 + mlir/lib/Bindings/Python/ShapeOps.td | 15 + mlir/lib/Bindings/Python/TensorOps.td | 15 + mlir/lib/CAPI/CMakeLists.txt | 2 +- mlir/lib/CAPI/Dialect/CMakeLists.txt | 48 + mlir/lib/CAPI/Dialect/Linalg.cpp | 14 + mlir/lib/CAPI/Dialect/SCF.cpp | 13 + mlir/lib/CAPI/Dialect/Shape.cpp | 13 + mlir/lib/CAPI/Dialect/Standard.cpp | 13 + mlir/lib/CAPI/Dialect/Tensor.cpp | 14 + mlir/lib/CAPI/IR/AffineExpr.cpp | 20 + mlir/lib/CAPI/IR/AffineMap.cpp | 17 +- mlir/lib/CAPI/IR/BuiltinTypes.cpp | 11 + mlir/lib/CAPI/Standard/CMakeLists.txt | 7 - mlir/lib/CAPI/Standard/StandardDialect.cpp | 25 - mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp | 73 +- .../GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp | 6 +- .../SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp | 4 +- .../Conversion/StandardToLLVM/StandardToLLVM.cpp | 18 +- .../Dialect/GPU/Transforms/AsyncRegionRewriter.cpp | 4 +- mlir/lib/Dialect/GPU/Transforms/PassDetail.h | 1 + mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp | 126 +- .../Dialect/Linalg/Transforms/FusionOnTensors.cpp | 99 +- mlir/lib/Dialect/Linalg/Transforms/Loops.cpp | 83 +- mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp | 5 +- mlir/lib/Dialect/Vector/VectorOps.cpp | 48 +- mlir/lib/IR/BuiltinTypes.cpp | 46 +- mlir/lib/IR/MLIRContext.cpp | 8 - mlir/lib/IR/TypeDetail.h | 43 - mlir/lib/Parser/AttributeParser.cpp | 5 + mlir/lib/TableGen/Builder.cpp | 74 + mlir/lib/TableGen/CMakeLists.txt | 1 + mlir/lib/TableGen/Operator.cpp | 12 + mlir/lib/TableGen/TypeDef.cpp | 53 + mlir/lib/Target/SPIRV/Deserialization.cpp | 139 +- mlir/lib/Target/SPIRV/Serialization.cpp | 49 + mlir/test/Bindings/Python/CMakeLists.txt | 4 +- mlir/test/Bindings/Python/ir_affine_expr.py | 275 ++ mlir/test/Bindings/Python/ir_affine_map.py | 148 ++ mlir/test/Bindings/Python/ir_types.py | 16 +- mlir/test/CAPI/ir.c | 52 +- .../lower-alloc-to-gpu-runtime-calls.mlir | 11 +- .../Conversion/VectorToSCF/vector-to-loops.mlir | 16 +- mlir/test/Dialect/Linalg/canonicalize.mlir | 36 + mlir/test/Dialect/Linalg/loop-order.mlir | 24 + mlir/test/Dialect/Linalg/reshape_fusion.mlir | 166 +- .../Linalg/reshape_linearization_fusion.mlir | 145 +- mlir/test/Dialect/SPIRV/IR/structure-ops.mlir | 14 + mlir/test/Dialect/Vector/canonicalize.mlir | 35 + mlir/test/Dialect/Vector/invalid.mlir | 31 + mlir/test/IR/invalid-ops.mlir | 8 + mlir/test/Target/SPIRV/spec-constant.mlir | 31 + mlir/test/lib/Dialect/Test/TestTypeDefs.td | 20 +- mlir/test/lib/Dialect/Test/TestTypes.cpp | 2 +- mlir/test/mlir-tblgen/typedefs.td | 24 +- mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp | 98 +- mlir/tools/mlir-tblgen/TypeDefGen.cpp | 245 +- openmp/libomptarget/plugins/CMakeLists.txt | 33 +- openmp/libomptarget/plugins/amdgpu/CMakeLists.txt | 1 + openmp/libomptarget/plugins/amdgpu/src/rtl.cpp | 2 +- openmp/libomptarget/plugins/common/CMakeLists.txt | 13 + .../plugins/common/elf_common/CMakeLists.txt | 15 + .../{elf_common.c => elf_common/elf_common.h} | 6 +- openmp/libomptarget/plugins/cuda/CMakeLists.txt | 1 + openmp/libomptarget/plugins/cuda/src/rtl.cpp | 2 +- .../plugins/generic-elf-64bit/src/rtl.cpp | 2 +- openmp/libomptarget/plugins/ve/CMakeLists.txt | 1 + openmp/libomptarget/plugins/ve/src/rtl.cpp | 2 +- 433 files changed, 20152 insertions(+), 4006 deletions(-) create mode 100644 clang/test/Sema/attr-enforce-tcb-errors.cpp create mode 100644 clang/test/Sema/attr-enforce-tcb.c create mode 100644 clang/test/Sema/attr-enforce-tcb.cpp rename libc/src/__support/{common.h.def => common.h} (54%) create mode 100644 lld/test/ELF/lto/exclude-libs-libcall.ll create mode 100644 llvm/test/CodeGen/AArch64/dag-combine-insert-subvector.ll create mode 100644 llvm/test/CodeGen/Hexagon/autohvx/widen-setcc.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll create mode 100644 llvm/test/CodeGen/VE/VELIntrinsics/extract.ll create mode 100644 llvm/test/CodeGen/VE/VELIntrinsics/insert.ll create mode 100644 llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll delete mode 100644 llvm/test/CodeGen/X86/fast-isel-constant.ll create mode 100644 llvm/test/CodeGen/X86/fast-isel-prolog-dbgloc.ll copy llvm/test/CodeGen/X86/{horizontal-shuffle-2.ll => horizontal-shuffle-3.ll} (51%) create mode 100644 llvm/test/CodeGen/X86/horizontal-sum.ll copy llvm/test/CodeGen/{X86 => }/lit.local.cfg (82%) create mode 100644 llvm/test/Transforms/LoopUnroll/unroll-after-peel.ll create mode 100644 llvm/test/Transforms/UniqueInternalLinkageNames/unique-internal [...] delete mode 100644 llvm/test/Transforms/UniqueLinkageNames/unique-internal-linkage [...] create mode 100644 mlir/include/mlir-c/Dialect/Linalg.h create mode 100644 mlir/include/mlir-c/Dialect/SCF.h create mode 100644 mlir/include/mlir-c/Dialect/Shape.h rename mlir/include/mlir-c/{StandardDialect.h => Dialect/Standard.h} (52%) create mode 100644 mlir/include/mlir-c/Dialect/Tensor.h create mode 100644 mlir/include/mlir/CAPI/Registration.h create mode 100644 mlir/include/mlir/TableGen/Builder.h create mode 100644 mlir/lib/Bindings/Python/LinalgOps.td create mode 100644 mlir/lib/Bindings/Python/ShapeOps.td create mode 100644 mlir/lib/Bindings/Python/TensorOps.td create mode 100644 mlir/lib/CAPI/Dialect/CMakeLists.txt create mode 100644 mlir/lib/CAPI/Dialect/Linalg.cpp create mode 100644 mlir/lib/CAPI/Dialect/SCF.cpp create mode 100644 mlir/lib/CAPI/Dialect/Shape.cpp create mode 100644 mlir/lib/CAPI/Dialect/Standard.cpp create mode 100644 mlir/lib/CAPI/Dialect/Tensor.cpp delete mode 100644 mlir/lib/CAPI/Standard/CMakeLists.txt delete mode 100644 mlir/lib/CAPI/Standard/StandardDialect.cpp create mode 100644 mlir/lib/TableGen/Builder.cpp create mode 100644 mlir/test/Bindings/Python/ir_affine_expr.py create mode 100644 mlir/test/Dialect/Linalg/loop-order.mlir create mode 100644 openmp/libomptarget/plugins/common/CMakeLists.txt create mode 100644 openmp/libomptarget/plugins/common/elf_common/CMakeLists.txt rename openmp/libomptarget/plugins/common/{elf_common.c => elf_common/elf_common.h} (93%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig updated (1d3160b4 -> 6604eae8)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig in repository toolchain/ci/base-artifacts. discards 1d3160b4 0: update: llvm-linux-qemu: boot new 6604eae8 0: update: llvm-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (1d3160b4) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 162 +- 02-prepare_abe/console.log | 440 +- 03-build_llvm/console.log | 13732 ++++++++++++------------ 04-build_linux/console.log | 758 +- 05-build_abe-qemu/console.log | 5994 ++++++----- 06-boot_linux/console.log | 492 +- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 10 +- console.log | 21590 +++++++++++++++++++------------------- jenkins/manifest.sh | 12 +- 10 files changed, 21588 insertions(+), 21604 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allyesconfig updated (7be3285248b -> 32bcfcda4e2)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allyesconfig in repository toolchain/ci/llvm-project. from 7be3285248b [OpenMP] Not set OPENMP_STANDALONE_BUILD=ON when building O [...] adds 407b1e65a46 [StringExtras] Add a helper class for comma-separated lists adds 02bc320545d CGDebugInfo: Delete unused DIFile* parameter adds 4739dd67e7a [LoopDeletion] Break backedge of outermost loops when known [...] adds d43a264a5dd Revert "[X86][SSE] Fold unpack(hop(),hop()) -> permute(hop())" adds 7539c75bb43 [DAGCombine] Remove the check for unsafe-fp-math when we ar [...] adds 5cf73dca77e [RISCV] Convert most of the information about RVV Pseudos i [...] adds 7f69860243e [LoopUnroll] Fix a crash adds ffa67873a3f [PowerPC] Add variants of 64-bit vector types for vec_sel. adds dcac2da1063 [IR Parser] Fix a crash handling zero width integer attributes. adds 6215c1b778f CGDebugInfo: Delete redundant test adds b8d28420885 CGDebugInfo: Delete unneeded UnwrapTypeForDebugInfo adds a40767ec885 [MLIR][SPIRV] Add (de-)serialization support for SpecConsta [...] adds 5e476061deb [NFC][AsmPrinter] Make comments for spill/reload more precise. adds 7b11f564dcf [JITLink] Rename PostAllocationPasses to PreFixupPasses. adds 131ce834e4b [RISCV] Clear isCodeGenOnly flag on VMSGE(U) pseudo instruc [...] adds af339f89a14 Remove redundant casts. adds cddd3faf5de [CSKY] Add visibility macro to fix link error adds ee27c767bd2 [clang-format] Skip UTF8 Byte Order Mark while sorting includes adds 0c8b748f321 [ARM] Additional trunc cost tests. NFC adds 7473940bae0 [clang-format] turn on formatting after "clang-format on" w [...] adds 89878e8c966 [clang-format] Find main include after block ended with #pr [...] adds dcefcd51e01 [ARM] Update trunc costs adds b7ccaca5370 [NFC] Remove min/max functions from InstructionCost adds 97100646d1b Reapply "[clang][cli] Port DiagnosticOpts to new option par [...] adds 40abeb11f45 [NFC][InstructionCost] Change LoopVectorizationCostModel::g [...] adds 8165a034203 [ARM] Add debug messages for the load store optimizer. NFC adds 1677c86124e [clangd] Add metrics for go-to-implementation. adds c5be0e0cc0e [X86] Fix tile register spill issue. adds 675be651062 Require chained analyses in BasicAA and AAResults to be transitive adds c37f68a8885 [SVE][CodeGen] Fix legalisation of floating-point masked gathers adds 41bf338dd1e Revert rGd43a264a5dd3 "Revert "[X86][SSE] Fold unpack(hop() [...] adds 59632292663 [X86][SSE] Add missing SSE test coverage for permute(hop,ho [...] adds b72ca799823 [VE] Support intrinsic to isnert/extract_subreg of v512i1 adds d02de139324 [VE] Support additional VMRGW and VMV intrinsic instructions adds c74751d4b5b [obj2yaml] - Fix the crash in getUniquedSectionName(). adds 8ea72b38873 [clang][AArch64][SVE] Avoid going through memory for coerce [...] adds a6db7cf1ce7 [llvm-readelf/obj] - Index phdrs and relocations from 0 whe [...] adds a94497a3429 [VPlan] Move initial quote emission from ::print to ::dumpB [...] adds a5b484c4d41 [obj2yaml][test] - Improve and fix section-group.yaml test. adds d36e879c21c [lldb] Disable PipeTest.OpenAsReader on windows adds 8112a2598ce [X86][SSE] Add 'vectorized sum' test patterns adds 2e17d9c0ee7 [ARM] Add uses for locals introduced for debug messages. NFC. adds 6dcf9207df1 [AMDGPU] Fix a urem combine test to test what it was supposed to adds 4fe7b16ae3f [mlir] Remove unnecessary llvm.mlir.cast in AsyncToLLVM lowering. adds 4c372a35cd8 [mlir] Make GpuAsyncRegion pass depend on async dialect. adds 8298ec2d629 [flang][driver] Copy input files into a temp dir when testing adds df86f15f0c5 [mlir][linalg] Support parsing attributes in named op spec adds 55225471d98 [mlir][linalg] Support permutation when lowering to loop nests adds 007358239de [DAGCombiner] Use getVectorElementCount inside visitINSERT_ [...] adds c163aae45ef [attributes] Add a facility for enforcing a Trusted Comput [...] adds eb0371e403a [VPlan] Unify value/recipe printing after VPDef transition. adds 419ef38a502 Revert "[attributes] Add a facility for enforcing a Truste [...] adds d59ddba7772 [mlir] Fix gpu-to-llvm lowering for gpu.alloc with dynamic sizes. adds a46982a2551 [X86] Add nounwind to lzcnt-cmp tests adds a0f82749f4f [X86] Extend lzcnt-cmp tests to test on non-lzcnt targets adds dbd5fa1e75d [ARM] Update existing test case with +pauth targets adds a2dbf3443af [clangd] Fix -check mode doesn't respect any tidy configs. adds 97517055128 [OpenMPOpt][WIP] Expand parallel region merging adds 31732e6f52c [clangd] Remove ScratchFS from tests adds e5eb5c8a7f3 NFC: Use -LABEL more adds c161775decd [FastISel] Flush local value map on every instruction adds 4214ca96145 [X86][AVX] Attempt to fold vpermf128(op(x,i),op(y,i)) -> op [...] adds 9c0dc0b2c1c [mlir][Linalg] Fold init_tensor -> linalg.tensor_reshape. adds c15b0e2229e [Clang][Docs] Fix ambiguity in clang-offload-bundler docs adds 7200d2cf089 [NFC] Disallow unused prefixes in CodeGen/PowerPC tests. adds 3d693bd0bd7 [mlir][vector] Add memory effects to transfer_read transfer [...] adds c4486cfd556 [mlir][Linalg] Fix reshape fusion to reshape the outs inste [...] adds be179b9946f [FastISel] NFC: Remove obsolete -fast-isel-sink-local-value [...] adds ac2224c0228 [ELF] --exclude-libs: localize defined libcall symbols refe [...] adds 171771e0780 [SystemZ] Minor NFC fix in SchedModels. adds 1f9c29228ce [FastISel] NFC: Clean up unnecessary bookkeeping adds 072714b9619 [X86] Regenerate vector-constrained-fp-intrinsics.ll tests adds 35c9baa11e4 [attributes] Add a facility for enforcing a Trusted Comput [...] adds a90214760d0 [Hexagon] Custom-widen SETCC's operands adds bcec0f27a2c [AMDGPU] Deduplicate VOP tablegen asm & ins adds 74628c43053 [mlir] Add Python bindings for AffineExpr adds e79bd0b4f25 [mlir] More Python bindings for AffineMap adds 547e3eef14a [mlir] Expose MemRef layout in Python bindings adds 47567ca5fac [flang][openxx][NFC] Remove duplicated function to check re [...] adds d8c6d24359f -funique-internal-linkage-names appends a hex md5hash suffi [...] adds 43a830ed941 Introduce new quiet mode and new option handling for -print [...] adds 5464baaae8c Fix minor build issue (NFC) adds 1027a22ccd7 [SystemZ][z/OS] Fix Permission denied pattern matching adds 195728c75aa [mlir] Add structural conversion to async dialect lowering. adds 37b41bd0879 [RISCV] Add scalable vector fcmp ISel patterns adds 30a7d430e86 [libc++] Turn off auto-formatting of generated files. NFC. adds 72f1f084670 [NFC][AMDGPU] Clarify memory model support for volatile adds 20741773013 [mlir][ODS] Add a C++ abstraction for OpBuilders adds 948be58258d [mlir][TypeDefGen] Add support for adding builders when gen [...] adds d79642b3db1 [mlir][IR][NFC] Move the definitions of Complex/Function/In [...] adds d3ff24cbf87 [ADT] Add makeIntrusiveRefCnt helper function adds 8ad998a6115 [tools] Mark output of tools as text if it is really text adds 05e90cefeb4 [NFC] Disallow unused prefixes under llvm/test/CodeGen adds c1ae378205d [mlir][vector] Add side-effect information to different loa [...] adds 53c866c286a Enable python bindings for tensor, shape and linalg dialects. adds cceb1bfcbbc [mlir][CAPI] Introduce standard source layout for mlir-c di [...] adds 110775809ad Revert "[mlir][linalg] Support parsing attributes in named [...] adds 288f3fc5dfe [InstCombine] reduce icmp(ashr X, C1), C2 to sign-bit test adds 32c073acb32 [GlobalISel] Map extractelt to G_EXTRACT_VECTOR_ELT adds aefeb5f136e [libc][NFC] Make __support/common.h an in tree header. adds 9b222b108a2 [c++20] Don't consider string literal operator templates fo [...] adds f4cec703ec8 Add an assert to CGDebugInfo::getTypeOrNull adds 7989684a2e4 [RISCV] Add scalable vector fadd/fsub/fmul/fdiv ISel patterns adds 046612d29d7 [mlir][vector] verify memref of vector memory ops adds a808d89d355 [PredicateInfo] Add test for one unknown condition in and/or (NFC) adds 00f773cf424 [SCCP] Fix misclassified conditions in test (NFC) adds b88c8f1aab5 CGDebugInfo: Delete unused parameters adds 32bcfcda4e2 Rename debug linkage name with -funique-internal-linkage-names No new revisions were added by this update. Summary of changes: clang-tools-extra/clangd/XRefs.cpp | 11 + clang-tools-extra/clangd/tool/Check.cpp | 1 + .../unittests/GlobalCompilationDatabaseTests.cpp | 75 +- clang/docs/ClangOffloadBundler.rst | 4 +- clang/include/clang/Basic/Attr.td | 16 + clang/include/clang/Basic/AttrDocs.td | 25 + clang/include/clang/Basic/DiagnosticOptions.h | 12 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 7 + clang/include/clang/Driver/Options.td | 112 +- clang/include/clang/Sema/Sema.h | 5 + clang/lib/CodeGen/CGCall.cpp | 15 + clang/lib/CodeGen/CGDebugInfo.cpp | 24 +- clang/lib/CodeGen/CGDebugInfo.h | 11 +- clang/lib/CodeGen/CodeGenFunction.cpp | 3 +- clang/lib/Format/Format.cpp | 16 +- clang/lib/Frontend/CompilerInvocation.cpp | 165 +- clang/lib/Headers/altivec.h | 40 + clang/lib/Sema/SemaChecking.cpp | 38 + clang/lib/Sema/SemaDecl.cpp | 4 + clang/lib/Sema/SemaDeclAttr.cpp | 77 + clang/lib/Sema/SemaLookup.cpp | 7 + ...sve-acle-__ARM_FEATURE_SVE_VECTOR_OPERATORS.cpp | 7 +- clang/test/CodeGen/attr-arm-sve-vector-bits-call.c | 93 +- clang/test/CodeGen/attr-arm-sve-vector-bits-cast.c | 27 +- .../CodeGen/attr-arm-sve-vector-bits-codegen.c | 27 +- clang/test/CodeGen/builtins-ppc-vsx.c | 60 + .../test/CodeGen/unique-internal-linkage-names.cpp | 20 +- ...pragma-attribute-supported-attributes-list.test | 2 + clang/test/Sema/attr-enforce-tcb-errors.cpp | 80 + clang/test/Sema/attr-enforce-tcb.c | 65 + clang/test/Sema/attr-enforce-tcb.cpp | 70 + clang/test/SemaCXX/cxx2a-user-defined-literals.cpp | 29 + clang/unittests/Format/SortIncludesTest.cpp | 112 + .../unittests/Frontend/CompilerInvocationTest.cpp | 15 + flang/lib/Semantics/check-directive-structure.h | 15 +- flang/lib/Semantics/check-omp-structure.cpp | 3 +- flang/test/Frontend/multiple-input-files.f90 | 10 +- flang/test/Semantics/omp-device-constructs.f90 | 2 +- libc/src/__support/CMakeLists.txt | 10 +- libc/src/__support/{common.h.def => common.h} | 18 +- .../algorithm.version.pass.cpp | 2 + .../support.limits.general/any.version.pass.cpp | 2 + .../support.limits.general/array.version.pass.cpp | 2 + .../support.limits.general/atomic.version.pass.cpp | 2 + .../barrier.version.pass.cpp | 2 + .../support.limits.general/bit.version.pass.cpp | 2 + .../support.limits.general/chrono.version.pass.cpp | 2 + .../support.limits.general/cmath.version.pass.cpp | 2 + .../compare.version.pass.cpp | 2 + .../complex.version.pass.cpp | 2 + .../concepts.version.pass.cpp | 2 + .../cstddef.version.pass.cpp | 2 + .../support.limits.general/deque.version.pass.cpp | 2 + .../exception.version.pass.cpp | 2 + .../execution.version.pass.cpp | 2 + .../filesystem.version.pass.cpp | 2 + .../forward_list.version.pass.cpp | 2 + .../functional.version.pass.cpp | 2 + .../iomanip.version.pass.cpp | 2 + .../istream.version.pass.cpp | 2 + .../iterator.version.pass.cpp | 2 + .../support.limits.general/latch.version.pass.cpp | 2 + .../support.limits.general/limits.version.pass.cpp | 2 + .../support.limits.general/list.version.pass.cpp | 2 + .../support.limits.general/locale.version.pass.cpp | 2 + .../support.limits.general/map.version.pass.cpp | 2 + .../support.limits.general/memory.version.pass.cpp | 2 + .../support.limits.general/mutex.version.pass.cpp | 2 + .../support.limits.general/new.version.pass.cpp | 2 + .../numbers.version.pass.cpp | 2 + .../numeric.version.pass.cpp | 2 + .../optional.version.pass.cpp | 2 + .../ostream.version.pass.cpp | 2 + .../support.limits.general/regex.version.pass.cpp | 2 + .../scoped_allocator.version.pass.cpp | 2 + .../semaphore.version.pass.cpp | 2 + .../support.limits.general/set.version.pass.cpp | 2 + .../shared_mutex.version.pass.cpp | 2 + .../support.limits.general/span.version.pass.cpp | 2 + .../support.limits.general/string.version.pass.cpp | 2 + .../string_view.version.pass.cpp | 2 + .../support.limits.general/thread.version.pass.cpp | 2 + .../support.limits.general/tuple.version.pass.cpp | 2 + .../type_traits.version.pass.cpp | 2 + .../unordered_map.version.pass.cpp | 2 + .../unordered_set.version.pass.cpp | 2 + .../utility.version.pass.cpp | 2 + .../variant.version.pass.cpp | 2 + .../support.limits.general/vector.version.pass.cpp | 2 + .../version.version.pass.cpp | 2 + .../generate_feature_test_macro_components.py | 2 + lld/ELF/Driver.cpp | 11 +- lld/test/ELF/lto/exclude-libs-libcall.ll | 28 + lld/test/wasm/debug-removed-fn.ll | 2 +- .../Shell/SymbolFile/NativePDB/disassembly.cpp | 4 +- lldb/test/Shell/SymbolFile/NativePDB/load-pdb.cpp | 2 +- lldb/unittests/Host/PipeTest.cpp | 3 + llvm/docs/AMDGPUUsage.rst | 48 +- llvm/include/llvm/ADT/IntrusiveRefCntPtr.h | 6 + llvm/include/llvm/ADT/StringExtras.h | 24 + llvm/include/llvm/CodeGen/FastISel.h | 25 +- .../include/llvm/ExecutionEngine/JITLink/JITLink.h | 4 +- llvm/include/llvm/Frontend/OpenMP/OMPIRBuilder.h | 5 +- llvm/include/llvm/IR/DebugInfoMetadata.h | 4 + llvm/include/llvm/IR/IntrinsicsVE.td | 18 + llvm/include/llvm/Option/OptParser.td | 1 + .../include/llvm/Passes/StandardInstrumentations.h | 14 +- llvm/include/llvm/Support/InstructionCost.h | 8 - .../llvm/Target/GlobalISel/SelectionDAGCompat.td | 2 +- llvm/include/llvm/Transforms/Utils/LoopUtils.h | 6 + llvm/lib/Analysis/AliasAnalysis.cpp | 4 +- llvm/lib/Analysis/BasicAliasAnalysis.cpp | 6 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 17 +- llvm/lib/CodeGen/InlineSpiller.cpp | 42 +- llvm/lib/CodeGen/MachineBasicBlock.cpp | 25 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 14 +- llvm/lib/CodeGen/SelectionDAG/FastISel.cpp | 246 +- llvm/lib/ExecutionEngine/JITLink/ELF_x86_64.cpp | 2 +- .../lib/ExecutionEngine/JITLink/JITLinkGeneric.cpp | 2 +- llvm/lib/ExecutionEngine/JITLink/MachO_x86_64.cpp | 2 +- llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 21 +- llvm/lib/Passes/StandardInstrumentations.cpp | 52 +- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 11 +- llvm/lib/Target/AArch64/AArch64InstrGISel.td | 2 + llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 14 + llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 3 +- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 195 +- llvm/lib/Target/AMDGPU/VOP3Instructions.td | 1 + llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp | 104 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 13 + llvm/lib/Target/CSKY/TargetInfo/CSKYTargetInfo.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonISelLowering.h | 1 + llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 87 +- .../Target/Hexagon/HexagonLoopIdiomRecognition.cpp | 1 - llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 65 +- llvm/lib/Target/RISCV/RISCVInstrFormats.td | 18 + llvm/lib/Target/RISCV/RISCVInstrInfoV.td | 22 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 137 +- llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td | 119 + llvm/lib/Target/RISCV/RISCVMCInstLower.cpp | 18 +- llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h | 43 +- llvm/lib/Target/SystemZ/SystemZScheduleZ13.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZ14.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZ15.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZ196.td | 2 +- llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td | 2 +- llvm/lib/Target/VE/VEInstrIntrinsicVL.td | 31 + llvm/lib/Target/X86/X86ISelLowering.cpp | 47 +- llvm/lib/Transforms/IPO/OpenMPOpt.cpp | 208 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 15 + llvm/lib/Transforms/Scalar/GVNHoist.cpp | 1 - llvm/lib/Transforms/Scalar/LoopDeletion.cpp | 51 + llvm/lib/Transforms/Utils/LoopUnroll.cpp | 105 +- llvm/lib/Transforms/Utils/LoopUtils.cpp | 32 + .../Utils/UniqueInternalLinkageNames.cpp | 20 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 55 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 2 +- llvm/lib/Transforms/Vectorize/VPlan.cpp | 72 +- llvm/lib/Transforms/Vectorize/VPlan.h | 16 +- llvm/lib/Transforms/Vectorize/VPlanSLP.cpp | 4 +- llvm/lib/Transforms/Vectorize/VPlanValue.h | 11 +- llvm/test/Analysis/CostModel/ARM/arith-overflow.ll | 48 +- llvm/test/Analysis/CostModel/ARM/cast.ll | 110 +- .../CostModel/ARM/mve-gather-scatter-cost.ll | 6 +- llvm/test/CodeGen/AArch64/arm64-abi_align.ll | 8 +- llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll | 15 +- llvm/test/CodeGen/AArch64/arm64-fast-isel-gv.ll | 6 +- .../CodeGen/AArch64/arm64-fast-isel-intrinsic.ll | 4 +- llvm/test/CodeGen/AArch64/arm64-fast-isel.ll | 21 +- .../AArch64/arm64-patchpoint-webkit_jscc.ll | 18 +- llvm/test/CodeGen/AArch64/cfguard-checks.ll | 4 +- .../AArch64/dag-combine-insert-subvector.ll | 28 + llvm/test/CodeGen/AArch64/elf-globals-static.ll | 10 + llvm/test/CodeGen/AArch64/large-stack.ll | 3 +- .../CodeGen/AArch64/sve-masked-gather-legalize.ll | 106 + llvm/test/CodeGen/AArch64/swifterror.ll | 8 +- .../AMDGPU/GlobalISel/combine-urem-pow-2.mir | 8 +- llvm/test/CodeGen/AMDGPU/fneg-combines.ll | 2 +- llvm/test/CodeGen/AMDGPU/frem.ll | 6 +- llvm/test/CodeGen/AMDGPU/lit.local.cfg | 10 - llvm/test/CodeGen/ARM/fast-isel-call.ll | 72 +- llvm/test/CodeGen/ARM/fast-isel-intrinsic.ll | 14 +- .../ARM/fast-isel-ldr-str-thumb-neg-index.ll | 18 +- llvm/test/CodeGen/ARM/fast-isel-ldrh-strh-arm.ll | 38 +- llvm/test/CodeGen/ARM/fast-isel-select.ll | 46 +- llvm/test/CodeGen/ARM/fast-isel-vararg.ll | 6 +- llvm/test/CodeGen/ARM/fast-isel.ll | 19 +- llvm/test/CodeGen/ARM/speculation-hardening-sls.ll | 12 +- llvm/test/CodeGen/ARM/swifterror.ll | 6 +- llvm/test/CodeGen/Hexagon/autohvx/widen-setcc.ll | 21 + llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll | 74 +- llvm/test/CodeGen/Mips/Fast-ISel/fastalloca.ll | 2 +- llvm/test/CodeGen/Mips/Fast-ISel/fpcmpa.ll | 100 +- llvm/test/CodeGen/Mips/Fast-ISel/icmpa.ll | 32 +- llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll | 18 +- llvm/test/CodeGen/Mips/Fast-ISel/overflt.ll | 4 +- llvm/test/CodeGen/Mips/Fast-ISel/shftopm.ll | 12 +- llvm/test/CodeGen/Mips/Fast-ISel/simplestore.ll | 6 +- llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll | 10 +- .../CodeGen/Mips/emergency-spill-slot-near-fp.ll | 3 + llvm/test/CodeGen/NVPTX/f16-instructions.ll | 4 +- llvm/test/CodeGen/NVPTX/fast-math.ll | 6 +- llvm/test/CodeGen/NVPTX/sqrt-approx.ll | 16 +- llvm/test/CodeGen/PowerPC/aix-lower-jump-table.ll | 4 +- llvm/test/CodeGen/PowerPC/aix32-cc-abi-vaarg.ll | 4 +- llvm/test/CodeGen/PowerPC/aix64-cc-abi-vaarg.ll | 4 +- llvm/test/CodeGen/PowerPC/elf-common.ll | 6 +- llvm/test/CodeGen/PowerPC/fast-isel-load-store.ll | 54 +- llvm/test/CodeGen/PowerPC/lower-massv.ll | 2 +- llvm/test/CodeGen/PowerPC/mcm-1.ll | 8 +- llvm/test/CodeGen/PowerPC/mcm-13.ll | 4 +- llvm/test/CodeGen/PowerPC/mcm-2.ll | 8 +- llvm/test/CodeGen/PowerPC/mcm-3.ll | 8 +- llvm/test/CodeGen/PowerPC/mcm-6.ll | 4 +- llvm/test/CodeGen/PowerPC/mcm-9.ll | 4 +- llvm/test/CodeGen/PowerPC/mcm-default.ll | 4 +- llvm/test/CodeGen/PowerPC/popcnt-zext.ll | 4 +- llvm/test/CodeGen/PowerPC/ppc32-pic.ll | 6 +- llvm/test/CodeGen/PowerPC/srem-lkk.ll | 4 +- llvm/test/CodeGen/PowerPC/srem-vector-lkk.ll | 8 +- llvm/test/CodeGen/PowerPC/testComparesigeuc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesigeui.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesigeull.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesigeus.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesileuc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesileui.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesileull.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesileus.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltsc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltsi.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltsll.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltss.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltuc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltui.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesiltus.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllgeuc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllgeui.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllgeull.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllgeus.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllleuc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllleui.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllleull.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllleus.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllltsll.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllltuc.ll | 6 +- llvm/test/CodeGen/PowerPC/testComparesllltus.ll | 6 +- llvm/test/CodeGen/PowerPC/urem-lkk.ll | 4 +- llvm/test/CodeGen/PowerPC/vec_splat.ll | 4 +- .../CodeGen/PowerPC/vector-popcnt-128-ult-ugt.ll | 10 +- llvm/test/CodeGen/PowerPC/vmladduhm.ll | 4 +- llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll | 2748 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll | 2748 ++++++++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv32.ll | 380 +++ llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv64.ll | 380 +++ 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llvm/test/CodeGen/X86/sqrt-fastmath.ll | 8 +- llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll | 16 +- .../X86/vector-constrained-fp-intrinsics.ll | 766 +++--- llvm/test/CodeGen/X86/vector-trunc.ll | 8 +- llvm/test/CodeGen/X86/volatile.ll | 38 +- llvm/test/CodeGen/{X86 => }/lit.local.cfg | 3 - llvm/test/DebugInfo/COFF/lines-bb-start.ll | 1 - llvm/test/DebugInfo/Mips/delay-slot.ll | 3 +- llvm/test/DebugInfo/X86/fission-ranges.ll | 24 +- llvm/test/DebugInfo/X86/prologue-stack.ll | 2 +- .../AArch64/armv8.3a-signed-pointer.txt | 2 + llvm/test/Other/change-printer.ll | 151 ++ .../Transforms/IndVarSimplify/exit_value_test2.ll | 6 +- llvm/test/Transforms/InstCombine/icmp-shr.ll | 78 +- llvm/test/Transforms/LoopDeletion/update-scev.ll | 3 +- llvm/test/Transforms/LoopDeletion/zero-btc.ll | 86 +- .../Transforms/LoopUnroll/unroll-after-peel.ll | 48 + .../Transforms/LoopVectorize/vplan-printing.ll | 4 +- .../Transforms/OpenMP/parallel_region_merging.ll | 1955 ++++++++++++-- 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llvm/unittests/ADT/IntrusiveRefCntPtrTest.cpp | 16 + llvm/unittests/ADT/StringExtrasTest.cpp | 14 + llvm/unittests/Support/InstructionCostTest.cpp | 4 +- llvm/unittests/Transforms/Vectorize/VPlanTest.cpp | 72 +- llvm/utils/TableGen/GlobalISelEmitter.cpp | 2 + llvm/utils/TableGen/OptParserEmitter.cpp | 12 +- mlir/cmake/modules/AddMLIRPythonExtension.cmake | 26 +- mlir/docs/OpDefinitions.md | 165 ++ mlir/include/mlir-c/AffineExpr.h | 23 +- mlir/include/mlir-c/AffineMap.h | 16 +- mlir/include/mlir-c/Bindings/Python/Interop.h | 21 + mlir/include/mlir-c/BuiltinTypes.h | 8 +- mlir/include/mlir-c/Dialect/Linalg.h | 25 + mlir/include/mlir-c/Dialect/SCF.h | 25 + mlir/include/mlir-c/Dialect/Shape.h | 25 + .../{StandardDialect.h => Dialect/Standard.h} | 22 +- mlir/include/mlir-c/Dialect/Tensor.h | 25 + mlir/include/mlir-c/Registration.h | 55 +- mlir/include/mlir/CAPI/Registration.h | 40 + .../mlir/Conversion/AsyncToLLVM/AsyncToLLVM.h | 16 + .../StandardToLLVM/ConvertStandardToLLVM.h | 2 +- mlir/include/mlir/Dialect/ArmSVE/ArmSVE.td | 2 +- mlir/include/mlir/Dialect/GPU/Passes.td | 1 + mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td | 8 + mlir/include/mlir/Dialect/Linalg/Passes.td | 22 +- .../mlir/Dialect/Linalg/Transforms/Transforms.h | 58 +- mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBase.td | 4 +- mlir/include/mlir/Dialect/Vector/VectorOps.td | 18 +- mlir/include/mlir/IR/BuiltinTypes.h | 219 +- mlir/include/mlir/IR/BuiltinTypes.td | 240 ++ mlir/include/mlir/IR/OpBase.td | 82 + mlir/include/mlir/TableGen/Builder.h | 85 + mlir/include/mlir/TableGen/Operator.h | 7 + mlir/include/mlir/TableGen/TypeDef.h | 43 +- mlir/lib/Bindings/Python/CMakeLists.txt | 20 +- mlir/lib/Bindings/Python/IRModules.cpp | 579 ++++- mlir/lib/Bindings/Python/IRModules.h | 29 + mlir/lib/Bindings/Python/LinalgOps.td | 16 + mlir/lib/Bindings/Python/ShapeOps.td | 15 + mlir/lib/Bindings/Python/TensorOps.td | 15 + mlir/lib/CAPI/CMakeLists.txt | 2 +- mlir/lib/CAPI/Dialect/CMakeLists.txt | 48 + mlir/lib/CAPI/Dialect/Linalg.cpp | 14 + mlir/lib/CAPI/Dialect/SCF.cpp | 13 + mlir/lib/CAPI/Dialect/Shape.cpp | 13 + mlir/lib/CAPI/Dialect/Standard.cpp | 13 + mlir/lib/CAPI/Dialect/Tensor.cpp | 14 + mlir/lib/CAPI/IR/AffineExpr.cpp | 20 + mlir/lib/CAPI/IR/AffineMap.cpp | 17 +- mlir/lib/CAPI/IR/BuiltinTypes.cpp | 11 + mlir/lib/CAPI/Standard/CMakeLists.txt | 7 - mlir/lib/CAPI/Standard/StandardDialect.cpp | 25 - mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp | 73 +- .../GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp | 6 +- .../SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp | 4 +- .../Conversion/StandardToLLVM/StandardToLLVM.cpp | 18 +- .../Dialect/GPU/Transforms/AsyncRegionRewriter.cpp | 4 +- mlir/lib/Dialect/GPU/Transforms/PassDetail.h | 1 + mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp | 126 +- .../Dialect/Linalg/Transforms/FusionOnTensors.cpp | 99 +- mlir/lib/Dialect/Linalg/Transforms/Loops.cpp | 83 +- mlir/lib/Dialect/SPIRV/IR/SPIRVOps.cpp | 5 +- mlir/lib/Dialect/Vector/VectorOps.cpp | 48 +- mlir/lib/IR/BuiltinTypes.cpp | 46 +- mlir/lib/IR/MLIRContext.cpp | 8 - mlir/lib/IR/TypeDetail.h | 43 - mlir/lib/Parser/AttributeParser.cpp | 5 + mlir/lib/TableGen/Builder.cpp | 74 + mlir/lib/TableGen/CMakeLists.txt | 1 + mlir/lib/TableGen/Operator.cpp | 12 + mlir/lib/TableGen/TypeDef.cpp | 53 + mlir/lib/Target/SPIRV/Deserialization.cpp | 139 +- mlir/lib/Target/SPIRV/Serialization.cpp | 49 + mlir/test/Bindings/Python/CMakeLists.txt | 4 +- mlir/test/Bindings/Python/ir_affine_expr.py | 275 ++ mlir/test/Bindings/Python/ir_affine_map.py | 148 ++ mlir/test/Bindings/Python/ir_types.py | 16 +- mlir/test/CAPI/ir.c | 52 +- .../lower-alloc-to-gpu-runtime-calls.mlir | 11 +- .../Conversion/VectorToSCF/vector-to-loops.mlir | 16 +- mlir/test/Dialect/Linalg/canonicalize.mlir | 36 + mlir/test/Dialect/Linalg/loop-order.mlir | 24 + mlir/test/Dialect/Linalg/reshape_fusion.mlir | 166 +- .../Linalg/reshape_linearization_fusion.mlir | 145 +- mlir/test/Dialect/SPIRV/IR/structure-ops.mlir | 14 + mlir/test/Dialect/Vector/canonicalize.mlir | 35 + mlir/test/Dialect/Vector/invalid.mlir | 31 + mlir/test/IR/invalid-ops.mlir | 8 + mlir/test/Target/SPIRV/spec-constant.mlir | 31 + mlir/test/lib/Dialect/Test/TestTypeDefs.td | 20 +- mlir/test/lib/Dialect/Test/TestTypes.cpp | 2 +- mlir/test/mlir-tblgen/typedefs.td | 24 +- mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp | 98 +- mlir/tools/mlir-tblgen/TypeDefGen.cpp | 245 +- 425 files changed, 20143 insertions(+), 4000 deletions(-) create mode 100644 clang/test/Sema/attr-enforce-tcb-errors.cpp create mode 100644 clang/test/Sema/attr-enforce-tcb.c create mode 100644 clang/test/Sema/attr-enforce-tcb.cpp rename libc/src/__support/{common.h.def => common.h} (54%) create mode 100644 lld/test/ELF/lto/exclude-libs-libcall.ll create mode 100644 llvm/test/CodeGen/AArch64/dag-combine-insert-subvector.ll create mode 100644 llvm/test/CodeGen/Hexagon/autohvx/widen-setcc.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/setcc-fp-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfadd-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfdiv-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfmul-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfsub-sdnode-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vsplats-fp.ll create mode 100644 llvm/test/CodeGen/VE/VELIntrinsics/extract.ll create mode 100644 llvm/test/CodeGen/VE/VELIntrinsics/insert.ll create mode 100644 llvm/test/CodeGen/X86/AMX/amx-spill-merge.ll delete mode 100644 llvm/test/CodeGen/X86/fast-isel-constant.ll create mode 100644 llvm/test/CodeGen/X86/fast-isel-prolog-dbgloc.ll copy llvm/test/CodeGen/X86/{horizontal-shuffle-2.ll => horizontal-shuffle-3.ll} (51%) create mode 100644 llvm/test/CodeGen/X86/horizontal-sum.ll copy llvm/test/CodeGen/{X86 => }/lit.local.cfg (82%) create mode 100644 llvm/test/Transforms/LoopUnroll/unroll-after-peel.ll create mode 100644 llvm/test/Transforms/UniqueInternalLinkageNames/unique-internal [...] delete mode 100644 llvm/test/Transforms/UniqueLinkageNames/unique-internal-linkage [...] create mode 100644 mlir/include/mlir-c/Dialect/Linalg.h create mode 100644 mlir/include/mlir-c/Dialect/SCF.h create mode 100644 mlir/include/mlir-c/Dialect/Shape.h rename mlir/include/mlir-c/{StandardDialect.h => Dialect/Standard.h} (52%) create mode 100644 mlir/include/mlir-c/Dialect/Tensor.h create mode 100644 mlir/include/mlir/CAPI/Registration.h create mode 100644 mlir/include/mlir/TableGen/Builder.h create mode 100644 mlir/lib/Bindings/Python/LinalgOps.td create mode 100644 mlir/lib/Bindings/Python/ShapeOps.td create mode 100644 mlir/lib/Bindings/Python/TensorOps.td create mode 100644 mlir/lib/CAPI/Dialect/CMakeLists.txt create mode 100644 mlir/lib/CAPI/Dialect/Linalg.cpp create mode 100644 mlir/lib/CAPI/Dialect/SCF.cpp create mode 100644 mlir/lib/CAPI/Dialect/Shape.cpp create mode 100644 mlir/lib/CAPI/Dialect/Standard.cpp create mode 100644 mlir/lib/CAPI/Dialect/Tensor.cpp delete mode 100644 mlir/lib/CAPI/Standard/CMakeLists.txt delete mode 100644 mlir/lib/CAPI/Standard/StandardDialect.cpp create mode 100644 mlir/lib/TableGen/Builder.cpp create mode 100644 mlir/test/Bindings/Python/ir_affine_expr.py create mode 100644 mlir/test/Dialect/Linalg/loop-order.mlir -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allyesconfig updated (c0304964 -> b5e9b262)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allyesconfig in repository toolchain/ci/base-artifacts. discards c0304964 0: update: llvm-linux-qemu: 19158 new b5e9b262 0: update: llvm-linux-qemu: 19158 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (c0304964) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 181 +- 02-prepare_abe/console.log | 438 +- 03-build_llvm/console.log | 13708 +++++++++++++-------------- 04-build_linux/console.log | 894 +- 07-check_regression/console.log | 6 +- 07-check_regression/results.regressions | 2 +- 08-update_baseline/console.log | 16 +- 08-update_baseline/results.regressions | 2 +- console.log | 15243 +++++++++++++++--------------- jenkins/manifest.sh | 10 +- 10 files changed, 15259 insertions(+), 15241 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[binutils-gdb] branch master updated (c6185dce03d -> 254c3783fee)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from c6185dce03d gdb: convert aarch64 to new-style debug macros new 254c3783fee sim: tests: get common tests working again The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: sim/testsuite/ChangeLog | 16 +++++++++++++++- sim/testsuite/common/alu-tst.c | 7 ++++--- sim/testsuite/common/bits-gen.c | 25 +++++++++++++------------ sim/testsuite/common/bits-tst.c | 39 ++++++++++++++------------------------- 4 files changed, 46 insertions(+), 41 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-defconfig updated (7b09f12773 -> b3f846c59d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-defconfig in repository toolchain/ci/qemu. from 7b09f12773 Merge remote-tracking branch 'remotes/pmaydell/tags/pull-tar [...] adds b115ea3a0d gitlab-ci.yml: Add openSUSE Leap 15.2 for gitlab CI/CD adds 661465c2e0 qtest/libqtest: fix heap-buffer-overflow in qtest_cb_for_eve [...] adds 124bd3e0a8 util/oslib-win32: Fix _aligned_malloc() arguments order adds 22ec0c696f fuzz: accelerate non-crash detection adds 7b339f287f fuzz: double the IOs to remove for every loop adds e72203abec fuzz: split write operand using binary approach adds 247ab240c2 fuzz: remove IO commands iteratively adds 9d20f2af53 fuzz: set bits in operand of write/out to zero adds dd21ed0edf fuzz: add minimization options adds 4cc5752303 fuzz: heuristic split write based on past IOs adds 4d306e59cb bsd-user: regenerate FreeBSD's system call numbers adds ea1ab4cf2c bsd-user: move strace OS/arch dependent code to host/arch dirs adds f6eb4a0841 bsd-user: Update strace.list for FreeBSD's latest syscalls adds 333168efe5 tests/acceptance: Fix race conditions in s390x tests & skip [...] adds b677001d70 fuzz: map all BARs and enable PCI devices adds b3f846c59d Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull- [...] No new revisions were added by this update. Summary of changes: .gitlab-ci.d/containers.yml | 5 + .gitlab-ci.yml | 31 ++ bsd-user/arm/target_arch_sysarch.h | 78 +++ bsd-user/arm/target_syscall.h | 36 ++ bsd-user/{signal.c => freebsd/os-strace.h} | 17 +- bsd-user/freebsd/strace.list | 65 ++- bsd-user/freebsd/syscall_nr.h | 695 ++++++++++++++------------ bsd-user/i386/target_arch_sysarch.h | 77 +++ bsd-user/i386/target_syscall.h | 19 + bsd-user/mips/target_arch_sysarch.h | 69 +++ bsd-user/mips/target_syscall.h | 52 ++ bsd-user/mips64/target_arch_sysarch.h | 69 +++ bsd-user/mips64/target_syscall.h | 53 ++ bsd-user/netbsd/os-strace.h | 1 + bsd-user/openbsd/os-strace.h | 1 + bsd-user/sparc/target_arch_sysarch.h | 52 ++ bsd-user/sparc/target_syscall.h | 24 +- bsd-user/sparc64/target_arch_sysarch.h | 52 ++ bsd-user/sparc64/target_syscall.h | 24 +- bsd-user/strace.c | 11 + bsd-user/x86_64/target_arch_sysarch.h | 76 +++ bsd-user/x86_64/target_syscall.h | 21 +- meson.build | 1 + scripts/oss-fuzz/minimize_qtest_trace.py | 260 ++++++++-- tests/acceptance/machine_s390_ccw_virtio.py | 14 +- tests/docker/dockerfiles/opensuse-leap.docker | 55 ++ tests/qtest/fuzz/generic_fuzz.c | 24 + tests/qtest/libqtest.c | 2 +- util/oslib-win32.c | 2 +- 29 files changed, 1500 insertions(+), 386 deletions(-) create mode 100644 bsd-user/arm/target_arch_sysarch.h create mode 100644 bsd-user/arm/target_syscall.h copy bsd-user/{signal.c => freebsd/os-strace.h} (60%) create mode 100644 bsd-user/i386/target_arch_sysarch.h create mode 100644 bsd-user/mips/target_arch_sysarch.h create mode 100644 bsd-user/mips/target_syscall.h create mode 100644 bsd-user/mips64/target_arch_sysarch.h create mode 100644 bsd-user/mips64/target_syscall.h create mode 100644 bsd-user/netbsd/os-strace.h create mode 100644 bsd-user/openbsd/os-strace.h create mode 100644 bsd-user/sparc/target_arch_sysarch.h create mode 100644 bsd-user/sparc64/target_arch_sysarch.h create mode 100644 bsd-user/x86_64/target_arch_sysarch.h create mode 100644 tests/docker/dockerfiles/opensuse-leap.docker -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-defconfig updated (1dc61d0b -> 33981ee0)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-defconfig in repository toolchain/ci/base-artifacts. discards 1dc61d0b 0: update: gcc-a958b2fc6dab3d8b01b6ee32178e2fccd97f77f8: boot new 33981ee0 0: update: qemu-b3f846c59d8405bb87c551187721fc92ff2f1b92: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (1dc61d0b) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 83 +- 02-prepare_abe/console.log | 438 +- 03-build_abe-binutils/console.log | 11242 +++++----- 04-build_abe-stage1/console.log | 16316 +++++++------- 05-build_linux/console.log | 440 +- 06-build_abe-qemu/console.log | 6706 +++--- 07-boot_linux/console.log | 490 +- 08-check_regression/console.log | 8 +- 08-check_regression/results.regressions | 2 +- 09-update_baseline/console.log | 10 +- 09-update_baseline/results.regressions | 2 +- console.log | 35789 +++++++++++++++--------------- jenkins/manifest.sh | 10 +- 13 files changed, 35755 insertions(+), 35781 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_cross/gnu-master-arm-build_cross updated (7b09f12773 -> b3f846c59d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_cross/gnu-master-arm-build_cross in repository toolchain/ci/qemu. from 7b09f12773 Merge remote-tracking branch 'remotes/pmaydell/tags/pull-tar [...] adds b115ea3a0d gitlab-ci.yml: Add openSUSE Leap 15.2 for gitlab CI/CD adds 661465c2e0 qtest/libqtest: fix heap-buffer-overflow in qtest_cb_for_eve [...] adds 124bd3e0a8 util/oslib-win32: Fix _aligned_malloc() arguments order adds 22ec0c696f fuzz: accelerate non-crash detection adds 7b339f287f fuzz: double the IOs to remove for every loop adds e72203abec fuzz: split write operand using binary approach adds 247ab240c2 fuzz: remove IO commands iteratively adds 9d20f2af53 fuzz: set bits in operand of write/out to zero adds dd21ed0edf fuzz: add minimization options adds 4cc5752303 fuzz: heuristic split write based on past IOs adds 4d306e59cb bsd-user: regenerate FreeBSD's system call numbers adds ea1ab4cf2c bsd-user: move strace OS/arch dependent code to host/arch dirs adds f6eb4a0841 bsd-user: Update strace.list for FreeBSD's latest syscalls adds 333168efe5 tests/acceptance: Fix race conditions in s390x tests & skip [...] adds b677001d70 fuzz: map all BARs and enable PCI devices adds b3f846c59d Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull- [...] No new revisions were added by this update. Summary of changes: .gitlab-ci.d/containers.yml | 5 + .gitlab-ci.yml | 31 ++ bsd-user/arm/target_arch_sysarch.h | 78 +++ bsd-user/arm/target_syscall.h | 36 ++ bsd-user/{signal.c => freebsd/os-strace.h} | 17 +- bsd-user/freebsd/strace.list | 65 ++- bsd-user/freebsd/syscall_nr.h | 695 ++++++++++++++------------ bsd-user/i386/target_arch_sysarch.h | 77 +++ bsd-user/i386/target_syscall.h | 19 + bsd-user/mips/target_arch_sysarch.h | 69 +++ bsd-user/mips/target_syscall.h | 52 ++ bsd-user/mips64/target_arch_sysarch.h | 69 +++ bsd-user/mips64/target_syscall.h | 53 ++ bsd-user/netbsd/os-strace.h | 1 + bsd-user/openbsd/os-strace.h | 1 + bsd-user/sparc/target_arch_sysarch.h | 52 ++ bsd-user/sparc/target_syscall.h | 24 +- bsd-user/sparc64/target_arch_sysarch.h | 52 ++ bsd-user/sparc64/target_syscall.h | 24 +- bsd-user/strace.c | 11 + bsd-user/x86_64/target_arch_sysarch.h | 76 +++ bsd-user/x86_64/target_syscall.h | 21 +- meson.build | 1 + scripts/oss-fuzz/minimize_qtest_trace.py | 260 ++++++++-- tests/acceptance/machine_s390_ccw_virtio.py | 14 +- tests/docker/dockerfiles/opensuse-leap.docker | 55 ++ tests/qtest/fuzz/generic_fuzz.c | 24 + tests/qtest/libqtest.c | 2 +- util/oslib-win32.c | 2 +- 29 files changed, 1500 insertions(+), 386 deletions(-) create mode 100644 bsd-user/arm/target_arch_sysarch.h create mode 100644 bsd-user/arm/target_syscall.h copy bsd-user/{signal.c => freebsd/os-strace.h} (60%) create mode 100644 bsd-user/i386/target_arch_sysarch.h create mode 100644 bsd-user/mips/target_arch_sysarch.h create mode 100644 bsd-user/mips/target_syscall.h create mode 100644 bsd-user/mips64/target_arch_sysarch.h create mode 100644 bsd-user/mips64/target_syscall.h create mode 100644 bsd-user/netbsd/os-strace.h create mode 100644 bsd-user/openbsd/os-strace.h create mode 100644 bsd-user/sparc/target_arch_sysarch.h create mode 100644 bsd-user/sparc64/target_arch_sysarch.h create mode 100644 bsd-user/x86_64/target_arch_sysarch.h create mode 100644 tests/docker/dockerfiles/opensuse-leap.docker -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

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