Tcwg-commits January 2021

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-defconfig updated (16234206 -> 331e9224)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-defconfig in repository toolchain/ci/base-artifacts. from 16234206 0: update: llvm-linux-qemu: boot new 331e9224 1: reset: linux-qemu: 19 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 133 +- 02-prepare_abe/console.log | 428 +- 03-build_llvm/console.log | 13640 +++++++++++----------- 04-build_linux/console.log | 683 +- 05-build_abe-qemu/console.log | 3456 ------ 06-boot_linux/console.log | 254 - 07-check_regression/console.log | 137 +- 07-check_regression/results.regressions | 4 +- 07-check_regression/trigger-build-linux | 4 + 07-check_regression/trigger-build-qemu | 4 + 08-update_baseline/console.log | 29 +- 08-update_baseline/results.regressions | 4 +- console.log | 18760 ++++++++++++------------------ jenkins/manifest.sh | 19 +- reset-baseline | 0 results | 10 +- 16 files changed, 15029 insertions(+), 22536 deletions(-) delete mode 100644 05-build_abe-qemu/console.log delete mode 100644 06-boot_linux/console.log create mode 100644 07-check_regression/trigger-build-linux create mode 100644 07-check_regression/trigger-build-qemu create mode 100644 reset-baseline -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig updated (e7a371f9fd0 -> 93592b726c7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig in repository toolchain/ci/llvm-project. from e7a371f9fd0 [LLD][COFF] Avoid std::vector resizes during type merging adds bb72adcaee7 [NFC] Use correct ssa.copy spelling when referring to the i [...] adds f4f158b2f89 [mlir][sparse] add vectorization strategies to sparse compiler adds 01c3135850d [LTO] Add test for freestanding LTO option. adds 18278ff1aac [flang] Fix accessibility of USEd name in .mod file adds 4cfccd51335 [libc][NFC] add macro for fuchsia to switch test backend to zxtest adds fb98a1be436 Fix the warnings on unused variables (NFC) adds f711cb9a8ad [FuncAttrs] Add additional willreturn tests (NFC) adds 6077d55381a [DSE] Add tests with stores of existing values. adds ea8034ec35a [libc][NFC] change isblank and iscntrl from implicit casting adds 74a42aedfe1 [test] Add Clang side tests for -fdebug-info-for-profiling adds 35debdfcaca [NFC] Fix build break by a initializer list converting error adds 82c4153e66f Revert "[AsmParser] make .ascii support spaces as separators" adds 39e6d242378 [NewPM] Only non-trivially loop unswitch at -O3 and for non [...] adds 7ec8f436598 [SPARC] Fix fp128 load/stores adds 854f0984f0b Fix llvm::Optional build breaks in MSVC using std::is_trivi [...] adds 86341247c4a [NFC] Rename ThinLTOPhase to ThinOrFullLTOPhase and move it [...] adds ddd03842c34 [SystemZ] Clear Available set in SystemZPostRASchedStrateg [...] adds c82deed6764 [libunwind] Unwind through aarch64/Linux sigreturn frame adds 3de92ca78cd [flang] Add tests for procedure arguments with implicit interfaces adds dfc1901d513 [RISCV] Custom lower ISD::VSCALE. adds cd4c55c9740 Fix grammar in diagnostic for wrong arity in a structured binding. adds 336ab2d51df [Support] On Windows, take the affinity mask into account adds ff40fb07ad6 [PowerPC] Try to fold sqrt/sdiv test results with the branch. adds eec856848cc Revert "[Support] On Windows, take the affinity mask into account" adds 9abac603090 ADT: Fix reference invalidation in SmallVector::push_back a [...] adds b196dc66072 [NFC] Remove unused entry in PassRegistry.def adds 56d1ffb927d Revert "ADT: Fix reference invalidation in SmallVector::pus [...] adds 5c1c39e8d80 [llvm] Use *Set::contains (NFC) adds 125ea20d55c [llvm] Use llvm::stable_sort (NFC) adds 4c1617dac8f [llvm] Use std::any_of (NFC) adds 49142991a68 Reapply "ADT: Fix reference invalidation in SmallVector::pu [...] adds 3043e5a5c33 ADT: Fix reference invalidation in N-element SmallVector::a [...] adds 752fafda3db [NFC] Fix -Wsometimes-uninitialized adds 260a856c2ab ADT: Fix reference invalidation in SmallVector::resize adds c224a834583 ADT: Reduce code duplication in SmallVector::resize by usin [...] adds 3f98b66f23f ADT: Reduce code duplication in SmallVector by reusing rese [...] adds 53b34601abf [Driver] -gsplit-dwarf: Produce .dwo regardless of -gN for [...] adds 6ed3083a965 ADT: Reduce code duplication in SmallVector by calling rese [...] adds ff5e8964255 Fix unused variable in CoroFrame.cpp when building Release [...] adds 885eae9d85d Add func call so we don't instruction-step into the builtin_trap adds 7ad54d19387 [lldb][wasm] Parse DWO section names adds 2bbf724feea Implement vAttachWait in lldb-server adds ed205f63b4a [mlir] Update doc to omit the usage of LLVMIntegerType adds 4b284b9ca80 [lldb] Fix TestPlatformProcessConnect.py adds 259936f4910 [NFC][AsmPrinter] Windows warning: Use explicit cast adds 2b1e25befef [AArch64] Adding ACLE intrinsics for the LS64 extension adds 4bb11b3eafb [LTO] Expose opt() in LTOBackend (NFC). adds 53e3b81faaf [lld][WebAssembly] Add support for handling table symbols adds d58512b2e31 [SLP] Don't vectorize stores of non-packed types (like i1, i2) adds 17f8c458de6 [clang] Use SourceLocations in unions [NFCI] adds af8d27a7a82 [DAG] visitVECTOR_SHUFFLE - pull out shuffle merging code i [...] adds 8f1d7f3753c [X86] Improve sum-of-reductions v4f32 test coverage adds a997a1d7fbe [lldb/test] Ensure launched processes are ready to be attached adds 7c30c05ff71 [DAG] visitVECTOR_SHUFFLE - MergeInnerShuffle - reset shuff [...] adds 2e25be0b613 [clangd] Add main file macros into the main-file index. adds 19297a41711 Change XCore code owner. adds 3bccd87a588 [clang][cli] NFC: Remove SSPBufferSize assignment adds fa2fe9608c1 [clang][cli] Port more CodeGenOptions to marshalling infras [...] adds 6abbba3fca9 Revert "Fix llvm::Optional build breaks in MSVC using std:: [...] adds 176f5e95e1a [clang-tidy] Use DenseSet<SourceLocation> in UpgradeDuratio [...] adds a1bbd1ef1db [flang][driver] Unify f18_version.h.in and Version.inc.in adds c23e34e606b [InferFunctionAttrs] Improve CHECK variable names (NFC). adds a1cba5b7a1f [SelectionDAG] Make use of KnownBits::commonBits. NFC. adds 517196e5691 [Analysis,CodeGen] Make use of KnownBits::makeConstant. NFC. adds 90b310f6caf [Support] Simplify KnownBits::icmp helpers. NFC. adds e8622d27c0e [Support] Add KnownBits::sextInReg exhaustive tests adds 332e220ef42 [docs] Update DebuggingJITedCode page after fix in LLDB adds 0b46f19a9ec [Support] Ensure KnownBits::sextInReg can handle the src == [...] adds 3e41ab18db2 [flang] Fix dangling pointer in LabelEnforce adds adb77a74569 [OpenCL] Improve online documentation. adds 6b9fa8a50d0 [mlir][linalg] Add docstring support for named op spec adds c0939fddf80 [Support] Simplify KnownBits::sextInReg implementation. adds a022be62538 [TableGen] Enhance !cast<string> to handle bit and bits types. adds dbaa6a1858a Revert "[AArch64] Attempt to sink mul operands" adds d0dbb0468c2 [Support] Remove redundant sign bit tests from KnownBits::g [...] adds 0a59647ee40 [SystemZ] misched-cutoff tests can only be tested on non-ND [...] adds 17fb21f875f [clangd] Remove another option that was effectively always [...] adds 7c9c2a2ea5e Revert "[RISCV] Legalize select when Zbt extension available" adds 0afdbb4d2de [flang][driver] Use __FLANG_VERISION__ in f18.cpp (nfc) adds e21bf875c0f [NFC] Disallow unused prefixes under MC/ARM adds 2f395b7092b [clangd] Make AST-based signals available to runWithPreamble. adds 8b09cf7956d [clangd] Trivial: Documentation fix in ASTSignals. adds b4e083b0ef7 [gn build] Port 2f395b7092bd adds 4864d9f7e91 [flang] Fix some module file issues exposed by Whizard adds 35c8a6cbf5f [NFC] Disallow unused prefixes under MC/AArch64 adds a03ffa98503 [NewPM] Fix placement of LoopFlatten adds b99782cf785 [X86][AVX] Adjust unsigned saturation downconvert negative test adds 5d165f0b893 [libomptarget][amdgpu] Fix kernel launch tracing to match p [...] adds 868da2ea939 [SelectionDAG] Remove an early-out from computeKnownBits fo [...] adds 85dfcaadc5f [LLDB] MinidumpParser: Prefer executable module even at hig [...] adds be40c12040a [HIP] Add signbit(long double) decl adds 6ebeba88f51 Support emptiness checks for unbounded FlatAffineConstraints. adds 763c1f99334 [OpenMP] Drop the static library libomptarget-nvptx adds 4fffbc150cc [clang][MSVC] Fix missing MSInheritanceAttr in template spe [...] new 202d359753d [X86] Add the FSRM feature (Fast Short Rep Mov) to Zen3. new 64e9e9aeee0 [OpenMP] Dropped unnecessary define when compiling deviceRT [...] new a8520f6970f [GWP-ASan] Minor refactor of optional components. new ca98baa0425 [openacc] Rename generated file from ACC.cpp.inc to ACC.inc [...] new 9e53c94d8dd [NFC] Update test to not check for 'opaque' in the file name. new 1d973b7ded1 [MLIR][TOSA] First lowerings from Tosa to Linalg new d8113cda782 Add newline to terminate debug message (NFC) new a3904cc77f1 [BasicAA] Handle recursive queries more efficiently new 00a61b327dd [mlir][ODS] Add new RangedTypesMatchWith operation predicate new 93592b726c7 [mlir][OpFormatGen] Format enum attribute cases as keywords [...] The 10 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../abseil/UpgradeDurationConversionsCheck.cpp | 4 +- .../abseil/UpgradeDurationConversionsCheck.h | 5 +- clang-tools-extra/clangd/AST.cpp | 1 + clang-tools-extra/clangd/ASTSignals.cpp | 42 ++ clang-tools-extra/clangd/ASTSignals.h | 39 ++ clang-tools-extra/clangd/CMakeLists.txt | 1 + clang-tools-extra/clangd/ClangdServer.cpp | 14 +- clang-tools-extra/clangd/CodeComplete.h | 10 - clang-tools-extra/clangd/CollectMacros.cpp | 8 +- clang-tools-extra/clangd/CollectMacros.h | 18 +- clang-tools-extra/clangd/SemanticHighlighting.cpp | 4 +- clang-tools-extra/clangd/TUScheduler.cpp | 73 +-- clang-tools-extra/clangd/TUScheduler.h | 3 + clang-tools-extra/clangd/XRefs.cpp | 2 +- clang-tools-extra/clangd/index/SymbolCollector.cpp | 21 +- clang-tools-extra/clangd/tool/ClangdMain.cpp | 1 - .../clangd/unittests/ASTSignalsTests.cpp | 75 +++ clang-tools-extra/clangd/unittests/CMakeLists.txt | 1 + .../clangd/unittests/CodeCompleteTests.cpp | 1 - .../clangd/unittests/CollectMacrosTests.cpp | 12 +- .../clangd/unittests/FindSymbolsTests.cpp | 12 +- .../clangd/unittests/ParsedASTTests.cpp | 4 +- .../clangd/unittests/TUSchedulerTests.cpp | 47 +- clang/docs/OpenCLSupport.rst | 90 +++- clang/docs/UsersManual.rst | 157 ++++--- clang/include/clang/AST/DependentDiagnostic.h | 6 +- clang/include/clang/AST/Expr.h | 39 +- clang/include/clang/AST/TemplateBase.h | 8 +- clang/include/clang/Basic/BuiltinsAArch64.def | 6 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 5 +- clang/include/clang/Basic/SourceManager.h | 33 +- clang/include/clang/Driver/Options.td | 57 ++- clang/include/clang/Sema/DeclSpec.h | 83 ++-- clang/include/clang/Sema/Designator.h | 49 +- clang/include/clang/Sema/Initialization.h | 18 +- clang/lib/AST/Expr.cpp | 12 +- clang/lib/AST/TemplateBase.cpp | 4 +- clang/lib/Basic/Targets/AArch64.cpp | 3 + clang/lib/CodeGen/CGBuiltin.cpp | 40 ++ clang/lib/Driver/ToolChains/Clang.cpp | 10 +- clang/lib/Frontend/CompilerInvocation.cpp | 42 -- .../Headers/__clang_cuda_math_forward_declares.h | 3 + clang/lib/Headers/arm_acle.h | 26 ++ clang/lib/Parse/ParseDeclCXX.cpp | 4 +- clang/lib/Sema/DeclSpec.cpp | 20 +- clang/lib/Sema/SemaDecl.cpp | 4 +- clang/lib/Sema/SemaDeclCXX.cpp | 10 +- clang/lib/Sema/SemaExpr.cpp | 3 +- clang/lib/Sema/SemaTemplate.cpp | 5 + clang/lib/Sema/SemaType.cpp | 14 +- clang/test/CodeGen/aarch64-ls64.c | 163 +++++++ clang/test/CodeGen/incomplete-function-type.c | 1 + .../test/CodeGenCXX/fdebug-info-for-profiling.cpp | 21 + .../CodeGenCXX/microsoft-abi-member-pointers.cpp | 10 + clang/test/Driver/split-debug.c | 8 + clang/test/Preprocessor/aarch64-target-features.c | 6 + clang/test/SemaCXX/cxx1z-decomposition.cpp | 15 + compiler-rt/lib/gwp_asan/optional/backtrace.h | 48 +- .../lib/gwp_asan/optional/backtrace_fuchsia.cpp | 11 +- .../lib/gwp_asan/optional/backtrace_linux_libc.cpp | 17 +- .../optional/backtrace_sanitizer_common.cpp | 16 +- compiler-rt/lib/gwp_asan/optional/printf.h | 33 ++ compiler-rt/lib/gwp_asan/optional/segv_handler.h | 71 +-- .../lib/gwp_asan/optional/segv_handler_fuchsia.cpp | 8 +- .../lib/gwp_asan/optional/segv_handler_posix.cpp | 173 ++++--- compiler-rt/lib/gwp_asan/tests/CMakeLists.txt | 2 +- compiler-rt/lib/gwp_asan/tests/harness.h | 13 +- .../printf_sanitizer_common.cpp | 15 +- compiler-rt/lib/scudo/scudo_allocator.cpp | 8 +- compiler-rt/lib/scudo/standalone/combined.h | 11 +- flang/CMakeLists.txt | 4 - flang/include/flang/Parser/dump-parse-tree.h | 2 +- flang/include/flang/Parser/parse-tree.h | 4 +- flang/include/flang/Version.inc.in | 3 + flang/lib/Parser/unparse.cpp | 2 +- flang/lib/Semantics/check-acc-structure.h | 4 +- flang/lib/Semantics/check-call.cpp | 17 +- flang/lib/Semantics/check-directive-structure.h | 4 +- flang/lib/Semantics/mod-file.cpp | 78 +++- flang/test/Semantics/call09.f90 | 20 +- flang/test/Semantics/modfile03.f90 | 18 + flang/test/Semantics/modfile35.f90 | 6 +- flang/test/Semantics/modfile37.f90 | 32 ++ flang/test/Semantics/modfile38.f90 | 35 ++ flang/tools/f18/CMakeLists.txt | 2 - flang/tools/f18/f18.cpp | 15 +- flang/tools/f18/f18_version.h.in | 9 - libc/src/ctype/isblank.cpp | 2 +- libc/src/ctype/iscntrl.cpp | 2 +- libc/utils/UnitTest/CMakeLists.txt | 3 +- libc/utils/UnitTest/FuchsiaTest.h | 20 + libc/utils/UnitTest/{Test.cpp => LibcTest.cpp} | 2 +- libc/utils/UnitTest/{Test.h => LibcTest.h} | 6 +- libc/utils/UnitTest/Test.h | 260 +---------- libunwind/include/__libunwind_config.h | 3 + libunwind/src/UnwindCursor.hpp | 110 ++++- libunwind/test/signal_unwind.pass.cpp | 9 +- libunwind/test/unwind_leaffunction.pass.cpp | 6 +- lld/MachO/InputSection.cpp | 2 +- lld/include/lld/Common/LLVM.h | 6 + lld/wasm/InputChunks.cpp | 4 + lld/wasm/InputFiles.cpp | 32 +- lld/wasm/InputFiles.h | 3 + lld/wasm/InputTable.h | 60 +++ lld/wasm/MarkLive.cpp | 4 + lld/wasm/SymbolTable.cpp | 65 +++ lld/wasm/SymbolTable.h | 7 + lld/wasm/Symbols.cpp | 45 ++ lld/wasm/Symbols.h | 68 ++- lld/wasm/SyntheticSections.cpp | 63 ++- lld/wasm/SyntheticSections.h | 26 +- lld/wasm/Writer.cpp | 17 +- lld/wasm/WriterUtils.cpp | 17 +- lld/wasm/WriterUtils.h | 1 + .../Python/lldbsuite/test/lldbplatformutil.py | 14 +- lldb/packages/Python/lldbsuite/test/lldbtest.py | 29 +- .../Plugins/ObjectFile/wasm/ObjectFileWasm.cpp | 61 ++- .../gdb-server/PlatformRemoteGDBServer.cpp | 2 +- .../GDBRemoteCommunicationServerLLGS.cpp | 98 ++++ .../gdb-remote/GDBRemoteCommunicationServerLLGS.h | 13 + .../GDBRemoteCommunicationServerPlatform.cpp | 2 +- .../Plugins/Process/minidump/MinidumpParser.cpp | 26 +- lldb/test/API/macosx/builtin-debugtrap/main.cpp | 1 + .../tools/lldb-server/TestGdbRemoteAttachWait.py | 75 +++ .../TestPlatformProcessConnect.py | 52 +-- .../ObjectFile/wasm/embedded-debug-sections.yaml | 100 ++++ .../Process/minidump/MinidumpParserTest.cpp | 41 ++ llvm/CODE_OWNERS.TXT | 8 +- llvm/docs/DebuggingJITedCode.rst | 201 ++++---- llvm/docs/LangRef.rst | 6 +- llvm/include/llvm/ADT/DepthFirstIterator.h | 2 +- llvm/include/llvm/ADT/SmallVector.h | 191 +++++--- llvm/include/llvm/Analysis/BasicAliasAnalysis.h | 7 +- llvm/include/llvm/Analysis/DivergenceAnalysis.h | 2 +- llvm/include/llvm/BinaryFormat/Wasm.h | 4 +- llvm/include/llvm/Frontend/OpenACC/CMakeLists.txt | 2 +- llvm/include/llvm/IR/IntrinsicsAArch64.td | 8 + llvm/include/llvm/LTO/LTOBackend.h | 6 + llvm/include/llvm/Object/Wasm.h | 5 +- llvm/include/llvm/Pass.h | 14 + llvm/include/llvm/Passes/PassBuilder.h | 20 +- llvm/include/llvm/Support/KnownBits.h | 4 +- llvm/include/llvm/Transforms/IPO/SampleProfile.h | 9 +- .../Vectorize/LoopVectorizationLegality.h | 2 +- llvm/lib/Analysis/BasicAliasAnalysis.cpp | 109 ++--- llvm/lib/Analysis/GlobalsModRef.cpp | 6 +- llvm/lib/Analysis/IRSimilarityIdentifier.cpp | 2 +- llvm/lib/Analysis/ValueTracking.cpp | 11 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 4 +- llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp | 3 +- llvm/lib/CodeGen/SafeStackLayout.cpp | 8 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 108 +++-- .../CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 6 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 10 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 43 +- llvm/lib/ExecutionEngine/MCJIT/MCJIT.h | 10 +- llvm/lib/LTO/LTOBackend.cpp | 8 +- llvm/lib/MC/MCParser/AsmParser.cpp | 13 +- llvm/lib/Object/WasmObjectFile.cpp | 7 +- llvm/lib/Passes/PassBuilder.cpp | 61 +-- llvm/lib/Passes/PassRegistry.def | 4 +- llvm/lib/Support/KnownBits.cpp | 43 +- llvm/lib/TableGen/Record.cpp | 4 +- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 12 +- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 37 -- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 12 +- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 10 +- .../Hexagon/MCTargetDesc/HexagonShuffler.cpp | 5 +- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp | 78 ++++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 43 +- llvm/lib/Target/RISCV/RISCVISelLowering.h | 7 + llvm/lib/Target/RISCV/RISCVInstrInfoB.td | 18 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 7 + llvm/lib/Target/RISCV/RISCVMCInstLower.cpp | 9 + llvm/lib/Target/Sparc/SparcISelLowering.cpp | 38 +- .../lib/Target/SystemZ/SystemZMachineScheduler.cpp | 1 + llvm/lib/Target/X86/X86.td | 3 +- llvm/lib/Transforms/Coroutines/CoroFrame.cpp | 2 + llvm/lib/Transforms/IPO/IROutliner.cpp | 11 +- llvm/lib/Transforms/IPO/SampleProfile.cpp | 27 +- llvm/lib/Transforms/Scalar/SROA.cpp | 2 +- llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp | 4 + llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 10 + .../CodeGen/AArch64/aarch64-matrix-umull-smull.ll | 186 -------- llvm/test/CodeGen/AArch64/ls64-intrinsics.ll | 92 ++++ llvm/test/CodeGen/PowerPC/fold_swtest_br.ll | 204 ++++++++ llvm/test/CodeGen/RISCV/rv32Zbb.ll | 137 ++++-- llvm/test/CodeGen/RISCV/rv32Zbbp.ll | 138 +++--- llvm/test/CodeGen/RISCV/rv32Zbs.ll | 52 ++- llvm/test/CodeGen/RISCV/rv32Zbt.ll | 480 ++++++++++++------- llvm/test/CodeGen/RISCV/rv64Zbt.ll | 112 +++-- llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll | 54 +++ llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll | 54 +++ llvm/test/CodeGen/SPARC/fp128-split.ll | 55 +++ llvm/test/CodeGen/SystemZ/misched-cutoff.ll | 51 ++ llvm/test/CodeGen/X86/avx512-trunc.ll | 20 +- llvm/test/CodeGen/X86/horizontal-sum.ll | 308 +++++++++--- llvm/test/CodeGen/X86/known-bits-vector.ll | 12 +- llvm/test/CodeGen/X86/memcpy-inline-fsrm.ll | 1 + llvm/test/LTO/X86/tli-nobuiltin.ll | 31 ++ llvm/test/MC/AArch64/armv8.7a-ls64.s | 4 +- llvm/test/MC/AArch64/armv8.7a-xs.s | 6 +- llvm/test/MC/AArch64/lit.local.cfg | 8 + llvm/test/MC/ARM/ldr-pseudo-cond-darwin.s | 4 +- llvm/test/MC/ARM/ldr-pseudo-cond.s | 4 +- llvm/test/MC/ARM/lit.local.cfg | 8 + llvm/test/MC/ARM/lsl-zero-errors.s | 6 +- llvm/test/MC/ARM/lsl-zero.s | 6 +- llvm/test/MC/ARM/mve-fp-registers.s | 22 +- llvm/test/MC/ARM/thumbv8m.s | 12 +- llvm/test/MC/AsmParser/directive_ascii.s | 8 - llvm/test/TableGen/cast-string.td | 59 +++ .../DeadStoreElimination/MSSA/multiblock-loops.ll | 4 +- .../MSSA/multiblock-memoryphis.ll | 4 +- .../DeadStoreElimination/MSSA/multiblock-simple.ll | 12 +- .../MSSA/stores-of-existing-values.ll | 284 +++++++++++ llvm/test/Transforms/FunctionAttrs/willreturn.ll | 65 ++- .../test/Transforms/InferFunctionAttrs/annotate.ll | 520 ++++++++++----------- .../test/Transforms/SLPVectorizer/X86/bad_types.ll | 11 +- .../ARM/nontrivial-unswitch-cost.ll | 119 ++--- .../test/Transforms/SimpleLoopUnswitch/pipeline.ll | 42 +- llvm/tools/llvm-profgen/PseudoProbe.cpp | 2 +- llvm/tools/llvm-readobj/WasmDumper.cpp | 2 +- llvm/tools/obj2yaml/elf2yaml.cpp | 2 +- llvm/unittests/ADT/SmallVectorTest.cpp | 152 ++++-- llvm/unittests/Support/KnownBitsTest.cpp | 20 + llvm/utils/TableGen/DAGISelEmitter.cpp | 3 +- llvm/utils/TableGen/GlobalISelEmitter.cpp | 25 +- llvm/utils/TableGen/RegisterInfoEmitter.cpp | 3 +- llvm/utils/TableGen/SearchableTableEmitter.cpp | 26 +- .../gn/secondary/clang-tools-extra/clangd/BUILD.gn | 1 + .../clang-tools-extra/clangd/unittests/BUILD.gn | 1 + .../llvm/include/llvm/Frontend/OpenACC/BUILD.gn | 2 +- mlir/docs/Dialects/Linalg.md | 10 +- mlir/docs/Tutorials/Toy/Ch-6.md | 4 +- mlir/include/mlir/Analysis/AffineStructures.h | 7 + mlir/include/mlir/Analysis/LinearTransform.h | 48 ++ mlir/include/mlir/Analysis/Presburger/Fraction.h | 2 + mlir/include/mlir/Analysis/Presburger/Matrix.h | 6 + mlir/include/mlir/Analysis/Presburger/Simplex.h | 30 +- mlir/include/mlir/Conversion/Passes.h | 1 + mlir/include/mlir/Conversion/Passes.td | 14 + .../mlir/Conversion/TosaToLinalg/TosaToLinalg.h | 36 ++ .../mlir/Dialect/Linalg/Transforms/Transforms.h | 8 +- mlir/include/mlir/IR/OpBase.td | 20 +- .../Dialect/Linalg/CPU/matmul-vs-matvec.mlir | 2 +- mlir/lib/Analysis/AffineStructures.cpp | 151 +++++- mlir/lib/Analysis/CMakeLists.txt | 2 + mlir/lib/Analysis/LinearTransform.cpp | 156 +++++++ mlir/lib/Analysis/Presburger/CMakeLists.txt | 2 +- mlir/lib/Analysis/Presburger/Matrix.cpp | 13 + mlir/lib/Analysis/Presburger/Simplex.cpp | 31 +- mlir/lib/Conversion/CMakeLists.txt | 1 + mlir/lib/Conversion/TosaToLinalg/CMakeLists.txt | 20 + mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp | 188 ++++++++ .../Conversion/TosaToLinalg/TosaToLinalgPass.cpp | 59 +++ .../Dialect/Linalg/Transforms/Sparsification.cpp | 210 +++++++-- .../Utils/GreedyPatternRewriteDriver.cpp | 2 +- mlir/test/Analysis/test-dominance.mlir | 4 +- mlir/test/Analysis/test-liveness.mlir | 2 +- .../Conversion/AffineToStandard/lower-affine.mlir | 54 +-- .../Conversion/LinalgToSPIRV/linalg-to-spirv.mlir | 2 +- .../Conversion/OpenMPToLLVM/convert-to-llvmir.mlir | 2 +- mlir/test/Conversion/SCFToGPU/parallel_loop.mlir | 4 +- .../Conversion/SCFToStandard/convert-to-cfg.mlir | 18 +- .../ShapeToStandard/convert-shape-constraints.mlir | 8 +- .../ShapeToStandard/shape-to-standard.mlir | 32 +- .../StandardToLLVM/convert-to-llvmir.mlir | 58 +-- .../StandardToSPIRV/std-ops-to-spirv.mlir | 54 +-- .../Conversion/TosaToLinalg/tosa-to-linalg.mlir | 140 ++++++ .../Conversion/VectorToSCF/vector-to-loops.mlir | 20 +- mlir/test/Dialect/Affine/parallelize.mlir | 4 +- mlir/test/Dialect/GPU/all-reduce-max.mlir | 48 +- mlir/test/Dialect/GPU/all-reduce.mlir | 8 +- .../Linalg/convert-elementwise-to-linalg.mlir | 8 +- mlir/test/Dialect/Linalg/loops.mlir | 18 +- mlir/test/Dialect/Linalg/sparse_1d.mlir | 114 ++--- mlir/test/Dialect/Linalg/sparse_2d.mlir | 194 ++++---- mlir/test/Dialect/Linalg/sparse_3d.mlir | 72 +-- mlir/test/Dialect/Linalg/sparse_vector.mlir | 310 ++++++++++++ mlir/test/Dialect/Linalg/tile-and-distribute.mlir | 8 +- mlir/test/Dialect/Linalg/vectorization.mlir | 8 +- mlir/test/Dialect/SCF/for-loop-specialization.mlir | 2 +- mlir/test/Dialect/SCF/ops.mlir | 20 +- .../Dialect/SCF/parallel-loop-specialization.mlir | 4 +- mlir/test/Dialect/SPIRV/IR/availability.mlir | 2 +- mlir/test/Dialect/SPIRV/IR/barrier-ops.mlir | 18 +- mlir/test/Dialect/SPIRV/IR/group-ops.mlir | 18 +- mlir/test/Dialect/SPIRV/IR/non-uniform-ops.mlir | 26 +- mlir/test/Dialect/SPIRV/IR/target-env.mlir | 2 +- .../Dialect/SPIRV/Transforms/vce-deduction.mlir | 2 +- mlir/test/Dialect/Standard/canonicalize.mlir | 20 +- mlir/test/Dialect/Standard/expand-ops.mlir | 26 +- mlir/test/Dialect/Standard/expand-tanh.mlir | 2 +- .../Dialect/Vector/vector-contract-transforms.mlir | 10 +- .../Vector/vector-transfer-full-partial-split.mlir | 16 +- mlir/test/Dialect/Vector/vector-transforms.mlir | 10 +- mlir/test/EDSC/builder-api-test.cpp | 44 +- mlir/test/IR/core-ops.mlir | 48 +- mlir/test/IR/invalid-ops.mlir | 36 +- mlir/test/IR/invalid.mlir | 2 +- mlir/test/Target/SPIRV/barrier-ops.mlir | 16 +- mlir/test/Target/SPIRV/group-ops.mlir | 8 +- mlir/test/Target/SPIRV/non-uniform-ops.mlir | 12 +- mlir/test/Transforms/buffer-deallocation.mlir | 18 +- mlir/test/Transforms/buffer-hoisting.mlir | 14 +- mlir/test/Transforms/buffer-loop-hoisting.mlir | 14 +- mlir/test/Transforms/canonicalize-block-merge.mlir | 4 +- mlir/test/Transforms/canonicalize.mlir | 12 +- mlir/test/Transforms/constant-fold.mlir | 116 ++--- mlir/test/Transforms/copy-removal.mlir | 6 +- mlir/test/Transforms/cse.mlir | 8 +- mlir/test/Transforms/parametric-tiling.mlir | 8 +- mlir/test/Transforms/promote-buffers-to-stack.mlir | 8 +- mlir/test/Transforms/sccp-callgraph.mlir | 2 +- mlir/test/Transforms/sccp-structured.mlir | 2 +- mlir/test/Transforms/sccp.mlir | 2 +- mlir/test/lib/Dialect/Test/TestOps.td | 9 + mlir/test/lib/Transforms/TestSparsification.cpp | 2 + .../mlir-linalg-ods-gen/test-linalg-ods-gen.tc | 19 + mlir/test/mlir-tblgen/op-format.mlir | 9 +- .../mlir-linalg-ods-gen/mlir-linalg-ods-gen.cpp | 75 ++- mlir/tools/mlir-tblgen/OpFormatGen.cpp | 236 +++++++--- mlir/unittests/Analysis/AffineStructuresTest.cpp | 203 +++++++- mlir/unittests/Analysis/CMakeLists.txt | 1 + mlir/unittests/Analysis/LinearTransformTest.cpp | 87 ++++ .../libomptarget/deviceRTLs/nvptx/CMakeLists.txt | 103 +--- openmp/libomptarget/plugins/amdgpu/src/rtl.cpp | 2 +- polly/lib/Support/RegisterPasses.cpp | 2 +- 329 files changed, 8049 insertions(+), 3602 deletions(-) create mode 100644 clang-tools-extra/clangd/ASTSignals.cpp create mode 100644 clang-tools-extra/clangd/ASTSignals.h create mode 100644 clang-tools-extra/clangd/unittests/ASTSignalsTests.cpp create mode 100644 clang/test/CodeGen/aarch64-ls64.c create mode 100644 clang/test/CodeGenCXX/fdebug-info-for-profiling.cpp create mode 100644 compiler-rt/lib/gwp_asan/optional/printf.h rename compiler-rt/lib/gwp_asan/tests/{optional => platform_specific}/printf_sanit [...] create mode 100644 flang/test/Semantics/modfile37.f90 create mode 100644 flang/test/Semantics/modfile38.f90 delete mode 100644 flang/tools/f18/f18_version.h.in create mode 100644 libc/utils/UnitTest/FuchsiaTest.h rename libc/utils/UnitTest/{Test.cpp => LibcTest.cpp} (99%) copy libc/utils/UnitTest/{Test.h => LibcTest.h} (98%) create mode 100644 lld/wasm/InputTable.h create mode 100644 lldb/test/API/tools/lldb-server/TestGdbRemoteAttachWait.py delete mode 100644 llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll create mode 100644 llvm/test/CodeGen/AArch64/ls64-intrinsics.ll create mode 100644 llvm/test/CodeGen/PowerPC/fold_swtest_br.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/rvv-vscale.i64.ll create mode 100644 llvm/test/CodeGen/SPARC/fp128-split.ll create mode 100644 llvm/test/CodeGen/SystemZ/misched-cutoff.ll create mode 100644 llvm/test/LTO/X86/tli-nobuiltin.ll create mode 100644 llvm/test/TableGen/cast-string.td create mode 100644 llvm/test/Transforms/DeadStoreElimination/MSSA/stores-of-existi [...] create mode 100644 mlir/include/mlir/Analysis/LinearTransform.h create mode 100644 mlir/include/mlir/Conversion/TosaToLinalg/TosaToLinalg.h create mode 100644 mlir/lib/Analysis/LinearTransform.cpp create mode 100644 mlir/lib/Conversion/TosaToLinalg/CMakeLists.txt create mode 100644 mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp create mode 100644 mlir/lib/Conversion/TosaToLinalg/TosaToLinalgPass.cpp create mode 100644 mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir create mode 100644 mlir/test/Dialect/Linalg/sparse_vector.mlir create mode 100644 mlir/unittests/Analysis/LinearTransformTest.cpp -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig updated (85f4a48f -> a582b4dd)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig in repository toolchain/ci/base-artifacts. from 85f4a48f 3: reset: linux-qemu: 8 new a582b4dd 4: update: llvm-93592b726c7587aa86548cc74268346e25a4a7f2: 8 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 112 +- 02-prepare_abe/console.log | 406 +- 03-build_llvm/console.log | 13651 +++++++++++++-------------- 04-build_linux/console.log | 491 +- 07-check_regression/console.log | 145 +- 07-check_regression/results.regressions | 4 +- 07-check_regression/trigger-build-linux | 4 - 07-check_regression/trigger-build-qemu | 4 - 08-update_baseline/console.log | 71 +- 08-update_baseline/results.regressions | 4 +- console.log | 14876 +++++++++++++++--------------- jenkins/manifest.sh | 16 +- reset-baseline | 0 results | 3 - 14 files changed, 14853 insertions(+), 14934 deletions(-) delete mode 100644 07-check_regression/trigger-build-linux delete mode 100644 07-check_regression/trigger-build-qemu delete mode 100644 reset-baseline -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_stm32/gnu_eabi-master-arm_eabi-coremark-Os_LTO created (now f9a577927eb)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_stm32/gnu_eabi-master-arm_eabi-coremark-Os_LTO in repository toolchain/ci/gcc. at f9a577927eb IBM Z: Fix linking to libatomic in target test cases This branch includes the following new commits: new f9a577927eb IBM Z: Fix linking to libatomic in target test cases The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk_stm32/gnu_eabi-master-arm_eabi-coremark-Os_LTO updated (5fae2a2c66 -> 10f92414d6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_stm32/gnu_eabi-master-arm_eabi-coremark-Os_LTO in repository toolchain/ci/binutils-gdb. from 5fae2a2c66 [gdb/breakpoint] Handle .plt.sec in in_plt_section adds 5a10699ff3 Updated translations for some subdirectories adds 8ca9c7eb67 bfin: Skip non SEC_ALLOC section for R_BFIN_FUNCDESC adds 58eadc4b69 Fix building gdb with gcc-4.x adds c14dee84dd Update my email address (long overdue!) adds 17e8913732 Add myself to gdb/MAINTAINERS adds 5aa06b1b14 Automatic date update in version.in adds 5fda40b28f gas: make [248]byte directives available everywhere adds 3624a6c15c PR26539, memory leak in inflate.c adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status adds 7cf91a2481 sim: m32r: clean up redundant test coverage adds 89bfc2a429 sim: frv: clean up redundant test coverage adds 137d6efd8a sim: mips: delete empty stub test dir adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness adds bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 26 + bfd/elf32-bfin.c | 235 +- bfd/elfnn-riscv.c | 319 +- bfd/elfxx-riscv.c | 54 +- bfd/elfxx-riscv.h | 4 +- bfd/version.h | 2 +- binutils/ChangeLog | 13 + binutils/MAINTAINERS | 6 +- binutils/po/sv.po | 3804 +++++++++++--------- binutils/readelf.c | 6 +- gas/ChangeLog | 30 + gas/config/obj-elf.c | 4 - gas/config/tc-riscv.c | 521 ++- gas/config/tc-riscv.h | 6 +- gas/doc/as.texi | 7 - gas/read.c | 3 + gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +- .../gas/riscv/priv-reg-fail-read-only-01.l | 136 +- .../gas/riscv/priv-reg-fail-read-only-02.l | 48 +- gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +- .../gas/riscv/priv-reg-fail-version-1p10.l | 48 +- .../gas/riscv/priv-reg-fail-version-1p11.l | 46 +- .../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +- gdb/ChangeLog | 10 + gdb/MAINTAINERS | 1 + gdb/testsuite/ChangeLog | 6 + gdb/testsuite/gdb.fortran/array-slices.exp | 2 +- gdb/trad-frame.c | 5 +- gold/ChangeLog | 4 + gold/po/fr.po | 730 ++-- include/ChangeLog | 11 + include/elf/riscv.h | 3 +- include/opcode/riscv-opc.h | 16 +- include/opcode/riscv.h | 127 +- ld/ChangeLog | 13 + ld/po/fr.po | 3699 ++++++++++--------- .../ld-riscv-elf/attr-merge-priv-spec-failed-01.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-02.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-03.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-04.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-05.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-06.d | 4 +- opcodes/ChangeLog | 16 + opcodes/riscv-dis.c | 30 +- opcodes/riscv-opc.c | 1456 ++++---- sim/ChangeLog | 7 + sim/configure | 16 +- sim/configure.ac | 16 +- sim/testsuite/ChangeLog | 36 + sim/testsuite/Makefile.in | 8 +- sim/testsuite/configure | 3264 ----------------- sim/testsuite/configure.ac | 32 - sim/testsuite/d10v-elf/Makefile.in | 180 - sim/testsuite/d10v-elf/configure | 2984 --------------- sim/testsuite/d10v-elf/configure.ac | 18 - sim/testsuite/d10v-elf/exit47.s | 4 - sim/testsuite/d10v-elf/loop.s | 6 - sim/testsuite/frv-elf/ChangeLog | 48 - sim/testsuite/frv-elf/Makefile.in | 158 - sim/testsuite/frv-elf/configure | 2984 --------------- sim/testsuite/frv-elf/configure.ac | 18 - sim/testsuite/frv-elf/loop.s | 2 - sim/testsuite/lib/sim-defs.exp | 23 +- sim/testsuite/m32r-elf/ChangeLog | 18 - sim/testsuite/m32r-elf/Makefile.in | 156 - sim/testsuite/m32r-elf/configure | 2984 --------------- sim/testsuite/m32r-elf/configure.ac | 18 - sim/testsuite/m32r-elf/hello.s | 17 - sim/testsuite/m32r-elf/loop.s | 2 - sim/testsuite/mips64el-elf/ChangeLog | 19 - sim/testsuite/mips64el-elf/Makefile.in | 170 - sim/testsuite/mips64el-elf/configure | 2984 --------------- sim/testsuite/mips64el-elf/configure.ac | 18 - sim/testsuite/sim/cris/ChangeLog | 7 + sim/testsuite/sim/cris/c/c.exp | 7 +- sim/testsuite/sim/cris/hw/rv-n-cris/rvc.exp | 2 +- sim/testsuite/{d10v-elf => sim/d10v}/ChangeLog | 5 + sim/testsuite/sim/d10v/allinsn.exp | 17 + .../{d10v-elf/t-trap.s => sim/d10v/exit47.s} | 5 +- sim/testsuite/{d10v-elf => sim/d10v}/hello.s | 3 + sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-i.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-id.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-im.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-ip.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-i.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-ld2w-id.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-ld2w-im.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-ld2w-ip.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-i.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-id.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-im.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-ip.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-is.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-i.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-id.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-im.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-ip.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-is.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-dbt.s | 7 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ld-st.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-mac.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-macros.i | 12 +- .../{d10v-elf => sim/d10v}/t-mod-ld-pre.s | 56 +- sim/testsuite/{d10v-elf => sim/d10v}/t-msbu.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-mulxu.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-mvtac.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-mvtc.s | 9 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rac.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-rachi.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-rdt.s | 7 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rep.s | 8 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rie-xx.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rte.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-sac.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sachi.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sadd.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-slae.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sp.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-sub.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sub2w.s | 16 +- sim/testsuite/{d10v-elf => sim/d10v}/t-subi.s | 4 + sim/testsuite/sim/d10v/t-trap.s | 10 + sim/testsuite/sim/frv/ChangeLog | 6 + .../{frv-elf/cache.s => sim/frv/cache.ms} | 6 +- .../{frv-elf/exit47.s => sim/frv/exit47.ms} | 6 + .../{frv-elf/grloop.s => sim/frv/grloop.ms} | 3 + .../{frv-elf/hello.s => sim/frv/hello.ms} | 3 + sim/testsuite/sim/frv/misc.exp | 19 + sim/testsuite/sim/m32r/ChangeLog | 4 + .../{m32r-elf/exit47.s => sim/m32r/exit47.ms} | 4 + 134 files changed, 6569 insertions(+), 21716 deletions(-) delete mode 100755 sim/testsuite/configure delete mode 100644 sim/testsuite/configure.ac delete mode 100644 sim/testsuite/d10v-elf/Makefile.in delete mode 100755 sim/testsuite/d10v-elf/configure delete mode 100644 sim/testsuite/d10v-elf/configure.ac delete mode 100644 sim/testsuite/d10v-elf/exit47.s delete mode 100644 sim/testsuite/d10v-elf/loop.s delete mode 100644 sim/testsuite/frv-elf/ChangeLog delete mode 100644 sim/testsuite/frv-elf/Makefile.in delete mode 100755 sim/testsuite/frv-elf/configure delete mode 100644 sim/testsuite/frv-elf/configure.ac delete mode 100644 sim/testsuite/frv-elf/loop.s delete mode 100644 sim/testsuite/m32r-elf/ChangeLog delete mode 100644 sim/testsuite/m32r-elf/Makefile.in delete mode 100755 sim/testsuite/m32r-elf/configure delete mode 100644 sim/testsuite/m32r-elf/configure.ac delete mode 100644 sim/testsuite/m32r-elf/hello.s delete mode 100644 sim/testsuite/m32r-elf/loop.s delete mode 100644 sim/testsuite/mips64el-elf/ChangeLog delete mode 100644 sim/testsuite/mips64el-elf/Makefile.in delete mode 100755 sim/testsuite/mips64el-elf/configure delete mode 100644 sim/testsuite/mips64el-elf/configure.ac rename sim/testsuite/{d10v-elf => sim/d10v}/ChangeLog (96%) create mode 100644 sim/testsuite/sim/d10v/allinsn.exp rename sim/testsuite/{d10v-elf/t-trap.s => sim/d10v/exit47.s} (52%) rename sim/testsuite/{d10v-elf => sim/d10v}/hello.s (54%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-d.s (76%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-i.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-id.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-im.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-ip.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-d.s (77%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-i.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-id.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-im.s (80%) rename sim/testsuite/{d10v-elf => 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sim/testsuite/{d10v-elf => sim/d10v}/t-macros.i (97%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mod-ld-pre.s (90%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-msbu.s (87%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mulxu.s (87%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mvtac.s (84%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mvtc.s (95%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rac.s (82%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rachi.s (87%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rdt.s (75%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rep.s (90%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rie-xx.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rte.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sac.s (85%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sachi.s (83%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sadd.s (92%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-slae.s (92%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sp.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sub.s (92%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sub2w.s (93%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-subi.s (92%) create mode 100644 sim/testsuite/sim/d10v/t-trap.s rename sim/testsuite/{frv-elf/cache.s => sim/frv/cache.ms} (95%) rename sim/testsuite/{frv-elf/exit47.s => sim/frv/exit47.ms} (50%) rename sim/testsuite/{frv-elf/grloop.s => sim/frv/grloop.ms} (86%) rename sim/testsuite/{frv-elf/hello.s => sim/frv/hello.ms} (86%) create mode 100644 sim/testsuite/sim/frv/misc.exp rename sim/testsuite/{m32r-elf/exit47.s => sim/m32r/exit47.ms} (66%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_stm32/gnu_eabi-master-arm_eabi-coremark-Os_LTO updated (eaa08962 -> 23a8a869)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_stm32/gnu_eabi-master-arm_eabi-coremark-Os_LTO in repository toolchain/ci/base-artifacts. discards eaa08962 0: init: binutils-gcc: -10 new 23a8a869 0: update: binutils-gcc-newlib: -9 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (eaa08962) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk_stm32/gnu_eabi-maste [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 113 +- 02-prepare_abe/console.log | 434 +-- 03-build_abe-binutils/console.log | 6827 +++++++++++++++++++++++++++++---- 04-build_abe-stage1/console.log | 133 + 09-check_regression/console.log | 26 +- 10-update_baseline/console.log | 36 + console.log | 7569 +++++++++++++++++++++++++++++++------ jenkins/manifest.sh | 19 +- results | 2 + 9 files changed, 12914 insertions(+), 2245 deletions(-) create mode 100644 04-build_abe-stage1/console.log create mode 100644 10-update_baseline/console.log -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-defconfig updated (7c79721606 -> 256af05f52)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-defconfig in repository toolchain/ci/qemu. from 7c79721606 Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-t [...] adds 8cd0b410a2 target/mips: Add CP0 Config0 register definitions for MIPS3 ISA adds b4cbbb47b0 target/mips: Replace CP0_Config0 magic values by proper definitions adds 07ae8ccd0f target/mips/addr: Add translation helpers for KSEG1 adds 737cca57d3 target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment adds bf5523773e target/mips/mips-defs: Reorder CPU_MIPS5 definition adds 8b0ea9b638 target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 adds b0586b38cb target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() adds ce49581feb hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() adds 08e2262fad target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 adds f395cef765 target/mips/mips-defs: Use ISA_MIPS32R2 definition to check [...] adds 4d1524d2ce target/mips/mips-defs: Use ISA_MIPS32R3 definition to check [...] adds d913c3992d target/mips/mips-defs: Use ISA_MIPS32R5 definition to check [...] adds 13514fc93e target/mips/mips-defs: Use ISA_MIPS32R6 definition to check [...] adds bbd5e4a27f target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 adds 7a47bae586 target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 adds bae4b15aa4 target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 adds 5f89ce4fc2 target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 adds 2e211e0a12 target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 adds 9bcd41d41f target/mips: Inline cpu_state_reset() in mips_cpu_reset() adds 81ddae7c30 target/mips: Extract FPU helpers to 'fpu_helper.h' adds f9bd3d79f4 target/mips: Add !CONFIG_USER_ONLY comment after #endif adds 2be565f9c2 target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs adds e9927723ba target/mips: Move common helpers from helper.c to cpu.c adds 4cb213dc90 target/mips: Rename helper.c as tlb_helper.c adds ca2690e36a target/mips: Fix code style for checkpatch.pl adds f2c5b39ecd target/mips: Move mmu_init() functions to tlb_helper.c adds 0dc351ca6b target/mips: Rename translate_init.c as cpu-defs.c adds e31309365e target/mips/translate: Extract DisasContext structure adds 46c9e2b3dd target/mips/translate: Add declarations for generic code adds 11a7511856 target/mips: Replace gen_exception_err(err=0) by gen_excepti [...] adds 3a4ef3b7ee target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_ [...] adds 8758d1b8aa target/mips: Declare generic FPU / Coprocessor functions in [...] adds 57eedcf7e3 target/mips: Extract FPU specific definitions to translate.h adds 8b7322add3 target/mips: Only build TCG code when CONFIG_TCG is set adds 311edee771 target/mips/translate: Extract decode_opc_legacy() from deco [...] adds d7efb69382 target/mips/translate: Expose check_mips_64() to 32-bit mode adds 25a1362875 target/mips: Introduce ase_msa_available() helper adds 72f31f60f8 target/mips: Simplify msa_reset() adds aa314198ca target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA adds 33942f9460 target/mips: Simplify MSA TCG logic adds 7e2a619a04 target/mips: Remove now unused ASE_MSA definition adds e2665f314d target/mips: Alias MSA vector registers on FPU scalar registers adds 959c5da28e target/mips: Extract msa_translate_init() from mips_tcg_init() adds 63af5b9018 target/mips: Remove CPUMIPSState* argument from gen_msa*() methods adds 810fda17c8 target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() adds 03e4d95c91 target/mips: Move msa_reset() to msa_helper.c adds 3ef60574b6 target/mips: Extract MSA helpers from op_helper.c adds edb2384728 target/mips: Extract MSA helper definitions adds 54ccff5102 target/mips: Declare gen_msa/_branch() in 'translate.h' adds 80e64a380f target/mips: Extract MSA translation routines adds 878b87b541 target/mips: Pass TCGCond argument to MSA gen_check_zero_element() adds c7a9ef7517 target/mips: Introduce decode tree bindings for MSA ASE adds 96e5b4c758 target/mips: Use decode_ase_msa() generated from decodetree adds a685f7d075 target/mips: Extract LSA/DLSA translation generators adds 5f21f30d85 target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes adds 3f7a927847 target/mips: Introduce decodetree helpers for Release6 LSA/D [...] adds 0e9524af2d target/mips: Remove now unreachable LSA/DLSA opcodes code adds aac357ec89 target/mips: Convert Rel6 Special2 opcode to decodetree adds ddc7ef8dfe target/mips: Convert Rel6 COP1X opcode to decodetree adds 6513ca15d8 target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree adds 9a7372e354 target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree adds dd5697b2f9 target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree adds 13a839cf48 target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree adds 1ff668dde2 target/mips: Convert Rel6 LLD/SCD opcodes to decodetree adds 27ea1bc077 target/mips: Convert Rel6 LL/SC opcodes to decodetree adds 6648042afb target/mips: Remove CPU_R5900 definition adds fc63010e9b target/mips: Remove CPU_NANOMIPS32 definition adds eaca85763b target/mips: Remove vendor specific CPU definitions adds cd669e2051 docs/system: Remove deprecated 'fulong2e' machine alias adds 256af05f52 Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mip [...] No new revisions were added by this update. Summary of changes: docs/system/deprecated.rst | 5 - docs/system/removed-features.rst | 5 + hw/mips/boston.c | 6 +- hw/mips/fuloong2e.c | 1 - linux-user/mips/cpu_loop.c | 7 +- target/mips/addr.c | 10 + target/mips/cp0_helper.c | 18 +- target/mips/cp0_timer.c | 4 +- .../mips/{translate_init.c.inc => cpu-defs.c.inc} | 128 +- target/mips/cpu.c | 255 +- target/mips/cpu.h | 23 +- target/mips/fpu_helper.c | 5 +- target/mips/fpu_helper.h | 59 + target/mips/gdbstub.c | 1 + target/mips/helper.h | 436 +-- target/mips/internal.h | 64 +- target/mips/kvm.c | 13 +- target/mips/machine.c | 1 + target/mips/meson.build | 21 +- target/mips/mips-defs.h | 56 +- target/mips/mips32r6.decode | 36 + target/mips/mips64r6.decode | 27 + target/mips/msa32.decode | 29 + target/mips/msa64.decode | 17 + target/mips/msa_helper.c | 430 +++ target/mips/msa_helper.h.inc | 443 +++ target/mips/msa_translate.c | 2286 +++++++++++ target/mips/op_helper.c | 396 +- target/mips/rel6_translate.c | 44 + target/mips/{helper.c => tlb_helper.c} | 266 +- target/mips/translate.c | 4034 ++++---------------- target/mips/translate.h | 177 + target/mips/translate_addr_const.c | 61 + 33 files changed, 4844 insertions(+), 4520 deletions(-) rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (92%) create mode 100644 target/mips/fpu_helper.h create mode 100644 target/mips/mips32r6.decode create mode 100644 target/mips/mips64r6.decode create mode 100644 target/mips/msa32.decode create mode 100644 target/mips/msa64.decode create mode 100644 target/mips/msa_helper.h.inc create mode 100644 target/mips/msa_translate.c create mode 100644 target/mips/rel6_translate.c rename target/mips/{helper.c => tlb_helper.c} (87%) create mode 100644 target/mips/translate.h create mode 100644 target/mips/translate_addr_const.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-defconfig updated (5ebdd53534d -> 63999d751df)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-defconfig in repository toolchain/ci/gcc. from 5ebdd53534d i386: Resolve variable shadowing in i386-options.c [PR98671] adds 77d372abec0 x86: Error on -fcf-protection with incompatible target adds 236d6a33ca6 mklog: skip unsupported files adds 7624c58c6b7 gcov: add one more pytest adds aa3d33dccb5 RTEMS: Fix Ada build for riscv adds 57a4f5e4eac libstdc++: Define function to throw filesystem_error [PR 98471] adds 6106dfb9f73 [nvptx libgomp plugin] Build only in supported configurations adds 9ac3e2feb3d libgo: update hurd support adds d0d2becf2df PR fortran/98661 - valgrind issues with error recovery adds c1a2cf88059 Revert "PR fortran/98661 - valgrind issues with error recovery" adds 9e1e6e63104 PR fortran/98661 - valgrind issues with error recovery adds 05a30af3f23 libstdc++: Implement N3644 for _GLIBCXX_DEBUG iterators adds 505caa7295b [gcn offloading] Only supported in 64-bit configurations adds 088e46b8d4d declare getpass in analyzer/sensitive-1.c test adds 6541fcadc86 use sigjmp_buf for analyzer sigsetjmp tests adds 3651c1b5c9c calibrate intervals to avoid zero in futures poll test adds bdd1b1f5552 PR fortran/93340 - fix missed substring simplifications adds f6ffd449e0c c++: Tweak g++.dg/template/pr98372.C. adds 8a18261afd9 analyzer: const fixes [PR98679] adds dea4a32b24f analyzer: fixes to -fdump-analyzer-json adds fe701195313 slp: elide intermediate nodes for complex add and avoid truncate adds 500600c7840 slp: Support optimizing load distribution adds e09173d84da slp: support complex multiply and complex multiply conjugate adds 31fac31800b slp: support complex FMA and complex FMA conjugate adds 478e571a3ee slp: support complex FMS and complex FMS conjugate adds b50df1e749b slp: Add complex operations class to share first match amon [...] adds 59832db9a71 slp: Add Tests for complex mul, mls and mla" adds f1096055854 Add GCC_EXTRA_DIAGNOSTIC_OUTPUT environment variable for fi [...] adds 02e7af1122c libstdc++: Implement N3644 for _GLIBCXX_DEBUG iterators adds 387f6c15d30 Handle fancy_abort before diagnostic initialization [PR98586] adds f1fc27b6c51 c++: Minor refactoring in process_init_constructor_record adds b95d97f1a5f jit: remove "Alpha" warning from docs adds 5fff80fd79c Daily bump. adds b0ccd3922f5 compiler: add support for reading embedcfg files adds c4eec1efae0 testsuite: Fix sed script errors in complex tests adds 2ea6f4a377e tree-optimization/98685 - fix placement of extern converts adds 7432f255b70 arm: Auto-vectorization for MVE: vshl adds bfab355012c arm: Auto-vectorization for MVE: vshr adds 0411ae7f08e libatomic, libgomp, libitc: Fix bootstrap [PR70454] adds cb60334b716 testsuite/96098 - remove redundant testcase adds 1a630642009 arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds d03f14c354a testsuite/96147 - remove scanning for ! vect_hw_misalign adds e1bd80fb706 testsuite/96147 - key scanning on vect_hw_misalign adds aa4ee5798fe testsuite/96147 - scan for vectorized load adds b36c9cd0947 testsuite/96147 - align vector access new dc8475e3348 Pytest in tests: improve new 446703ccc2c tree-optimization/96376 - do not check alignment for invari [...] new f1d054017ef Revert "arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 [...] new 63999d751df arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics The 4 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: contrib/ChangeLog | 4 + contrib/mklog.py | 3 + gcc/ChangeLog | 214 ++++++ gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 6 + gcc/ada/Makefile.rtl | 5 + gcc/analyzer/ChangeLog | 22 + gcc/analyzer/analyzer.h | 2 +- gcc/analyzer/engine.cc | 29 +- gcc/analyzer/exploded-graph.h | 4 + gcc/analyzer/pending-diagnostic.h | 2 +- gcc/analyzer/store.cc | 2 +- gcc/analyzer/store.h | 4 +- gcc/analyzer/supergraph.cc | 29 +- gcc/config/arm/arm_neon.h | 31 + gcc/config/arm/mve.md | 47 +- gcc/config/arm/neon.md | 53 -- gcc/config/arm/vec-common.md | 58 ++ gcc/config/gcn/mkoffload.c | 260 +++---- gcc/config/i386/i386-options.c | 8 +- gcc/cp/ChangeLog | 10 + gcc/cp/typeck2.c | 23 +- gcc/diagnostic.c | 183 ++++- gcc/diagnostic.h | 23 +- gcc/doc/install.texi | 2 +- gcc/doc/invoke.texi | 19 + gcc/doc/md.texi | 134 ++++ gcc/doc/sourcebuild.texi | 4 + gcc/fortran/ChangeLog | 29 + gcc/fortran/gfortran.h | 1 + gcc/fortran/primary.c | 55 ++ gcc/fortran/resolve.c | 10 +- gcc/go/Make-lang.in | 1 + gcc/go/gofrontend/MERGE | 2 +- gcc/go/gofrontend/embed.cc | 628 ++++++++++++++++ gcc/go/gofrontend/gogo.h | 4 + gcc/internal-fn.def | 6 + gcc/jit/ChangeLog | 6 + gcc/jit/docs/_build/texinfo/libgccjit.texi | 10 +- gcc/jit/docs/cp/index.rst | 4 - gcc/jit/docs/index.rst | 4 - gcc/optabs.def | 6 + gcc/opts.c | 4 +- gcc/testsuite/ChangeLog | 126 ++++ gcc/testsuite/g++.dg/gcov/gcov-17.C | 40 + gcc/testsuite/g++.dg/gcov/test-gcov-17.py | 37 + gcc/testsuite/g++.dg/template/pr98372.C | 2 +- gcc/testsuite/gcc.dg/analyzer/sensitive-1.c | 5 + gcc/testsuite/gcc.dg/analyzer/sigsetjmp-5.c | 2 +- gcc/testsuite/gcc.dg/analyzer/sigsetjmp-6.c | 2 +- ...w-locus-GCC_EXTRA_DIAGNOSTIC_OUTPUT-fixits-v1.c | 71 ++ ...w-locus-GCC_EXTRA_DIAGNOSTIC_OUTPUT-fixits-v2.c | 71 ++ gcc/testsuite/gcc.dg/plugin/plugin.exp | 2 + gcc/testsuite/gcc.dg/vect/bb-slp-32.c | 1 + gcc/testsuite/gcc.dg/vect/bb-slp-9.c | 2 +- gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c | 20 - gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c | 15 + .../gcc.dg/vect/complex/complex-mla-template.c | 101 +++ .../gcc.dg/vect/complex/complex-mls-template.c | 101 +++ .../gcc.dg/vect/complex/complex-mul-template.c | 71 ++ .../complex/fast-math-bb-slp-complex-mla-double.c | 9 + .../complex/fast-math-bb-slp-complex-mla-float.c | 8 + .../fast-math-bb-slp-complex-mla-half-float.c | 9 + .../complex/fast-math-bb-slp-complex-mls-double.c | 9 + .../complex/fast-math-bb-slp-complex-mls-float.c | 8 + .../fast-math-bb-slp-complex-mls-half-float.c | 9 + .../complex/fast-math-bb-slp-complex-mul-double.c | 9 + .../complex/fast-math-bb-slp-complex-mul-float.c | 8 + .../fast-math-bb-slp-complex-mul-half-float.c | 9 + .../vect/complex/fast-math-complex-mla-double.c | 8 + .../vect/complex/fast-math-complex-mla-float.c | 8 + .../complex/fast-math-complex-mla-half-float.c | 8 + .../vect/complex/fast-math-complex-mls-double.c | 8 + .../vect/complex/fast-math-complex-mls-float.c | 8 + .../complex/fast-math-complex-mls-half-float.c | 8 + .../vect/complex/fast-math-complex-mul-double.c | 8 + .../vect/complex/fast-math-complex-mul-float.c | 8 + .../complex/fast-math-complex-mul-half-float.c | 8 + gcc/testsuite/gcc.dg/vect/slp-43.c | 4 +- gcc/testsuite/gcc.dg/vect/slp-45.c | 2 +- .../aarch64/advsimd-intrinsics/p64_p128.c | 46 +- gcc/testsuite/gcc.target/arm/simd/mve-vshl.c | 62 ++ gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 59 ++ gcc/testsuite/gcc.target/arm/simd/vceqz_p64.c | 17 + gcc/testsuite/gcc.target/arm/simd/vceqzq_p64.c | 17 + gcc/testsuite/gcc.target/i386/pr98667-1.c | 9 + gcc/testsuite/gcc.target/i386/pr98667-2.c | 9 + gcc/testsuite/gcc.target/i386/pr98667-3.c | 7 + gcc/testsuite/gfortran.dg/pr98661.f90 | 19 + gcc/testsuite/lib/gcov.exp | 31 +- gcc/testsuite/substr_10.f90 | 11 + gcc/testsuite/substr_9.f90 | 28 + gcc/tree-vect-slp-patterns.c | 823 ++++++++++++++++++++- gcc/tree-vect-slp.c | 165 ++++- gcc/tree-vect-stmts.c | 23 +- libatomic/configure.tgt | 56 +- libgo/Makefile.am | 2 +- libgo/Makefile.in | 2 +- libgo/go/crypto/x509/root_hurd.go | 6 + libgo/go/runtime/export_pipe2_test.go | 2 +- libgo/go/runtime/nbpipe_test.go | 2 +- libgo/go/runtime/os_hurd.go | 18 +- libgo/misc/cgo/test/cthread_unix.c | 2 +- libgomp/ChangeLog | 9 + libgomp/configure | 86 ++- libgomp/configure.tgt | 35 +- libgomp/plugin/configfrag.ac | 92 ++- libgomp/plugin/plugin-nvptx.c | 9 - libitm/configure.tgt | 37 +- libstdc++-v3/ChangeLog | 51 ++ libstdc++-v3/include/bits/fs_path.h | 61 +- libstdc++-v3/include/bits/hashtable_policy.h | 8 +- libstdc++-v3/include/debug/macros.h | 5 + libstdc++-v3/include/debug/safe_iterator.h | 4 +- libstdc++-v3/include/debug/safe_iterator.tcc | 5 +- libstdc++-v3/include/debug/safe_local_iterator.h | 4 +- libstdc++-v3/src/c++11/debug.cc | 5 +- .../testsuite/23_containers/deque/debug/98466.cc | 40 + .../23_containers/unordered_map/debug/98466.cc | 44 ++ .../testsuite/30_threads/future/members/poll.cc | 33 +- 120 files changed, 4177 insertions(+), 545 deletions(-) create mode 100644 gcc/go/gofrontend/embed.cc create mode 100644 gcc/testsuite/g++.dg/gcov/gcov-17.C create mode 100644 gcc/testsuite/g++.dg/gcov/test-gcov-17.py create mode 100644 gcc/testsuite/gcc.dg/plugin/diagnostic-test-show-locus-GCC_EXTR [...] create mode 100644 gcc/testsuite/gcc.dg/plugin/diagnostic-test-show-locus-GCC_EXTR [...] delete mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/complex-mla-template.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/complex-mls-template.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/complex-mul-template.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mla- [...] create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mla-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mla- [...] create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mls- [...] create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mls-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mls- [...] create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mul- [...] create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mul-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-bb-slp-complex-mul- [...] create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mla-double.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mla-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mla-half-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mls-double.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mls-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mls-half-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mul-double.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mul-float.c create mode 100644 gcc/testsuite/gcc.dg/vect/complex/fast-math-complex-mul-half-float.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vshl.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vshr.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vceqz_p64.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vceqzq_p64.c create mode 100644 gcc/testsuite/gcc.target/i386/pr98667-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr98667-2.c create mode 100644 gcc/testsuite/gcc.target/i386/pr98667-3.c create mode 100644 gcc/testsuite/gfortran.dg/pr98661.f90 create mode 100644 gcc/testsuite/substr_10.f90 create mode 100644 gcc/testsuite/substr_9.f90 create mode 100644 libstdc++-v3/testsuite/23_containers/deque/debug/98466.cc create mode 100644 libstdc++-v3/testsuite/23_containers/unordered_map/debug/98466.cc -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-defconfig updated (8ca9c7eb67 -> 10f92414d6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-defconfig in repository toolchain/ci/binutils-gdb. from 8ca9c7eb67 bfin: Skip non SEC_ALLOC section for R_BFIN_FUNCDESC adds 58eadc4b69 Fix building gdb with gcc-4.x adds c14dee84dd Update my email address (long overdue!) adds 17e8913732 Add myself to gdb/MAINTAINERS adds 5aa06b1b14 Automatic date update in version.in adds 5fda40b28f gas: make [248]byte directives available everywhere adds 3624a6c15c PR26539, memory leak in inflate.c adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status adds 7cf91a2481 sim: m32r: clean up redundant test coverage adds 89bfc2a429 sim: frv: clean up redundant test coverage adds 137d6efd8a sim: mips: delete empty stub test dir adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness adds bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 20 + bfd/elfnn-riscv.c | 319 +- bfd/elfxx-riscv.c | 54 +- bfd/elfxx-riscv.h | 4 +- bfd/version.h | 2 +- binutils/ChangeLog | 9 + binutils/MAINTAINERS | 6 +- binutils/readelf.c | 6 +- gas/ChangeLog | 30 + gas/config/obj-elf.c | 4 - gas/config/tc-riscv.c | 521 ++-- gas/config/tc-riscv.h | 6 +- gas/doc/as.texi | 7 - gas/read.c | 3 + gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +- .../gas/riscv/priv-reg-fail-read-only-01.l | 136 +- .../gas/riscv/priv-reg-fail-read-only-02.l | 48 +- gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +- .../gas/riscv/priv-reg-fail-version-1p10.l | 48 +- .../gas/riscv/priv-reg-fail-version-1p11.l | 46 +- .../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +- gdb/ChangeLog | 10 + gdb/MAINTAINERS | 1 + gdb/testsuite/ChangeLog | 6 + gdb/testsuite/gdb.fortran/array-slices.exp | 2 +- gdb/trad-frame.c | 5 +- include/ChangeLog | 11 + include/elf/riscv.h | 3 +- include/opcode/riscv-opc.h | 16 +- include/opcode/riscv.h | 127 +- ld/ChangeLog | 9 + .../ld-riscv-elf/attr-merge-priv-spec-failed-01.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-02.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-03.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-04.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-05.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-06.d | 4 +- opcodes/ChangeLog | 16 + opcodes/riscv-dis.c | 30 +- opcodes/riscv-opc.c | 1456 +++++---- sim/ChangeLog | 7 + sim/configure | 16 +- sim/configure.ac | 16 +- sim/testsuite/ChangeLog | 36 + sim/testsuite/Makefile.in | 8 +- sim/testsuite/configure | 3264 -------------------- sim/testsuite/configure.ac | 32 - sim/testsuite/d10v-elf/Makefile.in | 180 -- sim/testsuite/d10v-elf/configure | 2984 ------------------ sim/testsuite/d10v-elf/configure.ac | 18 - sim/testsuite/d10v-elf/exit47.s | 4 - sim/testsuite/d10v-elf/loop.s | 6 - sim/testsuite/frv-elf/ChangeLog | 48 - sim/testsuite/frv-elf/Makefile.in | 158 - sim/testsuite/frv-elf/configure | 2984 ------------------ sim/testsuite/frv-elf/configure.ac | 18 - sim/testsuite/frv-elf/loop.s | 2 - sim/testsuite/lib/sim-defs.exp | 23 +- sim/testsuite/m32r-elf/ChangeLog | 18 - sim/testsuite/m32r-elf/Makefile.in | 156 - sim/testsuite/m32r-elf/configure | 2984 ------------------ sim/testsuite/m32r-elf/configure.ac | 18 - sim/testsuite/m32r-elf/hello.s | 17 - sim/testsuite/m32r-elf/loop.s | 2 - sim/testsuite/mips64el-elf/ChangeLog | 19 - sim/testsuite/mips64el-elf/Makefile.in | 170 - sim/testsuite/mips64el-elf/configure | 2984 ------------------ sim/testsuite/mips64el-elf/configure.ac | 18 - sim/testsuite/sim/cris/ChangeLog | 7 + sim/testsuite/sim/cris/c/c.exp | 7 +- sim/testsuite/sim/cris/hw/rv-n-cris/rvc.exp | 2 +- sim/testsuite/{d10v-elf => sim/d10v}/ChangeLog | 5 + sim/testsuite/sim/d10v/allinsn.exp | 17 + .../{d10v-elf/t-trap.s => sim/d10v/exit47.s} | 5 +- sim/testsuite/{d10v-elf => sim/d10v}/hello.s | 3 + sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-i.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-id.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-im.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-ip.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-i.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-ld2w-id.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-ld2w-im.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-ld2w-ip.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-i.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-id.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-im.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-ip.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-is.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-i.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-id.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-im.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-ip.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-is.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-dbt.s | 7 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ld-st.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-mac.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-macros.i | 12 +- .../{d10v-elf => sim/d10v}/t-mod-ld-pre.s | 56 +- sim/testsuite/{d10v-elf => sim/d10v}/t-msbu.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-mulxu.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-mvtac.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-mvtc.s | 9 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rac.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-rachi.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-rdt.s | 7 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rep.s | 8 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rie-xx.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rte.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-sac.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sachi.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sadd.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-slae.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sp.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-sub.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sub2w.s | 16 +- sim/testsuite/{d10v-elf => sim/d10v}/t-subi.s | 4 + sim/testsuite/sim/d10v/t-trap.s | 10 + sim/testsuite/sim/frv/ChangeLog | 6 + .../{frv-elf/cache.s => sim/frv/cache.ms} | 6 +- .../{frv-elf/exit47.s => sim/frv/exit47.ms} | 6 + .../{frv-elf/grloop.s => sim/frv/grloop.ms} | 3 + .../{frv-elf/hello.s => sim/frv/hello.ms} | 3 + sim/testsuite/sim/frv/misc.exp | 19 + sim/testsuite/sim/m32r/ChangeLog | 4 + .../{m32r-elf/exit47.s => sim/m32r/exit47.ms} | 4 + 129 files changed, 2042 insertions(+), 17757 deletions(-) delete mode 100755 sim/testsuite/configure delete mode 100644 sim/testsuite/configure.ac delete mode 100644 sim/testsuite/d10v-elf/Makefile.in delete mode 100755 sim/testsuite/d10v-elf/configure delete mode 100644 sim/testsuite/d10v-elf/configure.ac delete mode 100644 sim/testsuite/d10v-elf/exit47.s delete mode 100644 sim/testsuite/d10v-elf/loop.s delete mode 100644 sim/testsuite/frv-elf/ChangeLog delete mode 100644 sim/testsuite/frv-elf/Makefile.in delete mode 100755 sim/testsuite/frv-elf/configure delete mode 100644 sim/testsuite/frv-elf/configure.ac delete mode 100644 sim/testsuite/frv-elf/loop.s delete mode 100644 sim/testsuite/m32r-elf/ChangeLog delete mode 100644 sim/testsuite/m32r-elf/Makefile.in delete mode 100755 sim/testsuite/m32r-elf/configure delete mode 100644 sim/testsuite/m32r-elf/configure.ac delete mode 100644 sim/testsuite/m32r-elf/hello.s delete mode 100644 sim/testsuite/m32r-elf/loop.s delete mode 100644 sim/testsuite/mips64el-elf/ChangeLog delete mode 100644 sim/testsuite/mips64el-elf/Makefile.in delete mode 100755 sim/testsuite/mips64el-elf/configure delete mode 100644 sim/testsuite/mips64el-elf/configure.ac rename sim/testsuite/{d10v-elf => sim/d10v}/ChangeLog (96%) create mode 100644 sim/testsuite/sim/d10v/allinsn.exp rename sim/testsuite/{d10v-elf/t-trap.s => sim/d10v/exit47.s} (52%) rename sim/testsuite/{d10v-elf => sim/d10v}/hello.s (54%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-d.s (76%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-i.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-id.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-im.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-ip.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-d.s (77%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-i.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-id.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-im.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-ip.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-d.s (76%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-i.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-id.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-im.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-ip.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-is.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-d.s (77%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-i.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-id.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-im.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-ip.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-is.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-dbt.s (88%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ld-st.s (88%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mac.s (95%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-macros.i (97%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mod-ld-pre.s (90%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-msbu.s (87%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mulxu.s (87%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mvtac.s (84%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mvtc.s (95%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rac.s (82%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rachi.s (87%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rdt.s (75%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rep.s (90%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rie-xx.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rte.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sac.s (85%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sachi.s (83%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sadd.s (92%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-slae.s (92%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sp.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sub.s (92%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sub2w.s (93%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-subi.s (92%) create mode 100644 sim/testsuite/sim/d10v/t-trap.s rename sim/testsuite/{frv-elf/cache.s => sim/frv/cache.ms} (95%) rename sim/testsuite/{frv-elf/exit47.s => sim/frv/exit47.ms} (50%) rename sim/testsuite/{frv-elf/grloop.s => sim/frv/grloop.ms} (86%) rename sim/testsuite/{frv-elf/hello.s => sim/frv/hello.ms} (86%) create mode 100644 sim/testsuite/sim/frv/misc.exp rename sim/testsuite/{m32r-elf/exit47.s => sim/m32r/exit47.ms} (66%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-defconfig updated (0367b643 -> 395c56e1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-defconfig in repository toolchain/ci/base-artifacts. discards 0367b643 0: update: binutils-gcc-linux-qemu: boot new 395c56e1 0: update: binutils-gcc-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (0367b643) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 191 +- 02-prepare_abe/console.log | 438 +- 03-build_abe-binutils/console.log | 12223 +++++----- 04-build_abe-stage1/console.log | 16438 ++++++------- 05-build_linux/console.log | 834 +- 06-build_abe-qemu/console.log | 6777 +++--- 07-boot_linux/console.log | 492 +- 08-check_regression/console.log | 24 +- 08-check_regression/results.regressions | 2 +- 09-update_baseline/console.log | 18 +- 09-update_baseline/results.regressions | 2 +- console.log | 37365 +++++++++++++++--------------- jenkins/manifest.sh | 18 +- 13 files changed, 37474 insertions(+), 37348 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

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Tcwg-commits January 2021