Tcwg-commits January 2021

tcwg-commits@lists.linaro.org

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9360 discussions

[linux] branch master updated (82821be8a2e1 -> 0bc9bc1d8b2f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository linux. from 82821be8a2e1 Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/li [...] new 77b6ec01c29a cifs: check pointer before freeing new 2659d3bff3e1 cifs: fix interrupted close commands new c13e7af04227 fs: cifs: remove unneeded variable in smb3_fs_context_dup new ed6b1920f84b cifs: connect: style: Simplify bool comparison new e54fd0716c3d cifs: style: replace one-element array with flexible-array new 7cd3c4126188 Merge tag '5.11-rc3-smb3' of git://git.samba.org/sfrench/cifs-2.6 new e789ca0cc1d5 ext4: combine ext4_handle_error() and save_error_info() new 4392fbc4bab5 ext4: drop sync argument of ext4_commit_super() new 05c2c00f3769 ext4: protect superblock modifications with a buffer lock new 2d01ddc86606 ext4: save error info to sb through journal if available new e92ad03fa534 ext4: use sbi instead of EXT4_SB(sb) in ext4_update_super() new dfd56c2c0c0d ext4: fix superblock checksum failure when setting password salt new a3f5cf14ff91 ext4: drop ext4_handle_dirty_super() new 5a3b590d4b2d ext4: don't leak old mountpoint samples new 23dd561ad9ea ext4: use IS_ERR instead of IS_ERR_OR_NULL and set inode n [...] new 31e203e09f03 ext4: fix wrong list_splice in ext4_fc_cleanup new 6b4b8e6b4ad8 ext4: fix bug for rename with RENAME_WHITEOUT new e9f53353e166 ext4: remove expensive flush on fast commit new 0bc9bc1d8b2f Merge tag 'ext4_for_linus_stable' of git://git.kernel.org/ [...] The 19 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: fs/cifs/connect.c | 2 +- fs/cifs/dfs_cache.c | 3 +- fs/cifs/fs_context.c | 4 +- fs/cifs/smb2pdu.c | 2 +- fs/cifs/smb2pdu.h | 2 +- fs/ext4/ext4_jbd2.c | 17 ----- fs/ext4/ext4_jbd2.h | 5 -- fs/ext4/fast_commit.c | 35 +++++----- fs/ext4/file.c | 7 +- fs/ext4/inode.c | 6 +- fs/ext4/ioctl.c | 3 + fs/ext4/namei.c | 27 ++++--- fs/ext4/resize.c | 20 ++++-- fs/ext4/super.c | 190 +++++++++++++++++++++++++++++++------------------- fs/ext4/xattr.c | 5 +- 15 files changed, 192 insertions(+), 136 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig updated (7c79721606 -> 7cb6b97300)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig in repository toolchain/ci/qemu. from 7c79721606 Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-t [...] adds 8cd0b410a2 target/mips: Add CP0 Config0 register definitions for MIPS3 ISA adds b4cbbb47b0 target/mips: Replace CP0_Config0 magic values by proper definitions adds 07ae8ccd0f target/mips/addr: Add translation helpers for KSEG1 adds 737cca57d3 target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment adds bf5523773e target/mips/mips-defs: Reorder CPU_MIPS5 definition adds 8b0ea9b638 target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 adds b0586b38cb target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() adds ce49581feb hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() adds 08e2262fad target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 adds f395cef765 target/mips/mips-defs: Use ISA_MIPS32R2 definition to check [...] adds 4d1524d2ce target/mips/mips-defs: Use ISA_MIPS32R3 definition to check [...] adds d913c3992d target/mips/mips-defs: Use ISA_MIPS32R5 definition to check [...] adds 13514fc93e target/mips/mips-defs: Use ISA_MIPS32R6 definition to check [...] adds bbd5e4a27f target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 adds 7a47bae586 target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 adds bae4b15aa4 target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 adds 5f89ce4fc2 target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 adds 2e211e0a12 target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 adds 9bcd41d41f target/mips: Inline cpu_state_reset() in mips_cpu_reset() adds 81ddae7c30 target/mips: Extract FPU helpers to 'fpu_helper.h' adds f9bd3d79f4 target/mips: Add !CONFIG_USER_ONLY comment after #endif adds 2be565f9c2 target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs adds e9927723ba target/mips: Move common helpers from helper.c to cpu.c adds 4cb213dc90 target/mips: Rename helper.c as tlb_helper.c adds ca2690e36a target/mips: Fix code style for checkpatch.pl adds f2c5b39ecd target/mips: Move mmu_init() functions to tlb_helper.c adds 0dc351ca6b target/mips: Rename translate_init.c as cpu-defs.c adds e31309365e target/mips/translate: Extract DisasContext structure adds 46c9e2b3dd target/mips/translate: Add declarations for generic code adds 11a7511856 target/mips: Replace gen_exception_err(err=0) by gen_excepti [...] adds 3a4ef3b7ee target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_ [...] adds 8758d1b8aa target/mips: Declare generic FPU / Coprocessor functions in [...] adds 57eedcf7e3 target/mips: Extract FPU specific definitions to translate.h adds 8b7322add3 target/mips: Only build TCG code when CONFIG_TCG is set adds 311edee771 target/mips/translate: Extract decode_opc_legacy() from deco [...] adds d7efb69382 target/mips/translate: Expose check_mips_64() to 32-bit mode adds 25a1362875 target/mips: Introduce ase_msa_available() helper adds 72f31f60f8 target/mips: Simplify msa_reset() adds aa314198ca target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA adds 33942f9460 target/mips: Simplify MSA TCG logic adds 7e2a619a04 target/mips: Remove now unused ASE_MSA definition adds e2665f314d target/mips: Alias MSA vector registers on FPU scalar registers adds 959c5da28e target/mips: Extract msa_translate_init() from mips_tcg_init() adds 63af5b9018 target/mips: Remove CPUMIPSState* argument from gen_msa*() methods adds 810fda17c8 target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() adds 03e4d95c91 target/mips: Move msa_reset() to msa_helper.c adds 3ef60574b6 target/mips: Extract MSA helpers from op_helper.c adds edb2384728 target/mips: Extract MSA helper definitions adds 54ccff5102 target/mips: Declare gen_msa/_branch() in 'translate.h' adds 80e64a380f target/mips: Extract MSA translation routines adds 878b87b541 target/mips: Pass TCGCond argument to MSA gen_check_zero_element() adds c7a9ef7517 target/mips: Introduce decode tree bindings for MSA ASE adds 96e5b4c758 target/mips: Use decode_ase_msa() generated from decodetree adds a685f7d075 target/mips: Extract LSA/DLSA translation generators adds 5f21f30d85 target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes adds 3f7a927847 target/mips: Introduce decodetree helpers for Release6 LSA/D [...] adds 0e9524af2d target/mips: Remove now unreachable LSA/DLSA opcodes code adds aac357ec89 target/mips: Convert Rel6 Special2 opcode to decodetree adds ddc7ef8dfe target/mips: Convert Rel6 COP1X opcode to decodetree adds 6513ca15d8 target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree adds 9a7372e354 target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree adds dd5697b2f9 target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree adds 13a839cf48 target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree adds 1ff668dde2 target/mips: Convert Rel6 LLD/SCD opcodes to decodetree adds 27ea1bc077 target/mips: Convert Rel6 LL/SC opcodes to decodetree adds 6648042afb target/mips: Remove CPU_R5900 definition adds fc63010e9b target/mips: Remove CPU_NANOMIPS32 definition adds eaca85763b target/mips: Remove vendor specific CPU definitions adds cd669e2051 docs/system: Remove deprecated 'fulong2e' machine alias adds 256af05f52 Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mip [...] adds 89fbea8737 9pfs: Fully restart unreclaim loop (CVE-2021-20181) adds a968a38005 Merge remote-tracking branch 'remotes/gkurz-gitlab/tags/9p-n [...] adds e80be993b5 ui/gtk: don't try to redefine SI prefixes adds 0431e369b0 ui/gtk: rename variable window to widget adds 3c4b8f8310 ui/gtk: limit virtual console max update interval adds 0fdc99775c ui/gtk: expose gd_monitor_update_interval adds cab82424f6 ui/gtk: update monitor interval on egl displays adds 521534df57 vnc: fix unfinalized tlscreds for VncDisplay adds 7b5fa0b583 ui: add support for remote power control to VNC server adds 5f8679fe46 vnc: Fix a memleak in vnc_display_connect() adds b3c2de9cd5 vnc: move check into vnc_cursor_define adds 9e1632ad07 vnc: move initialization to framebuffer_update_request adds 763deea7e9 vnc: add support for extended desktop resize adds 7cb6b97300 Merge remote-tracking branch 'remotes/kraxel/tags/ui-2021011 [...] No new revisions were added by this update. Summary of changes: docs/system/deprecated.rst | 5 - docs/system/removed-features.rst | 5 + hw/9pfs/9p.c | 6 +- hw/mips/boston.c | 6 +- hw/mips/fuloong2e.c | 1 - include/ui/gtk.h | 3 +- linux-user/mips/cpu_loop.c | 7 +- qemu-options.hx | 4 + target/mips/addr.c | 10 + target/mips/cp0_helper.c | 18 +- target/mips/cp0_timer.c | 4 +- .../mips/{translate_init.c.inc => cpu-defs.c.inc} | 128 +- target/mips/cpu.c | 255 +- target/mips/cpu.h | 23 +- target/mips/fpu_helper.c | 5 +- target/mips/fpu_helper.h | 59 + target/mips/gdbstub.c | 1 + target/mips/helper.h | 436 +-- target/mips/internal.h | 64 +- target/mips/kvm.c | 13 +- target/mips/machine.c | 1 + target/mips/meson.build | 21 +- target/mips/mips-defs.h | 56 +- target/mips/mips32r6.decode | 36 + target/mips/mips64r6.decode | 27 + target/mips/msa32.decode | 29 + target/mips/msa64.decode | 17 + target/mips/msa_helper.c | 430 +++ target/mips/msa_helper.h.inc | 443 +++ target/mips/msa_translate.c | 2286 +++++++++++ target/mips/op_helper.c | 396 +- target/mips/rel6_translate.c | 44 + target/mips/{helper.c => tlb_helper.c} | 266 +- target/mips/translate.c | 4034 ++++---------------- target/mips/translate.h | 177 + target/mips/translate_addr_const.c | 61 + ui/gtk-egl.c | 3 + ui/gtk.c | 25 +- ui/vnc.c | 147 +- ui/vnc.h | 15 + 40 files changed, 5016 insertions(+), 4551 deletions(-) rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (92%) create mode 100644 target/mips/fpu_helper.h create mode 100644 target/mips/mips32r6.decode create mode 100644 target/mips/mips64r6.decode create mode 100644 target/mips/msa32.decode create mode 100644 target/mips/msa64.decode create mode 100644 target/mips/msa_helper.h.inc create mode 100644 target/mips/msa_translate.c create mode 100644 target/mips/rel6_translate.c rename target/mips/{helper.c => tlb_helper.c} (87%) create mode 100644 target/mips/translate.h create mode 100644 target/mips/translate_addr_const.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig updated (b0ccd3922f5 -> 0425f4c1b63)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig in repository toolchain/ci/gcc. from b0ccd3922f5 compiler: add support for reading embedcfg files adds c4eec1efae0 testsuite: Fix sed script errors in complex tests adds 2ea6f4a377e tree-optimization/98685 - fix placement of extern converts adds 7432f255b70 arm: Auto-vectorization for MVE: vshl adds bfab355012c arm: Auto-vectorization for MVE: vshr adds 0411ae7f08e libatomic, libgomp, libitc: Fix bootstrap [PR70454] adds cb60334b716 testsuite/96098 - remove redundant testcase adds 1a630642009 arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds d03f14c354a testsuite/96147 - remove scanning for ! vect_hw_misalign adds e1bd80fb706 testsuite/96147 - key scanning on vect_hw_misalign adds aa4ee5798fe testsuite/96147 - scan for vectorized load adds b36c9cd0947 testsuite/96147 - align vector access adds dc8475e3348 Pytest in tests: improve adds 446703ccc2c tree-optimization/96376 - do not check alignment for invari [...] adds f1d054017ef Revert "arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 [...] adds 63999d751df arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds f9a577927eb IBM Z: Fix linking to libatomic in target test cases adds 7f6cdaa9a8d rtl-ssa: Fix a silly typo adds f2cc526f47a recog: Fix insn_change_watermark destructor adds 5a783f42d77 aarch64: Add a minipass for fusing CC insns [PR88836] adds 492b90f33df c++: Fix langspecs with -fsyntax-only [PR98591] adds 1ba71fabb78 preprocessor: Make quoting : [PR 95253] adds 7d0df0aeb67 i386: Use cpp_define_formatted for __SIZEOF_FLOAT80__ definition adds d3959070aa4 [PATCH] aarch64: Implement vmlsl[_high]* intrinsics using builtins adds 50dbced2f37 openmp: Change the way of building of reduction array type adds adb520606ce c-family: Improve MEM_REF printing for diagnostics [PR98597] adds a3128bf0128 bootstrap: fix failing diagnostic selftest on Windows [PR98696] adds aaec739250b testsuite: Add testcase coverage for already fixed [PR96671] adds c0194736b47 gcc.dg/analyzer tests: use __builtin_alloca, not alloca.h adds cd09079cfd5 c++: Fix list-init of array of no-copy type [PR63707] adds ad260343385 AArch64: Add NEON, SVE and SVE2 RTL patterns for Multiply, [...] adds 424deca72b6 c++: Fix copy elision for base initialization adds d75199f7823 c++: Avoid redundant copy in {} init [PR98642] adds e63c2161d09 drop -dumpbase-ext from producer string adds 5c046034e3e match.pd: Optimize (x < 0) ^ (y < 0) to (x ^ y) < 0 etc. [PR96681] adds 0425f4c1b63 match.pd: Generalize the PR64309 simplifications [PR96669] No new revisions were added by this update. Summary of changes: gcc/Makefile.in | 7 + gcc/c-family/c-pretty-print.c | 259 ++++++++++++++---- gcc/c/c-typeck.c | 4 +- gcc/config.gcc | 2 +- gcc/config/aarch64/aarch64-cc-fusion.cc | 296 +++++++++++++++++++++ gcc/config/aarch64/aarch64-passes.def | 1 + gcc/config/aarch64/aarch64-protos.h | 1 + gcc/config/aarch64/aarch64-simd-builtins.def | 8 + gcc/config/aarch64/aarch64-simd.md | 56 +++- gcc/config/aarch64/aarch64-sve.md | 56 ++++ gcc/config/aarch64/aarch64-sve2.md | 42 +++ gcc/config/aarch64/arm_neon.h | 84 +----- gcc/config/aarch64/iterators.md | 109 +++++++- gcc/config/aarch64/t-aarch64 | 6 + gcc/config/arm/arm_neon.h | 31 +++ gcc/config/arm/mve.md | 47 +++- gcc/config/arm/neon.md | 53 ---- gcc/config/arm/vec-common.md | 58 ++++ gcc/config/i386/i386-c.c | 9 +- gcc/cp/call.c | 145 ++++++++-- gcc/cp/cp-tree.h | 3 +- gcc/cp/lang-specs.h | 40 +-- gcc/cp/tree.c | 10 +- gcc/cp/typeck2.c | 21 +- gcc/diagnostic.c | 12 +- gcc/doc/install.texi | 2 +- gcc/doc/sourcebuild.texi | 4 + gcc/match.pd | 39 ++- gcc/opts.c | 1 + gcc/recog.h | 8 +- gcc/rtl-ssa/functions.h | 2 +- gcc/rtl-ssa/member-fns.inl | 2 +- gcc/testsuite/g++.dg/cpp0x/initlist-array13.C | 16 ++ gcc/testsuite/g++.dg/cpp1z/elide4.C | 24 ++ gcc/testsuite/g++.dg/cpp1z/elide5.C | 15 ++ gcc/testsuite/g++.dg/modules/pr98591.H | 3 + gcc/testsuite/gcc.dg/analyzer/alloca-leak.c | 4 +- gcc/testsuite/gcc.dg/analyzer/data-model-1.c | 5 +- gcc/testsuite/gcc.dg/analyzer/malloc-1.c | 3 +- gcc/testsuite/gcc.dg/analyzer/malloc-paths-8.c | 7 +- gcc/testsuite/gcc.dg/tree-ssa/pr96669-1.c | 59 ++++ gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c | 51 ++++ gcc/testsuite/gcc.dg/tree-ssa/pr96671-2.c | 51 ++++ gcc/testsuite/gcc.dg/tree-ssa/pr96681.c | 35 +++ gcc/testsuite/gcc.dg/uninit-38.c | 80 +++--- gcc/testsuite/gcc.dg/uninit-40.c | 50 ++++ gcc/testsuite/gcc.dg/vect/bb-slp-32.c | 1 + gcc/testsuite/gcc.dg/vect/bb-slp-9.c | 2 +- gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c | 20 -- gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c | 15 ++ .../gcc.dg/vect/complex/complex-mla-template.c | 28 +- .../gcc.dg/vect/complex/complex-mls-template.c | 28 +- gcc/testsuite/gcc.dg/vect/slp-43.c | 4 +- gcc/testsuite/gcc.dg/vect/slp-45.c | 2 +- .../aarch64/advsimd-intrinsics/p64_p128.c | 46 +++- .../gcc.target/aarch64/sve/acle/general/ldff1_8.c | 32 +++ gcc/testsuite/gcc.target/aarch64/sve/ptest_1.c | 10 + gcc/testsuite/gcc.target/arm/simd/mve-vshl.c | 62 +++++ gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 59 ++++ gcc/testsuite/gcc.target/arm/simd/vceqz_p64.c | 17 ++ gcc/testsuite/gcc.target/arm/simd/vceqzq_p64.c | 17 ++ .../gcc.target/s390/md/atomic_exchange-1.c | 2 +- gcc/testsuite/gcc.target/s390/s390.exp | 4 + gcc/testsuite/lib/gcov.exp | 31 ++- gcc/tree-vect-slp.c | 11 +- gcc/tree-vect-stmts.c | 23 +- libatomic/configure.tgt | 56 ++-- libcpp/mkdeps.c | 1 - libgomp/configure.tgt | 35 ++- libitm/configure.tgt | 37 ++- 70 files changed, 1920 insertions(+), 444 deletions(-) create mode 100644 gcc/config/aarch64/aarch64-cc-fusion.cc create mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist-array13.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/elide4.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/elide5.C create mode 100644 gcc/testsuite/g++.dg/modules/pr98591.H create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96669-1.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96671-2.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96681.c create mode 100644 gcc/testsuite/gcc.dg/uninit-40.c delete mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/ldff1_8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/ptest_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vshl.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vshr.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vceqz_p64.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vceqzq_p64.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig updated (bb3eddb5bd -> 5a11fff005)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig in repository toolchain/ci/binutils-gdb. from bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 adds 5a11fff005 gdb/tui: compare pointer to nullptr, not 0 No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 20 + bfd/elfnn-riscv.c | 319 +++-- bfd/elfxx-riscv.c | 54 +- bfd/elfxx-riscv.h | 4 +- gas/ChangeLog | 23 + gas/config/tc-riscv.c | 521 ++++--- gas/config/tc-riscv.h | 6 +- gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +- .../gas/riscv/priv-reg-fail-read-only-01.l | 136 +- .../gas/riscv/priv-reg-fail-read-only-02.l | 48 +- gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +- .../gas/riscv/priv-reg-fail-version-1p10.l | 48 +- .../gas/riscv/priv-reg-fail-version-1p11.l | 46 +- .../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +- gdb/ChangeLog | 4 + gdb/testsuite/ChangeLog | 6 + gdb/testsuite/gdb.fortran/array-slices.exp | 2 +- gdb/tui/tui.c | 4 +- include/ChangeLog | 11 + include/elf/riscv.h | 3 +- include/opcode/riscv-opc.h | 16 +- include/opcode/riscv.h | 127 +- ld/ChangeLog | 9 + .../ld-riscv-elf/attr-merge-priv-spec-failed-01.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-02.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-03.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-04.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-05.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-06.d | 4 +- opcodes/ChangeLog | 16 + opcodes/riscv-dis.c | 30 +- opcodes/riscv-opc.c | 1456 ++++++++++---------- 32 files changed, 1582 insertions(+), 1541 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig updated (e1ce0d47 -> 5f03720a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-lts-allmodconfig in repository toolchain/ci/base-artifacts. discards e1ce0d47 0: update: binutils-gcc-linux-qemu: boot new 5f03720a 0: update: binutils-gcc-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (e1ce0d47) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 226 +- 02-prepare_abe/console.log | 444 +- 03-build_abe-binutils/console.log | 12092 ++++---- 04-build_abe-stage1/console.log | 16460 +++++------ 05-build_linux/console.log | 9394 +++--- 06-build_abe-qemu/console.log | 6854 +++-- 07-boot_linux/console.log | 8 +- 08-check_regression/console.log | 12 +- 08-check_regression/results.regressions | 2 +- 09-update_baseline/console.log | 12 +- 09-update_baseline/results.regressions | 2 +- console.log | 45478 +++++++++++++++--------------- jenkins/manifest.sh | 16 +- 13 files changed, 45514 insertions(+), 45486 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/interesting-commits] branch linaro-local/ci/tcwg_bmk_tk1 updated (e927c7f -> e8f6ffa)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1 in repository toolchain/ci/interesting-commits. from e927c7f Add regression 03eb09292ef228d1d12b5168cdd748583b1f992a from [...] new e8f6ffa Add regression 3c57e692357c79ee7623dfc1586652aee2aefb8f from [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig updated (7c79721606 -> 7cb6b97300)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig in repository toolchain/ci/qemu. from 7c79721606 Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-t [...] adds 8cd0b410a2 target/mips: Add CP0 Config0 register definitions for MIPS3 ISA adds b4cbbb47b0 target/mips: Replace CP0_Config0 magic values by proper definitions adds 07ae8ccd0f target/mips/addr: Add translation helpers for KSEG1 adds 737cca57d3 target/mips/mips-defs: Remove USE_HOST_FLOAT_REGS comment adds bf5523773e target/mips/mips-defs: Reorder CPU_MIPS5 definition adds 8b0ea9b638 target/mips/mips-defs: Rename CPU_MIPSxx Release 1 as CPU_MIPSxxR1 adds b0586b38cb target/mips/mips-defs: Introduce CPU_MIPS64 and cpu_type_is_64bit() adds ce49581feb hw/mips/boston: Check 64-bit support with cpu_type_is_64bit() adds 08e2262fad target/mips/mips-defs: Use ISA_MIPS32 definition to check Release 1 adds f395cef765 target/mips/mips-defs: Use ISA_MIPS32R2 definition to check [...] adds 4d1524d2ce target/mips/mips-defs: Use ISA_MIPS32R3 definition to check [...] adds d913c3992d target/mips/mips-defs: Use ISA_MIPS32R5 definition to check [...] adds 13514fc93e target/mips/mips-defs: Use ISA_MIPS32R6 definition to check [...] adds bbd5e4a27f target/mips/mips-defs: Rename ISA_MIPS32 as ISA_MIPS_R1 adds 7a47bae586 target/mips/mips-defs: Rename ISA_MIPS32R2 as ISA_MIPS_R2 adds bae4b15aa4 target/mips/mips-defs: Rename ISA_MIPS32R3 as ISA_MIPS_R3 adds 5f89ce4fc2 target/mips/mips-defs: Rename ISA_MIPS32R5 as ISA_MIPS_R5 adds 2e211e0a12 target/mips/mips-defs: Rename ISA_MIPS32R6 as ISA_MIPS_R6 adds 9bcd41d41f target/mips: Inline cpu_state_reset() in mips_cpu_reset() adds 81ddae7c30 target/mips: Extract FPU helpers to 'fpu_helper.h' adds f9bd3d79f4 target/mips: Add !CONFIG_USER_ONLY comment after #endif adds 2be565f9c2 target/mips: Remove consecutive CONFIG_USER_ONLY ifdefs adds e9927723ba target/mips: Move common helpers from helper.c to cpu.c adds 4cb213dc90 target/mips: Rename helper.c as tlb_helper.c adds ca2690e36a target/mips: Fix code style for checkpatch.pl adds f2c5b39ecd target/mips: Move mmu_init() functions to tlb_helper.c adds 0dc351ca6b target/mips: Rename translate_init.c as cpu-defs.c adds e31309365e target/mips/translate: Extract DisasContext structure adds 46c9e2b3dd target/mips/translate: Add declarations for generic code adds 11a7511856 target/mips: Replace gen_exception_err(err=0) by gen_excepti [...] adds 3a4ef3b7ee target/mips: Replace gen_exception_end(EXCP_RI) by gen_rsvd_ [...] adds 8758d1b8aa target/mips: Declare generic FPU / Coprocessor functions in [...] adds 57eedcf7e3 target/mips: Extract FPU specific definitions to translate.h adds 8b7322add3 target/mips: Only build TCG code when CONFIG_TCG is set adds 311edee771 target/mips/translate: Extract decode_opc_legacy() from deco [...] adds d7efb69382 target/mips/translate: Expose check_mips_64() to 32-bit mode adds 25a1362875 target/mips: Introduce ase_msa_available() helper adds 72f31f60f8 target/mips: Simplify msa_reset() adds aa314198ca target/mips: Use CP0_Config3 to set MIPS_HFLAG_MSA adds 33942f9460 target/mips: Simplify MSA TCG logic adds 7e2a619a04 target/mips: Remove now unused ASE_MSA definition adds e2665f314d target/mips: Alias MSA vector registers on FPU scalar registers adds 959c5da28e target/mips: Extract msa_translate_init() from mips_tcg_init() adds 63af5b9018 target/mips: Remove CPUMIPSState* argument from gen_msa*() methods adds 810fda17c8 target/mips: Explode gen_msa_branch() as gen_msa_BxZ_V/BxZ() adds 03e4d95c91 target/mips: Move msa_reset() to msa_helper.c adds 3ef60574b6 target/mips: Extract MSA helpers from op_helper.c adds edb2384728 target/mips: Extract MSA helper definitions adds 54ccff5102 target/mips: Declare gen_msa/_branch() in 'translate.h' adds 80e64a380f target/mips: Extract MSA translation routines adds 878b87b541 target/mips: Pass TCGCond argument to MSA gen_check_zero_element() adds c7a9ef7517 target/mips: Introduce decode tree bindings for MSA ASE adds 96e5b4c758 target/mips: Use decode_ase_msa() generated from decodetree adds a685f7d075 target/mips: Extract LSA/DLSA translation generators adds 5f21f30d85 target/mips: Introduce decodetree helpers for MSA LSA/DLSA opcodes adds 3f7a927847 target/mips: Introduce decodetree helpers for Release6 LSA/D [...] adds 0e9524af2d target/mips: Remove now unreachable LSA/DLSA opcodes code adds aac357ec89 target/mips: Convert Rel6 Special2 opcode to decodetree adds ddc7ef8dfe target/mips: Convert Rel6 COP1X opcode to decodetree adds 6513ca15d8 target/mips: Convert Rel6 CACHE/PREF opcodes to decodetree adds 9a7372e354 target/mips: Convert Rel6 LWL/LWR/SWL/SWR opcodes to decodetree adds dd5697b2f9 target/mips: Convert Rel6 LWLE/LWRE/SWLE/SWRE opcodes to decodetree adds 13a839cf48 target/mips: Convert Rel6 LDL/LDR/SDL/SDR opcodes to decodetree adds 1ff668dde2 target/mips: Convert Rel6 LLD/SCD opcodes to decodetree adds 27ea1bc077 target/mips: Convert Rel6 LL/SC opcodes to decodetree adds 6648042afb target/mips: Remove CPU_R5900 definition adds fc63010e9b target/mips: Remove CPU_NANOMIPS32 definition adds eaca85763b target/mips: Remove vendor specific CPU definitions adds cd669e2051 docs/system: Remove deprecated 'fulong2e' machine alias adds 256af05f52 Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mip [...] adds 89fbea8737 9pfs: Fully restart unreclaim loop (CVE-2021-20181) adds a968a38005 Merge remote-tracking branch 'remotes/gkurz-gitlab/tags/9p-n [...] adds e80be993b5 ui/gtk: don't try to redefine SI prefixes adds 0431e369b0 ui/gtk: rename variable window to widget adds 3c4b8f8310 ui/gtk: limit virtual console max update interval adds 0fdc99775c ui/gtk: expose gd_monitor_update_interval adds cab82424f6 ui/gtk: update monitor interval on egl displays adds 521534df57 vnc: fix unfinalized tlscreds for VncDisplay adds 7b5fa0b583 ui: add support for remote power control to VNC server adds 5f8679fe46 vnc: Fix a memleak in vnc_display_connect() adds b3c2de9cd5 vnc: move check into vnc_cursor_define adds 9e1632ad07 vnc: move initialization to framebuffer_update_request adds 763deea7e9 vnc: add support for extended desktop resize adds 7cb6b97300 Merge remote-tracking branch 'remotes/kraxel/tags/ui-2021011 [...] No new revisions were added by this update. Summary of changes: docs/system/deprecated.rst | 5 - docs/system/removed-features.rst | 5 + hw/9pfs/9p.c | 6 +- hw/mips/boston.c | 6 +- hw/mips/fuloong2e.c | 1 - include/ui/gtk.h | 3 +- linux-user/mips/cpu_loop.c | 7 +- qemu-options.hx | 4 + target/mips/addr.c | 10 + target/mips/cp0_helper.c | 18 +- target/mips/cp0_timer.c | 4 +- .../mips/{translate_init.c.inc => cpu-defs.c.inc} | 128 +- target/mips/cpu.c | 255 +- target/mips/cpu.h | 23 +- target/mips/fpu_helper.c | 5 +- target/mips/fpu_helper.h | 59 + target/mips/gdbstub.c | 1 + target/mips/helper.h | 436 +-- target/mips/internal.h | 64 +- target/mips/kvm.c | 13 +- target/mips/machine.c | 1 + target/mips/meson.build | 21 +- target/mips/mips-defs.h | 56 +- target/mips/mips32r6.decode | 36 + target/mips/mips64r6.decode | 27 + target/mips/msa32.decode | 29 + target/mips/msa64.decode | 17 + target/mips/msa_helper.c | 430 +++ target/mips/msa_helper.h.inc | 443 +++ target/mips/msa_translate.c | 2286 +++++++++++ target/mips/op_helper.c | 396 +- target/mips/rel6_translate.c | 44 + target/mips/{helper.c => tlb_helper.c} | 266 +- target/mips/translate.c | 4034 ++++---------------- target/mips/translate.h | 177 + target/mips/translate_addr_const.c | 61 + ui/gtk-egl.c | 3 + ui/gtk.c | 25 +- ui/vnc.c | 147 +- ui/vnc.h | 15 + 40 files changed, 5016 insertions(+), 4551 deletions(-) rename target/mips/{translate_init.c.inc => cpu-defs.c.inc} (92%) create mode 100644 target/mips/fpu_helper.h create mode 100644 target/mips/mips32r6.decode create mode 100644 target/mips/mips64r6.decode create mode 100644 target/mips/msa32.decode create mode 100644 target/mips/msa64.decode create mode 100644 target/mips/msa_helper.h.inc create mode 100644 target/mips/msa_translate.c create mode 100644 target/mips/rel6_translate.c rename target/mips/{helper.c => tlb_helper.c} (87%) create mode 100644 target/mips/translate.h create mode 100644 target/mips/translate_addr_const.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig updated (59832db9a71 -> 9beb6d88eff)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig in repository toolchain/ci/gcc. from 59832db9a71 slp: Add Tests for complex mul, mls and mla" adds f1096055854 Add GCC_EXTRA_DIAGNOSTIC_OUTPUT environment variable for fi [...] adds 02e7af1122c libstdc++: Implement N3644 for _GLIBCXX_DEBUG iterators adds 387f6c15d30 Handle fancy_abort before diagnostic initialization [PR98586] adds f1fc27b6c51 c++: Minor refactoring in process_init_constructor_record adds b95d97f1a5f jit: remove "Alpha" warning from docs adds 5fff80fd79c Daily bump. adds b0ccd3922f5 compiler: add support for reading embedcfg files adds c4eec1efae0 testsuite: Fix sed script errors in complex tests adds 2ea6f4a377e tree-optimization/98685 - fix placement of extern converts adds 7432f255b70 arm: Auto-vectorization for MVE: vshl adds bfab355012c arm: Auto-vectorization for MVE: vshr adds 0411ae7f08e libatomic, libgomp, libitc: Fix bootstrap [PR70454] adds cb60334b716 testsuite/96098 - remove redundant testcase adds 1a630642009 arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds d03f14c354a testsuite/96147 - remove scanning for ! vect_hw_misalign adds e1bd80fb706 testsuite/96147 - key scanning on vect_hw_misalign adds aa4ee5798fe testsuite/96147 - scan for vectorized load adds b36c9cd0947 testsuite/96147 - align vector access adds dc8475e3348 Pytest in tests: improve adds 446703ccc2c tree-optimization/96376 - do not check alignment for invari [...] adds f1d054017ef Revert "arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 [...] adds 63999d751df arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds f9a577927eb IBM Z: Fix linking to libatomic in target test cases adds 7f6cdaa9a8d rtl-ssa: Fix a silly typo adds f2cc526f47a recog: Fix insn_change_watermark destructor adds 5a783f42d77 aarch64: Add a minipass for fusing CC insns [PR88836] adds 492b90f33df c++: Fix langspecs with -fsyntax-only [PR98591] adds 1ba71fabb78 preprocessor: Make quoting : [PR 95253] adds 7d0df0aeb67 i386: Use cpp_define_formatted for __SIZEOF_FLOAT80__ definition adds d3959070aa4 [PATCH] aarch64: Implement vmlsl[_high]* intrinsics using builtins adds 50dbced2f37 openmp: Change the way of building of reduction array type adds adb520606ce c-family: Improve MEM_REF printing for diagnostics [PR98597] adds a3128bf0128 bootstrap: fix failing diagnostic selftest on Windows [PR98696] adds aaec739250b testsuite: Add testcase coverage for already fixed [PR96671] adds c0194736b47 gcc.dg/analyzer tests: use __builtin_alloca, not alloca.h adds cd09079cfd5 c++: Fix list-init of array of no-copy type [PR63707] adds ad260343385 AArch64: Add NEON, SVE and SVE2 RTL patterns for Multiply, [...] adds 424deca72b6 c++: Fix copy elision for base initialization adds d75199f7823 c++: Avoid redundant copy in {} init [PR98642] adds e63c2161d09 drop -dumpbase-ext from producer string adds 5c046034e3e match.pd: Optimize (x < 0) ^ (y < 0) to (x ^ y) < 0 etc. [PR96681] adds 0425f4c1b63 match.pd: Generalize the PR64309 simplifications [PR96669] adds e1efa6af61a preprocessor: Make quoting : [PR 95253] adds 9beb6d88eff c++: Fix qualified array-type construction [PR 98538] No new revisions were added by this update. Summary of changes: contrib/ChangeLog | 4 + gcc/ChangeLog | 214 +++++++ gcc/DATESTAMP | 2 +- gcc/Makefile.in | 7 + gcc/ada/ChangeLog | 6 + gcc/analyzer/ChangeLog | 22 + gcc/c-family/c-pretty-print.c | 259 +++++++-- gcc/c/c-typeck.c | 4 +- gcc/config.gcc | 2 +- gcc/config/aarch64/aarch64-cc-fusion.cc | 296 ++++++++++ gcc/config/aarch64/aarch64-passes.def | 1 + gcc/config/aarch64/aarch64-protos.h | 1 + gcc/config/aarch64/aarch64-simd-builtins.def | 8 + gcc/config/aarch64/aarch64-simd.md | 56 +- gcc/config/aarch64/aarch64-sve.md | 56 ++ gcc/config/aarch64/aarch64-sve2.md | 42 ++ gcc/config/aarch64/arm_neon.h | 84 +-- gcc/config/aarch64/iterators.md | 109 +++- gcc/config/aarch64/t-aarch64 | 6 + gcc/config/arm/arm_neon.h | 31 + gcc/config/arm/mve.md | 47 +- gcc/config/arm/neon.md | 53 -- gcc/config/arm/vec-common.md | 58 ++ gcc/config/i386/i386-c.c | 9 +- gcc/cp/ChangeLog | 10 + gcc/cp/call.c | 145 ++++- gcc/cp/cp-tree.h | 3 +- gcc/cp/lang-specs.h | 40 +- gcc/cp/tree.c | 18 +- gcc/cp/typeck2.c | 44 +- gcc/diagnostic.c | 189 ++++++- gcc/diagnostic.h | 23 +- gcc/doc/install.texi | 2 +- gcc/doc/invoke.texi | 19 + gcc/doc/sourcebuild.texi | 4 + gcc/fortran/ChangeLog | 29 + gcc/go/Make-lang.in | 1 + gcc/go/gofrontend/MERGE | 2 +- gcc/go/gofrontend/embed.cc | 628 +++++++++++++++++++++ gcc/go/gofrontend/gogo.h | 4 + gcc/jit/ChangeLog | 6 + gcc/jit/docs/_build/texinfo/libgccjit.texi | 10 +- gcc/jit/docs/cp/index.rst | 4 - gcc/jit/docs/index.rst | 4 - gcc/match.pd | 39 +- gcc/opts.c | 5 +- gcc/recog.h | 8 +- gcc/rtl-ssa/functions.h | 2 +- gcc/rtl-ssa/member-fns.inl | 2 +- gcc/testsuite/ChangeLog | 126 +++++ gcc/testsuite/g++.dg/cpp0x/initlist-array13.C | 16 + gcc/testsuite/g++.dg/cpp1z/elide4.C | 24 + gcc/testsuite/g++.dg/cpp1z/elide5.C | 15 + gcc/testsuite/g++.dg/modules/dep-1_a.C | 4 +- gcc/testsuite/g++.dg/modules/dep-1_b.C | 4 +- gcc/testsuite/g++.dg/modules/dep-2.C | 6 +- gcc/testsuite/g++.dg/modules/pr98591.H | 3 + gcc/testsuite/g++.dg/template/pr98538.C | 18 + gcc/testsuite/gcc.dg/analyzer/alloca-leak.c | 4 +- gcc/testsuite/gcc.dg/analyzer/data-model-1.c | 5 +- gcc/testsuite/gcc.dg/analyzer/malloc-1.c | 3 +- gcc/testsuite/gcc.dg/analyzer/malloc-paths-8.c | 7 +- ...w-locus-GCC_EXTRA_DIAGNOSTIC_OUTPUT-fixits-v1.c | 71 +++ ...w-locus-GCC_EXTRA_DIAGNOSTIC_OUTPUT-fixits-v2.c | 71 +++ gcc/testsuite/gcc.dg/plugin/plugin.exp | 2 + gcc/testsuite/gcc.dg/tree-ssa/pr96669-1.c | 59 ++ gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c | 51 ++ gcc/testsuite/gcc.dg/tree-ssa/pr96671-2.c | 51 ++ gcc/testsuite/gcc.dg/tree-ssa/pr96681.c | 35 ++ gcc/testsuite/gcc.dg/uninit-38.c | 80 +-- gcc/testsuite/gcc.dg/uninit-40.c | 50 ++ gcc/testsuite/gcc.dg/vect/bb-slp-32.c | 1 + gcc/testsuite/gcc.dg/vect/bb-slp-9.c | 2 +- gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c | 20 - gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c | 15 + .../gcc.dg/vect/complex/complex-mla-template.c | 28 +- .../gcc.dg/vect/complex/complex-mls-template.c | 28 +- gcc/testsuite/gcc.dg/vect/slp-43.c | 4 +- gcc/testsuite/gcc.dg/vect/slp-45.c | 2 +- .../aarch64/advsimd-intrinsics/p64_p128.c | 46 +- .../gcc.target/aarch64/sve/acle/general/ldff1_8.c | 32 ++ gcc/testsuite/gcc.target/aarch64/sve/ptest_1.c | 10 + gcc/testsuite/gcc.target/arm/simd/mve-vshl.c | 62 ++ gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 59 ++ gcc/testsuite/gcc.target/arm/simd/vceqz_p64.c | 17 + gcc/testsuite/gcc.target/arm/simd/vceqzq_p64.c | 17 + .../gcc.target/s390/md/atomic_exchange-1.c | 2 +- gcc/testsuite/gcc.target/s390/s390.exp | 4 + gcc/testsuite/lib/gcov.exp | 31 +- gcc/tree-vect-slp.c | 11 +- gcc/tree-vect-stmts.c | 23 +- libatomic/configure.tgt | 56 +- libcpp/mkdeps.c | 1 - libgomp/ChangeLog | 9 + libgomp/configure.tgt | 35 +- libitm/configure.tgt | 37 +- libstdc++-v3/ChangeLog | 51 ++ .../testsuite/23_containers/deque/debug/98466.cc | 8 +- 98 files changed, 3413 insertions(+), 521 deletions(-) create mode 100644 gcc/config/aarch64/aarch64-cc-fusion.cc create mode 100644 gcc/go/gofrontend/embed.cc create mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist-array13.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/elide4.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/elide5.C create mode 100644 gcc/testsuite/g++.dg/modules/pr98591.H create mode 100644 gcc/testsuite/g++.dg/template/pr98538.C create mode 100644 gcc/testsuite/gcc.dg/plugin/diagnostic-test-show-locus-GCC_EXTR [...] create mode 100644 gcc/testsuite/gcc.dg/plugin/diagnostic-test-show-locus-GCC_EXTR [...] create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96669-1.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96671-2.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96681.c create mode 100644 gcc/testsuite/gcc.dg/uninit-40.c delete mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/ldff1_8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/ptest_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vshl.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vshr.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vceqz_p64.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vceqzq_p64.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig updated (c14dee84dd -> 5a11fff005)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig in repository toolchain/ci/binutils-gdb. from c14dee84dd Update my email address (long overdue!) adds 17e8913732 Add myself to gdb/MAINTAINERS adds 5aa06b1b14 Automatic date update in version.in adds 5fda40b28f gas: make [248]byte directives available everywhere adds 3624a6c15c PR26539, memory leak in inflate.c adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status adds 7cf91a2481 sim: m32r: clean up redundant test coverage adds 89bfc2a429 sim: frv: clean up redundant test coverage adds 137d6efd8a sim: mips: delete empty stub test dir adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness adds bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 adds 5a11fff005 gdb/tui: compare pointer to nullptr, not 0 No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 20 + bfd/elfnn-riscv.c | 319 +- bfd/elfxx-riscv.c | 54 +- bfd/elfxx-riscv.h | 4 +- bfd/version.h | 2 +- binutils/ChangeLog | 5 + binutils/readelf.c | 6 +- gas/ChangeLog | 30 + gas/config/obj-elf.c | 4 - gas/config/tc-riscv.c | 521 ++-- gas/config/tc-riscv.h | 6 +- gas/doc/as.texi | 7 - gas/read.c | 3 + gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +- .../gas/riscv/priv-reg-fail-read-only-01.l | 136 +- .../gas/riscv/priv-reg-fail-read-only-02.l | 48 +- gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +- .../gas/riscv/priv-reg-fail-version-1p10.l | 48 +- .../gas/riscv/priv-reg-fail-version-1p11.l | 46 +- .../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +- gdb/ChangeLog | 8 + gdb/MAINTAINERS | 1 + gdb/testsuite/ChangeLog | 6 + gdb/testsuite/gdb.fortran/array-slices.exp | 2 +- gdb/tui/tui.c | 4 +- include/ChangeLog | 11 + include/elf/riscv.h | 3 +- include/opcode/riscv-opc.h | 16 +- include/opcode/riscv.h | 127 +- ld/ChangeLog | 9 + .../ld-riscv-elf/attr-merge-priv-spec-failed-01.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-02.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-03.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-04.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-05.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-06.d | 4 +- opcodes/ChangeLog | 16 + opcodes/riscv-dis.c | 30 +- opcodes/riscv-opc.c | 1456 +++++---- sim/ChangeLog | 7 + sim/configure | 16 +- sim/configure.ac | 16 +- sim/testsuite/ChangeLog | 36 + sim/testsuite/Makefile.in | 8 +- sim/testsuite/configure | 3264 -------------------- sim/testsuite/configure.ac | 32 - sim/testsuite/d10v-elf/Makefile.in | 180 -- sim/testsuite/d10v-elf/configure | 2984 ------------------ sim/testsuite/d10v-elf/configure.ac | 18 - sim/testsuite/d10v-elf/exit47.s | 4 - sim/testsuite/d10v-elf/loop.s | 6 - sim/testsuite/frv-elf/ChangeLog | 48 - sim/testsuite/frv-elf/Makefile.in | 158 - sim/testsuite/frv-elf/configure | 2984 ------------------ sim/testsuite/frv-elf/configure.ac | 18 - sim/testsuite/frv-elf/loop.s | 2 - sim/testsuite/lib/sim-defs.exp | 23 +- sim/testsuite/m32r-elf/ChangeLog | 18 - sim/testsuite/m32r-elf/Makefile.in | 156 - sim/testsuite/m32r-elf/configure | 2984 ------------------ sim/testsuite/m32r-elf/configure.ac | 18 - sim/testsuite/m32r-elf/hello.s | 17 - sim/testsuite/m32r-elf/loop.s | 2 - sim/testsuite/mips64el-elf/ChangeLog | 19 - sim/testsuite/mips64el-elf/Makefile.in | 170 - sim/testsuite/mips64el-elf/configure | 2984 ------------------ sim/testsuite/mips64el-elf/configure.ac | 18 - sim/testsuite/sim/cris/ChangeLog | 7 + sim/testsuite/sim/cris/c/c.exp | 7 +- sim/testsuite/sim/cris/hw/rv-n-cris/rvc.exp | 2 +- sim/testsuite/{d10v-elf => sim/d10v}/ChangeLog | 5 + sim/testsuite/sim/d10v/allinsn.exp | 17 + .../{d10v-elf/t-trap.s => sim/d10v/exit47.s} | 5 +- sim/testsuite/{d10v-elf => sim/d10v}/hello.s | 3 + sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-i.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-id.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-im.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-ip.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-i.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-ld2w-id.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-ld2w-im.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-ld2w-ip.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-i.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-id.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-im.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-ip.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-is.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-d.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-i.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-id.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-im.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-ip.s | 6 +- .../{d10v-elf => sim/d10v}/t-ae-st2w-is.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-dbt.s | 7 +- sim/testsuite/{d10v-elf => sim/d10v}/t-ld-st.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-mac.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-macros.i | 12 +- .../{d10v-elf => sim/d10v}/t-mod-ld-pre.s | 56 +- sim/testsuite/{d10v-elf => sim/d10v}/t-msbu.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-mulxu.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-mvtac.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-mvtc.s | 9 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rac.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-rachi.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-rdt.s | 7 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rep.s | 8 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rie-xx.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-rte.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-sac.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sachi.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sadd.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-slae.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sp.s | 6 +- sim/testsuite/{d10v-elf => sim/d10v}/t-sub.s | 4 + sim/testsuite/{d10v-elf => sim/d10v}/t-sub2w.s | 16 +- sim/testsuite/{d10v-elf => sim/d10v}/t-subi.s | 4 + sim/testsuite/sim/d10v/t-trap.s | 10 + sim/testsuite/sim/frv/ChangeLog | 6 + .../{frv-elf/cache.s => sim/frv/cache.ms} | 6 +- .../{frv-elf/exit47.s => sim/frv/exit47.ms} | 6 + .../{frv-elf/grloop.s => sim/frv/grloop.ms} | 3 + .../{frv-elf/hello.s => sim/frv/hello.ms} | 3 + sim/testsuite/sim/frv/misc.exp | 19 + sim/testsuite/sim/m32r/ChangeLog | 4 + .../{m32r-elf/exit47.s => sim/m32r/exit47.ms} | 4 + 128 files changed, 2031 insertions(+), 17755 deletions(-) delete mode 100755 sim/testsuite/configure delete mode 100644 sim/testsuite/configure.ac delete mode 100644 sim/testsuite/d10v-elf/Makefile.in delete mode 100755 sim/testsuite/d10v-elf/configure delete mode 100644 sim/testsuite/d10v-elf/configure.ac delete mode 100644 sim/testsuite/d10v-elf/exit47.s delete mode 100644 sim/testsuite/d10v-elf/loop.s delete mode 100644 sim/testsuite/frv-elf/ChangeLog delete mode 100644 sim/testsuite/frv-elf/Makefile.in delete mode 100755 sim/testsuite/frv-elf/configure delete mode 100644 sim/testsuite/frv-elf/configure.ac delete mode 100644 sim/testsuite/frv-elf/loop.s delete mode 100644 sim/testsuite/m32r-elf/ChangeLog delete mode 100644 sim/testsuite/m32r-elf/Makefile.in delete mode 100755 sim/testsuite/m32r-elf/configure delete mode 100644 sim/testsuite/m32r-elf/configure.ac delete mode 100644 sim/testsuite/m32r-elf/hello.s delete mode 100644 sim/testsuite/m32r-elf/loop.s delete mode 100644 sim/testsuite/mips64el-elf/ChangeLog delete mode 100644 sim/testsuite/mips64el-elf/Makefile.in delete mode 100755 sim/testsuite/mips64el-elf/configure delete mode 100644 sim/testsuite/mips64el-elf/configure.ac rename sim/testsuite/{d10v-elf => sim/d10v}/ChangeLog (96%) create mode 100644 sim/testsuite/sim/d10v/allinsn.exp rename sim/testsuite/{d10v-elf/t-trap.s => sim/d10v/exit47.s} (52%) rename sim/testsuite/{d10v-elf => sim/d10v}/hello.s (54%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-d.s (76%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-i.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-id.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-im.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld-ip.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-d.s (77%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-i.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-id.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-im.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-ld2w-ip.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-d.s (76%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-i.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-id.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-im.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-ip.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st-is.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-d.s (77%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-i.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-id.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-im.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-ip.s (80%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ae-st2w-is.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-dbt.s (88%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-ld-st.s (88%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mac.s (95%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-macros.i (97%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mod-ld-pre.s (90%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-msbu.s (87%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mulxu.s (87%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mvtac.s (84%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-mvtc.s (95%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rac.s (82%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rachi.s (87%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rdt.s (75%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rep.s (90%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rie-xx.s (79%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-rte.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sac.s (85%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sachi.s (83%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sadd.s (92%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-slae.s (92%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sp.s (78%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sub.s (92%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-sub2w.s (93%) rename sim/testsuite/{d10v-elf => sim/d10v}/t-subi.s (92%) create mode 100644 sim/testsuite/sim/d10v/t-trap.s rename sim/testsuite/{frv-elf/cache.s => sim/frv/cache.ms} (95%) rename sim/testsuite/{frv-elf/exit47.s => sim/frv/exit47.ms} (50%) rename sim/testsuite/{frv-elf/grloop.s => sim/frv/grloop.ms} (86%) rename sim/testsuite/{frv-elf/hello.s => sim/frv/hello.ms} (86%) create mode 100644 sim/testsuite/sim/frv/misc.exp rename sim/testsuite/{m32r-elf/exit47.s => sim/m32r/exit47.ms} (66%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig updated (3a266628 -> 45061ef1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig in repository toolchain/ci/base-artifacts. discards 3a266628 0: update: binutils-gcc-linux-qemu: boot new 45061ef1 0: update: binutils-gcc-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (3a266628) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-lt [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 181 +- 02-prepare_abe/console.log | 444 +- 03-build_abe-binutils/console.log | 11838 ++++----- 04-build_abe-stage1/console.log | 20807 ++++++++------- 05-build_linux/console.log | 822 +- 06-build_abe-qemu/console.log | 6797 +++-- 07-boot_linux/console.log | 492 +- 08-check_regression/console.log | 2 +- 08-check_regression/results.regressions | 2 +- 09-update_baseline/console.log | 10 +- 09-update_baseline/results.regressions | 2 +- console.log | 41413 +++++++++++++++--------------- jenkins/manifest.sh | 16 +- 13 files changed, 41372 insertions(+), 41454 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

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Tcwg-commits January 2021