Tcwg-commits January 2021

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Oz_LTO updated (a7d007a6 -> ef257763)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/llvm-master-arm-spec2k6-Oz_LTO in repository toolchain/ci/base-artifacts. from a7d007a6 1: reset: gcc-3e8fb15a8cfd0e62dd474af9f536863392ed7572: 1 new ef257763 2: reset: gcc-3c57e692357c79ee7623dfc1586652aee2aefb8f: 1 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 243 +- 02-prepare_abe/console.log | 356 +- 03-build_abe-binutils/console.log | 10835 +- 04-build_abe-stage1/console.log | 20315 ++-- 05-build_abe-linux/console.log | 2000 +- 06-build_abe-glibc/console.log | 39019 +++---- 07-build_abe-stage2/console.log | 40544 +++---- 08-build_llvm-true/console.log | 13401 ++- 10-benchmark--Oz_LTO_mthumb/benchmark-start.log | 2 +- 10-benchmark--Oz_LTO_mthumb/benchmark.log | 82 +- 10-benchmark--Oz_LTO_mthumb/console.log | 323 +- 11-check_regression/console.log | 910 +- 11-check_regression/extra-bisect-params | 2 +- 11-check_regression/results-0.csv | 147 +- 11-check_regression/results-1.csv | 151 +- 11-check_regression/results-brief.csv | 38 +- 11-check_regression/results-compare.csv | 10 +- 11-check_regression/results-full.csv | 153 +- 11-check_regression/results.csv | 46 +- 11-check_regression/results.log | 3128 +- 11-check_regression/results.regressions | 5 +- 11-check_regression/trigger-bisect | 4 +- 12-update_baseline/console.log | 780 +- 12-update_baseline/extra-bisect-params | 2 +- 12-update_baseline/results-0.csv | 147 +- 12-update_baseline/results-1.csv | 151 +- 12-update_baseline/results-brief.csv | 38 +- 12-update_baseline/results-compare.csv | 10 +- 12-update_baseline/results-full.csv | 153 +- 12-update_baseline/results.csv | 46 +- 12-update_baseline/results.log | 3180 +- 12-update_baseline/results.regressions | 5 +- console.log | 128728 +++++++++++---------- jenkins/manifest.sh | 12 +- results | 7 +- results_id | 2 +- 36 files changed, 132886 insertions(+), 132089 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[binutils-gdb] branch master updated (1368b914e93 -> ad92f33d386)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 1368b914e93 sim: testsuite: flatten tree new eb6e6af8c17 PR26002 undefined symbol VER_NDX_GLOBAL vs. VER_NDX_LOCAL new ad92f33d386 Tidy inflateEnd calls The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: bfd/ChangeLog | 10 ++++++++++ bfd/compress.c | 3 +-- bfd/elflink.c | 2 +- binutils/ChangeLog | 4 ++++ binutils/readelf.c | 4 ++-- ld/ChangeLog | 7 +++++++ ld/testsuite/ld-elfvers/vers16.dsym | 2 +- ld/testsuite/ld-elfvers/vers6.dsym | 2 +- 8 files changed, 27 insertions(+), 7 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-defconfig updated (bc054afb -> 92becb00)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-defconfig in repository toolchain/ci/base-artifacts. discards bc054afb 2: update: llvm-7dc3575ef2dc85d92aa3ad916d0eb73a0aa088c9: 19 new 92becb00 2: update: qemu-7cb6b97300f0405b4c6856c49bdc33fa3265852f: 19 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (bc054afb) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 181 +- 02-prepare_abe/console.log | 438 +- 03-build_llvm/console.log | 13677 ++++++++++++++------------- 04-build_linux/console.log | 400 +- 07-check_regression/console.log | 2 +- 07-check_regression/results.regressions | 6 +- 08-update_baseline/console.log | 104 +- 08-update_baseline/results.regressions | 6 +- console.log | 14802 +++++++++++++++--------------- jenkins/manifest.sh | 8 +- 10 files changed, 14658 insertions(+), 14966 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-defconfig updated (752fafda3db -> 7dc3575ef2d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-defconfig in repository toolchain/ci/llvm-project. from 752fafda3db [NFC] Fix -Wsometimes-uninitialized adds 260a856c2ab ADT: Fix reference invalidation in SmallVector::resize adds c224a834583 ADT: Reduce code duplication in SmallVector::resize by usin [...] adds 3f98b66f23f ADT: Reduce code duplication in SmallVector by reusing rese [...] adds 53b34601abf [Driver] -gsplit-dwarf: Produce .dwo regardless of -gN for [...] adds 6ed3083a965 ADT: Reduce code duplication in SmallVector by calling rese [...] adds ff5e8964255 Fix unused variable in CoroFrame.cpp when building Release [...] adds 885eae9d85d Add func call so we don't instruction-step into the builtin_trap adds 7ad54d19387 [lldb][wasm] Parse DWO section names adds 2bbf724feea Implement vAttachWait in lldb-server adds ed205f63b4a [mlir] Update doc to omit the usage of LLVMIntegerType adds 4b284b9ca80 [lldb] Fix TestPlatformProcessConnect.py adds 259936f4910 [NFC][AsmPrinter] Windows warning: Use explicit cast adds 2b1e25befef [AArch64] Adding ACLE intrinsics for the LS64 extension adds 4bb11b3eafb [LTO] Expose opt() in LTOBackend (NFC). adds 53e3b81faaf [lld][WebAssembly] Add support for handling table symbols adds d58512b2e31 [SLP] Don't vectorize stores of non-packed types (like i1, i2) adds 17f8c458de6 [clang] Use SourceLocations in unions [NFCI] adds af8d27a7a82 [DAG] visitVECTOR_SHUFFLE - pull out shuffle merging code i [...] adds 8f1d7f3753c [X86] Improve sum-of-reductions v4f32 test coverage adds a997a1d7fbe [lldb/test] Ensure launched processes are ready to be attached adds 7c30c05ff71 [DAG] visitVECTOR_SHUFFLE - MergeInnerShuffle - reset shuff [...] adds 2e25be0b613 [clangd] Add main file macros into the main-file index. adds 19297a41711 Change XCore code owner. adds 3bccd87a588 [clang][cli] NFC: Remove SSPBufferSize assignment adds fa2fe9608c1 [clang][cli] Port more CodeGenOptions to marshalling infras [...] adds 6abbba3fca9 Revert "Fix llvm::Optional build breaks in MSVC using std:: [...] adds 176f5e95e1a [clang-tidy] Use DenseSet<SourceLocation> in UpgradeDuratio [...] adds a1bbd1ef1db [flang][driver] Unify f18_version.h.in and Version.inc.in adds c23e34e606b [InferFunctionAttrs] Improve CHECK variable names (NFC). adds a1cba5b7a1f [SelectionDAG] Make use of KnownBits::commonBits. NFC. adds 517196e5691 [Analysis,CodeGen] Make use of KnownBits::makeConstant. NFC. adds 90b310f6caf [Support] Simplify KnownBits::icmp helpers. NFC. adds e8622d27c0e [Support] Add KnownBits::sextInReg exhaustive tests adds 332e220ef42 [docs] Update DebuggingJITedCode page after fix in LLDB adds 0b46f19a9ec [Support] Ensure KnownBits::sextInReg can handle the src == [...] adds 3e41ab18db2 [flang] Fix dangling pointer in LabelEnforce adds adb77a74569 [OpenCL] Improve online documentation. adds 6b9fa8a50d0 [mlir][linalg] Add docstring support for named op spec adds c0939fddf80 [Support] Simplify KnownBits::sextInReg implementation. adds a022be62538 [TableGen] Enhance !cast<string> to handle bit and bits types. adds dbaa6a1858a Revert "[AArch64] Attempt to sink mul operands" adds d0dbb0468c2 [Support] Remove redundant sign bit tests from KnownBits::g [...] adds 0a59647ee40 [SystemZ] misched-cutoff tests can only be tested on non-ND [...] adds 17fb21f875f [clangd] Remove another option that was effectively always [...] adds 7c9c2a2ea5e Revert "[RISCV] Legalize select when Zbt extension available" adds 0afdbb4d2de [flang][driver] Use __FLANG_VERISION__ in f18.cpp (nfc) adds e21bf875c0f [NFC] Disallow unused prefixes under MC/ARM adds 2f395b7092b [clangd] Make AST-based signals available to runWithPreamble. adds 8b09cf7956d [clangd] Trivial: Documentation fix in ASTSignals. adds b4e083b0ef7 [gn build] Port 2f395b7092bd adds 4864d9f7e91 [flang] Fix some module file issues exposed by Whizard adds 35c8a6cbf5f [NFC] Disallow unused prefixes under MC/AArch64 adds a03ffa98503 [NewPM] Fix placement of LoopFlatten adds b99782cf785 [X86][AVX] Adjust unsigned saturation downconvert negative test adds 5d165f0b893 [libomptarget][amdgpu] Fix kernel launch tracing to match p [...] adds 868da2ea939 [SelectionDAG] Remove an early-out from computeKnownBits fo [...] adds 85dfcaadc5f [LLDB] MinidumpParser: Prefer executable module even at hig [...] adds be40c12040a [HIP] Add signbit(long double) decl adds 6ebeba88f51 Support emptiness checks for unbounded FlatAffineConstraints. adds 763c1f99334 [OpenMP] Drop the static library libomptarget-nvptx adds 4fffbc150cc [clang][MSVC] Fix missing MSInheritanceAttr in template spe [...] adds 202d359753d [X86] Add the FSRM feature (Fast Short Rep Mov) to Zen3. adds 64e9e9aeee0 [OpenMP] Dropped unnecessary define when compiling deviceRT [...] adds a8520f6970f [GWP-ASan] Minor refactor of optional components. adds ca98baa0425 [openacc] Rename generated file from ACC.cpp.inc to ACC.inc [...] adds 9e53c94d8dd [NFC] Update test to not check for 'opaque' in the file name. adds 1d973b7ded1 [MLIR][TOSA] First lowerings from Tosa to Linalg adds d8113cda782 Add newline to terminate debug message (NFC) adds a3904cc77f1 [BasicAA] Handle recursive queries more efficiently adds 00a61b327dd [mlir][ODS] Add new RangedTypesMatchWith operation predicate adds 93592b726c7 [mlir][OpFormatGen] Format enum attribute cases as keywords [...] adds e3b9af92a48 [Driver] -gsplit-dwarf: Produce .dwo regardless of -gN for [...] adds 387d3c24792 [RISCV] Merge Utils library into MCTargetDesc adds c8fb6ee3415 [mlir][PatternRewriter] Add a new hook to selectively repla [...] adds 5cf2696317a [mlir] Remove TosaToLinalg dependency on all Passes adds a71877edfbb [clang] Do not crash when CXXRecordDecl has a non-CXXRecord [...] adds e2d7d3cb0ea [mlir][docs] Bring bufferization docs up to date. adds 0f588ac03e1 [PowerPC] Only use some extend mne if assembler is modern enough adds 0975604cc01 [gn build] (manually) port 387d3c24792f adds e7228062b2b [libc] Use #undef isascii in specific header adds f85b1531666 Add -fexceptions to test as it uses them and fails on platf [...] adds b894a9fb237 [RISCV] Optimize select_cc after fp compare expansion adds 4fcb25583c3 Re-land [Support] On Windows, take the affinity mask into account adds 5b42fd8dd4e [LTO] Test format fix (NFC) adds 8a53a7375a8 [RISCV][NFC] Regenerate Calling Convention Tests adds a55a0a3056b [mlir] Remove over specified memory effects adds 4183999e0fe [clangd] Reduce logspam for CDB scanning adds 722ae10907e [mlir][Linalg] Add canonicalization to remove no-op linalg [...] adds b21905dfe37 [SLP] remove unnecessary state in matching reductions adds 547b032ccc8 [OpenMP] Remove omptarget-nvptx from deps as it is no longe [...] adds 774c9c6ef3a [mlir][Linalg] Add canonicalization of linalg op -> dim op. adds 42444d0cf0c [mlir][Linalg] NFC: Verify tiling on linalg.generic operati [...] adds 6e7094c14b2 [libomptarget][nvptx][nfc] Move target_impl functions out o [...] adds d6acf3c2012 [flang] Fix use-associated procedure in generic adds 036bc798f2a [AArch64][GlobalISel] Assign FPR banks to loads which are u [...] adds 9dfeec85300 Reland "[AsmParser] make .ascii support spaces as separators" adds 214387c2c69 [libomptarget][nvptx] Reduce calls to cuda header adds 1fabe6e5191 [libTooling] Change `addInclude` to use expansion locs. adds 8f283cafddf [AArch64][GlobalISel] Add selection support for fpr bank so [...] adds 2423ec58376 [libc] Add memmove implementation. adds 9bcc0d1040d [CodeGen, Transforms] Use llvm::sort (NFC) adds 2efcbe24a75 [llvm] Use llvm::drop_begin (NFC) adds 7dc3575ef2d [llvm] Remove redundant return and continue statements (NFC) No new revisions were added by this update. Summary of changes: .../abseil/UpgradeDurationConversionsCheck.cpp | 4 +- .../abseil/UpgradeDurationConversionsCheck.h | 5 +- clang-tools-extra/clangd/ASTSignals.cpp | 42 + clang-tools-extra/clangd/ASTSignals.h | 39 + clang-tools-extra/clangd/CMakeLists.txt | 1 + clang-tools-extra/clangd/ClangdServer.cpp | 14 +- clang-tools-extra/clangd/CodeComplete.h | 10 - clang-tools-extra/clangd/CollectMacros.cpp | 8 +- clang-tools-extra/clangd/CollectMacros.h | 18 +- .../clangd/GlobalCompilationDatabase.cpp | 2 +- clang-tools-extra/clangd/SemanticHighlighting.cpp | 4 +- clang-tools-extra/clangd/TUScheduler.cpp | 73 +- clang-tools-extra/clangd/TUScheduler.h | 3 + clang-tools-extra/clangd/XRefs.cpp | 2 +- clang-tools-extra/clangd/index/SymbolCollector.cpp | 21 +- clang-tools-extra/clangd/tool/ClangdMain.cpp | 1 - .../clangd/unittests/ASTSignalsTests.cpp | 75 ++ clang-tools-extra/clangd/unittests/CMakeLists.txt | 1 + .../clangd/unittests/CodeCompleteTests.cpp | 1 - .../clangd/unittests/CollectMacrosTests.cpp | 12 +- .../clangd/unittests/FindSymbolsTests.cpp | 12 +- .../clangd/unittests/ParsedASTTests.cpp | 4 +- .../clangd/unittests/TUSchedulerTests.cpp | 47 +- .../readability-function-cognitive-complexity.cpp | 2 +- clang/docs/OpenCLSupport.rst | 90 +- clang/docs/UsersManual.rst | 157 ++- clang/include/clang/AST/DependentDiagnostic.h | 6 +- clang/include/clang/AST/Expr.h | 39 +- clang/include/clang/AST/TemplateBase.h | 8 +- clang/include/clang/Basic/BuiltinsAArch64.def | 6 + clang/include/clang/Basic/SourceManager.h | 33 +- clang/include/clang/Driver/Options.td | 57 +- clang/include/clang/Sema/DeclSpec.h | 83 +- clang/include/clang/Sema/Designator.h | 49 +- clang/include/clang/Sema/Initialization.h | 18 +- .../clang/Tooling/Transformer/RewriteRule.h | 10 +- clang/lib/AST/Expr.cpp | 12 +- clang/lib/AST/TemplateBase.cpp | 4 +- clang/lib/Basic/Targets/AArch64.cpp | 3 + clang/lib/CodeGen/CGBuiltin.cpp | 40 + clang/lib/Driver/ToolChains/Clang.cpp | 18 +- clang/lib/Frontend/CompilerInvocation.cpp | 42 - .../Headers/__clang_cuda_math_forward_declares.h | 3 + clang/lib/Headers/arm_acle.h | 26 + clang/lib/Parse/ParseDeclCXX.cpp | 4 +- clang/lib/Sema/DeclSpec.cpp | 20 +- clang/lib/Sema/SemaDecl.cpp | 4 +- clang/lib/Sema/SemaDeclCXX.cpp | 3 +- clang/lib/Sema/SemaExpr.cpp | 3 +- clang/lib/Sema/SemaTemplate.cpp | 5 + clang/lib/Sema/SemaType.cpp | 14 +- clang/lib/Tooling/Transformer/RewriteRule.cpp | 7 +- clang/test/CodeGen/aarch64-ls64.c | 163 +++ clang/test/CodeGen/incomplete-function-type.c | 1 + .../CodeGenCXX/microsoft-abi-member-pointers.cpp | 10 + clang/test/Driver/split-debug.c | 9 + clang/test/Preprocessor/aarch64-target-features.c | 6 + clang/test/SemaTemplate/temp_class_spec.cpp | 14 + compiler-rt/lib/gwp_asan/optional/backtrace.h | 48 +- .../lib/gwp_asan/optional/backtrace_fuchsia.cpp | 11 +- .../lib/gwp_asan/optional/backtrace_linux_libc.cpp | 17 +- .../optional/backtrace_sanitizer_common.cpp | 16 +- compiler-rt/lib/gwp_asan/optional/printf.h | 33 + compiler-rt/lib/gwp_asan/optional/segv_handler.h | 71 +- .../lib/gwp_asan/optional/segv_handler_fuchsia.cpp | 8 +- .../lib/gwp_asan/optional/segv_handler_posix.cpp | 173 ++- compiler-rt/lib/gwp_asan/tests/CMakeLists.txt | 2 +- compiler-rt/lib/gwp_asan/tests/harness.h | 13 +- .../printf_sanitizer_common.cpp | 15 +- compiler-rt/lib/scudo/scudo_allocator.cpp | 8 +- compiler-rt/lib/scudo/standalone/combined.h | 11 +- flang/CMakeLists.txt | 4 - flang/include/flang/Parser/dump-parse-tree.h | 2 +- flang/include/flang/Parser/parse-tree.h | 4 +- flang/include/flang/Version.inc.in | 3 + flang/lib/Parser/unparse.cpp | 2 +- flang/lib/Semantics/check-acc-structure.h | 4 +- flang/lib/Semantics/check-directive-structure.h | 4 +- flang/lib/Semantics/mod-file.cpp | 79 +- flang/lib/Semantics/resolve-names.cpp | 27 +- flang/test/Semantics/modfile07.f90 | 26 + flang/test/Semantics/modfile35.f90 | 6 +- flang/test/Semantics/modfile37.f90 | 32 + flang/test/Semantics/modfile38.f90 | 35 + flang/test/Semantics/resolve53.f90 | 4 +- flang/tools/f18/CMakeLists.txt | 2 - flang/tools/f18/f18.cpp | 15 +- flang/tools/f18/f18_version.h.in | 9 - libc/config/linux/aarch64/entrypoints.txt | 1 + libc/config/linux/x86_64/entrypoints.txt | 1 + libc/src/ctype/isascii.h | 2 + libc/src/string/CMakeLists.txt | 12 + libc/src/string/memmove.cpp | 61 + libc/src/{ctype/isascii.h => string/memmove.h} | 12 +- libc/test/src/ctype/isascii_test.cpp | 4 +- libc/test/src/string/CMakeLists.txt | 11 + libc/test/src/string/memmove_test.cpp | 70 + libc/utils/UnitTest/FuchsiaTest.h | 6 - lld/include/lld/Common/LLVM.h | 6 + lld/test/ELF/lto/devirt_vcall_vis_public.ll | 36 +- lld/wasm/InputChunks.cpp | 4 + lld/wasm/InputFiles.cpp | 32 +- lld/wasm/InputFiles.h | 3 + lld/wasm/InputTable.h | 60 + lld/wasm/MarkLive.cpp | 4 + lld/wasm/SymbolTable.cpp | 65 + lld/wasm/SymbolTable.h | 7 + lld/wasm/Symbols.cpp | 45 + lld/wasm/Symbols.h | 68 +- lld/wasm/SyntheticSections.cpp | 63 +- lld/wasm/SyntheticSections.h | 26 +- lld/wasm/Writer.cpp | 17 +- lld/wasm/WriterUtils.cpp | 17 +- lld/wasm/WriterUtils.h | 1 + .../Python/lldbsuite/test/lldbplatformutil.py | 14 +- lldb/packages/Python/lldbsuite/test/lldbtest.py | 29 +- .../Plugins/ObjectFile/wasm/ObjectFileWasm.cpp | 61 +- .../gdb-server/PlatformRemoteGDBServer.cpp | 2 +- .../GDBRemoteCommunicationServerLLGS.cpp | 98 ++ .../gdb-remote/GDBRemoteCommunicationServerLLGS.h | 13 + .../GDBRemoteCommunicationServerPlatform.cpp | 2 +- .../Plugins/Process/minidump/MinidumpParser.cpp | 26 +- lldb/test/API/macosx/builtin-debugtrap/main.cpp | 1 + .../tools/lldb-server/TestGdbRemoteAttachWait.py | 75 ++ .../TestPlatformProcessConnect.py | 52 +- .../ObjectFile/wasm/embedded-debug-sections.yaml | 100 ++ .../Process/minidump/MinidumpParserTest.cpp | 41 + llvm/CODE_OWNERS.TXT | 8 +- llvm/docs/DebuggingJITedCode.rst | 201 +-- llvm/include/llvm/ADT/Optional.h | 7 +- llvm/include/llvm/ADT/SmallVector.h | 37 +- llvm/include/llvm/Analysis/BasicAliasAnalysis.h | 7 +- llvm/include/llvm/BinaryFormat/Wasm.h | 4 +- llvm/include/llvm/CodeGen/LiveRegUnits.h | 1 - llvm/include/llvm/Frontend/OpenACC/CMakeLists.txt | 2 +- llvm/include/llvm/IR/IntrinsicsAArch64.td | 8 + llvm/include/llvm/LTO/LTOBackend.h | 6 + llvm/include/llvm/Object/Wasm.h | 5 +- llvm/include/llvm/Support/KnownBits.h | 4 +- llvm/include/llvm/Support/Program.h | 12 +- llvm/lib/Analysis/BasicAliasAnalysis.cpp | 109 +- llvm/lib/Analysis/GlobalsModRef.cpp | 6 +- llvm/lib/Analysis/LazyCallGraph.cpp | 2 +- llvm/lib/Analysis/ModuleSummaryAnalysis.cpp | 2 +- llvm/lib/Analysis/VFABIDemangling.cpp | 6 +- llvm/lib/Analysis/ValueTracking.cpp | 11 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 4 +- .../AsmPrinter/DbgEntityHistoryCalculator.cpp | 2 +- llvm/lib/CodeGen/CodeGenPrepare.cpp | 4 +- llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp | 2 +- llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp | 3 +- .../CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp | 8 +- llvm/lib/CodeGen/MachinePipeliner.cpp | 1 - llvm/lib/CodeGen/RDFLiveness.cpp | 4 +- llvm/lib/CodeGen/RegAllocFast.cpp | 3 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 106 +- .../CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 6 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 10 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 43 +- llvm/lib/Demangle/MicrosoftDemangleNodes.cpp | 1 - llvm/lib/FileCheck/FileCheck.cpp | 1 - llvm/lib/IR/AutoUpgrade.cpp | 1 - llvm/lib/LTO/LTOBackend.cpp | 8 +- llvm/lib/MC/MCParser/AsmParser.cpp | 13 +- llvm/lib/Object/WasmObjectFile.cpp | 7 +- llvm/lib/Passes/PassBuilder.cpp | 6 +- llvm/lib/Passes/StandardInstrumentations.cpp | 1 - llvm/lib/Support/KnownBits.cpp | 43 +- llvm/lib/Support/Program.cpp | 14 +- llvm/lib/Support/Unix/Path.inc | 2 - llvm/lib/Support/Unix/Program.inc | 6 +- llvm/lib/Support/Windows/Program.inc | 18 +- llvm/lib/Support/Windows/Threading.inc | 25 +- llvm/lib/TableGen/Record.cpp | 4 +- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 12 +- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 38 - llvm/lib/Target/AArch64/AArch64InstrGISel.td | 12 + llvm/lib/Target/AArch64/AArch64InstrInfo.td | 10 +- .../AArch64/GISel/AArch64InstructionSelector.cpp | 19 +- .../AArch64/GISel/AArch64RegisterBankInfo.cpp | 14 +- .../AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp | 1 - llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp | 1 - llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp | 1 - llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp | 2 - .../Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp | 2 +- .../PowerPC/MCTargetDesc/PPCMCTargetDesc.cpp | 12 +- llvm/lib/Target/PowerPC/PPC.td | 4 + llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 1 - llvm/lib/Target/PowerPC/PPCInstr64Bit.td | 7 +- llvm/lib/Target/PowerPC/PPCInstrInfo.td | 7 + llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 2 + llvm/lib/Target/PowerPC/PPCSubtarget.h | 2 + llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 7 + llvm/lib/Target/RISCV/AsmParser/CMakeLists.txt | 1 - llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 4 +- llvm/lib/Target/RISCV/CMakeLists.txt | 2 - .../RISCV/Disassembler/RISCVDisassembler.cpp | 2 +- llvm/lib/Target/RISCV/MCTargetDesc/CMakeLists.txt | 3 +- .../Target/RISCV/MCTargetDesc/RISCVAsmBackend.h | 2 +- .../{Utils => MCTargetDesc}/RISCVBaseInfo.cpp | 0 .../RISCV/{Utils => MCTargetDesc}/RISCVBaseInfo.h | 5 +- .../Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp | 4 +- .../Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp | 5 +- .../RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp | 2 +- .../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 2 +- .../RISCV/{Utils => MCTargetDesc}/RISCVMatInt.cpp | 0 .../RISCV/{Utils => MCTargetDesc}/RISCVMatInt.h | 0 llvm/lib/Target/RISCV/RISCV.h | 2 +- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 2 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 27 +- llvm/lib/Target/RISCV/RISCVISelLowering.h | 6 + llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfoB.td | 18 +- llvm/lib/Target/RISCV/RISCVSubtarget.h | 2 +- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 2 +- llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp | 2 +- llvm/lib/Target/RISCV/Utils/CMakeLists.txt | 10 - .../Target/WebAssembly/WebAssemblyISelLowering.cpp | 3 +- llvm/lib/Target/X86/X86.td | 3 +- llvm/lib/Target/X86/X86FlagsCopyLowering.cpp | 1 - llvm/lib/Target/X86/X86IndirectThunks.cpp | 1 - llvm/lib/Target/X86/X86MCInstLower.cpp | 6 +- llvm/lib/TextAPI/MachO/InterfaceFile.cpp | 2 - llvm/lib/Transforms/Coroutines/CoroFrame.cpp | 12 +- llvm/lib/Transforms/IPO/AttributorAttributes.cpp | 1 - llvm/lib/Transforms/IPO/IROutliner.cpp | 2 - llvm/lib/Transforms/IPO/OpenMPOpt.cpp | 4 +- llvm/lib/Transforms/IPO/ThinLTOBitcodeWriter.cpp | 2 +- llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp | 4 +- .../Instrumentation/SanitizerCoverage.cpp | 2 +- .../Transforms/Scalar/ConstraintElimination.cpp | 7 +- .../Transforms/Scalar/LowerMatrixIntrinsics.cpp | 1 - llvm/lib/Transforms/Scalar/NewGVN.cpp | 7 +- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 17 +- .../AArch64/GlobalISel/regbank-fp-use-def.mir | 46 +- .../CodeGen/AArch64/GlobalISel/select-fp-casts.mir | 48 +- .../CodeGen/AArch64/aarch64-matrix-umull-smull.ll | 186 --- llvm/test/CodeGen/AArch64/ls64-intrinsics.ll | 92 ++ llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll | 12 +- llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll | 8 +- llvm/test/CodeGen/RISCV/callee-saved-gprs.ll | 8 +- .../RISCV/calling-conv-ilp32-ilp32f-common.ll | 12 +- .../calling-conv-ilp32-ilp32f-ilp32d-common.ll | 44 +- llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll | 12 +- llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll | 12 +- .../RISCV/calling-conv-ilp32f-ilp32d-common.ll | 10 +- .../RISCV/calling-conv-lp64-lp64f-common.ll | 4 +- .../RISCV/calling-conv-lp64-lp64f-lp64d-common.ll | 22 +- llvm/test/CodeGen/RISCV/calling-conv-lp64.ll | 12 +- .../test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll | 4 +- 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llvm/test/MC/ARM/lsl-zero-errors.s | 6 +- llvm/test/MC/ARM/lsl-zero.s | 6 +- llvm/test/MC/ARM/mve-fp-registers.s | 22 +- llvm/test/MC/ARM/thumbv8m.s | 12 +- llvm/test/MC/AsmParser/directive_ascii.s | 8 + .../MC/Disassembler/PowerPC/ppc64-encoding-ext.txt | 11 +- llvm/test/MC/PowerPC/modern-aix-as.s | 16 + llvm/test/TableGen/cast-string.td | 59 + .../test/Transforms/InferFunctionAttrs/annotate.ll | 520 +++---- .../test/Transforms/SLPVectorizer/X86/bad_types.ll | 11 +- .../test/tools/gold/X86/devirt_vcall_vis_public.ll | 30 +- llvm/tools/llvm-mca/CodeRegion.cpp | 1 - llvm/tools/llvm-pdbutil/DumpOutputStyle.cpp | 1 - llvm/tools/llvm-profdata/llvm-profdata.cpp | 1 - llvm/tools/llvm-profgen/ProfiledBinary.cpp | 2 - llvm/tools/llvm-readobj/WasmDumper.cpp | 2 +- llvm/tools/llvm-xray/xray-stacks.cpp | 3 +- llvm/unittests/ADT/OptionalTest.cpp | 121 -- llvm/unittests/ADT/SmallVectorTest.cpp | 12 +- llvm/unittests/Support/KnownBitsTest.cpp | 20 + llvm/unittests/Support/ThreadPool.cpp | 101 +- llvm/utils/TableGen/X86FoldTablesEmitter.cpp | 2 - .../gn/secondary/clang-tools-extra/clangd/BUILD.gn | 1 + .../clang-tools-extra/clangd/unittests/BUILD.gn | 1 + .../llvm/include/llvm/Frontend/OpenACC/BUILD.gn | 2 +- .../llvm/lib/Target/RISCV/AsmParser/BUILD.gn | 1 - .../gn/secondary/llvm/lib/Target/RISCV/BUILD.gn | 2 - .../llvm/lib/Target/RISCV/Disassembler/BUILD.gn | 1 - .../llvm/lib/Target/RISCV/MCTargetDesc/BUILD.gn | 11 +- .../secondary/llvm/lib/Target/RISCV/Utils/BUILD.gn | 27 - ...erization.md => BufferDeallocationInternals.md} | 404 +----- mlir/docs/Bufferization.md | 1419 ++++---------------- mlir/docs/Dialects/Linalg.md | 10 +- mlir/docs/Interfaces.md | 2 +- mlir/docs/Tutorials/Toy/Ch-6.md | 4 +- mlir/include/mlir/Analysis/AffineStructures.h | 7 + mlir/include/mlir/Analysis/LinearTransform.h | 48 + mlir/include/mlir/Analysis/Presburger/Fraction.h | 2 + mlir/include/mlir/Analysis/Presburger/Matrix.h | 6 + mlir/include/mlir/Analysis/Presburger/Simplex.h | 30 +- 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mlir/lib/Conversion/CMakeLists.txt | 1 + mlir/lib/Conversion/TosaToLinalg/CMakeLists.txt | 20 + mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp | 188 +++ .../Conversion/TosaToLinalg/TosaToLinalgPass.cpp | 59 + mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp | 178 ++- mlir/lib/Dialect/Linalg/IR/LinalgTypes.cpp | 3 - mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp | 14 +- mlir/lib/IR/PatternMatch.cpp | 35 + mlir/lib/Transforms/Utils/DialectConversion.cpp | 15 + .../Utils/GreedyPatternRewriteDriver.cpp | 2 +- mlir/test/Analysis/test-dominance.mlir | 4 +- mlir/test/Analysis/test-liveness.mlir | 2 +- .../Conversion/AffineToStandard/lower-affine.mlir | 54 +- .../Conversion/LinalgToSPIRV/linalg-to-spirv.mlir | 2 +- .../Conversion/OpenMPToLLVM/convert-to-llvmir.mlir | 2 +- mlir/test/Conversion/SCFToGPU/parallel_loop.mlir | 4 +- .../Conversion/SCFToStandard/convert-to-cfg.mlir | 18 +- .../ShapeToStandard/convert-shape-constraints.mlir | 8 +- .../ShapeToStandard/shape-to-standard.mlir | 32 +- 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mlir/unittests/Analysis/CMakeLists.txt | 1 + mlir/unittests/Analysis/LinearTransformTest.cpp | 87 ++ .../libomptarget/deviceRTLs/nvptx/CMakeLists.txt | 103 +- .../deviceRTLs/nvptx/src/target_impl.cu | 128 +- .../deviceRTLs/nvptx/src/target_impl.h | 140 +- .../deviceRTLs/nvptx/test/CMakeLists.txt | 2 +- openmp/libomptarget/plugins/amdgpu/src/rtl.cpp | 2 +- 416 files changed, 8010 insertions(+), 5271 deletions(-) create mode 100644 clang-tools-extra/clangd/ASTSignals.cpp create mode 100644 clang-tools-extra/clangd/ASTSignals.h create mode 100644 clang-tools-extra/clangd/unittests/ASTSignalsTests.cpp create mode 100644 clang/test/CodeGen/aarch64-ls64.c create mode 100644 compiler-rt/lib/gwp_asan/optional/printf.h rename compiler-rt/lib/gwp_asan/tests/{optional => platform_specific}/printf_sanit [...] create mode 100644 flang/test/Semantics/modfile37.f90 create mode 100644 flang/test/Semantics/modfile38.f90 delete mode 100644 flang/tools/f18/f18_version.h.in create mode 100644 libc/src/string/memmove.cpp copy libc/src/{ctype/isascii.h => string/memmove.h} (54%) create mode 100644 libc/test/src/string/memmove_test.cpp create mode 100644 lld/wasm/InputTable.h create mode 100644 lldb/test/API/tools/lldb-server/TestGdbRemoteAttachWait.py rename llvm/lib/Target/RISCV/{Utils => MCTargetDesc}/RISCVBaseInfo.cpp (100%) rename llvm/lib/Target/RISCV/{Utils => MCTargetDesc}/RISCVBaseInfo.h (98%) rename llvm/lib/Target/RISCV/{Utils => MCTargetDesc}/RISCVMatInt.cpp (100%) rename llvm/lib/Target/RISCV/{Utils => MCTargetDesc}/RISCVMatInt.h (100%) delete mode 100644 llvm/lib/Target/RISCV/Utils/CMakeLists.txt delete mode 100644 llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll create mode 100644 llvm/test/CodeGen/AArch64/ls64-intrinsics.ll create mode 100644 llvm/test/MC/PowerPC/modern-aix-as.s create mode 100644 llvm/test/TableGen/cast-string.td delete mode 100644 llvm/utils/gn/secondary/llvm/lib/Target/RISCV/Utils/BUILD.gn copy mlir/docs/{Bufferization.md => BufferDeallocationInternals.md} (66%) create mode 100644 mlir/include/mlir/Analysis/LinearTransform.h create mode 100644 mlir/include/mlir/Conversion/TosaToLinalg/TosaToLinalg.h create mode 100644 mlir/lib/Analysis/LinearTransform.cpp create mode 100644 mlir/lib/Conversion/TosaToLinalg/CMakeLists.txt create mode 100644 mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp create mode 100644 mlir/lib/Conversion/TosaToLinalg/TosaToLinalgPass.cpp create mode 100644 mlir/test/Conversion/TosaToLinalg/tosa-to-linalg.mlir create mode 100644 mlir/test/Transforms/test-pattern-selective-replacement.mlir create mode 100644 mlir/unittests/Analysis/LinearTransformTest.cpp -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-defconfig updated (b60abb0a -> bc054afb)

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4 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-release-aarch64-check_binutils updated (ae31dcdb -> d79338f2)

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[binutils-gdb] branch master updated (e403a898b58 -> 1368b914e93)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from e403a898b58 Automatic date update in version.in new 1368b914e93 sim: testsuite: flatten tree The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: sim/testsuite/ChangeLog | 5 +++++ sim/testsuite/Makefile.in | 1 - sim/testsuite/{sim => }/aarch64/ChangeLog | 0 sim/testsuite/{sim => }/aarch64/adds.s | 0 sim/testsuite/{sim => }/aarch64/addv.s | 0 sim/testsuite/{sim => }/aarch64/allinsn.exp | 0 sim/testsuite/{sim => }/aarch64/bit.s | 0 sim/testsuite/{sim => }/aarch64/cmtst.s | 0 sim/testsuite/{sim => }/aarch64/cnt.s | 0 sim/testsuite/{sim => }/aarch64/fcmXX.s | 0 sim/testsuite/{sim => }/aarch64/fcmp.s | 0 sim/testsuite/{sim => }/aarch64/fcsel.s | 0 sim/testsuite/{sim => }/aarch64/fcvtl.s | 0 sim/testsuite/{sim => }/aarch64/fcvtz.s | 0 sim/testsuite/{sim => }/aarch64/fminnm.s | 0 sim/testsuite/{sim => }/aarch64/fstur.s | 0 sim/testsuite/{sim => }/aarch64/ldn_multiple.s | 0 sim/testsuite/{sim => }/aarch64/ldn_single.s | 0 sim/testsuite/{sim => }/aarch64/ldnr.s | 0 sim/testsuite/{sim => }/aarch64/mla.s | 0 sim/testsuite/{sim => }/aarch64/mls.s | 0 sim/testsuite/{sim => }/aarch64/mul.s | 0 sim/testsuite/{sim => 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0 sim/testsuite/{sim => }/arm/iwmmxt/tbcst.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/testutils.inc | 0 sim/testsuite/{sim => }/arm/iwmmxt/textrm.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tinsr.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmia.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmiaph.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmiaxy.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/tmovmsk.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wacc.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wadd.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/waligni.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/walignr.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wand.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wandn.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wavg2.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wcmpeq.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wcmpgt.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmac.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmadd.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmax.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmin.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmov.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wmul.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wor.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wpack.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wror.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsad.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wshufh.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsll.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsra.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsrl.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wsub.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckeh.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckel.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckih.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wunpckil.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wxor.cgs | 0 sim/testsuite/{sim => }/arm/iwmmxt/wzero.cgs | 0 sim/testsuite/{sim => }/arm/ldm.cgs | 0 sim/testsuite/{sim => }/arm/ldr.cgs | 0 sim/testsuite/{sim => }/arm/ldrb.cgs | 0 sim/testsuite/{sim => }/arm/ldrh.cgs | 0 sim/testsuite/{sim => }/arm/ldrsb.cgs | 0 sim/testsuite/{sim => }/arm/ldrsh.cgs | 0 sim/testsuite/{sim => }/arm/misaligned1.ms | 0 sim/testsuite/{sim => }/arm/misaligned2.ms | 0 sim/testsuite/{sim => }/arm/misaligned3.ms | 0 sim/testsuite/{sim => }/arm/misc.exp | 0 sim/testsuite/{sim => }/arm/mla.cgs | 0 sim/testsuite/{sim => }/arm/mov.cgs | 0 sim/testsuite/{sim => }/arm/movw-movt.ms | 0 sim/testsuite/{sim => }/arm/mrs.cgs | 0 sim/testsuite/{sim => }/arm/msr.cgs | 0 sim/testsuite/{sim => }/arm/mul.cgs | 0 sim/testsuite/{sim => }/arm/mvn.cgs | 0 sim/testsuite/{sim => }/arm/orr.cgs | 0 sim/testsuite/{sim => }/arm/rsb.cgs | 0 sim/testsuite/{sim => }/arm/rsc.cgs | 0 sim/testsuite/{sim => }/arm/sbc.cgs | 0 sim/testsuite/{sim => }/arm/smlal.cgs | 0 sim/testsuite/{sim => }/arm/smull.cgs | 0 sim/testsuite/{sim => }/arm/stm.cgs | 0 sim/testsuite/{sim => }/arm/str.cgs | 0 sim/testsuite/{sim => }/arm/strb.cgs | 0 sim/testsuite/{sim => }/arm/strh.cgs | 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sim/testsuite/{sim => }/arm/thumb/mvn.cgs | 0 sim/testsuite/{sim => }/arm/thumb/neg.cgs | 0 sim/testsuite/{sim => }/arm/thumb/orr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/pop-pc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/pop.cgs | 0 sim/testsuite/{sim => }/arm/thumb/push-lr.cgs | 0 sim/testsuite/{sim => }/arm/thumb/push.cgs | 0 sim/testsuite/{sim => }/arm/thumb/ror.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sbc.cgs | 0 sim/testsuite/{sim => }/arm/thumb/stmia.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str-sprel.cgs | 0 sim/testsuite/{sim => }/arm/thumb/str.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strb-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strb.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strh-imm.cgs | 0 sim/testsuite/{sim => }/arm/thumb/strh.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sub-sp.cgs | 0 sim/testsuite/{sim => }/arm/thumb/sub.cgs | 0 sim/testsuite/{sim => }/arm/thumb/subi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/subi8.cgs | 0 sim/testsuite/{sim => }/arm/thumb/swi.cgs | 0 sim/testsuite/{sim => }/arm/thumb/testutils.inc | 0 sim/testsuite/{sim => }/arm/thumb/tst.cgs | 0 sim/testsuite/{sim => }/arm/tst.cgs | 0 sim/testsuite/{sim => }/arm/umlal.cgs | 0 sim/testsuite/{sim => }/arm/umull.cgs | 0 sim/testsuite/{sim => }/arm/xscale/blx.cgs | 0 sim/testsuite/{sim => }/arm/xscale/mia.cgs | 0 sim/testsuite/{sim => }/arm/xscale/miaph.cgs | 0 sim/testsuite/{sim => }/arm/xscale/miaxy.cgs | 0 sim/testsuite/{sim => }/arm/xscale/mra.cgs | 0 sim/testsuite/{sim => }/arm/xscale/testutils.inc | 0 sim/testsuite/{sim => }/arm/xscale/xscale.exp | 0 sim/testsuite/{sim => }/avr/ChangeLog | 0 sim/testsuite/{sim => }/avr/allinsn.exp | 0 sim/testsuite/{sim => }/avr/pass.s | 0 sim/testsuite/{sim => }/avr/testutils.inc | 0 sim/testsuite/{sim => }/bfin/.gitignore | 0 sim/testsuite/{sim => }/bfin/10272_small.s | 0 sim/testsuite/{sim => }/bfin/10436.s | 0 sim/testsuite/{sim => }/bfin/10622.s | 0 sim/testsuite/{sim => }/bfin/10742.s | 0 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(100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sat_aa.S (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_search.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sgn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_iuw32.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_iutsh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_iutsh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_mix.s (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align16.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align24.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_l.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expexp_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_pack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmaxvmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_a0alr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp.s (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_except_illopcode.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_user_mode.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable_enable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_loopsetup_stld.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nested.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nmi.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_reload.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tcount.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tscale.S (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drlo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_pibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p.s 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=> }/cris/asm/moveq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moveqpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mover.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverbpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverdpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverpcb.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverpcd.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverpcw.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverwpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movesmp.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movmp.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movmp8.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movpmv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movpmv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movppc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movpr.ms (100%) rename sim/testsuite/{sim => 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=> }/frv/fbgtlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fble.cgs (100%) rename sim/testsuite/{sim => }/frv/fblelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fblg.cgs (100%) rename sim/testsuite/{sim => }/frv/fblglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fblt.cgs (100%) rename sim/testsuite/{sim => }/frv/fbltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbne.cgs (100%) rename sim/testsuite/{sim => }/frv/fbnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbno.cgs (100%) rename sim/testsuite/{sim => }/frv/fbnolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbo.cgs (100%) rename sim/testsuite/{sim => }/frv/fbolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbra.cgs (100%) rename sim/testsuite/{sim => }/frv/fbralr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbu.cgs (100%) rename sim/testsuite/{sim => }/frv/fbue.cgs (100%) rename sim/testsuite/{sim => }/frv/fbuelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbug.cgs (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/frv/fckul.cgs (100%) rename sim/testsuite/{sim => }/frv/fckule.cgs (100%) rename sim/testsuite/{sim => }/frv/fcmpd.cgs (100%) rename sim/testsuite/{sim => }/frv/fcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/fdabss.cgs (100%) rename sim/testsuite/{sim => }/frv/fdadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fdcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/fddivs.cgs (100%) rename sim/testsuite/{sim => }/frv/fditos.cgs (100%) rename sim/testsuite/{sim => }/frv/fdivd.cgs (100%) rename sim/testsuite/{sim => }/frv/fdivs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmas.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmss.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmulcs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/fdnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsads.cgs (100%) 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sim/testsuite/{sim => }/frv/fnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fnop.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/addss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr400/csdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maveh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/scutss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/slass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smsss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/subss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcpl.cgs (100%) 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=> }/frv/interrupts/illinsn.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/mp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/privileged_instruction.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/regalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/reset.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/shadow_regs.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/timer.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpil.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.pcgs (100%) rename sim/testsuite/{sim => }/frv/ld.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfu.cgs (100%) rename sim/testsuite/{sim => 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rename sim/testsuite/{sim => }/v850/satsubi.cgs (100%) rename sim/testsuite/{sim => }/v850/satsubr.cgs (100%) rename sim/testsuite/{sim => }/v850/shl.cgs (100%) rename sim/testsuite/{sim => }/v850/shr.cgs (100%) rename sim/testsuite/{sim => }/v850/testutils.cgs (100%) rename sim/testsuite/{sim => }/v850/testutils.inc (100%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[gcc] branch releases/gcc-9 updated (669f3c7bc02 -> 891c4f6f4d3)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch releases/gcc-9 in repository gcc. from 669f3c7bc02 Daily bump. new 891c4f6f4d3 Daily bump. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[gcc] branch releases/gcc-8 updated (2771e1a25fa -> ada7e1c3556)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch releases/gcc-8 in repository gcc. from 2771e1a25fa Daily bump. new ada7e1c3556 Daily bump. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

[gcc] branch releases/gcc-10 updated (ed0aa6151e7 -> 5d201f32885)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch releases/gcc-10 in repository gcc. from ed0aa6151e7 Daily bump. new 5d201f32885 Daily bump. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 5 months

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Tcwg-commits January 2021