Tcwg-commits January 2021

tcwg-commits@lists.linaro.org

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9360 discussions

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig updated (68b007788a -> edf0f284b1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig in repository toolchain/ci/binutils-gdb. from 68b007788a ld/x86: Add -z report-relative-reloc adds 75a933f399 ld/elf/x86: Don't compare IFUNC address in the shared object adds 514fca98df Automatic date update in version.in adds edf0f284b1 PR binutils/23460: Increase the max number of open files to 20 No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 6 ++++++ bfd/elfxx-x86.c | 3 +-- bfd/version.h | 2 +- ld/ChangeLog | 14 ++++++++++++++ ld/testsuite/ld-ifunc/ifunc.exp | 22 ++-------------------- ld/testsuite/ld-ifunc/pr23169a.c | 2 +- ld/testsuite/ld-plugin/lto.exp | 2 +- 7 files changed, 26 insertions(+), 25 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig updated (7b6684dc -> 5cb439ae)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig in repository toolchain/ci/base-artifacts. discards 7b6684dc 0: update: binutils-gcc-linux-qemu: boot new 5cb439ae 0: update: binutils-gcc-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (7b6684dc) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-ma [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 244 +- 02-prepare_abe/console.log | 434 +- 03-build_abe-binutils/console.log | 11992 +++++---- 04-build_abe-stage1/console.log | 20830 ++++++++------- 05-build_linux/console.log | 578 +- 06-build_abe-qemu/console.log | 6752 ++--- 07-boot_linux/console.log | 418 +- 08-check_regression/console.log | 12 +- 08-check_regression/results.regressions | 3 +- 09-update_baseline/console.log | 18 +- 09-update_baseline/results.regressions | 3 +- console.log | 41278 +++++++++++++++--------------- jenkins/manifest.sh | 20 +- 13 files changed, 41256 insertions(+), 41326 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_cross/gnu-release-arm-build_cross updated (ed0aa6151e7 -> 8f2ed3fe616)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_cross/gnu-release-arm-build_cross in repository toolchain/ci/gcc. from ed0aa6151e7 Daily bump. adds 5d201f32885 Daily bump. adds 8f2ed3fe616 Daily bump. No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_cross/gnu-release-arm-build_cross updated (bddcdba2 -> 56ced96c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_cross/gnu-release-arm-build_cross in repository toolchain/ci/base-artifacts. discards bddcdba2 0: update: binutils-gcc-glibc-qemu: 6 new 56ced96c 0: update: binutils-gcc-glibc-qemu: 6 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (bddcdba2) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_cross/gnu-release-arm-bu [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 224 +- 02-prepare_abe/console.log | 422 +- 04-build_abe-binutils/console.log | 11590 ++-- 05-build_abe-stage1/console.log | 18370 +++--- 06-build_abe-linux/console.log | 1992 +- 07-build_abe-glibc/console.log | 38243 ++++++------ 08-build_abe-stage2/console.log | 40450 ++++++------ 09-build_abe-qemu/console.log | 4018 +- 10-check_regression/console.log | 16 +- 11-update_baseline/console.log | 16 +- console.log | 115405 +++++++++++++++++------------------ jenkins/manifest.sh | 10 +- 12 files changed, 115352 insertions(+), 115404 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-O2 updated (c50c65a8bf -> 86f65dffc2)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-O2 in repository toolchain/ci/glibc. from c50c65a8bf nptl: Fix comment typo in pthread_cond_wait.c adds f5082c7010 aarch64: push the set of rules before falling into slow path adds 6cc992412c alpha: Provide wait4 for static library [BZ #27150] adds ef8c78a6c6 Import idx.h from gnulib adds 47f4316095 Import filename.h from gnulib adds 448a256359 malloc: Add scratch_buffer_dupfree adds c6e0b0b5b0 stdlib: Sync canonicalize with gnulib [BZ #10635] [BZ #26592 [...] adds ecdb06cdf2 support: Add support_small_thread_stack_size adds 3016596a81 Add SEGV_MTEAERR and SEGV_MTESERR from Linux 5.10. adds caa884dda7 Remove dbl-64/wordsize-64 adds 9e97f239ea Remove dbl-64/wordsize-64 (part 2) adds ecce11aa07 x86: Support GNU_PROPERTY_X86_ISA_1_V[234] marker [BZ #26717] adds 18b640c570 Update NEWS for CVE-2019-25013. adds 2f056e8a5d aarch64: define PI_STATIC_AND_HIDDEN adds eeaa19f75e mntent: Use __putc_unlocked instead of fputc_unlocked adds 1b5c9dfeb2 ARC: Regenerate ulps adds c6e2ca2c3f POSIX locale: Fix typo in comment adds a7e9dbb774 Add xchdir to libsupport. adds 7a72265436 Add xfchmod to libsupport adds 2cd361b511 posix: Correct attribute access mode on readlinkat [BZ #27024]. adds c31b1f5231 riscv: support GNU indirect function adds 313bfd505e riscv: Initialize $gp before resolving the IRELATIVE relocation adds 1c426b1d59 Update STATX_ATTR_DAX value from Linux 5.10. adds 7b9c3260bc support: Add xchmod wrapper adds 42dda89dcb posix: Fix return value of system if shell can not be execut [...] adds 4dddd7e9cb posix: Sync tempname with gnulib [BZ #26648] adds bf7db6d369 math: Add BZ#18980 fix back on dbl-64 cosh adds 87d583c6e8 install: Replace scripts/output-format.sed with objdump -f [ [...] adds 0400f92833 Makerules: Do not require startup files for format.lds probe object adds f430293d84 posix: consume less entropy on tempname adds 2ef23b5205 x86: Set header.feature_1 in TCB for always-on CET [BZ #27177] adds 86a4d3fa7d elf: work around a gcc bug in elf_get_dynamic_info adds efbbd9c33a ldconfig/x86: Store ISA level in cache and aux cache adds cf12900645 Use the right argument code in unnormal tests adds 7137d682eb ifuncmain6pie: Remove the circular IFUNC dependency [BZ #20019] adds d18f59bf92 Fix x86 build with --enable-tunable=no adds 2d651eb926 x86: Move x86 processor cache info to cpu_features adds cc528f9a7e math/test-tgmath2: Fix fabs failure when no long double adds 86f65dffc2 ld.so: Add --list-tunables to print tunable values No new revisions were added by this update. Summary of changes: Makerules | 16 +- NEWS | 7 + benchtests/strcoll-inputs/filelist#en_US.UTF-8 | 1 - config.h.in | 3 + config.make.in | 1 - configure | 19 - configure.ac | 11 - elf/Makefile | 13 + elf/cache.c | 39 +- elf/dl-cache.c | 4 + elf/dl-main.h | 2 +- elf/dl-tunables.c | 43 ++ elf/dl-tunables.h | 2 + elf/dl-usage.c | 7 +- elf/elf.h | 35 +- elf/get-dynamic-info.h | 41 +- elf/ifuncmain6pie.c | 14 +- elf/ifuncmod6.c | 8 +- elf/ldconfig.c | 18 +- elf/readelflib.c | 81 ++- elf/readlib.c | 7 +- elf/rtld.c | 19 + elf/tst-glibc-hwcaps-2-cache.c | 45 ++ .../etc/ld.so.conf | 0 .../postclean.req | 0 elf/tst-glibc-hwcaps-2-cache.script | 8 + elf/tst-rtld-list-tunables.exp | 14 + elf/tst-rtld-list-tunables.sh | 34 ++ include/filename.h | 112 +++++ include/idx.h | 114 +++++ include/scratch_buffer.h | 16 + io/bits/statx-generic.h | 2 +- libc-abis | 1 + localedata/locales/POSIX | 2 +- malloc/Makefile | 1 + malloc/Versions | 1 + .../scratch_buffer_dupfree.c | 38 +- malloc/tst-scratch_buffer.c | 26 +- manual/tunables.texi | 38 ++ math/libm-test-driver.c | 12 +- math/libm-test-fpclassify.inc | 14 +- math/libm-test-isinf.inc | 14 +- math/libm-test-isnan.inc | 14 +- math/libm-test-issignaling.inc | 14 +- math/test-tgmath2.c | 4 +- misc/mntent_r.c | 12 +- posix/unistd.h | 2 +- scripts/output-format.sed | 35 -- stdlib/canonicalize.c | 546 +++++++++++++++------ stdlib/test-bz22786.c | 11 +- stdlib/tst-system.c | 17 + support/Makefile | 3 + support/support_set_small_thread_stack_size.c | 12 +- .../wordsize-64/s_getpayload.c => support/xchdir.c | 25 +- .../sysv/linux/alpha/wait4.c => support/xchmod.c | 22 +- .../sysv/linux/alpha/wait4.c => support/xfchmod.c | 22 +- support/xthread.h | 2 + support/xunistd.h | 3 + sysdeps/aarch64/Implies | 1 - sysdeps/aarch64/configure | 5 + sysdeps/aarch64/configure.ac | 4 + sysdeps/aarch64/dl-tlsdesc.S | 2 + sysdeps/alpha/Implies | 1 - sysdeps/arc/fpu/libm-test-ulps | 8 +- sysdeps/generic/dl-cache.h | 16 +- .../linux/alpha/wait4.c => generic/dl-isa-level.h} | 21 +- .../s_getpayload.c => generic/elf-read-prop.h} | 31 +- sysdeps/generic/ldconfig.h | 22 +- sysdeps/ieee754/dbl-64/e_acosh.c | 50 +- sysdeps/ieee754/dbl-64/e_cosh.c | 76 ++- sysdeps/ieee754/dbl-64/e_fmod.c | 202 +++----- sysdeps/ieee754/dbl-64/e_log10.c | 42 +- sysdeps/ieee754/dbl-64/s_frexp.c | 81 +-- sysdeps/ieee754/dbl-64/s_getpayload.c | 15 +- sysdeps/ieee754/dbl-64/s_issignaling.c | 14 +- sysdeps/ieee754/dbl-64/s_llround.c | 49 +- sysdeps/ieee754/dbl-64/s_lround.c | 57 +-- sysdeps/ieee754/dbl-64/s_modf.c | 80 ++- sysdeps/ieee754/dbl-64/s_remquo.c | 43 +- sysdeps/ieee754/dbl-64/s_roundeven.c | 79 +-- sysdeps/ieee754/dbl-64/s_scalbln.c | 63 ++- sysdeps/ieee754/dbl-64/s_scalbn.c | 63 ++- sysdeps/ieee754/dbl-64/s_setpayload_main.c | 42 +- sysdeps/ieee754/dbl-64/s_totalorder.c | 32 +- sysdeps/ieee754/dbl-64/s_totalordermag.c | 24 +- sysdeps/ieee754/dbl-64/wordsize-64/e_acosh.c | 68 --- sysdeps/ieee754/dbl-64/wordsize-64/e_cosh.c | 85 ---- sysdeps/ieee754/dbl-64/wordsize-64/e_fmod.c | 106 ---- sysdeps/ieee754/dbl-64/wordsize-64/e_log10.c | 87 ---- sysdeps/ieee754/dbl-64/wordsize-64/s_frexp.c | 66 --- sysdeps/ieee754/dbl-64/wordsize-64/s_issignaling.c | 43 -- sysdeps/ieee754/dbl-64/wordsize-64/s_llround.c | 75 --- sysdeps/ieee754/dbl-64/wordsize-64/s_lround.c | 86 ---- sysdeps/ieee754/dbl-64/wordsize-64/s_modf.c | 65 --- sysdeps/ieee754/dbl-64/wordsize-64/s_remquo.c | 111 ----- sysdeps/ieee754/dbl-64/wordsize-64/s_roundeven.c | 71 --- sysdeps/ieee754/dbl-64/wordsize-64/s_scalbln.c | 60 --- sysdeps/ieee754/dbl-64/wordsize-64/s_scalbn.c | 60 --- .../ieee754/dbl-64/wordsize-64/s_setpayload_main.c | 54 -- sysdeps/ieee754/dbl-64/wordsize-64/s_totalorder.c | 76 --- .../ieee754/dbl-64/wordsize-64/s_totalordermag.c | 73 --- sysdeps/mips/mips64/Implies | 1 - sysdeps/posix/system.c | 4 + sysdeps/posix/tempname.c | 291 ++++++----- sysdeps/riscv/dl-irel.h | 56 +++ sysdeps/riscv/dl-machine.h | 44 +- sysdeps/s390/s390-64/Implies | 1 - sysdeps/sparc/sparc64/Implies | 1 - sysdeps/unix/sysv/linux/alpha/wait4.c | 2 + sysdeps/unix/sysv/linux/arm/readelflib.c | 22 +- sysdeps/unix/sysv/linux/bits/siginfo-consts.h | 6 +- sysdeps/unix/sysv/linux/faccessat.c | 3 +- sysdeps/unix/sysv/linux/ia64/readelflib.c | 22 +- sysdeps/unix/sysv/linux/mips/readelflib.c | 22 +- sysdeps/unix/sysv/linux/powerpc/readelflib.c | 22 +- sysdeps/unix/sysv/linux/riscv/readelflib.c | 22 +- sysdeps/unix/sysv/linux/s390/readelflib.c | 22 +- sysdeps/unix/sysv/linux/sparc/readelflib.c | 22 +- sysdeps/unix/sysv/linux/x86/elf-read-prop.h | 60 +++ sysdeps/unix/sysv/linux/x86/readelflib.c | 23 +- sysdeps/unix/sysv/linux/x86_64/Makefile | 51 ++ .../unix/sysv/linux/x86_64/tst-glibc-hwcaps-2.c | 84 ++++ .../sysv/linux/x86_64/x86-64-isa-level-VALUE.c | 4 + sysdeps/x86/Makefile | 36 ++ .../wordsize-64/s_getpayload.c => x86/abi-note.c} | 32 +- sysdeps/x86/cacheinfo.c | 46 +- sysdeps/x86/cacheinfo.h | 400 +-------------- sysdeps/x86/configure | 79 +++ sysdeps/x86/configure.ac | 66 +++ sysdeps/x86/cpu-features.c | 38 +- sysdeps/x86/dl-cacheinfo.h | 460 +++++++++++++++++ sysdeps/x86/dl-cet.c | 17 +- .../s_getpayload.c => x86/dl-isa-level.h} | 28 +- sysdeps/x86/dl-prop.h | 113 +++-- sysdeps/x86/get-isa-level.h | 67 +++ sysdeps/x86/include/cpu-features.h | 24 + sysdeps/x86/isa-level.c | 97 ++++ sysdeps/x86/link_map.h | 18 +- sysdeps/x86/tst-isa-level-1.c | 104 ++++ sysdeps/x86/tst-isa-level-mod-1-baseline.c | 1 + sysdeps/x86/tst-isa-level-mod-1-v2.c | 1 + sysdeps/x86/tst-isa-level-mod-1-v3.c | 1 + sysdeps/x86/tst-isa-level-mod-1-v4.c | 1 + .../alpha/wait4.c => x86/tst-isa-level-mod-1.c} | 19 +- sysdeps/x86/tst-setjmp-cet.c | 1 + sysdeps/x86_64/Implies | 1 - sysdeps/x86_64/dl-hwcaps-subdirs.c | 31 +- sysdeps/x86_64/tst-glibc-hwcaps.c | 41 +- 148 files changed, 3442 insertions(+), 3001 deletions(-) create mode 100644 elf/tst-glibc-hwcaps-2-cache.c copy elf/{tst-glibc-hwcaps-cache.root => tst-glibc-hwcaps-2-cache.root}/etc/ld.so. [...] copy elf/{tst-glibc-hwcaps-cache.root => tst-glibc-hwcaps-2-cache.root}/postclean. [...] create mode 100644 elf/tst-glibc-hwcaps-2-cache.script create mode 100644 elf/tst-rtld-list-tunables.exp create mode 100755 elf/tst-rtld-list-tunables.sh create mode 100644 include/filename.h create mode 100644 include/idx.h copy support/support_set_small_thread_stack_size.c => malloc/scratch_buffer_dupfre [...] delete mode 100644 scripts/output-format.sed copy sysdeps/ieee754/dbl-64/wordsize-64/s_getpayload.c => support/xchdir.c (59%) copy sysdeps/unix/sysv/linux/alpha/wait4.c => support/xchmod.c (64%) copy sysdeps/unix/sysv/linux/alpha/wait4.c => support/xfchmod.c (64%) copy sysdeps/{unix/sysv/linux/alpha/wait4.c => generic/dl-isa-level.h} (64%) copy sysdeps/{ieee754/dbl-64/wordsize-64/s_getpayload.c => generic/elf-read-prop.h} (58%) delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/e_acosh.c delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/e_cosh.c delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/e_fmod.c delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/e_log10.c delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_frexp.c delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_issignaling.c delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_llround.c delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_lround.c delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_modf.c delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_remquo.c delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_roundeven.c delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_scalbln.c delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_scalbn.c delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_setpayload_main.c delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_totalorder.c delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_totalordermag.c create mode 100644 sysdeps/riscv/dl-irel.h create mode 100644 sysdeps/unix/sysv/linux/x86/elf-read-prop.h create mode 100644 sysdeps/unix/sysv/linux/x86_64/tst-glibc-hwcaps-2.c create mode 100644 sysdeps/unix/sysv/linux/x86_64/x86-64-isa-level-VALUE.c copy sysdeps/{ieee754/dbl-64/wordsize-64/s_getpayload.c => x86/abi-note.c} (52%) rename sysdeps/{ieee754/dbl-64/wordsize-64/s_getpayload.c => x86/dl-isa-level.h} (56%) create mode 100644 sysdeps/x86/get-isa-level.h create mode 100644 sysdeps/x86/isa-level.c create mode 100644 sysdeps/x86/tst-isa-level-1.c create mode 100644 sysdeps/x86/tst-isa-level-mod-1-baseline.c create mode 100644 sysdeps/x86/tst-isa-level-mod-1-v2.c create mode 100644 sysdeps/x86/tst-isa-level-mod-1-v3.c create mode 100644 sysdeps/x86/tst-isa-level-mod-1-v4.c copy sysdeps/{unix/sysv/linux/alpha/wait4.c => x86/tst-isa-level-mod-1.c} (64%) create mode 100644 sysdeps/x86/tst-setjmp-cet.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-O2 updated (3d52735bab -> 514fca98df)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-O2 in repository toolchain/ci/binutils-gdb. from 3d52735bab sim: include stdlib.h for atoi() adds 18b9872261 RISC-V: Ouput __global_pointer$ as dynamic symbol when gener [...] adds de6a7ee4bd asan: heap buffer overflow in _bfd_vms_slurp_egsd adds 40b119304e Re: elf: Allow mixed ordered/unordered inputs for non-reloca [...] adds 5f8c2a1507 Update config.sub and config.guess adds d750c713c9 Update libiberty with latest sources from gcc mainline adds c8bad65eee is_relocatable_executable --exclude-libs failure adds b281a04ff0 ld sysroot-prefix test fails adds b5ff370e96 Fix TUI source window drawing adds 1b6d4bb223 Redraw both spaces between line numbers and source code adds 5519536196 Prevent flickering when redrawing the TUI source window adds b09ad6eae9 libctf: do not print array declarators backwards adds 57f97d0e6d libctf, ld: CTF dumper changes for consistency adds 91e7ce2fd7 libctf, ld: more dumper improvements adds ffeece6ac2 libctf, ld: prohibit getting the size or alignment of forwards adds 37002871ac libctf, ld: dump enums: generally improve dump formatting adds 1038406a8f libctf: rip out BFD_DEPENDENCIES / BFD_LIBADD adds c59e30ed17 libctf: new testsuite adds 9bc769718d libctf: new test of enum lookups with the _next iterator adds abed0b0718 libctf: warn about information loss because of unreleased fo [...] adds 6c3a38777b libctf, include: support unnamed structure members better adds 8769046e5a libctf: remove outdated comment about parent dict importing adds abe4ca69a1 libctf: fix lookups of pointers by name in parent dicts adds 608a333d7d libctf: fix old ChangeLog typo adds b4b6ea4680 libctf, ld: fix formatting of forwards to unions and enums adds 70d3120f32 libctf, testsuite: don't run without a suitable compiler adds 0814dbfbfc libctf, testsuite: adjust for real return type of ctf_member_count adds 85dd67bd6d Automatic date update in version.in adds 0c7f5bd08c sim: h8300: simplify testsuite runner adds a2f8e947a8 sim: h8300: fix test mach markers adds c004e77f7d sim: testsuite: delete unused Make-common.in file adds 865288236d sim: fr30: delete unused testsuite adds fbc09e7af7 RISC-V: Implement support for big endian targets. adds f36ce378b4 RISC-V: Fix riscv gas/ld testsuites failures for big endian. adds 286d2f2cd7 RISC-V: Mention -mbig-endian and -mlittle-endian in doc adds 22206e847d gas APP macro tests adds 73624512cf ld rgn-at10 and rgn-at11 test adds 3677b72961 sparc-sun-solaris2 and sparc64-sun-solaris2 config adds 85f55c2b75 sparc-elf ld test fails adds 599c86c4a5 score-elf binutils-all/strip-13 fail adds 4b186f88b8 gdbsupport: common-utils.h: fix typo in header adds 3c55062cc1 gdb/testsuite: fix race in gdb.threads/signal-while-stepping [...] adds b49180acf2 Fix fixed-point binary operation type handling adds 1606216201 config.sub update broke powerpc-eabivle adds 4018f4e0fc ld pr22471 test fails adds f526791a6f Regen ld/po/BLD-POTFILES.in adds e2ede46cb2 Automatic date update in version.in adds 6987d5a1bb binutils/readelf.c: Correct grammar in comment adds d4e57b87a3 bfin: Check bfd_link_hash_indirect adds 2652cfad8d RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructio [...] adds 1861f7cfbf sim: cris: fix C tests with newer toolchains adds 9446bcf6be fix paths in ChangeLog adds 4d4490b8d7 ld: xfail riscv64*-*-* for ld-scripts/empty-address-2 tests. adds aa881ecde4 RISC-V: Add pause hint instruction. adds 78e4948694 [gdb/build] Fix gdbserver build with -fsanitize=address adds 17d60030ae Fix another path length problem opening files on Win32 systems. adds d4813f1046 Fix regression in Ada aggregate assignment adds 8e604ff077 xfail more cases of complaints about relocs in read-only sections adds dc20061339 sh-pe ld XPASSes adds 959d6a673e Fix regression in Ada do_full_match adds 3b288c8e2e m68k: Require m68020up rather than m68000up for CHK.L instruction. adds d1bcae833b ELF: Don't generate unused section symbols adds 1b0927db3c Updated French translation for the opcodes/ subdirectory. adds f478212851 libtool.m4: update GNU/Hurd test from upstream. In upstream [...] adds e904f56d02 gdb/sim: add support for exporting memory map adds bfc7d04afb sim: h8300: delete opcode caching adds a39487c668 sim: cris: use -sim with C tests for cris-elf targets adds e6c1dbbfe8 sim: cris: disable test that crashes the linker adds 0f8e278da2 sim: ChangeLog: move arch-specific entries into the arch dir adds 9a50f40e82 Automatic date update in version.in adds f4cfa91741 sim: ppc: stub out sim_memory_map adds e343681375 gdb/fortran: Correct the lval type for array elements of int [...] adds 1940319c0e [gdb] Fix internal-error in process_event_stop_test adds fb932b57cb Treat the AArch64 register id_aa64mmfr2_el1 as a core system [...] adds e84c871648 Fix places in the AArch64 opcodes library code where a call [...] adds 3c8c6de21d gdb: user variables with components of dynamic type adds ed20522215 Updated Swedish translation for the opcodes/ subdirectory adds d00f086803 gdb: add missing test for completion of invalid /FMT strings adds 6abd4cf281 gdb: check for empty strings in get_standard_cache_dir/get_s [...] adds 8fc48b7961 Pass void_context_p to parse_expression adds 46f900c065 sim: require a C11 compiler adds a7e906e8f5 Automatic date update in version.in adds 6430704567 configure regen adds aae7fcb8d7 POWER10: Add Return-Oriented Programming instructions adds b1b29aa51a elf: Verify section size for mixed ordered/unordered inputs adds ba9e922fa0 ld/x86-64: Also set LAM_U57 when setting LAM_U48 adds ce0be4070f sim: common: add missing stdlib.h for abort() adds 055bc77a80 Add Changelog entries and NEWS entries for 2.36 branch adds 573fe3fbc1 Change version number to 2.36.50 and regenerate files adds be2c78856d Update release howto with 2.37 numbers adds b5a4a01af4 sim: hw: rework code to avoid gcc warnings adds f41464416a sim: pru: fix include ordering with sim-main.h adds 0a94990bf6 ld/x86-64: Properly Handle -z lam-u48/lam-u57 adds bf470982f9 sim: enable -Werror by default for some arches adds 50df264dae sim: clean up stale AC_PREREQ refs adds f8cab0b995 sim: sh64: delete port adds f074c07d8d sim: common: clean up asprintf includes a bit adds 7eb99e5e27 sim: cr16/d10v: move storage out of header adds a9fd212a24 sim: replace rindex with strrchr adds 50ad1254d5 GCC: Pass --plugin to AR and RANLIB adds a4966cd965 Binutils: Pass --plugin to AR and RANLIB adds af019bfde9 Support the PGO build for binutils+gdb adds 66beed0227 Fix erroneous agent expression test adds bc167b6b3e Remove a use of print_expression adds 54585eee2e Avoid crash in compile_to_object adds 5834526f4b Automatic date update in version.in adds 46b1518d4c Automatic date update in version.in adds a8aa72b913 Updated translations for multiple subdirectories adds 68ed285428 sim: clean up C11 header includes adds 933306703a sim: rl78: move storage out of header adds 90e123dd60 sim: common: fix printf formats adds a0c38f0d70 sim: or1k: fix include ordering with sim-main.h adds 5c1008a41f sim: call SIM_AC_OPTION_WARNINGS(no) in remaining ports adds 9c70334dee sim: always call SIM_AC_OPTION_WARNINGS adds c0f6e439cc Add support for more MIPS variants to the linker command line. adds 82c70b08df aarch64: Remove support for CSRE adds 10dadadc5b [gdb/testsuite] Fix gdb.arch/amd64-stap-three-arg-disp.S adds 062eaacbac gdb: change jit_debug to a bool adds eef401dce1 gdb: convert solib-aix to new-style debug macros adds c6185dce03 gdb: convert aarch64 to new-style debug macros adds 254c3783fe sim: tests: get common tests working again adds eabdd87b2e Automatic date update in version.in adds 03c02f3116 GCC: Check if AR works with --plugin and rc adds 83b33c6cb9 Binutils: Check if AR works with --plugin and rc adds 44124a4683 binuitils: Check if AR is usable for LTO build adds f631b79abe sim: or1k: delete redundant SIM_AC_OPTION_INLINE call adds f220ef633c sim: common: use #error properly adds 68895f7d7e sim: README-HACKING: clean up stale run references adds 5e9e2f41eb sim: or1k: clean up stale build entries adds e998918e98 sim: or1k: fix mixing of code & decl warning adds 7c654b719d gdb/fortran: add symbol base comparison operators adds ce38f5edf1 gdb: fix debug dump of OP_BOOL expressions adds 6d104cac0a Updated translations for some subdirectories adds c2e9a4a3ed elf/x86-64: Adjust R_AMD64_DIR64/R_AMD64_DIR32 for PE/x86-64 inputs adds 18bfb5057f [gdb/testsuite] Require is_amd64_regs_target in gdb.base/dis [...] adds d546b61084 Implement a workaround for GNU mak jobserver adds 5291fe3cd1 aarch64: Add support for bfloat16 in gdb. adds b2f2ae0d6f gdb: remove pre_init_ui_hook from top.c adds 3f94e58859 [gdb/testsuite] Add have_mpx in lib/gdb.exp adds 16e9019ef7 gdb: move baud_rate and serial_parity declarations to serial.h adds fe7a351a8e gdb: move read{now,never}_symbol_files declarations to symfile.h adds 24a7f1b548 gdb: fix indentation in infrun.c adds 3034143dc6 src-release: fix indentation adds 4180301e81 Automatic date update in version.in adds 62fe7512a7 sim: watch: fix pc watchpoints on little endian host systems adds c54f3efdc2 sim: watch: fix range expression processing adds 2ce40d1a51 Add SEH support to code generated by dlltool. adds 8c4645b488 Remove sflag_info param from wild callback functions adds b209b5a6b8 SHF_LINK_ORDER fixup_link_order in ld adds 5347ed60c5 Regen Makefile.in for jobserver.m4 aclocal.m4 dependency adds 844bf810cf x86: Don't generate GOT_symbol for PLT relocations adds b634d11d61 ld: Check for ELF input before accessing ELF section data adds 54ca900277 gdb: convert jit to new-style debug macros adds 5e12f48ffb gdb: bool-ify file_is_auto_load_safe adds db972fce46 gdb: bool-ify ext_lang_auto_load_enabled and friends adds 5bf7e91b2b gdb: bool-ify users of file_is_auto_load_safe adds 506195754c gdb: bool-ify maybe_add_script_{text,file} adds fb0f5031bb gdb: turn arc_debug into a bool adds d8d1feb424 gdb: convert arc to new-style debug macros adds 4120e4885b Re: SHF_LINK_ORDER fixup_link_order in ld adds 3eeabe12c3 Automatic date update in version.in adds c9d220893e gdb: make the remote target track its own thread resume state adds bd497355ea gdb: remove target_ops::commit_resume implementation in reco [...] adds 8f66807b98 gdb: better handling of 'S' packets adds d9b1deff13 sim: watch: add basic default handler that traps adds 54780889e9 sim: h8300: drop separate eightbit memory buffer adds adb0bd8fda gas: bfin: fix build time warnings adds abad28152e gas: bfin: build lexer with -Werror adds 271bea6acd ld: tests: add -msim when testing bfin targets adds 7e0d77ef5f Fix an illegal memory access parsing a win32pstatus note wit [...] adds 116d0cf103 [gdb/testsuite] Fix gdb.base/style.exp with -m32 adds 5fae2a2c66 [gdb/breakpoint] Handle .plt.sec in in_plt_section adds 5a10699ff3 Updated translations for some subdirectories adds 8ca9c7eb67 bfin: Skip non SEC_ALLOC section for R_BFIN_FUNCDESC adds 58eadc4b69 Fix building gdb with gcc-4.x adds c14dee84dd Update my email address (long overdue!) adds 17e8913732 Add myself to gdb/MAINTAINERS adds 5aa06b1b14 Automatic date update in version.in adds 5fda40b28f gas: make [248]byte directives available everywhere adds 3624a6c15c PR26539, memory leak in inflate.c adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status adds 7cf91a2481 sim: m32r: clean up redundant test coverage adds 89bfc2a429 sim: frv: clean up redundant test coverage adds 137d6efd8a sim: mips: delete empty stub test dir adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness adds bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 adds 5a11fff005 gdb/tui: compare pointer to nullptr, not 0 adds e403a898b5 Automatic date update in version.in adds 1368b914e9 sim: testsuite: flatten tree adds eb6e6af8c1 PR26002 undefined symbol VER_NDX_GLOBAL vs. VER_NDX_LOCAL adds ad92f33d38 Tidy inflateEnd calls adds 68b007788a ld/x86: Add -z report-relative-reloc adds 75a933f399 ld/elf/x86: Don't compare IFUNC address in the shared object adds 514fca98df Automatic date update in version.in No new revisions were added by this update. Summary of changes: ChangeLog | 159 + Makefile.def | 4 +- Makefile.in | 81 +- Makefile.tpl | 63 +- bfd/ChangeLog | 295 + bfd/Makefile.in | 1 + bfd/aclocal.m4 | 1 + bfd/aix386-core.c | 1 + bfd/aout-target.h | 1 + bfd/bfd-in2.h | 24 +- bfd/bfdio.c | 23 +- bfd/binary.c | 1 + bfd/cisco-core.c | 2 + bfd/coff-alpha.c | 1 + bfd/coff-i386.c | 4 +- bfd/coff-ia64.c | 1 + bfd/coff-mips.c | 3 + bfd/coff-rs6000.c | 2 + bfd/coff-sh.c | 2 + bfd/coff-tic30.c | 1 + bfd/coff-tic54x.c | 26 + bfd/coff-x86_64.c | 2 + bfd/coff64-rs6000.c | 2 + bfd/coffcode.h | 3 + bfd/compress.c | 3 +- bfd/config.bfd | 17 +- bfd/configure | 87 +- bfd/configure.ac | 4 + bfd/doc/Makefile.in | 1 + bfd/elf-linker-x86.h | 3 + bfd/elf.c | 20 +- bfd/elf32-bfin.c | 245 +- bfd/elf32-i386.c | 36 + bfd/elf32-score.c | 10 +- bfd/elf32-score7.c | 10 +- bfd/elf64-x86-64.c | 33 + bfd/elfcode.h | 8 +- bfd/elflink.c | 256 +- bfd/elfnn-riscv.c | 425 +- bfd/elfxx-riscv.c | 56 +- bfd/elfxx-riscv.h | 4 +- bfd/elfxx-target.h | 6 + bfd/elfxx-x86.c | 72 +- bfd/elfxx-x86.h | 7 + bfd/hppabsd-core.c | 1 + bfd/hpux-core.c | 1 + bfd/i386msdos.c | 1 + bfd/ihex.c | 1 + bfd/irix-core.c | 1 + bfd/mach-o-target.c | 1 + bfd/mmo.c | 1 + bfd/netbsd-core.c | 1 + bfd/osf-core.c | 1 + bfd/pdp11.c | 1 + bfd/pef.c | 2 + bfd/plugin.c | 1 + bfd/po/bfd.pot | 2574 +-- bfd/po/fr.po | 2666 +-- bfd/po/pt.po | 2681 ++-- bfd/po/sr.po | 2687 ++-- bfd/po/uk.po | 2666 +-- bfd/ppcboot.c | 1 + bfd/ptrace-core.c | 1 + bfd/reloc.c | 7 + bfd/sco5-core.c | 1 + bfd/section.c | 7 +- bfd/som.c | 1 + bfd/srec.c | 2 + bfd/syms.c | 3 + bfd/targets.c | 18 + bfd/tekhex.c | 1 + bfd/trad-core.c | 1 + bfd/verilog.c | 1 + bfd/version.h | 2 +- bfd/version.m4 | 2 +- bfd/vms-alpha.c | 4 +- bfd/vms-lib.c | 1 + bfd/wasm-module.c | 1 + bfd/xsym.c | 1 + binutils/BRANCHES | 1 + binutils/ChangeLog | 97 + binutils/MAINTAINERS | 6 +- binutils/Makefile.in | 1 + binutils/NEWS | 2 + binutils/README-how-to-make-a-release | 40 +- binutils/aclocal.m4 | 1 + binutils/configure | 85 +- binutils/configure.ac | 2 + binutils/dlltool.c | 50 +- binutils/doc/Makefile.in | 1 + binutils/objcopy.c | 24 + binutils/po/binutils.pot | 3317 ++-- binutils/po/fr.po | 3826 +++-- binutils/po/pt.po | 3943 ++--- binutils/po/sr.po | 3845 +++-- binutils/po/sv.po | 3804 +++-- binutils/po/uk.po | 3840 +++-- binutils/readelf.c | 10 +- binutils/testsuite/binutils-all/readelf.exp | 6 +- binutils/testsuite/binutils-all/readelf.s-64 | 2 +- .../{readelf.s-64 => readelf.s-64-unused} | 0 binutils/testsuite/binutils-all/readelf.ss | 5 +- binutils/testsuite/binutils-all/readelf.ss-64 | 5 +- .../{readelf.ss-64 => readelf.ss-64-unused} | 0 .../binutils-all/{readelf.ss => readelf.ss-unused} | 0 binutils/testsuite/lib/binutils-common.exp | 31 + config.guess | 272 +- config.sub | 638 +- config/ChangeLog | 19 + config/gcc-plugin.m4 | 40 + config/jobserver.m4 | 24 + configure | 246 +- configure.ac | 84 + cpu/ChangeLog | 4 + elfcpp/ChangeLog | 4 + gas/ChangeLog | 223 + gas/Makefile.am | 4 +- gas/Makefile.in | 5 +- gas/NEWS | 10 +- gas/aclocal.m4 | 1 + gas/config/bfin-lex.l | 5 +- gas/config/obj-elf.c | 7 +- gas/config/tc-aarch64.c | 31 - gas/config/tc-i386.c | 39 +- gas/config/tc-riscv.c | 569 +- gas/config/tc-riscv.h | 8 +- gas/configure | 85 +- gas/configure.ac | 2 + gas/configure.tgt | 4 +- gas/doc/Makefile.in | 1 + gas/doc/as.texi | 8 +- gas/doc/c-aarch64.texi | 2 - gas/doc/c-riscv.texi | 8 + gas/po/fr.po | 7239 ++++----- gas/po/gas.pot | 2131 +-- gas/po/uk.po | 7237 ++++----- gas/read.c | 6 + gas/subsegs.c | 4 + gas/testsuite/gas/aarch64/csre-invalid.d | 3 - gas/testsuite/gas/aarch64/csre-invalid.s | 6 - gas/testsuite/gas/aarch64/csre.d | 29 - gas/testsuite/gas/aarch64/csre_csr-invalid.d | 3 - gas/testsuite/gas/aarch64/csre_csr-invalid.l | 2 - gas/testsuite/gas/aarch64/csre_csr-invalid.s | 4 - gas/testsuite/gas/aarch64/csre_csr.d | 10 - gas/testsuite/gas/aarch64/csre_csr.s | 4 - gas/testsuite/gas/cfi/cfi-label.d | 4 +- gas/testsuite/gas/elf/elf.exp | 6 +- gas/testsuite/gas/elf/section2.e | 7 - .../gas/elf/{section2.e => section2.e-unused} | 0 gas/testsuite/gas/elf/symver.d | 4 - gas/testsuite/gas/i386/i386.exp | 4 + gas/testsuite/gas/i386/ilp32/elf/symver.d | 4 - gas/testsuite/gas/i386/ilp32/x86-64-size-1.d | 24 +- gas/testsuite/gas/i386/ilp32/x86-64-size-3.d | 16 +- gas/testsuite/gas/i386/ilp32/x86-64-size-5.d | 12 +- gas/testsuite/gas/i386/ilp32/x86-64-unwind.d | 6 +- gas/testsuite/gas/i386/no-got.d | 17 + gas/testsuite/gas/i386/no-got.s | 5 + gas/testsuite/gas/i386/size-1.d | 24 +- gas/testsuite/gas/i386/size-3.d | 16 +- gas/testsuite/gas/i386/svr4.d | 3 - gas/testsuite/gas/i386/x86-64-no-got.d | 17 + gas/testsuite/gas/i386/x86-64-no-got.s | 5 + gas/testsuite/gas/i386/x86-64-size-1.d | 24 +- gas/testsuite/gas/i386/x86-64-size-3.d | 16 +- gas/testsuite/gas/i386/x86-64-size-5.d | 12 +- gas/testsuite/gas/i386/x86-64-unwind.d | 10 +- gas/testsuite/gas/macros/app1.d | 1 + gas/testsuite/gas/macros/app2.d | 1 + gas/testsuite/gas/macros/app3.d | 1 + gas/testsuite/gas/macros/app4.d | 1 + gas/testsuite/gas/ppc/ppc.exp | 2 + gas/testsuite/gas/ppc/rop-checks.d | 3 + gas/testsuite/gas/ppc/rop-checks.l | 17 + gas/testsuite/gas/ppc/rop-checks.s | 18 + gas/testsuite/gas/ppc/rop.d | 27 + gas/testsuite/gas/ppc/rop.s | 21 + gas/testsuite/gas/riscv/bitmanip-insns-32.d | 37 + gas/testsuite/gas/riscv/bitmanip-insns-64.d | 55 + gas/testsuite/gas/riscv/bitmanip-insns.s | 58 + gas/testsuite/gas/riscv/li32.d | 2 +- gas/testsuite/gas/riscv/li64.d | 2 +- gas/testsuite/gas/riscv/lla32.d | 2 +- gas/testsuite/gas/riscv/lla64.d | 2 +- gas/testsuite/gas/riscv/march-ok-g2.d | 2 +- gas/testsuite/gas/riscv/march-ok-g2_p1.d | 2 +- gas/testsuite/gas/riscv/march-ok-g2p0.d | 2 +- gas/testsuite/gas/riscv/march-ok-i2p0.d | 2 +- gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d | 2 +- .../gas/riscv/march-ok-nse-with-version.d | 2 +- gas/testsuite/gas/riscv/march-ok-two-nse.d | 2 +- gas/testsuite/gas/riscv/pause.d | 10 + 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sim/testsuite/{sim => }/bfin/c_compi2opd_dr_eq_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_eq_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags.S (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imgebl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imltbl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lz_inc_dec.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imgebl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imltbl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lz_inc_dec.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0_pm_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0a1s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_abs_a.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_neg_a.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_absabs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_negneg.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_abs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_absabs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_alhwx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_awx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop1ew.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop2.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop3.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_bytepack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteunpack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_disalnexcpt.s (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd12_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd20_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd20_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rlh_rnd.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rr_lph_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm_aa.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft_x.s 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rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_a0alr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align16.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align24.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_l.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expexp_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_lp.s (100%) rename sim/testsuite/{sim => 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=> }/bfin/c_ldst_st_p_d_pp_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_xh.s (100%) rename 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(100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_bot.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_prelc.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_top.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_overlap.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc0.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc1.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc0.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc1.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_stld.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_prelc.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_topbotcntr.s (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_interr_ctl.s (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_loop.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_loop_user_except.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_ppop_illegal_adr.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_ppopm_illegal_adr.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_supervisor.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user_superivsor.S (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ld_ld.s (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pcpr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_clisti_interr.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_csync_mmr.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_except_rtx.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pcpr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_nop.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_raise_rt_i_n.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_rts.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_neg_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_sft_2_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_shadd_1_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp_pair.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_acc_acc.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dag_lz_dep.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_acc_acc.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dep_nostall.s (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/bfin/c_seq_dec_raise_pushpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_brcc_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_call_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_j_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_brcc_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_call_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_j_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_brcc_mp_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_mmr_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_mmrj_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_raise_mmr_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_raise_mmrj_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_brcc_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmr_mvp.S (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/frv/cknc.cgs (100%) rename sim/testsuite/{sim => }/frv/ckne.cgs (100%) rename sim/testsuite/{sim => }/frv/ckno.cgs (100%) rename sim/testsuite/{sim => }/frv/cknv.cgs (100%) rename sim/testsuite/{sim => }/frv/ckp.cgs (100%) rename sim/testsuite/{sim => }/frv/ckra.cgs (100%) rename sim/testsuite/{sim => }/frv/ckv.cgs (100%) rename sim/testsuite/{sim => }/frv/cld.cgs (100%) rename sim/testsuite/{sim => }/frv/cldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/cldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldd.cgs (100%) rename sim/testsuite/{sim => }/frv/clddf.cgs (100%) rename sim/testsuite/{sim => }/frv/clddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/clddu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldf.cgs (100%) rename sim/testsuite/{sim => }/frv/cldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/cldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldq.cgs (100%) rename sim/testsuite/{sim => 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(100%) rename sim/testsuite/{sim => }/frv/cscan.cgs (100%) rename sim/testsuite/{sim => }/frv/csdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/csll.cgs (100%) rename sim/testsuite/{sim => }/frv/csllcc.cgs (100%) rename sim/testsuite/{sim => }/frv/csmul.cgs (100%) rename sim/testsuite/{sim => }/frv/csmulcc.cgs (100%) rename sim/testsuite/{sim => }/frv/csra.cgs (100%) rename sim/testsuite/{sim => }/frv/csracc.cgs (100%) rename sim/testsuite/{sim => }/frv/csrl.cgs (100%) rename sim/testsuite/{sim => }/frv/csrlcc.cgs (100%) rename sim/testsuite/{sim => }/frv/cst.cgs (100%) rename sim/testsuite/{sim => }/frv/cstb.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstd.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdu.cgs (100%) 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=> }/frv/fabsd.cgs (100%) rename sim/testsuite/{sim => }/frv/fabss.cgs (100%) rename sim/testsuite/{sim => }/frv/faddd.cgs (100%) rename sim/testsuite/{sim => }/frv/fadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fbeq.cgs (100%) rename sim/testsuite/{sim => }/frv/fbeqlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbge.cgs (100%) rename sim/testsuite/{sim => }/frv/fbgelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbgt.cgs (100%) rename sim/testsuite/{sim => }/frv/fbgtlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fble.cgs (100%) rename sim/testsuite/{sim => }/frv/fblelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fblg.cgs (100%) rename sim/testsuite/{sim => }/frv/fblglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fblt.cgs (100%) rename sim/testsuite/{sim => }/frv/fbltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbne.cgs (100%) rename sim/testsuite/{sim => }/frv/fbnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbno.cgs (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/frv/fmovd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmss.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuld.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegd.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fnop.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/addss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr400/csdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maveh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/scutss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/slass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smsss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/subss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcpl.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcul.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs (100%) rename sim/testsuite/{sim => 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rename sim/testsuite/{sim => }/frv/fr550/maddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/frv/ftige.cgs (100%) rename sim/testsuite/{sim => }/frv/ftigt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftile.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftine.cgs (100%) rename sim/testsuite/{sim => }/frv/ftino.cgs (100%) rename sim/testsuite/{sim => }/frv/ftio.cgs (100%) rename sim/testsuite/{sim => }/frv/ftira.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiu.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiue.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiug.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiuge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiul.cgs (100%) rename sim/testsuite/{sim => }/frv/ftle.cgs (100%) rename sim/testsuite/{sim => }/frv/ftlg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftlt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftne.cgs (100%) rename sim/testsuite/{sim => }/frv/ftno.cgs (100%) rename sim/testsuite/{sim => }/frv/fto.cgs (100%) rename sim/testsuite/{sim => }/frv/ftra.cgs (100%) rename sim/testsuite/{sim => }/frv/ftu.cgs (100%) rename sim/testsuite/{sim => }/frv/ftue.cgs (100%) rename sim/testsuite/{sim => }/frv/ftug.cgs (100%) rename sim/testsuite/{sim => }/frv/ftuge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftul.cgs (100%) rename sim/testsuite/{sim => }/frv/ftule.cgs (100%) create mode 100644 sim/testsuite/frv/grloop.ms create mode 100644 sim/testsuite/frv/hello.ms rename sim/testsuite/{sim => }/frv/icei.cgs (100%) rename sim/testsuite/{sim => }/frv/ici.cgs (100%) rename sim/testsuite/{sim => }/frv/icpl.cgs (100%) rename sim/testsuite/{sim => }/frv/icul.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts.exp (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr400.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr500.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign-fr550.cgs (100%) rename sim/testsuite/{sim => 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=> }/frv/interrupts/shadow_regs.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/timer.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpil.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.pcgs (100%) rename sim/testsuite/{sim => }/frv/ld.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldd.cgs (100%) rename sim/testsuite/{sim => }/frv/lddc.cgs (100%) rename sim/testsuite/{sim => }/frv/lddcu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddf.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldq.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsh.cgs (100%) rename sim/testsuite/{sim => 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}/frv/mcmpuh.cgs (100%) rename sim/testsuite/{sim => }/frv/mcop1.cgs (100%) rename sim/testsuite/{sim => }/frv/mcop2.cgs (100%) rename sim/testsuite/{sim => }/frv/mcplhi.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpli.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutss.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mdrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdunpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/membar.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhd.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhw.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/mhtob.cgs (100%) create mode 100644 sim/testsuite/frv/misc.exp rename sim/testsuite/{sim => }/frv/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mnop.cgs (100%) rename sim/testsuite/{sim => }/frv/mnot.cgs (100%) rename sim/testsuite/{sim => }/frv/mor.cgs (100%) rename sim/testsuite/{sim => }/frv/mov.cgs (100%) rename sim/testsuite/{sim => }/frv/movfg.cgs (100%) rename sim/testsuite/{sim => }/frv/movfgd.cgs (100%) rename sim/testsuite/{sim => }/frv/movfgq.cgs (100%) rename sim/testsuite/{sim => }/frv/movgf.cgs (100%) rename sim/testsuite/{sim => }/frv/movgfd.cgs (100%) rename sim/testsuite/{sim => }/frv/movgfq.cgs (100%) rename sim/testsuite/{sim => }/frv/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/mpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mqlclrhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqlmths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsaths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotri.cgs (100%) rename sim/testsuite/{sim => }/frv/msaths.cgs (100%) rename sim/testsuite/{sim => }/frv/msathu.cgs (100%) rename sim/testsuite/{sim => }/frv/msllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrlhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mtrap.cgs (100%) rename sim/testsuite/{sim => }/frv/munpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mwcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mwcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mwtacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mwtaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mxor.cgs (100%) rename sim/testsuite/{sim => }/frv/nandcr.cgs (100%) rename sim/testsuite/{sim => }/frv/nandncr.cgs (100%) rename sim/testsuite/{sim => }/frv/nfadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdadds.cgs (100%) rename sim/testsuite/{sim => }/frv/nfdcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/nfddivs.cgs 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=> }/frv/nfstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/nfsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/nld.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldd.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddf.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddi.cgs (100%) rename sim/testsuite/{sim => }/frv/nlddu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhfi.cgs (100%) rename sim/testsuite/{sim => }/frv/nldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/nldi.cgs (100%) rename sim/testsuite/{sim => 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3 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-O2 updated (a1a864a2 -> 7d531686)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-O2 in repository toolchain/ci/base-artifacts. discards a1a864a2 3: update: binutils-gcc-glibc: 1 new 7d531686 3: update: binutils-glibc: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (a1a864a2) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 130 +- 02-prepare_abe/console.log | 434 +- 03-build_abe-binutils/console.log | 10758 +-- 04-build_abe-stage1/console.log | 19992 +++-- 05-build_abe-linux/console.log | 1996 +- 06-build_abe-glibc/console.log | 39684 +++++---- 07-build_abe-stage2/console.log | 40363 +++++---- 09-benchmark--O2_marm/benchmark-start.log | 2 +- 09-benchmark--O2_marm/benchmark.log | 12 +- 09-benchmark--O2_marm/console.log | 201 +- 10-check_regression/console.log | 3646 +- 10-check_regression/results-0.csv | 3303 +- 10-check_regression/results-1.csv | 3224 +- 10-check_regression/results-brief.csv | 58 +- 10-check_regression/results-compare.csv | 6 +- 10-check_regression/results-full.csv | 3490 +- 10-check_regression/results.csv | 240 +- 10-check_regression/results.log | 4370 +- 11-update_baseline/console.log | 7354 +- 11-update_baseline/results-1.csv | 3224 +- 11-update_baseline/results-brief.csv | 56 +- 11-update_baseline/results-compare.csv | 3 +- 11-update_baseline/results-full.csv | 3222 +- 11-update_baseline/results.csv | 238 +- 11-update_baseline/results.log | 3276 +- 11-update_baseline/results.regressions | 2 +- console.log | 124808 +++++++++++++-------------- jenkins/manifest.sh | 18 +- results_id | 2 +- 29 files changed, 136774 insertions(+), 137338 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-check_binutils updated (3624a6c15c -> edf0f284b1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-check_binutils in repository toolchain/ci/binutils-gdb. from 3624a6c15c PR26539, memory leak in inflate.c adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status adds 7cf91a2481 sim: m32r: clean up redundant test coverage adds 89bfc2a429 sim: frv: clean up redundant test coverage adds 137d6efd8a sim: mips: delete empty stub test dir adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness adds bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 adds 5a11fff005 gdb/tui: compare pointer to nullptr, not 0 adds e403a898b5 Automatic date update in version.in adds 1368b914e9 sim: testsuite: flatten tree adds eb6e6af8c1 PR26002 undefined symbol VER_NDX_GLOBAL vs. VER_NDX_LOCAL adds ad92f33d38 Tidy inflateEnd calls adds 68b007788a ld/x86: Add -z report-relative-reloc adds 75a933f399 ld/elf/x86: Don't compare IFUNC address in the shared object adds 514fca98df Automatic date update in version.in new edf0f284b1 PR binutils/23460: Increase the max number of open files to 20 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. 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include/opcode/riscv-opc.h | 16 +- include/opcode/riscv.h | 127 +- ld/ChangeLog | 49 + ld/NEWS | 3 + ld/emulparams/elf32_x86_64.sh | 1 + ld/emulparams/elf_i386.sh | 1 + ld/emulparams/elf_x86_64.sh | 1 + ld/emulparams/x86-report-relative.sh | 11 + ld/ld.texi | 4 + ld/testsuite/ld-elfvers/vers16.dsym | 2 +- ld/testsuite/ld-elfvers/vers6.dsym | 2 +- ld/testsuite/ld-i386/i386.exp | 1 + ld/testsuite/ld-i386/report-reloc-1.d | 10 + ld/testsuite/ld-i386/report-reloc-1.l | 2 + ld/testsuite/ld-i386/report-reloc-1.s | 12 + ld/testsuite/ld-ifunc/ifunc.exp | 22 +- ld/testsuite/ld-ifunc/pr23169a.c | 2 +- ld/testsuite/ld-plugin/lto.exp | 2 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-01.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-02.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-03.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-04.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-05.d | 4 +- .../ld-riscv-elf/attr-merge-priv-spec-failed-06.d | 4 +- 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}/sh/shlr2.s | 0 sim/testsuite/{sim => }/sh/shlr8.s | 0 sim/testsuite/{sim => }/sh/swap.s | 0 sim/testsuite/{sim => }/sh/testutils.inc | 0 sim/testsuite/sim/cris/ChangeLog | 197 -- sim/testsuite/sim/cris/c/c.exp | 248 -- sim/testsuite/sim/cris/hw/rv-n-cris/rvc.exp | 249 -- sim/testsuite/sim/frv/ChangeLog | 76 - sim/testsuite/sim/m32r/ChangeLog | 122 - sim/testsuite/{sim => }/v850/ChangeLog | 0 sim/testsuite/{sim => }/v850/allinsns.exp | 0 sim/testsuite/{sim => }/v850/bsh.cgs | 0 sim/testsuite/{sim => }/v850/div.cgs | 0 sim/testsuite/{sim => }/v850/divh.cgs | 0 sim/testsuite/{sim => }/v850/divh_3.cgs | 0 sim/testsuite/{sim => }/v850/divhu.cgs | 0 sim/testsuite/{sim => }/v850/divu.cgs | 0 sim/testsuite/{sim => }/v850/sar.cgs | 0 sim/testsuite/{sim => }/v850/satadd.cgs | 0 sim/testsuite/{sim => }/v850/satsub.cgs | 0 sim/testsuite/{sim => }/v850/satsubi.cgs | 0 sim/testsuite/{sim => }/v850/satsubr.cgs | 0 sim/testsuite/{sim => }/v850/shl.cgs | 0 sim/testsuite/{sim => }/v850/shr.cgs | 0 sim/testsuite/{sim => }/v850/testutils.cgs | 0 sim/testsuite/{sim => }/v850/testutils.inc | 0 3006 files changed, 4914 insertions(+), 20383 deletions(-) create mode 100644 ld/emulparams/x86-report-relative.sh create mode 100644 ld/testsuite/ld-i386/report-reloc-1.d create mode 100644 ld/testsuite/ld-i386/report-reloc-1.l create mode 100644 ld/testsuite/ld-i386/report-reloc-1.s create mode 100644 ld/testsuite/ld-x86-64/report-reloc-1-x32.d create mode 100644 ld/testsuite/ld-x86-64/report-reloc-1.d create mode 100644 ld/testsuite/ld-x86-64/report-reloc-1.l create mode 100644 ld/testsuite/ld-x86-64/report-reloc-1.s rename sim/testsuite/{sim => }/aarch64/ChangeLog (100%) rename sim/testsuite/{sim => }/aarch64/adds.s (100%) rename sim/testsuite/{sim => }/aarch64/addv.s (100%) rename sim/testsuite/{sim => }/aarch64/allinsn.exp (100%) rename sim/testsuite/{sim => }/aarch64/bit.s (100%) rename sim/testsuite/{sim => }/aarch64/cmtst.s (100%) rename sim/testsuite/{sim => }/aarch64/cnt.s (100%) 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(100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_a0alr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align16.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align24.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_l.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expexp_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_pack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmaxvmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_a0alr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_except_illopcode.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_user_mode.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable_enable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_loopsetup_stld.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nested.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nmi.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_reload.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tcount.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tscale.S (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drlo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_pibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_ppmm_hbx.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_hi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_lo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_h_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_lohi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_hi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_lo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_lohi.s (100%) rename sim/testsuite/{sim => }/bfin/c_linkage.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_alshft_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_arith_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bitclr.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bitset.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bittgl.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bittst.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft_astat.S (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft_astat.S (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_nbittst.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_bot.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_prelc.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_top.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_overlap.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc0.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc1.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc0.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc1.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_stld.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_prelc.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_topbotcntr.s (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_interr_ctl.s (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_loop.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_loop_user_except.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_ppop_illegal_adr.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_ppopm_illegal_adr.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_supervisor.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user_superivsor.S (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ld_ld.s (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pcpr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_clisti_interr.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_csync_mmr.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_except_rtx.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pcpr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_nop.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_raise_rt_i_n.S (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_rts.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_neg_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_sft_2_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_shadd_1_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp_pair.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_acc_acc.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dag_lz_dep.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_acc_acc.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dep_nostall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_imlb.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_dr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dep_nostall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dep_stall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_imlb.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dep_nostall.s (100%) rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dep_stall.s (100%) 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sim/testsuite/{sim => }/frv/fitod.cgs (100%) rename sim/testsuite/{sim => }/frv/fitos.cgs (100%) rename sim/testsuite/{sim => }/frv/fmad.cgs (100%) rename sim/testsuite/{sim => }/frv/fmaddd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fmas.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmss.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuld.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegd.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fnop.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/addss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr400/csdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maveh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/scutss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/slass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smsss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/subss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcpl.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcul.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs (100%) rename sim/testsuite/{sim => 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(100%) rename sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/dcpl.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/dcul.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mabshs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs (100%) rename sim/testsuite/{sim => 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(100%) rename sim/testsuite/{sim => }/frv/ftle.cgs (100%) rename sim/testsuite/{sim => }/frv/ftlg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftlt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftne.cgs (100%) rename sim/testsuite/{sim => }/frv/ftno.cgs (100%) rename sim/testsuite/{sim => }/frv/fto.cgs (100%) rename sim/testsuite/{sim => }/frv/ftra.cgs (100%) rename sim/testsuite/{sim => }/frv/ftu.cgs (100%) rename sim/testsuite/{sim => }/frv/ftue.cgs (100%) rename sim/testsuite/{sim => }/frv/ftug.cgs (100%) rename sim/testsuite/{sim => }/frv/ftuge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftul.cgs (100%) rename sim/testsuite/{sim => }/frv/ftule.cgs (100%) create mode 100644 sim/testsuite/frv/grloop.ms create mode 100644 sim/testsuite/frv/hello.ms rename sim/testsuite/{sim => }/frv/icei.cgs (100%) rename sim/testsuite/{sim => }/frv/ici.cgs (100%) rename sim/testsuite/{sim => }/frv/icpl.cgs (100%) rename sim/testsuite/{sim => }/frv/icul.cgs (100%) rename sim/testsuite/{sim => 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rename sim/testsuite/{sim => }/frv/lddf.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldq.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/ldshi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldub.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/lduh.cgs (100%) rename sim/testsuite/{sim => }/frv/lduhi.cgs (100%) rename sim/testsuite/{sim => }/frv/lduhu.cgs (100%) rename sim/testsuite/{sim => }/frv/lrbranch.pcgs (100%) rename sim/testsuite/{sim => }/frv/mabshs.cgs (100%) rename sim/testsuite/{sim => }/frv/maddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/maddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mand.cgs (100%) rename sim/testsuite/{sim => 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=> }/frv/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mdrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdunpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/membar.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhd.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhw.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/mhtob.cgs (100%) create mode 100644 sim/testsuite/frv/misc.exp rename sim/testsuite/{sim => }/frv/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mnop.cgs (100%) rename sim/testsuite/{sim => }/frv/mnot.cgs (100%) rename sim/testsuite/{sim => }/frv/mor.cgs (100%) rename sim/testsuite/{sim => }/frv/mov.cgs (100%) rename sim/testsuite/{sim => }/frv/movfg.cgs (100%) rename sim/testsuite/{sim => }/frv/movfgd.cgs (100%) rename sim/testsuite/{sim => }/frv/movfgq.cgs (100%) rename sim/testsuite/{sim => }/frv/movgf.cgs (100%) rename sim/testsuite/{sim => }/frv/movgfd.cgs (100%) rename sim/testsuite/{sim => }/frv/movgfq.cgs (100%) rename sim/testsuite/{sim => }/frv/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/mpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mqlclrhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqlmths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsaths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotri.cgs (100%) rename sim/testsuite/{sim => }/frv/msaths.cgs (100%) rename sim/testsuite/{sim => }/frv/msathu.cgs (100%) rename sim/testsuite/{sim => }/frv/msllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrlhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mtrap.cgs (100%) rename sim/testsuite/{sim => }/frv/munpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mwcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mwcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mwtacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mwtaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mxor.cgs (100%) rename sim/testsuite/{sim => }/frv/nandcr.cgs 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3 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-check_binutils updated (198f635c -> fed3c2d7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-check_binutils in repository toolchain/ci/base-artifacts. discards 198f635c 2: update: binutils-3624a6c15ce48e03d43983ec11d586d97ca08728: 1 new fed3c2d7 2: update: binutils-edf0f284b13293bb9740795131d18fe281139c48: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (198f635c) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-master-aarch64-c [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 166 +- 02-prepare_abe/console.log | 435 +- 03-build_abe-binutils/console.log | 14236 ++++++++++---------- 04-build_abe-check_binutils/console.log | 5087 ++++---- 05-check_regression/console.log | 296 +- 05-check_regression/results.regressions | 4 +- 06-update_baseline/console.log | 816 +- 06-update_baseline/results.regressions | 4 +- console.log | 21046 +++++++++++++++--------------- jenkins/manifest.sh | 8 +- sumfiles/binutils.log.xz | Bin 37436 -> 37428 bytes sumfiles/binutils.sum | 2 +- sumfiles/gas.log.xz | Bin 71332 -> 71344 bytes sumfiles/gas.sum | 4 +- sumfiles/ld.log.xz | Bin 106804 -> 106844 bytes sumfiles/ld.sum | 4 +- sumfiles/libctf.log.xz | Bin 1528 -> 1528 bytes sumfiles/libctf.sum | 2 +- 18 files changed, 21093 insertions(+), 21017 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_debug updated (b0ccd3922f5 -> 3804e937b0e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_debug in repository toolchain/ci/gcc. from b0ccd3922f5 compiler: add support for reading embedcfg files adds c4eec1efae0 testsuite: Fix sed script errors in complex tests adds 2ea6f4a377e tree-optimization/98685 - fix placement of extern converts adds 7432f255b70 arm: Auto-vectorization for MVE: vshl adds bfab355012c arm: Auto-vectorization for MVE: vshr adds 0411ae7f08e libatomic, libgomp, libitc: Fix bootstrap [PR70454] adds cb60334b716 testsuite/96098 - remove redundant testcase adds 1a630642009 arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds d03f14c354a testsuite/96147 - remove scanning for ! vect_hw_misalign adds e1bd80fb706 testsuite/96147 - key scanning on vect_hw_misalign adds aa4ee5798fe testsuite/96147 - scan for vectorized load adds b36c9cd0947 testsuite/96147 - align vector access adds dc8475e3348 Pytest in tests: improve adds 446703ccc2c tree-optimization/96376 - do not check alignment for invari [...] adds f1d054017ef Revert "arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 [...] adds 63999d751df arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds f9a577927eb IBM Z: Fix linking to libatomic in target test cases adds 7f6cdaa9a8d rtl-ssa: Fix a silly typo adds f2cc526f47a recog: Fix insn_change_watermark destructor adds 5a783f42d77 aarch64: Add a minipass for fusing CC insns [PR88836] adds 492b90f33df c++: Fix langspecs with -fsyntax-only [PR98591] adds 1ba71fabb78 preprocessor: Make quoting : [PR 95253] adds 7d0df0aeb67 i386: Use cpp_define_formatted for __SIZEOF_FLOAT80__ definition adds d3959070aa4 [PATCH] aarch64: Implement vmlsl[_high]* intrinsics using builtins adds 50dbced2f37 openmp: Change the way of building of reduction array type adds adb520606ce c-family: Improve MEM_REF printing for diagnostics [PR98597] adds a3128bf0128 bootstrap: fix failing diagnostic selftest on Windows [PR98696] adds aaec739250b testsuite: Add testcase coverage for already fixed [PR96671] adds c0194736b47 gcc.dg/analyzer tests: use __builtin_alloca, not alloca.h adds cd09079cfd5 c++: Fix list-init of array of no-copy type [PR63707] adds ad260343385 AArch64: Add NEON, SVE and SVE2 RTL patterns for Multiply, [...] adds 424deca72b6 c++: Fix copy elision for base initialization adds d75199f7823 c++: Avoid redundant copy in {} init [PR98642] adds e63c2161d09 drop -dumpbase-ext from producer string adds 5c046034e3e match.pd: Optimize (x < 0) ^ (y < 0) to (x ^ y) < 0 etc. [PR96681] adds 0425f4c1b63 match.pd: Generalize the PR64309 simplifications [PR96669] adds e1efa6af61a preprocessor: Make quoting : [PR 95253] adds 9beb6d88eff c++: Fix qualified array-type construction [PR 98538] adds b90e4a97419 fortran: Fixes a bug in ISO_Fortran_binding.c. adds c029fcb5680 Reset force_source_line in final.c adds f1ad419ebfd rs6000, vector integer multiply/divide/modulo instructions adds 2f7f0d32e74 Daily bump. adds 2c356f221bb libstdc++-v3: Add -fcf-protection=none to -march=i486 adds b673e7547fb cd_dce: Return TODO_update_address_taken from last cd_dce [ [...] adds e2559c3945a match.pd: Optimize ((cst << x) & 1) [PR96669] adds 7e02426ba0c nios2: Remove custom instruction warnings adds 42f4e239924 nios2: Add -mcustom-fpu-cfg=fph2 adds 5e5d56919dd RTEMS: Add -mcustom-fpu-cfg=fph2 multilib adds a6d22fb21c6 openmp: Add support for the OpenMP 5.0 task detach clause adds a2960a04d51 testsuite: Fix up a testcase to find the right ISO_Fortran_ [...] new 59cf67d1cf7 Daily bump. new 3804e937b0e Default to DWARF5 The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 239 +++++++++++++ gcc/DATESTAMP | 2 +- gcc/Makefile.in | 7 + gcc/builtin-types.def | 8 +- gcc/c-family/ChangeLog | 17 + gcc/c-family/c-pragma.h | 3 +- gcc/c-family/c-pretty-print.c | 259 +++++++++++--- gcc/c/ChangeLog | 15 + gcc/c/c-parser.c | 57 ++- gcc/c/c-typeck.c | 62 +++- gcc/common.opt | 2 +- gcc/config.gcc | 2 +- gcc/config/aarch64/aarch64-cc-fusion.cc | 296 +++++++++++++++ gcc/config/aarch64/aarch64-passes.def | 1 + gcc/config/aarch64/aarch64-protos.h | 1 + gcc/config/aarch64/aarch64-simd-builtins.def | 8 + gcc/config/aarch64/aarch64-simd.md | 56 ++- gcc/config/aarch64/aarch64-sve.md | 56 +++ gcc/config/aarch64/aarch64-sve2.md | 42 +++ gcc/config/aarch64/arm_neon.h | 84 +---- gcc/config/aarch64/iterators.md | 109 +++++- gcc/config/aarch64/t-aarch64 | 6 + gcc/config/arm/arm_neon.h | 31 ++ gcc/config/arm/mve.md | 47 ++- gcc/config/arm/neon.md | 53 --- gcc/config/arm/vec-common.md | 58 +++ gcc/config/i386/i386-c.c | 9 +- gcc/config/nios2/nios2.c | 51 ++- gcc/config/nios2/t-rtems | 146 +------- gcc/config/rs6000/altivec.h | 4 + gcc/config/rs6000/altivec.md | 2 - gcc/config/rs6000/rs6000-builtin.def | 21 ++ gcc/config/rs6000/rs6000-call.c | 53 +++ gcc/config/rs6000/rs6000.md | 5 +- gcc/config/rs6000/vsx.md | 211 ++++++++--- gcc/cp/ChangeLog | 45 +++ gcc/cp/call.c | 145 ++++++-- gcc/cp/cp-tree.h | 3 +- gcc/cp/lang-specs.h | 40 ++- gcc/cp/parser.c | 53 ++- gcc/cp/pt.c | 1 + gcc/cp/semantics.c | 61 +++- gcc/cp/tree.c | 18 +- gcc/cp/typeck2.c | 21 +- gcc/diagnostic.c | 12 +- gcc/doc/extend.texi | 120 +++++++ gcc/doc/install.texi | 2 +- gcc/doc/invoke.texi | 35 +- gcc/doc/sourcebuild.texi | 4 + gcc/final.c | 1 + gcc/fortran/ChangeLog | 23 ++ gcc/fortran/dump-parse-tree.c | 6 + gcc/fortran/frontend-passes.c | 1 + gcc/fortran/gfortran.h | 2 + gcc/fortran/openmp.c | 60 +++- gcc/fortran/trans-openmp.c | 16 + gcc/fortran/trans-types.c | 3 + gcc/fortran/types.def | 8 +- gcc/gimplify.c | 14 + gcc/go/ChangeLog | 4 + gcc/match.pd | 46 ++- gcc/omp-builtins.def | 2 +- gcc/omp-expand.c | 19 +- gcc/omp-low.c | 47 +++ gcc/opts.c | 1 + gcc/passes.def | 8 +- gcc/recog.h | 8 +- gcc/rtl-ssa/functions.h | 2 +- gcc/rtl-ssa/member-fns.inl | 2 +- gcc/testsuite/ChangeLog | 180 ++++++++++ gcc/testsuite/c-c++-common/gomp/task-detach-1.c | 37 ++ gcc/testsuite/g++.dg/cpp0x/initlist-array13.C | 16 + gcc/testsuite/g++.dg/cpp1z/elide4.C | 24 ++ gcc/testsuite/g++.dg/cpp1z/elide5.C | 15 + gcc/testsuite/g++.dg/gomp/task-detach-1.C | 29 ++ gcc/testsuite/g++.dg/modules/dep-1_a.C | 4 +- gcc/testsuite/g++.dg/modules/dep-1_b.C | 4 +- gcc/testsuite/g++.dg/modules/dep-2.C | 6 +- gcc/testsuite/g++.dg/modules/pr98591.H | 3 + gcc/testsuite/g++.dg/template/pr98538.C | 18 + gcc/testsuite/gcc.dg/analyzer/alloca-leak.c | 4 +- gcc/testsuite/gcc.dg/analyzer/data-model-1.c | 5 +- gcc/testsuite/gcc.dg/analyzer/malloc-1.c | 3 +- gcc/testsuite/gcc.dg/analyzer/malloc-paths-8.c | 7 +- gcc/testsuite/gcc.dg/gomp/task-detach-1.c | 20 ++ gcc/testsuite/gcc.dg/tree-ssa/pr96669-1.c | 59 +++ gcc/testsuite/gcc.dg/tree-ssa/pr96669-2.c | 30 ++ gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c | 51 +++ gcc/testsuite/gcc.dg/tree-ssa/pr96671-2.c | 51 +++ gcc/testsuite/gcc.dg/tree-ssa/pr96681.c | 35 ++ gcc/testsuite/gcc.dg/uninit-38.c | 80 ++--- gcc/testsuite/gcc.dg/uninit-40.c | 50 +++ gcc/testsuite/gcc.dg/vect/bb-slp-32.c | 1 + gcc/testsuite/gcc.dg/vect/bb-slp-9.c | 2 +- gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c | 20 -- gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c | 15 + .../gcc.dg/vect/complex/complex-mla-template.c | 28 +- .../gcc.dg/vect/complex/complex-mls-template.c | 28 +- gcc/testsuite/gcc.dg/vect/slp-43.c | 4 +- gcc/testsuite/gcc.dg/vect/slp-45.c | 2 +- .../aarch64/advsimd-intrinsics/p64_p128.c | 46 ++- .../gcc.target/aarch64/sve/acle/general/ldff1_8.c | 32 ++ gcc/testsuite/gcc.target/aarch64/sve/ptest_1.c | 10 + gcc/testsuite/gcc.target/arm/simd/mve-vshl.c | 62 ++++ gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 59 +++ gcc/testsuite/gcc.target/arm/simd/vceqz_p64.c | 17 + gcc/testsuite/gcc.target/arm/simd/vceqzq_p64.c | 17 + gcc/testsuite/gcc.target/i386/pr96271.c | 11 + .../gcc.target/powerpc/builtins-1-p10-runnable.c | 398 +++++++++++++++++++++ .../gcc.target/s390/md/atomic_exchange-1.c | 2 +- gcc/testsuite/gcc.target/s390/s390.exp | 4 + gcc/testsuite/gfortran.dg/gomp/task-detach-1.f90 | 29 ++ .../iso_fortran_binding_uint8_array.f90 | 11 + .../iso_fortran_binding_uint8_array_driver.c | 25 ++ gcc/testsuite/lib/gcov.exp | 31 +- gcc/tree-core.h | 29 +- gcc/tree-nested.c | 2 + gcc/tree-pretty-print.c | 6 + gcc/tree-ssa-dce.c | 15 +- gcc/tree-vect-slp.c | 11 +- gcc/tree-vect-stmts.c | 23 +- gcc/tree.c | 15 +- include/ChangeLog | 4 + include/gomp-constants.h | 1 + libatomic/ChangeLog | 9 + libatomic/configure.tgt | 56 +-- libcpp/ChangeLog | 5 + libcpp/mkdeps.c | 1 - libgfortran/ChangeLog | 6 + libgfortran/runtime/ISO_Fortran_binding.c | 3 +- libgomp/ChangeLog | 52 +++ libgomp/configure.tgt | 35 +- libgomp/fortran.c | 6 + libgomp/libgomp.h | 7 + libgomp/libgomp.map | 2 + libgomp/libgomp_g.h | 2 +- libgomp/omp.h.in | 7 + libgomp/omp_lib.f90.in | 9 + libgomp/omp_lib.h.in | 4 + libgomp/priority_queue.c | 57 +++ libgomp/priority_queue.h | 5 + libgomp/task.c | 132 +++++-- libgomp/team.c | 4 + .../testsuite/libgomp.c-c++-common/task-detach-1.c | 36 ++ .../testsuite/libgomp.c-c++-common/task-detach-2.c | 37 ++ .../testsuite/libgomp.c-c++-common/task-detach-3.c | 33 ++ .../testsuite/libgomp.c-c++-common/task-detach-4.c | 24 ++ .../testsuite/libgomp.c-c++-common/task-detach-5.c | 42 +++ .../testsuite/libgomp.c-c++-common/task-detach-6.c | 46 +++ .../testsuite/libgomp.fortran/task-detach-1.f90 | 33 ++ .../testsuite/libgomp.fortran/task-detach-2.f90 | 34 ++ .../testsuite/libgomp.fortran/task-detach-3.f90 | 33 ++ .../testsuite/libgomp.fortran/task-detach-4.f90 | 22 ++ .../testsuite/libgomp.fortran/task-detach-5.f90 | 39 ++ .../testsuite/libgomp.fortran/task-detach-6.f90 | 44 +++ libitm/ChangeLog | 7 + libitm/configure.tgt | 37 +- libstdc++-v3/ChangeLog | 5 + .../atomic_flag/test_and_set/explicit-hle.cc | 2 +- 159 files changed, 4683 insertions(+), 740 deletions(-) create mode 100644 gcc/config/aarch64/aarch64-cc-fusion.cc create mode 100644 gcc/testsuite/c-c++-common/gomp/task-detach-1.c create mode 100644 gcc/testsuite/g++.dg/cpp0x/initlist-array13.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/elide4.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/elide5.C create mode 100644 gcc/testsuite/g++.dg/gomp/task-detach-1.C create mode 100644 gcc/testsuite/g++.dg/modules/pr98591.H create mode 100644 gcc/testsuite/g++.dg/template/pr98538.C create mode 100644 gcc/testsuite/gcc.dg/gomp/task-detach-1.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96669-1.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96669-2.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96671-2.c create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr96681.c create mode 100644 gcc/testsuite/gcc.dg/uninit-40.c delete mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c create mode 100644 gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/acle/general/ldff1_8.c create mode 100644 gcc/testsuite/gcc.target/aarch64/sve/ptest_1.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vshl.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/mve-vshr.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vceqz_p64.c create mode 100644 gcc/testsuite/gcc.target/arm/simd/vceqzq_p64.c create mode 100644 gcc/testsuite/gcc.target/i386/pr96271.c create mode 100644 gcc/testsuite/gcc.target/powerpc/builtins-1-p10-runnable.c create mode 100644 gcc/testsuite/gfortran.dg/gomp/task-detach-1.f90 create mode 100644 gcc/testsuite/gfortran.dg/iso_fortran_binding_uint8_array.f90 create mode 100644 gcc/testsuite/gfortran.dg/iso_fortran_binding_uint8_array_driver.c create mode 100644 libgomp/testsuite/libgomp.c-c++-common/task-detach-1.c create mode 100644 libgomp/testsuite/libgomp.c-c++-common/task-detach-2.c create mode 100644 libgomp/testsuite/libgomp.c-c++-common/task-detach-3.c create mode 100644 libgomp/testsuite/libgomp.c-c++-common/task-detach-4.c create mode 100644 libgomp/testsuite/libgomp.c-c++-common/task-detach-5.c create mode 100644 libgomp/testsuite/libgomp.c-c++-common/task-detach-6.c create mode 100644 libgomp/testsuite/libgomp.fortran/task-detach-1.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/task-detach-2.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/task-detach-3.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/task-detach-4.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/task-detach-5.f90 create mode 100644 libgomp/testsuite/libgomp.fortran/task-detach-6.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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Tcwg-commits January 2021