Tcwg-commits January 2021

tcwg-commits@lists.linaro.org

5 participants
9360 discussions

[gcc] branch master updated (e11e5d3889f -> e28bd09498b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from e11e5d3889f Map long double built-ins correctly with IEEE 128-bit long double. new e28bd09498b testsuite: Fix up a testcase to find the right ISO_Fort [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/testsuite/gfortran.dg/ISO_Fortran_binding_18.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[binutils-gdb] branch master updated (cdeba395cff -> f237f998d11)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from cdeba395cff [gdb/testsuite] Fix gdb.arch/i386-gnu-cfi.exp new f237f998d11 gdb/tui: remove special handling of locator/status window The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/ChangeLog | 51 +++++++++++++++++++++ gdb/Makefile.in | 2 + gdb/tui/tui-data.h | 2 +- gdb/tui/tui-disasm.c | 13 +++--- gdb/tui/tui-layout.c | 16 ++----- gdb/tui/tui-location.c | 81 +++++++++++++++++++++++++++++++++ gdb/tui/tui-location.h | 93 ++++++++++++++++++++++++++++++++++++++ gdb/tui/tui-source.c | 9 ++-- gdb/tui/tui-stack.c | 114 +++++++++++------------------------------------ gdb/tui/tui-stack.h | 19 -------- gdb/tui/tui-wingeneral.c | 4 -- gdb/tui/tui-winsource.c | 3 +- gdb/tui/tui.h | 1 + 13 files changed, 270 insertions(+), 138 deletions(-) create mode 100644 gdb/tui/tui-location.c create mode 100644 gdb/tui/tui-location.h -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[glibc] branch master updated (5ee506ed35 -> 6032ae6514)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository glibc. from 5ee506ed35 powerpc64: Workaround sigtramp vdso return call new d04d64804d Update alpha libm-test-ulps new 341063c3b1 Update sparc libm-test-ulps new c177f6610c ia64: Fix brk call on statup new a7b21a7830 sh: Update libm-tests-ulps new 4a3f20b33a Update ia64 libm-test-ulps new 4e04691107 Update libc.pot for 2.33 release new 6032ae6514 Update translations The 7 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: po/be.po | 306 +- po/bg.po | 680 ++-- po/ca.po | 664 ++-- po/cs.po | 680 ++-- po/da.po | 610 ++-- po/de.po | 680 ++-- po/el.po | 376 +- po/eo.po | 689 ++-- po/es.po | 658 ++-- po/fi.po | 606 ++-- po/fr.po | 680 ++-- po/gl.po | 532 +-- po/hr.po | 803 +++-- po/hu.po | 420 +-- po/ia.po | 222 +- po/id.po | 610 ++-- po/it.po | 614 ++-- po/ja.po | 614 ++-- po/ko.po | 680 ++-- po/libc.pot | 744 ++-- po/lt.po | 410 +-- po/nb.po | 352 +- po/nl.po | 680 ++-- po/pl.po | 680 ++-- po/pt.po | 4822 +++++++++++++++++++++++--- po/pt_BR.po | 694 ++-- po/ru.po | 680 ++-- po/rw.po | 14 +- po/sk.po | 526 +-- po/sl.po | 340 +- po/sv.po | 680 ++-- po/tr.po | 680 ++-- po/uk.po | 680 ++-- po/vi.po | 664 ++-- po/zh_CN.po | 664 ++-- po/zh_TW.po | 680 ++-- sysdeps/alpha/fpu/libm-test-ulps | 23 +- sysdeps/ia64/fpu/libm-test-ulps | 4 +- sysdeps/sh/libm-test-ulps | 42 +- sysdeps/sparc/fpu/libm-test-ulps | 23 +- sysdeps/unix/sysv/linux/{i386 => ia64}/brk.c | 12 +- 41 files changed, 14639 insertions(+), 10579 deletions(-) copy sysdeps/unix/sysv/linux/{i386 => ia64}/brk.c (77%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[glibc] branch master updated (757a14b5ac -> 5ee506ed35)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository glibc. from 757a14b5ac Fix nss/tst-reload2 for systems without PATH_MAX new 5ee506ed35 powerpc64: Workaround sigtramp vdso return call The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: sysdeps/powerpc/powerpc64/backtrace.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[gcc] branch master updated (6bb207b468d -> e11e5d3889f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 6bb207b468d c++: Fix up handling of register ... asm ("...") vars in te [...] new e11e5d3889f Map long double built-ins correctly with IEEE 128-bit long double. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/rs6000/rs6000.c | 135 +++++-- .../gcc.target/powerpc/float128-longdouble-math.c | 442 +++++++++++++++++++++ .../gcc.target/powerpc/float128-longdouble-stdio.c | 36 ++ gcc/testsuite/gcc.target/powerpc/float128-math.c | 16 +- 4 files changed, 589 insertions(+), 40 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/float128-longdouble-math.c create mode 100644 gcc/testsuite/gcc.target/powerpc/float128-longdouble-stdio.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[binutils-gdb] branch master updated (8ee511afd84 -> cdeba395cff)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 8ee511afd84 gdb: rename get_type_arch to type::arch new c47b145e1a5 [gdb/testsuite] Fix g0 search in gdb.arch/i386-sse-stack-align.exp new cdeba395cff [gdb/testsuite] Fix gdb.arch/i386-gnu-cfi.exp The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/testsuite/ChangeLog | 12 ++++++++ gdb/testsuite/gdb.arch/i386-gnu-cfi.exp | 26 +++++++++++----- gdb/testsuite/gdb.arch/i386-sse-stack-align.S | 40 ++++++++++++------------- gdb/testsuite/gdb.arch/i386-sse-stack-align.c | 13 ++++---- gdb/testsuite/gdb.arch/i386-sse-stack-align.exp | 2 +- 5 files changed, 59 insertions(+), 34 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-Os updated (7137d682eb -> 757a14b5ac)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-Os in repository toolchain/ci/glibc. from 7137d682eb ifuncmain6pie: Remove the circular IFUNC dependency [BZ #20019] adds d18f59bf92 Fix x86 build with --enable-tunable=no adds 2d651eb926 x86: Move x86 processor cache info to cpu_features adds cc528f9a7e math/test-tgmath2: Fix fabs failure when no long double adds 86f65dffc2 ld.so: Add --list-tunables to print tunable values adds 96f17e6e63 ARC: nofpu: Regenerate ulps adds f678099de9 Update hppa libm-test-ulps adds a031b3abad Update powerpc-nofpu libm-test-ulps. adds 07169fcac7 Update arm libm-test-ulps. adds 202586f73e Update MIPS libm-test-ulps. adds 0887fff0b0 Hurd: Add rtld-strncpy-c.c adds 0ec583d926 libmvec: Add extra-test-objs to test-extras adds cabc8a2916 elf: Avoid RELATIVE relocation for _dl_sysinfo adds 22b79ed7f4 Use <startup.h> in __libc_init_secure adds 1006250ea2 posix: Fix regex_internal.h on bootstrap adds 961d7cff51 stdlib: Add testcase for BZ #26241 adds d7ee6bd8c2 posix: Fix fnmatch.c on bootstrap adds ff6d62e9ed <sys/platform/x86.h>: Remove the C preprocessor magic adds 058308066c elf: Make the tunable struct definition internal only adds bfe04789a8 elf: Avoid RELATIVE relocs in __tunables_init adds 374cef32ac configure: Check for static PIE support adds 04af1eb313 csu: Avoid weak ref for __ehdr_start in static PIE adds 47618209d0 Use hidden visibility for early static PIE code adds 86d439b06f csu: Move static pie self relocation later [BZ #27072] adds 2682695e5c Make libc symbols hidden in static PIE adds 28f2ce2772 aarch64: revert memcpy optimze for kunpeng to avoid performa [...] adds 46c1c765d1 Revert "linux: Move {f}xstat{at} to compat symbols" for stat [...] adds 7a5ab88e21 x86: Check ifunc resolver with CPU_FEATURE_USABLE [BZ #27072] adds 527c89cd32 powerpc64: Select POWER9 machine for the scv instruction adds f543259500 x86-64: Update tst-glibc-hwcaps-2.c for x86-64 baseline adds 5f478eb0fb x86: Properly match CPU features in /proc/cpuinfo [BZ #27222] adds 42d6270439 linux: mips: Fix getdents64 fallback on mips64-n32 adds 56ef6ab0cd manual: Correct argument order in mount examples [BZ #27207] adds fcfa4bb48d Update C-SKY libm-test-ulps adds 31f6488722 Fix misplaced const adds c3c4a25e65 aarch64: Move and update the definition of MTE_ENABLED adds ad47748992 Update INSTALL with package versions that are known to work adds 04c6a8073d aarch64: Fix the list of tested IFUNC variants [BZ #26818] adds 3725ee39db benchtests: Do not build bench-timing-type with MODULE_NAME=libc adds df359a25ba Revert "Make libc symbols hidden in static PIE" [BZ #27237] adds 7d88c6142c gconv: Fix assertion failure in ISO-2022-JP-3 module (bug 27256) adds 01cdcf783a elf: Limit tst-prelink-cmp target archs adds 429029a73e nsswitch: do not reload if "/" changes new 757a14b5ac Fix nss/tst-reload2 for systems without PATH_MAX The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: INSTALL | 26 +- NEWS | 4 + benchtests/Makefile | 14 +- config.h.in | 3 + configure | 13 + configure.ac | 4 + csu/libc-start.c | 15 +- elf/Makefile | 20 +- elf/dl-main.h | 2 +- elf/dl-reloc-static-pie.c | 2 + elf/dl-support.c | 16 +- elf/dl-tunable-types.h | 42 +- elf/dl-tunables.c | 49 +- elf/dl-tunables.h | 37 +- elf/dl-usage.c | 7 +- elf/enbl-secure.c | 10 +- elf/rtld.c | 19 + .../multiarch/init-arch.h => elf/tst-prelink-cmp.c | 38 +- elf/tst-prelink.exp | 1 - elf/tst-rtld-list-tunables.exp | 14 + elf/tst-rtld-list-tunables.sh | 34 + iconvdata/Makefile | 4 +- iconvdata/bug-iconv14.c | 127 ++++ iconvdata/iso-2022-jp-3.c | 67 +- include/shlib-compat.h | 23 +- manual/install.texi | 24 +- manual/platform.texi | 7 +- manual/sysinfo.texi | 4 +- manual/tunables.texi | 38 + math/test-tgmath2.c | 4 +- misc/sbrk.c | 4 + nss/Makefile | 2 +- nss/nss_database.c | 27 + nss/nss_module.c | 13 + nss/nss_module.h | 3 + nss/tst-reload2.c | 130 ++++ nss/tst-reload2.root/etc/nsswitch.conf | 2 + nss/tst-reload2.root/subdir/etc/group | 1 + nss/tst-reload2.root/subdir/etc/nsswitch.conf | 2 + nss/tst-reload2.root/tst-reload2.script | 3 + posix/fnmatch.c | 2 +- posix/regex_internal.h | 6 +- scripts/gen-tunables.awk | 16 +- stdlib/Makefile | 3 +- stdlib/tst-canon-bz26341.c | 101 +++ sysdeps/aarch64/configure | 4 + sysdeps/aarch64/configure.ac | 3 + sysdeps/aarch64/multiarch/ifunc-impl-list.c | 8 +- sysdeps/aarch64/multiarch/init-arch.h | 13 +- sysdeps/aarch64/multiarch/memcpy.c | 2 +- sysdeps/aarch64/multiarch/strlen.c | 11 +- sysdeps/arc/nofpu/libm-test-ulps | 11 +- sysdeps/arm/libm-test-ulps | 23 +- sysdeps/csky/fpu/libm-test-ulps | 82 ++- sysdeps/csky/nofpu/libm-test-ulps | 33 +- sysdeps/generic/startup.h | 26 + sysdeps/hppa/fpu/libm-test-ulps | 23 +- sysdeps/i386/configure | 3 + sysdeps/i386/configure.ac | 3 + sysdeps/mach/hurd/fxstat.c | 4 +- sysdeps/mach/hurd/fxstat64.c | 2 +- sysdeps/mach/hurd/fxstatat.c | 3 +- sysdeps/mach/hurd/fxstatat64.c | 3 +- .../mach/hurd/i386/i686/multiarch/rtld-strncpy-c.c | 1 + sysdeps/mach/hurd/i386/ld.abilist | 1 - sysdeps/mach/hurd/i386/libc.abilist | 1 + sysdeps/mach/hurd/lxstat.c | 2 +- sysdeps/mach/hurd/lxstat64.c | 3 +- sysdeps/mach/hurd/xstat.c | 2 +- sysdeps/mach/hurd/xstat64.c | 2 +- sysdeps/mips/mips32/libm-test-ulps | 23 +- sysdeps/mips/mips64/libm-test-ulps | 23 +- sysdeps/powerpc/nofpu/libm-test-ulps | 33 +- sysdeps/powerpc/powerpc64/sysdep.h | 3 + sysdeps/unix/sysv/linux/aarch64/libc-start.c | 5 + sysdeps/unix/sysv/linux/fxstat.c | 4 +- sysdeps/unix/sysv/linux/fxstat64.c | 4 +- sysdeps/unix/sysv/linux/fxstatat.c | 4 +- sysdeps/unix/sysv/linux/fxstatat64.c | 4 +- sysdeps/unix/sysv/linux/i386/ld.abilist | 1 - sysdeps/unix/sysv/linux/i386/libc.abilist | 1 + sysdeps/unix/sysv/linux/i386/startup.h | 29 +- sysdeps/unix/sysv/linux/lxstat.c | 2 +- sysdeps/unix/sysv/linux/lxstat64.c | 4 +- sysdeps/unix/sysv/linux/mips/mips64/getdents64.c | 37 +- sysdeps/unix/sysv/linux/powerpc/powerpc64/clone.S | 3 + sysdeps/unix/sysv/linux/powerpc/sysdep.h | 5 +- sysdeps/unix/sysv/linux/tst-getdents64.c | 29 +- sysdeps/unix/sysv/linux/x86_64/64/ld.abilist | 1 - sysdeps/unix/sysv/linux/x86_64/64/libc.abilist | 1 + .../unix/sysv/linux/x86_64/tst-glibc-hwcaps-2.c | 5 +- sysdeps/unix/sysv/linux/x86_64/x32/ld.abilist | 1 - sysdeps/unix/sysv/linux/x86_64/x32/libc.abilist | 1 + sysdeps/unix/sysv/linux/xstat.c | 6 +- sysdeps/unix/sysv/linux/xstat64.c | 5 +- sysdeps/x86/Makefile | 15 + sysdeps/x86/Versions | 7 +- sysdeps/x86/bits/platform/x86.h | 299 ++++++++ sysdeps/x86/cacheinfo.c | 48 +- sysdeps/x86/cacheinfo.h | 400 +---------- sysdeps/x86/cpu-features.c | 103 ++- sysdeps/x86/dl-cacheinfo.h | 460 ++++++++++++ sysdeps/x86/dl-get-cpu-features.c | 8 +- .../libc-start.c => x86/get-cpuid-feature-leaf.c} | 24 +- sysdeps/x86/get-isa-level.h | 3 +- sysdeps/x86/include/cpu-features.h | 781 ++++++++++++++++++++- sysdeps/x86/libc-start.c | 5 + sysdeps/x86/sys/platform/x86.h | 777 +------------------- sysdeps/x86/tst-cpu-features-cpuinfo.c | 43 +- sysdeps/x86/tst-get-cpu-features.c | 29 +- sysdeps/x86/tst-ifunc-isa-1-static.c | 1 + .../aarch64/libc-start.c => x86/tst-ifunc-isa-1.c} | 22 +- sysdeps/x86/tst-ifunc-isa-2-static.c | 1 + .../hurd/fxstatat.c => x86/tst-ifunc-isa-2.c} | 30 +- sysdeps/x86/tst-ifunc-isa.h | 104 +++ sysdeps/x86/tst-isa-level-1.c | 3 +- sysdeps/x86_64/configure | 3 + sysdeps/x86_64/configure.ac | 3 + sysdeps/x86_64/dl-hwcaps-subdirs.c | 4 +- sysdeps/x86_64/fpu/Makefile | 8 + sysdeps/x86_64/tst-glibc-hwcaps.c | 3 +- 121 files changed, 3036 insertions(+), 1634 deletions(-) copy sysdeps/aarch64/multiarch/init-arch.h => elf/tst-prelink-cmp.c (50%) delete mode 100644 elf/tst-prelink.exp create mode 100644 elf/tst-rtld-list-tunables.exp create mode 100755 elf/tst-rtld-list-tunables.sh create mode 100644 iconvdata/bug-iconv14.c create mode 100644 nss/tst-reload2.c create mode 100644 nss/tst-reload2.root/etc/nsswitch.conf create mode 100644 nss/tst-reload2.root/subdir/etc/group create mode 100644 nss/tst-reload2.root/subdir/etc/nsswitch.conf create mode 100644 nss/tst-reload2.root/tst-reload2.script create mode 100644 stdlib/tst-canon-bz26341.c create mode 100644 sysdeps/mach/hurd/i386/i686/multiarch/rtld-strncpy-c.c create mode 100644 sysdeps/x86/bits/platform/x86.h copy sysdeps/{unix/sysv/linux/aarch64/libc-start.c => x86/get-cpuid-feature-leaf.c} (64%) create mode 100644 sysdeps/x86/tst-ifunc-isa-1-static.c copy sysdeps/{unix/sysv/linux/aarch64/libc-start.c => x86/tst-ifunc-isa-1.c} (68%) create mode 100644 sysdeps/x86/tst-ifunc-isa-2-static.c copy sysdeps/{mach/hurd/fxstatat.c => x86/tst-ifunc-isa-2.c} (60%) create mode 100644 sysdeps/x86/tst-ifunc-isa.h -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-Os updated (a958b2fc6da -> 87301e3956d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-Os in repository toolchain/ci/gcc. from a958b2fc6da aarch64: Add support for unpacked SVE ASRD adds 67fbb7f0fda Daily bump. adds ab88f360723 analyzer: fix ICE merging dereferencing unknown ptrs [PR98628] adds 640296c367f make FOR_EACH_IMM_USE_STMT safe for early exits adds 240f0a490da Delete dead code in ix86_expand_sse_comi. adds 814299a9d49 c++: -Wmissing-field-initializers in unevaluated ctx [PR98620] adds ab96073df00 MAINTAINERS: Add myself for write after approval adds ff99d05f40f configure, make: Fix up --enable-link-serialization adds 13d47c37a2c reassoc: Optimize in reassoc x < 0 && y < 0 to (x | y) < 0 [...] adds 24ea113f75c widening_mul: Fix up ICE caused by my signed multiplication [...] adds b2230210f17 gcov: add more debugging facility adds e91910d3576 options: properly compare string arguments adds 52a170b1a18 tree-optimization/98550 - fix BB vect unrolling check adds e0bec6ceac4 c++: Fix ICE with CTAD in concept [PR98611] adds cf2ac1c30af [PR97969] LRA: Transform pattern `plus (plus (hard reg, con [...] adds 25bef68902f arm: Add movmisalign patterns for MVE (PR target/97875) adds 1aff68d54c3 Fix typo in function-abi.h adds 248feb2fa2c gcov: fix printf format for 32-bit hosts adds e2aa8a5f982 libcody: Simplify configure [PR 98414, 98509] adds 728fee7a798 MAINTAINERS: Fix spacing adds 5a9cfad2de9 Avoid a couple more ICEs in print_mem_ref (PR c/98597). adds cfaaa6a1ca7 syscall: ensure openat uses variadic libc wrapper adds 6851dda2e79 Daily bump. adds abb3993e49c amdgcn: Fix subdf3 pattern adds c8812bac8ee amdgcn: Improve FP division accuracy adds 3df6fac0080 amdgcn: Fix exec register live-on-entry to BB in md-reorg adds 7993fe1877a amdgcn: Remove dead code for fixed v0 register adds b668a06e37f i386: Optimize _mm_unpacklo_epi8 of 0 vector as second argu [...] adds 3f325179b32 [PATCH v2] aarch64: Add cpu cost tables for A64FX adds 6b70fa678b1 ipa: remove a dead code adds 5d057bfeff7 i386: Add define_insn_and_split patterns for btrl [PR96938] adds ffd28c265e6 tree-optimization/98640 - fix bogus sign-extension with VN adds 4c598b038df doc: Fix typos in C++ Modules documentation adds 0db5f488486 libstdc++: Remove <debug/array> from Doxygen config adds 7875e8dc831 if-to-switch: fix also virtual phis adds b1d1e2b54c6 i386, expand: Optimize also 256-bit and 512-bit permutatati [...] adds 2b356e689c3 hurd: libgcc unwinding over signal trampolines with SIGINFO adds c23aea6edc9 gcc-changelog: Allow modifications to old ChangeLogs without entry adds f04e7e540e2 libstdc++: Fix typo in ChangeLog-2020 adds e9cb89b936f Hurd: Enable ifunc by default adds 40b371a7c2f sh: Remove match_scratch operand test adds 6d75168146f rtl-ssa: Fix reversed comparisons in accesses.h comment adds 5ab67cdee61 aarch64: Tighten condition on sve/sel* tests adds 3ddc18251a8 tree-optimization/92645 - improve SLP with existing vectors adds cf7a3353061 aarch64: Add support for unpacked SVE MLA and MAD adds 264a1269b44 aarch64: Add support for unpacked SVE MLS and MSB adds 11cbea852b0 c++: Fix cp_build_function_call_vec [PR 98626] adds a2d04f3d2c9 mklog: support define_insn_and_split format adds 285fa338b06 tree-optimization/92645 - avoid harmful early BIT_FIELD_REF [...] adds 7d7ef413ef1 gcc-changelog: Support multiline parentheses wrapping adds 8fc183ccd06 match.pd: Fold (~X | C) ^ D into (X | C) ^ (~D ^ C) if (~D [...] adds 796ead19f85 c++: Failure to lookup using-decl name [PR98231] adds 8cba7cb3202 or1k: Implement profile hook calling _mcount adds e1171c32502 or1k: Add builtin define to detect hard float adds b77f6d2fa84 or1k: Support for softfloat to emulate hw exceptions adds 6ed637c585b or1k: Add note to indicate execstack adds e40fdcc4f42 or1k: Fixup exception header data encodings adds be0851b8e93 Daily bump. adds c7f1ff01a23 aarch64: Reimplement vmovn_high_* intrinsics using builtins adds 52cd1cd1b67 aarch64: reimplement vqmovn_high* intrinsics using builtins adds 48f8d1d48f2 aarch64: Reimplememnt vmovn/vmovl intrinsics with builtins instead adds e45c41988bf vect: Account for unused IFN_LOAD_LANES results adds 8f8762a2e86 match.pd: Optimize ~(X >> Y) to ~X >> Y if ~X can be simpli [...] adds 0efdc7b31c2 i386: Fix the pmovzx SSE4.1 define_insn_and_split patterns [...] adds 08a4adcf2b6 i386: Remove reduntand assignment in i386-options.c [PR98671] adds d61d2a5f3ce c++: Fix erroneous parm comparison logic [PR 98372] adds 194a9d67be4 libstdc++: Update copyright dates on new files adds a802a2ef5f1 arm: Replace calls to __builtin_vcge* by <=,>= in arm_neon. [...] adds a512079ef40 i386: Update PR target/95021 tests adds 2182274f510 tree-optimization/98674 - improve dependence analysis adds 5ebdd53534d i386: Resolve variable shadowing in i386-options.c [PR98671] adds 77d372abec0 x86: Error on -fcf-protection with incompatible target adds 236d6a33ca6 mklog: skip unsupported files adds 7624c58c6b7 gcov: add one more pytest adds aa3d33dccb5 RTEMS: Fix Ada build for riscv adds 57a4f5e4eac libstdc++: Define function to throw filesystem_error [PR 98471] adds 6106dfb9f73 [nvptx libgomp plugin] Build only in supported configurations adds 9ac3e2feb3d libgo: update hurd support adds d0d2becf2df PR fortran/98661 - valgrind issues with error recovery adds c1a2cf88059 Revert "PR fortran/98661 - valgrind issues with error recovery" adds 9e1e6e63104 PR fortran/98661 - valgrind issues with error recovery adds 05a30af3f23 libstdc++: Implement N3644 for _GLIBCXX_DEBUG iterators adds 505caa7295b [gcn offloading] Only supported in 64-bit configurations adds 088e46b8d4d declare getpass in analyzer/sensitive-1.c test adds 6541fcadc86 use sigjmp_buf for analyzer sigsetjmp tests adds 3651c1b5c9c calibrate intervals to avoid zero in futures poll test adds bdd1b1f5552 PR fortran/93340 - fix missed substring simplifications adds f6ffd449e0c c++: Tweak g++.dg/template/pr98372.C. adds 8a18261afd9 analyzer: const fixes [PR98679] adds dea4a32b24f analyzer: fixes to -fdump-analyzer-json adds fe701195313 slp: elide intermediate nodes for complex add and avoid truncate adds 500600c7840 slp: Support optimizing load distribution adds e09173d84da slp: support complex multiply and complex multiply conjugate adds 31fac31800b slp: support complex FMA and complex FMA conjugate adds 478e571a3ee slp: support complex FMS and complex FMS conjugate adds b50df1e749b slp: Add complex operations class to share first match amon [...] adds 59832db9a71 slp: Add Tests for complex mul, mls and mla" adds f1096055854 Add GCC_EXTRA_DIAGNOSTIC_OUTPUT environment variable for fi [...] adds 02e7af1122c libstdc++: Implement N3644 for _GLIBCXX_DEBUG iterators adds 387f6c15d30 Handle fancy_abort before diagnostic initialization [PR98586] adds f1fc27b6c51 c++: Minor refactoring in process_init_constructor_record adds b95d97f1a5f jit: remove "Alpha" warning from docs adds 5fff80fd79c Daily bump. adds b0ccd3922f5 compiler: add support for reading embedcfg files adds c4eec1efae0 testsuite: Fix sed script errors in complex tests adds 2ea6f4a377e tree-optimization/98685 - fix placement of extern converts adds 7432f255b70 arm: Auto-vectorization for MVE: vshl adds bfab355012c arm: Auto-vectorization for MVE: vshr adds 0411ae7f08e libatomic, libgomp, libitc: Fix bootstrap [PR70454] adds cb60334b716 testsuite/96098 - remove redundant testcase adds 1a630642009 arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds d03f14c354a testsuite/96147 - remove scanning for ! vect_hw_misalign adds e1bd80fb706 testsuite/96147 - key scanning on vect_hw_misalign adds aa4ee5798fe testsuite/96147 - scan for vectorized load adds b36c9cd0947 testsuite/96147 - align vector access adds dc8475e3348 Pytest in tests: improve adds 446703ccc2c tree-optimization/96376 - do not check alignment for invari [...] adds f1d054017ef Revert "arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 [...] adds 63999d751df arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics adds f9a577927eb IBM Z: Fix linking to libatomic in target test cases adds 7f6cdaa9a8d rtl-ssa: Fix a silly typo adds f2cc526f47a recog: Fix insn_change_watermark destructor adds 5a783f42d77 aarch64: Add a minipass for fusing CC insns [PR88836] adds 492b90f33df c++: Fix langspecs with -fsyntax-only [PR98591] adds 1ba71fabb78 preprocessor: Make quoting : [PR 95253] adds 7d0df0aeb67 i386: Use cpp_define_formatted for __SIZEOF_FLOAT80__ definition adds d3959070aa4 [PATCH] aarch64: Implement vmlsl[_high]* intrinsics using builtins adds 50dbced2f37 openmp: Change the way of building of reduction array type adds adb520606ce c-family: Improve MEM_REF printing for diagnostics [PR98597] adds a3128bf0128 bootstrap: fix failing diagnostic selftest on Windows [PR98696] adds aaec739250b testsuite: Add testcase coverage for already fixed [PR96671] adds c0194736b47 gcc.dg/analyzer tests: use __builtin_alloca, not alloca.h adds cd09079cfd5 c++: Fix list-init of array of no-copy type [PR63707] adds ad260343385 AArch64: Add NEON, SVE and SVE2 RTL patterns for Multiply, [...] adds 424deca72b6 c++: Fix copy elision for base initialization adds d75199f7823 c++: Avoid redundant copy in {} init [PR98642] adds e63c2161d09 drop -dumpbase-ext from producer string adds 5c046034e3e match.pd: Optimize (x < 0) ^ (y < 0) to (x ^ y) < 0 etc. [PR96681] adds 0425f4c1b63 match.pd: Generalize the PR64309 simplifications [PR96669] adds e1efa6af61a preprocessor: Make quoting : [PR 95253] adds 9beb6d88eff c++: Fix qualified array-type construction [PR 98538] adds b90e4a97419 fortran: Fixes a bug in ISO_Fortran_binding.c. adds c029fcb5680 Reset force_source_line in final.c adds f1ad419ebfd rs6000, vector integer multiply/divide/modulo instructions adds 2f7f0d32e74 Daily bump. adds 2c356f221bb libstdc++-v3: Add -fcf-protection=none to -march=i486 adds b673e7547fb cd_dce: Return TODO_update_address_taken from last cd_dce [ [...] adds e2559c3945a match.pd: Optimize ((cst << x) & 1) [PR96669] adds 7e02426ba0c nios2: Remove custom instruction warnings adds 42f4e239924 nios2: Add -mcustom-fpu-cfg=fph2 adds 5e5d56919dd RTEMS: Add -mcustom-fpu-cfg=fph2 multilib adds a6d22fb21c6 openmp: Add support for the OpenMP 5.0 task detach clause adds a2960a04d51 testsuite: Fix up a testcase to find the right ISO_Fortran_ [...] adds 59cf67d1cf7 Daily bump. adds 3804e937b0e Default to DWARF5 adds 0f4c8f517b7 ipa: Adjust cgraph verifier to materialization on demand (P [...] adds 192105b6a2a Avoid assuming SSA_NAME_IDENTIFIER is nonnull. adds 56b5d13e278 aix: default to DWARF 4. adds b654d23a470 testsuite: Skip DWARF 5 testcases on AIX. adds 4c9bcd5c81a Daily bump. adds 4905f404018 Fix ChangeLog entries. adds 994fb69ac1b testsuite: powerpc fold-vec and sse updates. adds d3b41bde961 libgomp: Don't access gomp_sem_t as int using atomics uncon [...] adds 0f951b3dd34 RTEMS: Fix libgomp build adds 2e43880dbd4 libstd++: : Add workaround for as Error: file number less t [...] adds a81d2f1e414 libstdc++: Fix narrow char test to use stringbuf not wstringbuf adds 104304cd246 testsuite/97299 - fix test condition of gcc.dg/vect/slp-reduc-3.c adds acdc49fabf0 [arm,testsuite]: Fix options for vceqz_p64.c and vceqzq_p64.c adds b8c3f5196e1 libgomp: enable linux-futex on riscv64 adds e393f03b1a7 testsuite/97494 - adjust gcc.dg/vect/slp-11b.c adds ec153f96f89 libstdc++: Only test writing to wostream if supported [PR 98725] adds c7e276b869b analyzer: use "malloc" attribute adds 66cbe54960c Avoid no-stack-protector-attr fails on hppa*-*-*. adds 76c1dd15e4a Skip asm goto tests on hppa*-*-*. adds f56e14101b9 aix: document dwarf 4 default (and TPF default) adds 9675ccd64ef widening_mul: Fix up signed multiplication overflow check h [...] adds 32b6e917ac4 c++: Add CTAD + pack expansion testcase adds a89c5d3539c [PR97847] IRA: Skip abnormal critical edge splitting adds 325e70b47c6 libbacktrace: use correct directory/filename for DWARF 5 adds bfde774667f libbacktrace: don't fail tests if dwz fails adds 9a3ab93ceb2 [committed] Minor fix to pr41445-7 testcase adds ef1f8ee67d4 Daily bump. adds c907e439413 compiler: read embedcfg files, parse go:embed directives adds 9ee33d7c33f RISC-V: The 'multilib-generator' enhancement. adds 665e80ca5ec Fix PR ada/98740 adds 9b8741c98f2 ipa-sra: Do not remove return values needed because of non-call EH adds 049bfd186fa OpenMP/Fortran: Fixes for {use,is}_device_ptr adds 7d6f7e92c3b ipa/97673 - fix input_location leak adds 4b690f161b8 sparc,rtems: add __FIX_LEON3FT_TN0018 for affected targets adds f27cd6f4226 middle-end/98638 - avoid SSA reference to stmts after SSA d [...] adds 66dd412feea ipa/98330 - avoid ICEing on call indirect call adds 8227106f566 [committed] Fix dwarf-float.c test in testsuite adds 763b865a17d aarch64: Remove testing of saturation cumulative QC bit adds 04b472ad0e1 aarch64: Relax flags of saturation builtins adds 04cdb132020 [PATCH, rs6000] Update pr88233.c test (pr91799) adds 6a2a38620cf alias: Fix offset checks involving section anchors [PR92294] adds 6e6f3ed47e5 c++: Fix null this pointer [PR 98624] adds 7266ff2a243 c++: Remove unused fn adds c37f1d4081f c++: ICE when late parsing noexcept/NSDMI [PR98333] adds 29853c65324 c++: Always check access during late-parsing of members [PR58993] adds 9693e255ee2 PR middle-end/98664 - inconsistent -Wfree-nonheap-object fo [...] adds d89b00c095e c++: ICE with USING_DECL redeclaration [PR98687] adds eed40bca6f2 compiler: initialize variables with go:embed directives adds 2b27f37f90c c++: Crash when deducing template arguments [PR98659] adds a311dfaf92c Update gcc de.po. adds 6bc6094fa3f testsuite: aix testsuite adjustments adds f35a4f96373 Daily bump. adds b83604c75fe dwarf2out: reset generation count in toplev::finalize [PR98751] adds c05cdfb3f63 OpenMP/Fortran: Fix gfortran.dg/gomp/is_device_ptr-2.f90 adds 7ab1abf3b82 openmp: Don't ICE on detach clause with erroneous decl [PR98742] adds 34599780d0d tree-optimization/98758 - fix integer arithmetic in data-re [...] adds 4d2ecd960a0 builtins: Fix up two bugs in access_ref::inform_access [PR98721] adds a95538b6c5a Fix gfortran.dg/gomp/task-detach-1.f90 for non 64bit pointers adds ea74a3f548e vect: Fix VLA SLP invariant optimisation [PR98535] adds 79e1251b642 c++: Defer access checking when processing bases [PR82613] adds cafcfcb5840 c++: Fix tsubsting CLASS_PLACEHOLDER_TEMPLATE [PR95434] adds 49e8c14ef6f Optimize combination of comparisons to dec+compare adds 261cdd23195 Handle overflow in dependence analysis lambda ops gracefully adds 4334b524274 [PR98722] LRA: Check that target has no 3-op add insn to tr [...] adds 27c792895bd debug: Fix up DWARF 5 -g -flto -ffat-lto-objects [PR98765] adds f8c67777661 rs6000: Fix rs6000_emit_le_vsx_store (PR98549) adds e140f5fd3e2 aarch64: Split vec_selects of bottom elements into simple move adds 911f797a9be c++: Avoid UB in signed shift [PR 98625] adds 0bb27b81a76 libgomp: Fix up GOMP_task on s390x adds 842afc4e289 Re: trapv question adds fb39c4fe445 aix: make ctype_inline.h thread-safe and avoid _OBJ_DATA ch [...] adds b93d0e36c0a Daily bump. adds e711b67a908 Fix incorrect optimization by cprop_hardreg. adds fa9d1ad2ff6 testsuite/98224 - un-XFAIL Walloca-2.c on ilp32 adds 8afef308b49 testsuite/98241 - remove ilp32 XFAIL of gcc.dg/pr78973.c adds f46a40112ca testsuite/97299 - more gcc.dg/vect/slp-reduc-3.c massaging adds eaf883710c0 Fortran: This patch fixes comments 23 and 24 of PR96320. adds a1a967ce1ff libstdc++: Regenerate Makefile.in adds 3c1cf7350bf c++: Stat-hack for members [PR 98530] adds 9be0a89c95c gcc/fortran/intrinsic.texi: Fix typo adds 0568f801eff arm: [testuiste] Fix ivopts.c target test [PR96372] adds e154009f35a Fix typo in arm_mve.h __arm_vcmpneq_s8 return type adds 279d3a89b79 d: Enable private member access for __traits adds 43705f3fa34 aarch64: Use canonical RTL for sqdmlal patterns adds 0fb7aa205af c++: Fix up potential_constant_expression_1 FOR/WHILE_STMT [...] adds 7944753fad5 c++: Fix null this pointer [PR 98624] adds f645da0e4ab c++: Fix excessive instantiation inside decltype [PR71879] adds efb6bc55a93 fwprop: Allow (subreg (mem)) simplifications adds 68ba1039c7d [PR98777] LRA: Use preliminary created pseudo for in LRA el [...] adds 9929d04ee24 testsuite: Adjust cpp2a/lambda-uneval regrex adds 7559d465fda Daily bump. adds 070a1fb5f52 MAINTAINERS: Update my e-mail address adds bca467e56fe c++: ICE with delayed noexcept and attribute used [PR97966] adds ee78c20e74d Lower AVX512 vector comparison to AVX version when dest is vector. adds 4e3beaca15c arm: Fix ICE with incompatible values for -mfp16-format [PR98636]. adds fd61ca67f97 tree-optimization/98786 - fix issue with phiopt and abnormals adds e287a2a11d7 on ARRAY_REFs sign-extend offsets only from sizetype's prec [...] adds 36fe1cdc953 match.pd: Replace incorrect simplifications into copysign [ [...] adds 8bad25eb56b middle-end/98773 - always sign extend CHREC_RIGHT adds 4804de453e7 driver: do not check file existence here [PR 98452] adds b46027c6544 Drop time profile for multi-threaded training run. adds b2922559758 rs6000: Support variable insert and Expand vec_insert in ex [...] adds e3a8ef8ef2a rs6000: Enable vec_insert for P8 with rs6000_expand_vector_ [...] adds 4be156d6bef middle-end/98793 - properly handle BLKmode vectors in vecto [...] adds eee8ed2f22b testsuite: Uniquify test names [PR 98795] adds 9d33785f57d tree-ssa-mathopts: Use proper poly_int64 comparison with pa [...] adds d7e681fc3af Testcase for old PR 47059 adds bf8ee9e4eed Fortran: Fix for class functions as associated target [PR98565]. adds 25fc4d01a8e c++: ICE when mangling operator name [PR98545] adds a9ed18295bf c++: Fix up ubsan false positives on references [PR95693] adds 90cbc769006 c++: Fix base copy elision thinko [PR98744] adds 32a93eac7ad MAINTAINERS: Add myself for write after approval adds b485fa167ef dwarf2out: Always emit required 0 entries for DWARF 5 in *. [...] adds d08677c11dc testsuite: Fix sse2-andnpd-1.c and sse-andnps-1.c testscase [...] adds b30e19b517f testsuite: Fix a typo - UINON_TYPE to UNION_TYPE - in gcc.t [...] adds 70ab52b8caf testsuite: Fix a typo - UINON_TYPE to UNION_TYPE - in gcc.t [...] adds 9cead790738 doc: ensure GCC_EXTRA_DIAGNOSTIC_OUTPUT gets an HTML anchor adds ab8cde87cac testsuite: Enable spbp.C on AIX. adds 89100826ace c++: ICE with noexcept in class in member function [PR96623] adds 16b7b8a32d4 aarch64: Use RTL builtins for integer mla intrinsics adds 8502e23d1f2 Daily bump. adds eb9883c1312 testsuite: fix gcc.target/powerpc ilp32 failures adds a8cef3cba69 c++: 'this' injection and static member functions [PR97399] adds c63f091db89 rs6000: Fix up __m64 typedef in mmintrin.h [PR97301] adds 7e0f147a29f c++: private inheritance access diagnostics fix [PR17314] adds 81f928ec8e8 libphobos: Fix executables segfault on mipsel architecture adds 6b1633378b7 Daily bump. adds 02551aa9996 Daily bump. adds 389b67feac7 Arm: Add NEON and MVE complex mul, mla and mls patterns. adds b7a0507ad9f fold: Fix up strn{case,}cmp folding [PR98771] adds 28229916e1b RTEMS: Fix GCC specification adds c6b0e33febb Fortran: Fix deferred character lengths in array constructo [...] adds 5d01fc7c116 Fix internal error on extension with interface at -O2 adds 0433fc2d7d4 RTEMS: Fix default linker script adds defc40db9e0 middle-end/98807 - more vector_element_bits fixes adds 5089df534b8 Restore profile reproducibility. adds e05a117dc4b Enable -fprofile-reproducible=parallel-runs for profiledbootstrap. adds fe5cb7f94d4 configure: Add workaround for buggy binutils 2.35 [PR98811] adds 10c83fb7131 gcc/fortran/intrinsic.texi: Fix typos adds 94ff4c9dd98 c++: [[no_unique_address]] in empty base [PR98463] adds d9ad3b422f0 Fix wrong format for fprintf. adds 0194e2f02d7 libgomp: Add documentation for omp_fulfill_event runtime function adds a43e0dfb63f Add test case for PR 96843. adds 7d54cccad33 Commit test case for PR 96386. adds d6f1cf644c4 PR c++/98646 - spurious -Wnonnull calling a member on the r [...] adds a61efd46937 PR fortran/70070 - ICE on initializing character data beyon [...] adds 161e4c08624 Daily bump. adds 667c8e33270 skip asan-poisoning of discarded vars adds 7423731691e dwarf2asm: Fix up -gdwarf-64 for 32-bit targets adds eb77a934eec testsuite: Fix up pr98807.c on i686-linux [PR98807] adds 5a36cae275a d: Merge upstream dmd 609c3ce2d, phobos 3dd5df686 adds d9f50366102 amdgcn: Allow V64DFmode min/max reductions adds b3cc0c9a6ac testsuite/g++.dg/modules/modules.exp: Janitorial fixes adds 80198c701a7 Commit test case for PR 67539. adds d40b21eebc9 libgcov: improve profile reproducibility adds 2e81b16c243 liblsan: build missing lsan_posix.cpp file adds 4b59dbb5d67 middle-end/98726 - fix VECTOR_CST element access adds 5bbc80d0e40 Fix dumping of VEC_WIDEN_{PLUS,MINUS}_{LO,HI}_EXPR adds 17ad8cdebe6 aarch64: Tighten up checks for ubfix [PR98681] adds 6e44c09b2df dwarf2asm: Fix bootstrap on powerpc*-*-* [PR98839] adds 9c41bcc59c2 Fix PR ada/98228 adds e80f1f6b7a3 testsuite: Fix TBAA in sse*and*p[sd]*.c tests adds a4dfd0f089a c++: constexpr and empty fields [PR97566] adds 96253f069ea c++: Invisible refs are not restrict [PR97474] adds 78739c2df78 c++: Add support for -std=c++23 adds e62bb7f0834 Daily bump. adds efc9ccbfd0c varpool: Restore GENERIC TREE_READONLY automatic var optimi [...] adds da5c25f3710 Rename PROP_trees to PROP_gimple adds 003f0414291 Fortran: Fix ICE due to elemental procedure pointers [PR98472]. adds 6cf43433750 testsuite: Fix TBAA in {sse,avx}*and*p[sd]*.c tests adds 530b1d68876 Fix ICE for [PR target/98833]. adds 686b1cdfdc4 libgcc, i386: Add .note.GNU-stack sections to the ms sse/av [...] adds 4225af228b5 Fortran: Fix ICE due to elemental procedure pointers [PR93924/5]. adds f004d6d9fab libstdc++: Add string contains member functions for C++2b adds 9d66505a5df aarch64: Use RTL builtins for integer mla_n intrinsics adds a199da782fc libstdc++: Optimize std::string_view::find [PR 66414] adds d2201ac0df4 aarch64: Use RTL builtins for integer mls intrinsics adds 3fd10728cb1 aarch64: Use RTL builtins for integer mls_n intrinsics adds c91db798ec6 tree-optimization/98854 - avoid some PHI BB vectorization adds 2bcceb6fc59 libstdc++: Add std::experimental::simd from the Parallelism TS 2 adds 02e32295b28 libstdc++: Add simd testsuite adds c31a633e13f libstdc++: Use printf to print control characters adds d53a4f9b681 aarch64: Use RTL builtins for [su]mlal intrinsics adds 3670dbe4905 libstdc++: Regenerate libstdc++ HTML docs adds 7a279bed24e Combine patterns for p10 load-cmpi fusion adds 55163419211 aarch64: Fix up *aarch64_bfxilsi_uxtw [PR98853] adds 9cd7c32549f c++: Dependent using enum [PR97874] adds 081c96621da [PR97684] IRA: Recalculate pseudo classes if we added new p [...] adds 1cdca4261e8 Fix strides for C descriptors with stride > 2. adds aa69f0a8203 Daily bump. adds f76d0d86454 RISC-V: Fix -march option parsing when extension exists. adds fbe37371cf3 rs6000: Fix vec insert ilp32 ICE and test failures [PR98799] adds a523add327c rtl-optimization/80960 - avoid creating garbage RTL in DSE adds c392d040f6c c++: Some C++20 and C++23 option help fixes adds 33a7a93218b PR fortran/86470 - ICE with OpenMP, class(*) allocatable adds f7a6d314e7f Fix LTO bootstrap on Windows adds fdb904a1822 aarch64: Reimplement vshrn_n* intrinsics using builtins adds d61ca09ec93 aarch64: Reimplement vshrn_high_n* intrinsics using builtins adds af66f4f1b06 c++: header unit template alias merging [PR 98770] adds 87301e3956d aarch64: Use RTL builtins for [su]mlal_n intrinsics No new revisions were added by this update. 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libstdc++-v3/testsuite/experimental/simd/tests/trunc_ceil_floor.cc create mode 100644 libstdc++-v3/testsuite/experimental/simd/tests/where.cc -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-Os updated (8ca9c7eb67 -> 53e556e5b4)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-Os in repository toolchain/ci/binutils-gdb. from 8ca9c7eb67 bfin: Skip non SEC_ALLOC section for R_BFIN_FUNCDESC adds 58eadc4b69 Fix building gdb with gcc-4.x adds c14dee84dd Update my email address (long overdue!) adds 17e8913732 Add myself to gdb/MAINTAINERS adds 5aa06b1b14 Automatic date update in version.in adds 5fda40b28f gas: make [248]byte directives available everywhere adds 3624a6c15c PR26539, memory leak in inflate.c adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status adds 7cf91a2481 sim: m32r: clean up redundant test coverage adds 89bfc2a429 sim: frv: clean up redundant test coverage adds 137d6efd8a sim: mips: delete empty stub test dir adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness adds bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 adds 5a11fff005 gdb/tui: compare pointer to nullptr, not 0 adds e403a898b5 Automatic date update in version.in adds 1368b914e9 sim: testsuite: flatten tree adds eb6e6af8c1 PR26002 undefined symbol VER_NDX_GLOBAL vs. VER_NDX_LOCAL adds ad92f33d38 Tidy inflateEnd calls adds 68b007788a ld/x86: Add -z report-relative-reloc adds 75a933f399 ld/elf/x86: Don't compare IFUNC address in the shared object adds 514fca98df Automatic date update in version.in adds edf0f284b1 PR binutils/23460: Increase the max number of open files to 20 adds d46153313b Automatic date update in version.in adds 25294ff049 gold: Remove the circular IFUNC dependency in ifuncmain6pie adds 994b251328 ld/elf: Ignore section symbols when matching linkonce with comdat adds 44365e88c0 PR27198, segv in S_IS_WEAK adds cecb191290 gdb: const-ify unpack_* functions in remote.c adds e3b2741b16 gdb: const-ify remote_target::add_current_inferior_and_threa [...] adds b5c8f22d28 gdb: move remote_target::start_remote variable to narrower scope adds aa2838ccc5 gdb: const-ify hostio methods parameter in remote.c adds d3d7d1ba3b [gdb/tdep] Handle si_addr_bnd in compat_siginfo_from_siginfo adds 326adec374 PR26378, sections initialised only by linker scripts are alw [...] adds 6a9ad81c44 gdb/riscv: use a single regset supply function for riscv fbs [...] adds 705989f19a as: Automatically enable DWARF5 support adds 02baa13385 gdb/testsuite: remove actual addresses from some test names adds 4cfcd3b333 sim: common: modernize gennltvals.sh adds 5e25901fcc sim: common: delete configure & Makefile adds f89f33e57c sim: common: simplify version script adds f0c1efa53d Automatic date update in version.in adds 85e963f185 ld: Just xfail riscv little endian targets for compressed1d.d test. adds 0e7620dcdc sim: bfin: delete accidental ADI copyright adds a75a6a4164 [GOLD] powerpc assertion failure adds 30845f113a PowerPC use_local_plt adds 0c4e2c6c88 [gdb/testsuite] Fix gdb.arch/i386-mpx.exp with -m32 adds 1485212328 [gdb/testsuite] Fix gdb.base/step-over-syscall.exp with -m32 adds c98de297b3 libctf, ld: fix data symbol test with newer GCC adds e05a3e5a49 libctf: lookup_by_name: do not return success for nonexisten [...] adds 26503e2f5e libctf, create: fix ctf_type_add of structs with unnamed members adds ccbe4c82d5 Use gdb::array_view for setting value bytes in trad-frame adds c65ca138c4 sim: ppc: update version script usage adds bdec2917b1 Convert some frame functions to use gdb::array_view. adds a9a87d3525 trad-frame cleanups adds 1c3b85ad28 use DISABLE_COPY_AND_ASSIGN in switch_thru_all_uis adds 11321a0505 Automatic date update in version.in adds 8bd10d6b16 PowerPC64 synthetic symbols adds 4bd7c90276 PowerPC: Don't generate unused section symbols adds 037e8112b9 [gdb/server] Don't overwrite fs/gs_base with -m32 adds 6f52fdf404 Fix a few stap parser issues and add a new test for probe ex [...] adds 1402665c8f [gdb/testsuite] Skip gdb.rust/*.exp for target board unix/-m32 adds 7c794afd54 [gdb/testsuite] Fix gdb.python/py-format-string.exp with -m32 adds 6571ffc620 gdb/testsuite: add links for handled control sequences in li [...] adds c3e96aa78f gdb/testsuite: rename _cur_x/_cur_y to _cur_col/_cur_row in [...] adds 3f0781f389 Automatic date update in version.in adds a6c11cbb14 gdb/remote.c: address conflicting enum and method name adds 6bd434d6ca gdb: make some variables static adds 17e593e966 gdb/dwarf: add some logging in dwarf2/read.c adds de53369b2e gdb/dwarf: add assertion in maybe_queue_comp_unit adds f9e9ba90b3 gdb/testsuite: use multi_line in gdb.base/skip.exp adds d4dd4fca16 gdb: change debug_bfd_cache to bool adds c78eec4424 mips XPASS pr26936 adds 498ff0328f PR27218, memory access violation in dwarf2dbg.c adds be07043ea8 PR27221, 058430b4a1 warnings while assembling the Linux kernel adds 7cb6d92a3f gdb: convert arm to new-style debug macros adds 325d39e4e0 Add Python support for hardware breakpoints adds a72d0f3d69 gdb/doc: reorder and group sections relating to aliases adds 730af66356 gdb/testsuite: improve logging in lib/tuiterm.exp adds 439706e6a9 gdb: use interruptible_select when connecting to a remote adds 1e15fcac94 gdb: convert bfd-cache to new-style debug macros adds d3abc0cee0 gdb: remove unused f77_array_offset_tbl from f-valprint.c adds a59902a7c1 gdb: convert auto-load to new-style debug macros adds d5d24e12f9 Fix build errors for armhf adds cd211c75cb Handle additional connection error adds e534c7e8c4 Automatic date update in version.in adds c651f0a614 MAINTAINERS: Update my e-mail address adds cc4bc93e52 gdb/doc: down case contents of @var adds fe461d2f70 gdb/doc: move @menu to the end of the node adds 5b7d941b90 gdb: add owner-related methods to struct type adds 3062502019 gdb: remove TYPE_OBJFILE_OWNED macro adds 344e9841d9 gdb: remove TYPE_OBJFILE macro adds baf2b57f18 gdb: move set remote commands to remote.c adds cda09ec9f9 gdb: move remote_debug to remote.{h,c} adds 02349803fc gdb: change remote_debug to bool adds 2189c31265 gdb: add remote_debug_printf adds d8c4766d31 gdb/doc: don't rely on @menu item within the docs adds e7b430724d gdb: don't print escape characters when a style is disabled adds 9d2d8a16e1 gdb: add new version style adds 0ac85db529 gdb/testsuite: eliminate gdb_suppress_tests mechanism adds 705646c074 Fix expected output of gdb.base/line65535.exp with dwarf-5 adds e753591581 Automatic date update in version.in adds 1af4c9c420 Disable bracketed paste mode in GDB tests adds ef45cb65a7 Use readline's variant of Windows patch adds d3ee35dbf7 Improve gdb_tilde_expand logic. adds dd5ca05f47 gdb: fix regression in copy_type_recursive adds c99d72de18 Automatic date update in version.in adds 9f7f6cb8d2 Remove call to reset from compile_to_object adds 18454c151f DWARF-5: Fix parsing DWARF-5 line number tables adds 3637a558a5 Use std::vector for "registers_used" in compile feature adds b10bae1875 Avoid crash when "compile" expression uses cooked register adds 68fcee4fa7 PR27228, .reloc wrong symbol emitted for undefined local symbol adds 9b351c9bc9 Minor updates to the 'how to make a release' document adds eea133e655 gas: Add a testcase for PR gas/27228 adds 940d0202fd DWARF-5: Ignore empty range in DWARF-5 line number tables adds 123b18bf62 Automatic date update in version.in adds b8df69003d Update linker scripts with the names of new DWARF-5 debug sections. adds 04de9f3e31 gdb/doc: move @menu blocks to the end of their enclosing @node adds 9e42b97628 Add some more DWARF-5 sections adds acd6125f01 Add test case for symbol menu for local enumerators adds 191849105b Specially handle array contexts in Ada expression resolution adds a625a8c9eb Fix fixed-point regression with recent GCC adds f3bdc2dbb9 gdb/docs: add parentheses in Python examples using print adds 9f6c202e57 [gdb/symtab] Handle DW_AT_ranges with DW_FORM_sec_off in par [...] adds 01a01e0ab3 Automatic date update in version.in adds d0021af39c [gdb/testsuite] Fix gdb.opt/solib-intra-step.exp with -m32 adds 4ca40594f9 [gdb/testsuite] Fix gdb.threads/killed-outside.exp with -m32 adds d56834cbfb arc: Log "pc" value in "arc_skip_prologue" adds e37709f090 Fix thinko in objcopy's memory freeing code. adds ac3571d941 Fix the date for the last entry in gdb/ChangeLog adds d0cc52bdf2 gdb: Add default reggroups for ARC adds 4287950e54 pr27228 testcase adds 9886ff0319 gas byte test adds a45ef9a30b gas testsuite tidy adds 1c9c9b9b55 PR27226, ld.bfd contains huge .rodata section adds c3ffb8f340 Segmentation fault i386-gen adds 4cb1265b3f bfd: add elfcore_write_file_note adds 4ef367bffd Use debug_prefixed_printf_cond in windows-nat.c adds 1f583bc2fc nios2: Don't disable relaxation with --gdwarf-N adds c22788d614 Automatic date update in version.in adds 2eda57ef61 ld: Fix a typo in testsuite/ld-x86-64/bnd-plt-1.d adds 67965ba289 Simplify the code at the end of objcopy's main() function. adds f04ce15e83 ld: depend on libctf adds bb3c2d4d94 Remove extra space after @pxref in gdb.texinfo adds 807f647cac GDB: aarch64: Add ability to displaced step over a BR/BLR in [...] adds 59b59f08f6 Avoid use after free with logging and debug redirect. adds 07b8b9e7c5 Automatic date update in version.in adds 22efa3d307 [gdb/testsuite] Fix ERROR in gdb.dwarf2/dw2-out-of-range-end [...] adds 2f985dd1ac [gdb/testsuite] Fix gdb.ada/out_of_line_in_inlined.exp with [...] adds def97fb945 PR27259, SHF_LINK_ORDER self-link adds 2a7f6487d0 [gdb/breakpoints] Fix longjmp master breakpoint with separat [...] adds 24cf63899b gdb: update comment for execute_command_to_string adds 47918cca26 gdb/testsuite: unset XDG_CONFIG_HOME adds 0318cca493 gold: Skip address size and segment selector for DWARF5 adds a7ad3cb1ff Fix binutils tools so that they can cope with the special /d [...] adds 53e556e5b4 ld: Add a test for PR ld/27259 No new revisions were added by this update. Summary of changes: ChangeLog | 5 + Makefile.def | 1 + Makefile.in | 1 + bfd/ChangeLog | 107 + bfd/compress.c | 3 +- bfd/dwarf2.c | 5 +- bfd/elf-bfd.h | 2 + bfd/elf-linker-x86.h | 3 + bfd/elf.c | 8 + bfd/elf32-ft32.c | 3 +- bfd/elf32-i386.c | 36 + bfd/elf32-ppc.c | 55 +- bfd/elf64-ppc.c | 83 +- bfd/elf64-x86-64.c | 33 + bfd/elflink.c | 32 +- bfd/elfnn-riscv.c | 319 +- bfd/elfxx-riscv.c | 54 +- bfd/elfxx-riscv.h | 4 +- bfd/elfxx-x86.c | 50 +- bfd/elfxx-x86.h | 4 + bfd/version.h | 2 +- binutils/ChangeLog | 36 + binutils/MAINTAINERS | 8 +- binutils/README-how-to-make-a-release | 24 +- binutils/bucomm.c | 15 + binutils/elfedit.c | 14 + binutils/objcopy.c | 33 +- binutils/readelf.c | 8 +- gas/ChangeLog | 139 + gas/config/obj-elf.c | 4 - gas/config/tc-i386.c | 3 + gas/config/tc-nios2.c | 4 - gas/config/tc-riscv.c | 521 ++- gas/config/tc-riscv.h | 6 +- gas/doc/as.texi | 7 - gas/dwarf2dbg.c | 33 +- gas/read.c | 3 + gas/testsuite/gas/all/byte.d | 4 - gas/testsuite/gas/all/byte.l | 3 - gas/testsuite/gas/all/byte.s | 2 - gas/testsuite/gas/all/gas.exp | 5 - gas/testsuite/gas/all/local-label-overflow.d | 5 +- gas/testsuite/gas/all/none.d | 2 +- gas/testsuite/gas/all/sleb128-2.d | 2 +- gas/testsuite/gas/all/sleb128-4.d | 3 +- gas/testsuite/gas/all/sleb128-5.d | 2 +- gas/testsuite/gas/all/sleb128-7.d | 2 +- gas/testsuite/gas/all/sleb128-9.d | 2 +- gas/testsuite/gas/all/string.d | 2 +- gas/testsuite/gas/elf/bignums.d | 2 +- gas/testsuite/gas/elf/dwarf-5-file0.d | 2 +- gas/testsuite/gas/elf/dwarf2-20.d | 4 - gas/testsuite/gas/elf/elf.exp | 6 +- gas/testsuite/gas/elf/group0c.d | 2 +- gas/testsuite/gas/elf/group1a.d | 2 +- gas/testsuite/gas/elf/missing-build-notes.d | 2 +- gas/testsuite/gas/elf/pr27228.d | 10 + gas/testsuite/gas/elf/pr27228.s | 5 + gas/testsuite/gas/elf/section-symbol-redef.d | 2 +- gas/testsuite/gas/elf/section0.d | 2 +- gas/testsuite/gas/elf/section1.d | 2 +- gas/testsuite/gas/elf/section10.d | 2 +- gas/testsuite/gas/elf/section11.d | 4 +- gas/testsuite/gas/elf/section15.d | 2 +- gas/testsuite/gas/elf/section4.d | 2 +- gas/testsuite/gas/elf/section6.d | 2 +- gas/testsuite/gas/elf/section7.d | 2 +- gas/testsuite/gas/elf/symtab.d | 4 +- gas/testsuite/gas/elf/symtab.s | 2 +- gas/testsuite/gas/elf/warn-2.s | 7 - gas/testsuite/gas/i386/i386.exp | 1 + gas/testsuite/gas/i386/pr27198.d | 2 + gas/testsuite/gas/i386/pr27198.err | 5 + gas/testsuite/gas/i386/pr27198.s | 1 + gas/testsuite/gas/lns/lns-diag-1.l | 2 - gas/testsuite/gas/m68hc11/indexed12.d | 4 - gas/testsuite/gas/macros/irp.d | 2 +- gas/testsuite/gas/macros/repeat.d | 2 +- gas/testsuite/gas/macros/rept.d | 2 +- gas/testsuite/gas/macros/test2.d | 2 +- gas/testsuite/gas/macros/test3.d | 1 - gas/testsuite/gas/macros/vararg.d | 2 +- gas/testsuite/gas/nios2/relax.d | 25 + gas/testsuite/gas/nios2/relax.s | 5 + gas/testsuite/gas/ppc/power4.d | 1 - gas/testsuite/gas/ppc/test1elf32.d | 1 - gas/testsuite/gas/ppc/test1elf64.d | 1 - gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +- .../gas/riscv/priv-reg-fail-read-only-01.l | 136 +- .../gas/riscv/priv-reg-fail-read-only-02.l | 48 +- gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +- .../gas/riscv/priv-reg-fail-version-1p10.l | 48 +- .../gas/riscv/priv-reg-fail-version-1p11.l | 46 +- .../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +- gas/write.c | 4 +- gdb/ChangeLog | 525 +++ gdb/MAINTAINERS | 5 +- gdb/Makefile.in | 1 + gdb/NEWS | 5 + gdb/aarch64-linux-tdep.c | 16 +- gdb/aarch64-tdep.c | 73 +- gdb/ada-lang.c | 26 +- gdb/alpha-mdebug-tdep.c | 4 +- gdb/alpha-tdep.c | 8 +- gdb/amd64-fbsd-tdep.c | 2 +- gdb/amd64-linux-tdep.c | 4 +- gdb/amd64-obsd-tdep.c | 2 +- gdb/arc-linux-tdep.c | 4 +- gdb/arc-tdep.c | 24 +- gdb/arch/aarch64-insn.h | 9 + gdb/arm-linux-tdep.c | 2 +- gdb/arm-tdep.c | 50 +- gdb/auto-load.c | 148 +- gdb/auto-load.h | 13 +- gdb/avr-tdep.c | 6 +- gdb/breakpoint.c | 182 +- gdb/cli/cli-cmds.c | 36 - gdb/cli/cli-interp.c | 8 + gdb/cli/cli-style.c | 17 +- gdb/cli/cli-style.h | 6 +- gdb/coffread.c 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}/bfin/c_dsp32mult_dr_ih.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_iu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_i.s | 0 .../{sim => }/bfin/c_dsp32mult_dr_m_iutsh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_mix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_t.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_tu.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_i.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_is.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_i.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_is.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_s.s | 0 .../{sim => }/bfin/c_dsp32mult_pair_m_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_u.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_a0alr.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_af.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rp.s | 0 .../{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s | 0 .../{sim => }/bfin/c_dsp32shift_align16.s | 0 .../{sim => }/bfin/c_dsp32shift_align24.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s | 0 .../{sim => }/bfin/c_dsp32shift_expadj_h.s | 0 .../{sim => }/bfin/c_dsp32shift_expadj_l.s | 0 .../{sim => }/bfin/c_dsp32shift_expadj_r.s | 0 .../{sim => }/bfin/c_dsp32shift_expexp_r.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shift_lhalf_rp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_pack.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_rot.s | 0 .../{sim => }/bfin/c_dsp32shift_rot_mix.s | 0 .../{sim => }/bfin/c_dsp32shift_signbits_r.s | 0 .../{sim => }/bfin/c_dsp32shift_signbits_rh.s | 0 .../{sim => }/bfin/c_dsp32shift_signbits_rl.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shift_vmax.s | 0 .../{sim => }/bfin/c_dsp32shift_vmaxvmax.s | 0 .../{sim => }/bfin/c_dsp32shiftim_a0alr.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_ln_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_lp_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rn_s.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rp.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahalf_rp_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s | 0 .../{sim => }/bfin/c_dsp32shiftim_ahh_s.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s | 0 .../{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s | 0 sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s | 0 .../{sim => }/bfin/c_dspldst_ld_dr_ippm.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s | 0 .../{sim => }/bfin/c_dspldst_ld_drhi_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s | 0 .../{sim => }/bfin/c_dspldst_ld_drlo_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s | 0 .../{sim => }/bfin/c_dspldst_st_dr_ippm.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s | 0 .../{sim => }/bfin/c_dspldst_st_drhi_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s | 0 .../{sim => }/bfin/c_dspldst_st_drlo_ipp.s | 0 sim/testsuite/{sim => }/bfin/c_except_illopcode.S | 0 sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S | 0 sim/testsuite/{sim => }/bfin/c_except_user_mode.S | 0 sim/testsuite/{sim => }/bfin/c_interr_disable.S | 0 .../{sim => }/bfin/c_interr_disable_enable.S | 0 sim/testsuite/{sim => }/bfin/c_interr_excpt.S | 0 .../{sim => }/bfin/c_interr_loopsetup_stld.S | 0 sim/testsuite/{sim => }/bfin/c_interr_nested.S | 0 sim/testsuite/{sim => }/bfin/c_interr_nmi.S | 0 sim/testsuite/{sim => }/bfin/c_interr_pending.S | 0 sim/testsuite/{sim => }/bfin/c_interr_pending_2.S | 0 sim/testsuite/{sim => }/bfin/c_interr_timer.S | 0 .../{sim => }/bfin/c_interr_timer_reload.S | 0 .../{sim => }/bfin/c_interr_timer_tcount.S | 0 .../{sim => }/bfin/c_interr_timer_tscale.S | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_drlo.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_dr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_dr.s | 0 .../{sim => }/bfin/c_ldimmhalf_lzhi_ibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_pr.s | 0 sim/testsuite/{sim => }/bfin/c_ldimmhalf_pibml.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xh.s | 0 .../{sim => }/bfin/c_ldst_ld_d_p_ppmm_hbx.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_p.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_mm.s | 0 sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_pp.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xb.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_b.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstidxl_st_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_ld_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_st_dr_h.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstii_st_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstiifp_st_preg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_hi.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_lo.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_h_xh.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_lohi.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_hi.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_lo.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dreg.s | 0 sim/testsuite/{sim => }/bfin/c_ldstpmod_st_lohi.s | 0 sim/testsuite/{sim => }/bfin/c_linkage.s | 0 .../{sim => }/bfin/c_logi2op_alshft_mix.s | 0 .../{sim => }/bfin/c_logi2op_arith_shft.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bitclr.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bitset.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bittgl.s | 0 sim/testsuite/{sim => }/bfin/c_logi2op_bittst.s | 0 .../{sim => }/bfin/c_logi2op_log_l_shft.s | 0 .../{sim => }/bfin/c_logi2op_log_l_shft_astat.S | 0 .../{sim => }/bfin/c_logi2op_log_r_shft.s | 0 .../{sim => }/bfin/c_logi2op_log_r_shft_astat.S | 0 sim/testsuite/{sim => }/bfin/c_logi2op_nbittst.s | 0 sim/testsuite/{sim => }/bfin/c_loopsetup_nested.s | 0 .../{sim => }/bfin/c_loopsetup_nested_bot.s | 0 .../{sim => }/bfin/c_loopsetup_nested_prelc.s | 0 .../{sim => }/bfin/c_loopsetup_nested_top.s | 0 sim/testsuite/{sim => }/bfin/c_loopsetup_overlap.s | 0 .../{sim => }/bfin/c_loopsetup_preg_div2_lc0.s | 0 .../{sim => }/bfin/c_loopsetup_preg_div2_lc1.s | 0 .../{sim => }/bfin/c_loopsetup_preg_lc0.s | 0 .../{sim => }/bfin/c_loopsetup_preg_lc1.s | 0 .../{sim => }/bfin/c_loopsetup_preg_stld.s | 0 sim/testsuite/{sim => }/bfin/c_loopsetup_prelc.s | 0 .../{sim => }/bfin/c_loopsetup_topbotcntr.s | 0 sim/testsuite/{sim => }/bfin/c_mmr_interr_ctl.s | 0 sim/testsuite/{sim => }/bfin/c_mmr_loop.S | 0 .../{sim => }/bfin/c_mmr_loop_user_except.S | 0 .../{sim => }/bfin/c_mmr_ppop_illegal_adr.S | 0 .../{sim => }/bfin/c_mmr_ppopm_illegal_adr.S | 0 sim/testsuite/{sim => }/bfin/c_mmr_timer.S | 0 sim/testsuite/{sim => }/bfin/c_mode_supervisor.S | 0 sim/testsuite/{sim => }/bfin/c_mode_user.S | 0 .../{sim => }/bfin/c_mode_user_superivsor.S | 0 .../{sim => }/bfin/c_multi_issue_dsp_ld_ld.s | 0 .../{sim => }/bfin/c_multi_issue_dsp_ldst_1.s | 0 .../{sim => }/bfin/c_multi_issue_dsp_ldst_2.s | 0 .../{sim => }/bfin/c_progctrl_call_pcpr.s | 0 sim/testsuite/{sim => }/bfin/c_progctrl_call_pr.s | 0 .../{sim => }/bfin/c_progctrl_clisti_interr.S | 0 .../{sim => }/bfin/c_progctrl_csync_mmr.S | 0 .../{sim => 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sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_a0alr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align16.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align24.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_l.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expexp_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_pack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmaxvmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_a0alr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_except_illopcode.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_user_mode.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable_enable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_loopsetup_stld.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nested.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nmi.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_reload.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tcount.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tscale.S (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drlo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_ibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_pibml.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_h.s 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}/bfin/c_ldst_st_p_d_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_mm.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_b.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dr_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstii_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_preg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_hi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_lo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_h_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_lohi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_hi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_lo.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_lohi.s (100%) rename sim/testsuite/{sim => }/bfin/c_linkage.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_alshft_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_arith_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bitclr.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bitset.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bittgl.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_bittst.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft_astat.S (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft.s (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft_astat.S (100%) rename sim/testsuite/{sim => }/bfin/c_logi2op_nbittst.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_bot.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_prelc.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_top.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_overlap.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc0.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc1.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc0.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc1.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_stld.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_prelc.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_topbotcntr.s (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_interr_ctl.s (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_loop.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_loop_user_except.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_ppop_illegal_adr.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_ppopm_illegal_adr.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_supervisor.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user_superivsor.S (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ld_ld.s (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pcpr.s (100%) rename sim/testsuite/{sim => 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}/frv/fcbulr.cgs (100%) rename sim/testsuite/{sim => }/frv/fckeq.cgs (100%) rename sim/testsuite/{sim => }/frv/fckge.cgs (100%) rename sim/testsuite/{sim => }/frv/fckgt.cgs (100%) rename sim/testsuite/{sim => }/frv/fckle.cgs (100%) rename sim/testsuite/{sim => }/frv/fcklg.cgs (100%) rename sim/testsuite/{sim => }/frv/fcklt.cgs (100%) rename sim/testsuite/{sim => }/frv/fckne.cgs (100%) rename sim/testsuite/{sim => }/frv/fckno.cgs (100%) rename sim/testsuite/{sim => }/frv/fcko.cgs (100%) rename sim/testsuite/{sim => }/frv/fckra.cgs (100%) rename sim/testsuite/{sim => }/frv/fcku.cgs (100%) rename sim/testsuite/{sim => }/frv/fckue.cgs (100%) rename sim/testsuite/{sim => }/frv/fckug.cgs (100%) rename sim/testsuite/{sim => }/frv/fckuge.cgs (100%) rename sim/testsuite/{sim => }/frv/fckul.cgs (100%) rename sim/testsuite/{sim => }/frv/fckule.cgs (100%) rename sim/testsuite/{sim => }/frv/fcmpd.cgs (100%) rename sim/testsuite/{sim => }/frv/fcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/fdabss.cgs (100%) rename sim/testsuite/{sim => }/frv/fdadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fdcmps.cgs (100%) rename sim/testsuite/{sim => }/frv/fddivs.cgs (100%) rename sim/testsuite/{sim => }/frv/fditos.cgs (100%) rename sim/testsuite/{sim => }/frv/fdivd.cgs (100%) rename sim/testsuite/{sim => }/frv/fdivs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmas.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmss.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmulcs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/fdnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsads.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/fdstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fdsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fdtoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fitod.cgs (100%) rename sim/testsuite/{sim => }/frv/fitos.cgs (100%) rename sim/testsuite/{sim => }/frv/fmad.cgs (100%) rename sim/testsuite/{sim => }/frv/fmaddd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmadds.cgs (100%) rename sim/testsuite/{sim => }/frv/fmas.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmovs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmss.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fmsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuld.cgs (100%) rename sim/testsuite/{sim => }/frv/fmuls.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegd.cgs (100%) rename sim/testsuite/{sim => }/frv/fnegs.cgs (100%) rename sim/testsuite/{sim => }/frv/fnop.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/addss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr400/csdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/maveh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/scutss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/sdivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/slass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smass.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smsss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/smu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/subss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr400/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcpl.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/dcul.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/allinsn.exp (100%) rename sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/dcpl.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/dcul.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mabshs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mtrap.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrtd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/fstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fteq.cgs (100%) rename sim/testsuite/{sim => }/frv/ftge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftgt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftieq.cgs (100%) rename sim/testsuite/{sim => }/frv/ftige.cgs (100%) rename sim/testsuite/{sim => }/frv/ftigt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftile.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftine.cgs (100%) rename sim/testsuite/{sim => }/frv/ftino.cgs (100%) rename sim/testsuite/{sim => }/frv/ftio.cgs (100%) rename sim/testsuite/{sim => }/frv/ftira.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiu.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiue.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiug.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiuge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftiul.cgs (100%) rename sim/testsuite/{sim => }/frv/ftle.cgs (100%) rename sim/testsuite/{sim => }/frv/ftlg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftlt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftne.cgs (100%) rename sim/testsuite/{sim => }/frv/ftno.cgs (100%) rename sim/testsuite/{sim => }/frv/fto.cgs (100%) rename sim/testsuite/{sim => }/frv/ftra.cgs (100%) rename sim/testsuite/{sim => }/frv/ftu.cgs (100%) rename sim/testsuite/{sim => }/frv/ftue.cgs (100%) rename sim/testsuite/{sim => }/frv/ftug.cgs (100%) rename sim/testsuite/{sim => }/frv/ftuge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftul.cgs (100%) rename sim/testsuite/{sim => }/frv/ftule.cgs (100%) create mode 100644 sim/testsuite/frv/grloop.ms create mode 100644 sim/testsuite/frv/hello.ms rename sim/testsuite/{sim => }/frv/icei.cgs (100%) rename sim/testsuite/{sim => }/frv/ici.cgs (100%) rename sim/testsuite/{sim => }/frv/icpl.cgs (100%) rename sim/testsuite/{sim => }/frv/icul.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts.exp (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr400.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr500.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/mp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/privileged_instruction.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/regalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/reset.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/shadow_regs.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/timer.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpil.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.pcgs (100%) rename sim/testsuite/{sim => }/frv/ld.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldd.cgs (100%) rename sim/testsuite/{sim => }/frv/lddc.cgs (100%) rename sim/testsuite/{sim => }/frv/lddcu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddf.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/lddi.cgs (100%) rename sim/testsuite/{sim => }/frv/lddu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldq.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/ldshi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldub.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/lduh.cgs (100%) rename sim/testsuite/{sim => }/frv/lduhi.cgs (100%) rename sim/testsuite/{sim => }/frv/lduhu.cgs (100%) rename sim/testsuite/{sim => }/frv/lrbranch.pcgs (100%) rename sim/testsuite/{sim => }/frv/mabshs.cgs (100%) rename sim/testsuite/{sim => }/frv/maddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/maddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mand.cgs (100%) rename sim/testsuite/{sim => }/frv/maveh.cgs (100%) rename sim/testsuite/{sim => }/frv/mbtoh.cgs (100%) rename sim/testsuite/{sim => }/frv/mbtohe.cgs (100%) rename sim/testsuite/{sim => }/frv/mclracc.cgs (100%) rename sim/testsuite/{sim => }/frv/mcmpsh.cgs (100%) rename sim/testsuite/{sim => }/frv/mcmpuh.cgs (100%) rename sim/testsuite/{sim => }/frv/mcop1.cgs (100%) rename sim/testsuite/{sim => }/frv/mcop2.cgs (100%) rename sim/testsuite/{sim => }/frv/mcplhi.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpli.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/mcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutss.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mdrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdunpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/membar.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhd.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhw.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethih.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethis.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsetloh.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsetlos.cgs (100%) rename sim/testsuite/{sim => }/frv/mhtob.cgs (100%) create mode 100644 sim/testsuite/frv/misc.exp rename sim/testsuite/{sim => }/frv/mmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmrdhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmrdhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mnop.cgs (100%) rename sim/testsuite/{sim => }/frv/mnot.cgs (100%) rename sim/testsuite/{sim => }/frv/mor.cgs (100%) rename sim/testsuite/{sim => }/frv/mov.cgs (100%) rename sim/testsuite/{sim => }/frv/movfg.cgs (100%) rename sim/testsuite/{sim => }/frv/movfgd.cgs (100%) rename sim/testsuite/{sim => }/frv/movfgq.cgs (100%) rename sim/testsuite/{sim => }/frv/movgf.cgs (100%) rename sim/testsuite/{sim => }/frv/movgfd.cgs (100%) rename sim/testsuite/{sim => }/frv/movgfq.cgs (100%) rename sim/testsuite/{sim => }/frv/movgs.cgs (100%) rename sim/testsuite/{sim => }/frv/movsg.cgs (100%) rename sim/testsuite/{sim => }/frv/mpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mqlclrhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqlmths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsaths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotri.cgs (100%) rename sim/testsuite/{sim => }/frv/msaths.cgs (100%) rename sim/testsuite/{sim => }/frv/msathu.cgs (100%) rename sim/testsuite/{sim => }/frv/msllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrlhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mtrap.cgs (100%) rename sim/testsuite/{sim => }/frv/munpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mwcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mwcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mwtacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mwtaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mxor.cgs (100%) rename sim/testsuite/{sim => }/frv/nandcr.cgs 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3 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-Os updated (615a4cf6 -> 666cffa8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-Os in repository toolchain/ci/base-artifacts. discards 615a4cf6 4: update: binutils-glibc: 1 discards a76fe08e 3: reset: gcc-0b76990a9d75d97b84014e37519086b81824c307: 1 discards 6320b831 2: update: binutils-glibc: 1 discards 7f159fd5 1: reset: gcc-9e64f17d044767248175fece80a2759d94c45fc4: 1 discards 18726372 0: update: binutils-glibc: 1 new 666cffa8 0: update: binutils-gcc-glibc: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (615a4cf6) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 210 +- 02-prepare_abe/console.log | 422 +- 03-build_abe-binutils/console.log | 11893 +-- 04-build_abe-stage1/console.log | 15551 ++-- 05-build_abe-linux/console.log | 1996 +- 06-build_abe-glibc/console.log | 40674 ++++++----- 07-build_abe-stage2/console.log | 32420 ++++----- 09-benchmark--Os/benchmark-start.log | 2 +- 09-benchmark--Os/benchmark.log | 14 +- 09-benchmark--Os/console.log | 187 +- 10-check_regression/console.log | 1988 +- 10-check_regression/results-0.csv | 1973 - 10-check_regression/results-1.csv | 1970 - 10-check_regression/results-brief.csv | 29 - 10-check_regression/results-compare.csv | 128 - 10-check_regression/results-full.csv | 1968 - 10-check_regression/results.csv | 128 - 10-check_regression/results.log | 4902 +- 11-update_baseline/console.log | 6214 +- 11-update_baseline/extra-bisect-params | 2 +- 11-update_baseline/results-0.csv | 1978 - 11-update_baseline/results-1.csv | 1970 - 11-update_baseline/results-brief.csv | 29 - 11-update_baseline/results-compare.csv | 128 - 11-update_baseline/results-full.csv | 1968 - 11-update_baseline/results.csv | 128 - 11-update_baseline/results.log | 4724 +- 11-update_baseline/results.regressions | 1 - console.log | 111567 +++++++++++++---------------- jenkins/manifest.sh | 26 +- results | 2 +- results_id | 2 +- 32 files changed, 104706 insertions(+), 140488 deletions(-) delete mode 100644 11-update_baseline/results.regressions -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

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