[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-Os updated (6cc992412c -> f678099de9)
by gitīŧ git.linaro.org
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-Os
in repository toolchain/ci/glibc.
from 6cc992412c alpha: Provide wait4 for static library [BZ #27150]
adds ef8c78a6c6 Import idx.h from gnulib
adds 47f4316095 Import filename.h from gnulib
adds 448a256359 malloc: Add scratch_buffer_dupfree
adds c6e0b0b5b0 stdlib: Sync canonicalize with gnulib [BZ #10635] [BZ #26592 [...]
adds ecdb06cdf2 support: Add support_small_thread_stack_size
adds 3016596a81 Add SEGV_MTEAERR and SEGV_MTESERR from Linux 5.10.
adds caa884dda7 Remove dbl-64/wordsize-64
adds 9e97f239ea Remove dbl-64/wordsize-64 (part 2)
adds ecce11aa07 x86: Support GNU_PROPERTY_X86_ISA_1_V[234] marker [BZ #26717]
adds 18b640c570 Update NEWS for CVE-2019-25013.
adds 2f056e8a5d aarch64: define PI_STATIC_AND_HIDDEN
adds eeaa19f75e mntent: Use __putc_unlocked instead of fputc_unlocked
adds 1b5c9dfeb2 ARC: Regenerate ulps
adds c6e2ca2c3f POSIX locale: Fix typo in comment
adds a7e9dbb774 Add xchdir to libsupport.
adds 7a72265436 Add xfchmod to libsupport
adds 2cd361b511 posix: Correct attribute access mode on readlinkat [BZ #27024].
adds c31b1f5231 riscv: support GNU indirect function
adds 313bfd505e riscv: Initialize $gp before resolving the IRELATIVE relocation
adds 1c426b1d59 Update STATX_ATTR_DAX value from Linux 5.10.
adds 7b9c3260bc support: Add xchmod wrapper
adds 42dda89dcb posix: Fix return value of system if shell can not be execut [...]
adds 4dddd7e9cb posix: Sync tempname with gnulib [BZ #26648]
adds bf7db6d369 math: Add BZ#18980 fix back on dbl-64 cosh
adds 87d583c6e8 install: Replace scripts/output-format.sed with objdump -f [ [...]
adds 0400f92833 Makerules: Do not require startup files for format.lds probe object
adds f430293d84 posix: consume less entropy on tempname
adds 2ef23b5205 x86: Set header.feature_1 in TCB for always-on CET [BZ #27177]
adds 86a4d3fa7d elf: work around a gcc bug in elf_get_dynamic_info
adds efbbd9c33a ldconfig/x86: Store ISA level in cache and aux cache
adds cf12900645 Use the right argument code in unnormal tests
adds 7137d682eb ifuncmain6pie: Remove the circular IFUNC dependency [BZ #20019]
adds d18f59bf92 Fix x86 build with --enable-tunable=no
adds 2d651eb926 x86: Move x86 processor cache info to cpu_features
adds cc528f9a7e math/test-tgmath2: Fix fabs failure when no long double
adds 86f65dffc2 ld.so: Add --list-tunables to print tunable values
new 96f17e6e63 ARC: nofpu: Regenerate ulps
new f678099de9 Update hppa libm-test-ulps
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
Makerules | 16 +-
NEWS | 7 +
benchtests/strcoll-inputs/filelist#en_US.UTF-8 | 1 -
config.h.in | 3 +
config.make.in | 1 -
configure | 19 -
configure.ac | 11 -
elf/Makefile | 13 +
elf/cache.c | 39 +-
elf/dl-cache.c | 4 +
elf/dl-main.h | 2 +-
elf/dl-tunables.c | 43 ++
elf/dl-tunables.h | 2 +
elf/dl-usage.c | 7 +-
elf/elf.h | 35 +-
elf/get-dynamic-info.h | 41 +-
elf/ifuncmain6pie.c | 14 +-
elf/ifuncmod6.c | 8 +-
elf/ldconfig.c | 18 +-
elf/readelflib.c | 81 ++-
elf/readlib.c | 7 +-
elf/rtld.c | 19 +
elf/tst-glibc-hwcaps-2-cache.c | 45 ++
.../etc/ld.so.conf | 0
.../postclean.req | 0
elf/tst-glibc-hwcaps-2-cache.script | 8 +
elf/tst-rtld-list-tunables.exp | 14 +
elf/tst-rtld-list-tunables.sh | 34 ++
include/filename.h | 112 +++++
include/idx.h | 114 +++++
include/scratch_buffer.h | 16 +
io/bits/statx-generic.h | 2 +-
libc-abis | 1 +
localedata/locales/POSIX | 2 +-
malloc/Makefile | 1 +
malloc/Versions | 1 +
.../scratch_buffer_dupfree.c | 38 +-
malloc/tst-scratch_buffer.c | 26 +-
manual/tunables.texi | 38 ++
math/libm-test-driver.c | 12 +-
math/libm-test-fpclassify.inc | 14 +-
math/libm-test-isinf.inc | 14 +-
math/libm-test-isnan.inc | 14 +-
math/libm-test-issignaling.inc | 14 +-
math/test-tgmath2.c | 4 +-
misc/mntent_r.c | 12 +-
posix/unistd.h | 2 +-
scripts/output-format.sed | 35 --
stdlib/canonicalize.c | 546 +++++++++++++++------
stdlib/test-bz22786.c | 11 +-
stdlib/tst-system.c | 17 +
support/Makefile | 3 +
support/support_set_small_thread_stack_size.c | 12 +-
.../wordsize-64/s_getpayload.c => support/xchdir.c | 25 +-
sysdeps/x86/link_map.h => support/xchmod.c | 25 +-
sysdeps/x86/link_map.h => support/xfchmod.c | 23 +-
support/xthread.h | 2 +
support/xunistd.h | 3 +
sysdeps/aarch64/Implies | 1 -
sysdeps/aarch64/configure | 5 +
sysdeps/aarch64/configure.ac | 4 +
sysdeps/alpha/Implies | 1 -
sysdeps/arc/fpu/libm-test-ulps | 8 +-
sysdeps/arc/nofpu/libm-test-ulps | 11 +-
sysdeps/generic/dl-cache.h | 16 +-
sysdeps/{x86/link_map.h => generic/dl-isa-level.h} | 20 +-
.../s_getpayload.c => generic/elf-read-prop.h} | 31 +-
sysdeps/generic/ldconfig.h | 22 +-
sysdeps/hppa/fpu/libm-test-ulps | 23 +-
sysdeps/ieee754/dbl-64/e_acosh.c | 50 +-
sysdeps/ieee754/dbl-64/e_cosh.c | 76 ++-
sysdeps/ieee754/dbl-64/e_fmod.c | 202 +++-----
sysdeps/ieee754/dbl-64/e_log10.c | 42 +-
sysdeps/ieee754/dbl-64/s_frexp.c | 81 +--
sysdeps/ieee754/dbl-64/s_getpayload.c | 15 +-
sysdeps/ieee754/dbl-64/s_issignaling.c | 14 +-
sysdeps/ieee754/dbl-64/s_llround.c | 49 +-
sysdeps/ieee754/dbl-64/s_lround.c | 57 +--
sysdeps/ieee754/dbl-64/s_modf.c | 80 ++-
sysdeps/ieee754/dbl-64/s_remquo.c | 43 +-
sysdeps/ieee754/dbl-64/s_roundeven.c | 79 +--
sysdeps/ieee754/dbl-64/s_scalbln.c | 63 ++-
sysdeps/ieee754/dbl-64/s_scalbn.c | 63 ++-
sysdeps/ieee754/dbl-64/s_setpayload_main.c | 42 +-
sysdeps/ieee754/dbl-64/s_totalorder.c | 32 +-
sysdeps/ieee754/dbl-64/s_totalordermag.c | 24 +-
sysdeps/ieee754/dbl-64/wordsize-64/e_acosh.c | 68 ---
sysdeps/ieee754/dbl-64/wordsize-64/e_cosh.c | 85 ----
sysdeps/ieee754/dbl-64/wordsize-64/e_fmod.c | 106 ----
sysdeps/ieee754/dbl-64/wordsize-64/e_log10.c | 87 ----
sysdeps/ieee754/dbl-64/wordsize-64/s_frexp.c | 66 ---
sysdeps/ieee754/dbl-64/wordsize-64/s_issignaling.c | 43 --
sysdeps/ieee754/dbl-64/wordsize-64/s_llround.c | 75 ---
sysdeps/ieee754/dbl-64/wordsize-64/s_lround.c | 86 ----
sysdeps/ieee754/dbl-64/wordsize-64/s_modf.c | 65 ---
sysdeps/ieee754/dbl-64/wordsize-64/s_remquo.c | 111 -----
sysdeps/ieee754/dbl-64/wordsize-64/s_roundeven.c | 71 ---
sysdeps/ieee754/dbl-64/wordsize-64/s_scalbln.c | 60 ---
sysdeps/ieee754/dbl-64/wordsize-64/s_scalbn.c | 60 ---
.../ieee754/dbl-64/wordsize-64/s_setpayload_main.c | 54 --
sysdeps/ieee754/dbl-64/wordsize-64/s_totalorder.c | 76 ---
.../ieee754/dbl-64/wordsize-64/s_totalordermag.c | 73 ---
sysdeps/mips/mips64/Implies | 1 -
sysdeps/posix/system.c | 4 +
sysdeps/posix/tempname.c | 291 ++++++-----
sysdeps/riscv/dl-irel.h | 56 +++
sysdeps/riscv/dl-machine.h | 44 +-
sysdeps/s390/s390-64/Implies | 1 -
sysdeps/sparc/sparc64/Implies | 1 -
sysdeps/unix/sysv/linux/arm/readelflib.c | 22 +-
sysdeps/unix/sysv/linux/bits/siginfo-consts.h | 6 +-
sysdeps/unix/sysv/linux/faccessat.c | 3 +-
sysdeps/unix/sysv/linux/ia64/readelflib.c | 22 +-
sysdeps/unix/sysv/linux/mips/readelflib.c | 22 +-
sysdeps/unix/sysv/linux/powerpc/readelflib.c | 22 +-
sysdeps/unix/sysv/linux/riscv/readelflib.c | 22 +-
sysdeps/unix/sysv/linux/s390/readelflib.c | 22 +-
sysdeps/unix/sysv/linux/sparc/readelflib.c | 22 +-
sysdeps/unix/sysv/linux/x86/elf-read-prop.h | 60 +++
sysdeps/unix/sysv/linux/x86/readelflib.c | 23 +-
sysdeps/unix/sysv/linux/x86_64/Makefile | 51 ++
.../unix/sysv/linux/x86_64/tst-glibc-hwcaps-2.c | 84 ++++
.../sysv/linux/x86_64/x86-64-isa-level-VALUE.c | 4 +
sysdeps/x86/Makefile | 36 ++
.../wordsize-64/s_getpayload.c => x86/abi-note.c} | 32 +-
sysdeps/x86/cacheinfo.c | 46 +-
sysdeps/x86/cacheinfo.h | 400 +--------------
sysdeps/x86/configure | 79 +++
sysdeps/x86/configure.ac | 66 +++
sysdeps/x86/cpu-features.c | 38 +-
sysdeps/x86/dl-cacheinfo.h | 460 +++++++++++++++++
sysdeps/x86/dl-cet.c | 17 +-
.../s_getpayload.c => x86/dl-isa-level.h} | 28 +-
sysdeps/x86/dl-prop.h | 113 +++--
sysdeps/x86/get-isa-level.h | 67 +++
sysdeps/x86/include/cpu-features.h | 24 +
sysdeps/x86/isa-level.c | 97 ++++
sysdeps/x86/link_map.h | 18 +-
sysdeps/x86/tst-isa-level-1.c | 104 ++++
sysdeps/x86/tst-isa-level-mod-1-baseline.c | 1 +
sysdeps/x86/tst-isa-level-mod-1-v2.c | 1 +
sysdeps/x86/tst-isa-level-mod-1-v3.c | 1 +
sysdeps/x86/tst-isa-level-mod-1-v4.c | 1 +
sysdeps/x86/{link_map.h => tst-isa-level-mod-1.c} | 20 +-
sysdeps/x86/tst-setjmp-cet.c | 1 +
sysdeps/x86_64/Implies | 1 -
sysdeps/x86_64/dl-hwcaps-subdirs.c | 31 +-
sysdeps/x86_64/tst-glibc-hwcaps.c | 41 +-
148 files changed, 3456 insertions(+), 3021 deletions(-)
create mode 100644 elf/tst-glibc-hwcaps-2-cache.c
copy elf/{tst-glibc-hwcaps-cache.root => tst-glibc-hwcaps-2-cache.root}/etc/ld.so. [...]
copy elf/{tst-glibc-hwcaps-cache.root => tst-glibc-hwcaps-2-cache.root}/postclean. [...]
create mode 100644 elf/tst-glibc-hwcaps-2-cache.script
create mode 100644 elf/tst-rtld-list-tunables.exp
create mode 100755 elf/tst-rtld-list-tunables.sh
create mode 100644 include/filename.h
create mode 100644 include/idx.h
copy support/support_set_small_thread_stack_size.c => malloc/scratch_buffer_dupfre [...]
delete mode 100644 scripts/output-format.sed
copy sysdeps/ieee754/dbl-64/wordsize-64/s_getpayload.c => support/xchdir.c (59%)
copy sysdeps/x86/link_map.h => support/xchmod.c (61%)
copy sysdeps/x86/link_map.h => support/xfchmod.c (61%)
copy sysdeps/{x86/link_map.h => generic/dl-isa-level.h} (61%)
copy sysdeps/{ieee754/dbl-64/wordsize-64/s_getpayload.c => generic/elf-read-prop.h} (58%)
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/e_acosh.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/e_cosh.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/e_fmod.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/e_log10.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_frexp.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_issignaling.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_llround.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_lround.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_modf.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_remquo.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_roundeven.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_scalbln.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_scalbn.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_setpayload_main.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_totalorder.c
delete mode 100644 sysdeps/ieee754/dbl-64/wordsize-64/s_totalordermag.c
create mode 100644 sysdeps/riscv/dl-irel.h
create mode 100644 sysdeps/unix/sysv/linux/x86/elf-read-prop.h
create mode 100644 sysdeps/unix/sysv/linux/x86_64/tst-glibc-hwcaps-2.c
create mode 100644 sysdeps/unix/sysv/linux/x86_64/x86-64-isa-level-VALUE.c
copy sysdeps/{ieee754/dbl-64/wordsize-64/s_getpayload.c => x86/abi-note.c} (52%)
rename sysdeps/{ieee754/dbl-64/wordsize-64/s_getpayload.c => x86/dl-isa-level.h} (56%)
create mode 100644 sysdeps/x86/get-isa-level.h
create mode 100644 sysdeps/x86/isa-level.c
create mode 100644 sysdeps/x86/tst-isa-level-1.c
create mode 100644 sysdeps/x86/tst-isa-level-mod-1-baseline.c
create mode 100644 sysdeps/x86/tst-isa-level-mod-1-v2.c
create mode 100644 sysdeps/x86/tst-isa-level-mod-1-v3.c
create mode 100644 sysdeps/x86/tst-isa-level-mod-1-v4.c
copy sysdeps/x86/{link_map.h => tst-isa-level-mod-1.c} (61%)
create mode 100644 sysdeps/x86/tst-setjmp-cet.c
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[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-Os updated (a958b2fc6da -> c7e276b869b)
by gitīŧ git.linaro.org
This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-Os
in repository toolchain/ci/gcc.
from a958b2fc6da aarch64: Add support for unpacked SVE ASRD
adds 67fbb7f0fda Daily bump.
adds ab88f360723 analyzer: fix ICE merging dereferencing unknown ptrs [PR98628]
adds 640296c367f make FOR_EACH_IMM_USE_STMT safe for early exits
adds 240f0a490da Delete dead code in ix86_expand_sse_comi.
adds 814299a9d49 c++: -Wmissing-field-initializers in unevaluated ctx [PR98620]
adds ab96073df00 MAINTAINERS: Add myself for write after approval
adds ff99d05f40f configure, make: Fix up --enable-link-serialization
adds 13d47c37a2c reassoc: Optimize in reassoc x < 0 && y < 0 to (x | y) < 0 [...]
adds 24ea113f75c widening_mul: Fix up ICE caused by my signed multiplication [...]
adds b2230210f17 gcov: add more debugging facility
adds e91910d3576 options: properly compare string arguments
adds 52a170b1a18 tree-optimization/98550 - fix BB vect unrolling check
adds e0bec6ceac4 c++: Fix ICE with CTAD in concept [PR98611]
adds cf2ac1c30af [PR97969] LRA: Transform pattern `plus (plus (hard reg, con [...]
adds 25bef68902f arm: Add movmisalign patterns for MVE (PR target/97875)
adds 1aff68d54c3 Fix typo in function-abi.h
adds 248feb2fa2c gcov: fix printf format for 32-bit hosts
adds e2aa8a5f982 libcody: Simplify configure [PR 98414, 98509]
adds 728fee7a798 MAINTAINERS: Fix spacing
adds 5a9cfad2de9 Avoid a couple more ICEs in print_mem_ref (PR c/98597).
adds cfaaa6a1ca7 syscall: ensure openat uses variadic libc wrapper
adds 6851dda2e79 Daily bump.
adds abb3993e49c amdgcn: Fix subdf3 pattern
adds c8812bac8ee amdgcn: Improve FP division accuracy
adds 3df6fac0080 amdgcn: Fix exec register live-on-entry to BB in md-reorg
adds 7993fe1877a amdgcn: Remove dead code for fixed v0 register
adds b668a06e37f i386: Optimize _mm_unpacklo_epi8 of 0 vector as second argu [...]
adds 3f325179b32 [PATCH v2] aarch64: Add cpu cost tables for A64FX
adds 6b70fa678b1 ipa: remove a dead code
adds 5d057bfeff7 i386: Add define_insn_and_split patterns for btrl [PR96938]
adds ffd28c265e6 tree-optimization/98640 - fix bogus sign-extension with VN
adds 4c598b038df doc: Fix typos in C++ Modules documentation
adds 0db5f488486 libstdc++: Remove <debug/array> from Doxygen config
adds 7875e8dc831 if-to-switch: fix also virtual phis
adds b1d1e2b54c6 i386, expand: Optimize also 256-bit and 512-bit permutatati [...]
adds 2b356e689c3 hurd: libgcc unwinding over signal trampolines with SIGINFO
adds c23aea6edc9 gcc-changelog: Allow modifications to old ChangeLogs without entry
adds f04e7e540e2 libstdc++: Fix typo in ChangeLog-2020
adds e9cb89b936f Hurd: Enable ifunc by default
adds 40b371a7c2f sh: Remove match_scratch operand test
adds 6d75168146f rtl-ssa: Fix reversed comparisons in accesses.h comment
adds 5ab67cdee61 aarch64: Tighten condition on sve/sel* tests
adds 3ddc18251a8 tree-optimization/92645 - improve SLP with existing vectors
adds cf7a3353061 aarch64: Add support for unpacked SVE MLA and MAD
adds 264a1269b44 aarch64: Add support for unpacked SVE MLS and MSB
adds 11cbea852b0 c++: Fix cp_build_function_call_vec [PR 98626]
adds a2d04f3d2c9 mklog: support define_insn_and_split format
adds 285fa338b06 tree-optimization/92645 - avoid harmful early BIT_FIELD_REF [...]
adds 7d7ef413ef1 gcc-changelog: Support multiline parentheses wrapping
adds 8fc183ccd06 match.pd: Fold (~X | C) ^ D into (X | C) ^ (~D ^ C) if (~D [...]
adds 796ead19f85 c++: Failure to lookup using-decl name [PR98231]
adds 8cba7cb3202 or1k: Implement profile hook calling _mcount
adds e1171c32502 or1k: Add builtin define to detect hard float
adds b77f6d2fa84 or1k: Support for softfloat to emulate hw exceptions
adds 6ed637c585b or1k: Add note to indicate execstack
adds e40fdcc4f42 or1k: Fixup exception header data encodings
adds be0851b8e93 Daily bump.
adds c7f1ff01a23 aarch64: Reimplement vmovn_high_* intrinsics using builtins
adds 52cd1cd1b67 aarch64: reimplement vqmovn_high* intrinsics using builtins
adds 48f8d1d48f2 aarch64: Reimplememnt vmovn/vmovl intrinsics with builtins instead
adds e45c41988bf vect: Account for unused IFN_LOAD_LANES results
adds 8f8762a2e86 match.pd: Optimize ~(X >> Y) to ~X >> Y if ~X can be simpli [...]
adds 0efdc7b31c2 i386: Fix the pmovzx SSE4.1 define_insn_and_split patterns [...]
adds 08a4adcf2b6 i386: Remove reduntand assignment in i386-options.c [PR98671]
adds d61d2a5f3ce c++: Fix erroneous parm comparison logic [PR 98372]
adds 194a9d67be4 libstdc++: Update copyright dates on new files
adds a802a2ef5f1 arm: Replace calls to __builtin_vcge* by <=,>= in arm_neon. [...]
adds a512079ef40 i386: Update PR target/95021 tests
adds 2182274f510 tree-optimization/98674 - improve dependence analysis
adds 5ebdd53534d i386: Resolve variable shadowing in i386-options.c [PR98671]
adds 77d372abec0 x86: Error on -fcf-protection with incompatible target
adds 236d6a33ca6 mklog: skip unsupported files
adds 7624c58c6b7 gcov: add one more pytest
adds aa3d33dccb5 RTEMS: Fix Ada build for riscv
adds 57a4f5e4eac libstdc++: Define function to throw filesystem_error [PR 98471]
adds 6106dfb9f73 [nvptx libgomp plugin] Build only in supported configurations
adds 9ac3e2feb3d libgo: update hurd support
adds d0d2becf2df PR fortran/98661 - valgrind issues with error recovery
adds c1a2cf88059 Revert "PR fortran/98661 - valgrind issues with error recovery"
adds 9e1e6e63104 PR fortran/98661 - valgrind issues with error recovery
adds 05a30af3f23 libstdc++: Implement N3644 for _GLIBCXX_DEBUG iterators
adds 505caa7295b [gcn offloading] Only supported in 64-bit configurations
adds 088e46b8d4d declare getpass in analyzer/sensitive-1.c test
adds 6541fcadc86 use sigjmp_buf for analyzer sigsetjmp tests
adds 3651c1b5c9c calibrate intervals to avoid zero in futures poll test
adds bdd1b1f5552 PR fortran/93340 - fix missed substring simplifications
adds f6ffd449e0c c++: Tweak g++.dg/template/pr98372.C.
adds 8a18261afd9 analyzer: const fixes [PR98679]
adds dea4a32b24f analyzer: fixes to -fdump-analyzer-json
adds fe701195313 slp: elide intermediate nodes for complex add and avoid truncate
adds 500600c7840 slp: Support optimizing load distribution
adds e09173d84da slp: support complex multiply and complex multiply conjugate
adds 31fac31800b slp: support complex FMA and complex FMA conjugate
adds 478e571a3ee slp: support complex FMS and complex FMS conjugate
adds b50df1e749b slp: Add complex operations class to share first match amon [...]
adds 59832db9a71 slp: Add Tests for complex mul, mls and mla"
adds f1096055854 Add GCC_EXTRA_DIAGNOSTIC_OUTPUT environment variable for fi [...]
adds 02e7af1122c libstdc++: Implement N3644 for _GLIBCXX_DEBUG iterators
adds 387f6c15d30 Handle fancy_abort before diagnostic initialization [PR98586]
adds f1fc27b6c51 c++: Minor refactoring in process_init_constructor_record
adds b95d97f1a5f jit: remove "Alpha" warning from docs
adds 5fff80fd79c Daily bump.
adds b0ccd3922f5 compiler: add support for reading embedcfg files
adds c4eec1efae0 testsuite: Fix sed script errors in complex tests
adds 2ea6f4a377e tree-optimization/98685 - fix placement of extern converts
adds 7432f255b70 arm: Auto-vectorization for MVE: vshl
adds bfab355012c arm: Auto-vectorization for MVE: vshr
adds 0411ae7f08e libatomic, libgomp, libitc: Fix bootstrap [PR70454]
adds cb60334b716 testsuite/96098 - remove redundant testcase
adds 1a630642009 arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics
adds d03f14c354a testsuite/96147 - remove scanning for ! vect_hw_misalign
adds e1bd80fb706 testsuite/96147 - key scanning on vect_hw_misalign
adds aa4ee5798fe testsuite/96147 - scan for vectorized load
adds b36c9cd0947 testsuite/96147 - align vector access
adds dc8475e3348 Pytest in tests: improve
adds 446703ccc2c tree-optimization/96376 - do not check alignment for invari [...]
adds f1d054017ef Revert "arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 [...]
adds 63999d751df arm: Implement vceqq_p64, vceqz_p64 and vceqzq_p64 intrinsics
adds f9a577927eb IBM Z: Fix linking to libatomic in target test cases
adds 7f6cdaa9a8d rtl-ssa: Fix a silly typo
adds f2cc526f47a recog: Fix insn_change_watermark destructor
adds 5a783f42d77 aarch64: Add a minipass for fusing CC insns [PR88836]
adds 492b90f33df c++: Fix langspecs with -fsyntax-only [PR98591]
adds 1ba71fabb78 preprocessor: Make quoting : [PR 95253]
adds 7d0df0aeb67 i386: Use cpp_define_formatted for __SIZEOF_FLOAT80__ definition
adds d3959070aa4 [PATCH] aarch64: Implement vmlsl[_high]* intrinsics using builtins
adds 50dbced2f37 openmp: Change the way of building of reduction array type
adds adb520606ce c-family: Improve MEM_REF printing for diagnostics [PR98597]
adds a3128bf0128 bootstrap: fix failing diagnostic selftest on Windows [PR98696]
adds aaec739250b testsuite: Add testcase coverage for already fixed [PR96671]
adds c0194736b47 gcc.dg/analyzer tests: use __builtin_alloca, not alloca.h
adds cd09079cfd5 c++: Fix list-init of array of no-copy type [PR63707]
adds ad260343385 AArch64: Add NEON, SVE and SVE2 RTL patterns for Multiply, [...]
adds 424deca72b6 c++: Fix copy elision for base initialization
adds d75199f7823 c++: Avoid redundant copy in {} init [PR98642]
adds e63c2161d09 drop -dumpbase-ext from producer string
adds 5c046034e3e match.pd: Optimize (x < 0) ^ (y < 0) to (x ^ y) < 0 etc. [PR96681]
adds 0425f4c1b63 match.pd: Generalize the PR64309 simplifications [PR96669]
adds e1efa6af61a preprocessor: Make quoting : [PR 95253]
adds 9beb6d88eff c++: Fix qualified array-type construction [PR 98538]
adds b90e4a97419 fortran: Fixes a bug in ISO_Fortran_binding.c.
adds c029fcb5680 Reset force_source_line in final.c
adds f1ad419ebfd rs6000, vector integer multiply/divide/modulo instructions
adds 2f7f0d32e74 Daily bump.
adds 2c356f221bb libstdc++-v3: Add -fcf-protection=none to -march=i486
adds b673e7547fb cd_dce: Return TODO_update_address_taken from last cd_dce [ [...]
adds e2559c3945a match.pd: Optimize ((cst << x) & 1) [PR96669]
adds 7e02426ba0c nios2: Remove custom instruction warnings
adds 42f4e239924 nios2: Add -mcustom-fpu-cfg=fph2
adds 5e5d56919dd RTEMS: Add -mcustom-fpu-cfg=fph2 multilib
adds a6d22fb21c6 openmp: Add support for the OpenMP 5.0 task detach clause
adds a2960a04d51 testsuite: Fix up a testcase to find the right ISO_Fortran_ [...]
adds 59cf67d1cf7 Daily bump.
adds 3804e937b0e Default to DWARF5
adds 0f4c8f517b7 ipa: Adjust cgraph verifier to materialization on demand (P [...]
adds 192105b6a2a Avoid assuming SSA_NAME_IDENTIFIER is nonnull.
adds 56b5d13e278 aix: default to DWARF 4.
adds b654d23a470 testsuite: Skip DWARF 5 testcases on AIX.
adds 4c9bcd5c81a Daily bump.
adds 4905f404018 Fix ChangeLog entries.
adds 994fb69ac1b testsuite: powerpc fold-vec and sse updates.
adds d3b41bde961 libgomp: Don't access gomp_sem_t as int using atomics uncon [...]
adds 0f951b3dd34 RTEMS: Fix libgomp build
adds 2e43880dbd4 libstd++: : Add workaround for as Error: file number less t [...]
adds a81d2f1e414 libstdc++: Fix narrow char test to use stringbuf not wstringbuf
adds 104304cd246 testsuite/97299 - fix test condition of gcc.dg/vect/slp-reduc-3.c
adds acdc49fabf0 [arm,testsuite]: Fix options for vceqz_p64.c and vceqzq_p64.c
adds b8c3f5196e1 libgomp: enable linux-futex on riscv64
adds e393f03b1a7 testsuite/97494 - adjust gcc.dg/vect/slp-11b.c
adds ec153f96f89 libstdc++: Only test writing to wostream if supported [PR 98725]
adds c7e276b869b analyzer: use "malloc" attribute
No new revisions were added by this update.
Summary of changes:
ChangeLog | 8 +
MAINTAINERS | 7 +-
contrib/ChangeLog | 30 +
contrib/gcc-changelog/git_commit.py | 44 +-
contrib/gcc-changelog/test_email.py | 12 +
contrib/gcc-changelog/test_patches.txt | 82 +
contrib/mklog.py | 15 +-
contrib/test_mklog.py | 42 +
gcc/ChangeLog | 918 ++++++++
gcc/DATESTAMP | 2 +-
gcc/Makefile.in | 7 +
gcc/ada/ChangeLog | 6 +
gcc/ada/Makefile.rtl | 5 +
gcc/analyzer/ChangeLog | 28 +
gcc/analyzer/analyzer.h | 3 +-
gcc/analyzer/diagnostic-manager.cc | 15 +-
gcc/analyzer/engine.cc | 29 +-
gcc/analyzer/exploded-graph.h | 4 +
gcc/analyzer/pending-diagnostic.h | 2 +-
gcc/analyzer/region-model-impl-calls.cc | 9 +
gcc/analyzer/region-model.cc | 9 +
gcc/analyzer/region-model.h | 1 +
gcc/analyzer/sm-malloc.cc | 767 +++++-
gcc/analyzer/store.cc | 9 +-
gcc/analyzer/store.h | 4 +-
gcc/analyzer/supergraph.cc | 29 +-
gcc/attribs.h | 2 +
gcc/builtin-types.def | 8 +-
gcc/builtins.c | 10 +
gcc/c-family/ChangeLog | 30 +
gcc/c-family/c-pragma.h | 3 +-
gcc/c-family/c-pretty-print.c | 286 ++-
gcc/c/ChangeLog | 15 +
gcc/c/c-parser.c | 57 +-
gcc/c/c-typeck.c | 62 +-
gcc/cgraph.c | 4 +-
gcc/cgraphunit.c | 2 -
gcc/common.opt | 2 +-
gcc/common/config/i386/i386-common.c | 2 +-
gcc/config.gcc | 6 +-
gcc/config/aarch64/aarch64-cc-fusion.cc | 296 +++
gcc/config/aarch64/aarch64-cost-tables.h | 103 +
gcc/config/aarch64/aarch64-passes.def | 1 +
gcc/config/aarch64/aarch64-protos.h | 1 +
gcc/config/aarch64/aarch64-simd-builtins.def | 23 +
gcc/config/aarch64/aarch64-simd.md | 145 +-
gcc/config/aarch64/aarch64-sve.md | 232 +-
gcc/config/aarch64/aarch64-sve2.md | 42 +
gcc/config/aarch64/aarch64.c | 79 +-
gcc/config/aarch64/arm_neon.h | 195 +-
gcc/config/aarch64/iterators.md | 115 +-
gcc/config/aarch64/t-aarch64 | 6 +
gcc/config/arm/arm.c | 9 +
gcc/config/arm/arm.h | 40 +
gcc/config/arm/arm_neon.h | 87 +-
gcc/config/arm/arm_neon_builtins.def | 2 -
gcc/config/arm/mve.md | 70 +-
gcc/config/arm/neon.md | 78 -
gcc/config/arm/vec-common.md | 81 +
gcc/config/gcn/gcn-valu.md | 62 +-
gcc/config/gcn/gcn.c | 28 +-
gcc/config/gcn/gcn.md | 3 +-
gcc/config/gcn/mkoffload.c | 260 +-
gcc/config/i386/i386-builtins.c | 2 +-
gcc/config/i386/i386-builtins.h | 4 -
gcc/config/i386/i386-c.c | 9 +-
gcc/config/i386/i386-expand.c | 31 +-
gcc/config/i386/i386-options.c | 25 +-
gcc/config/i386/i386-options.h | 2 +-
gcc/config/i386/i386.c | 2 +-
gcc/config/i386/i386.h | 6 +-
gcc/config/i386/i386.md | 65 +
gcc/config/i386/predicates.md | 32 +
gcc/config/i386/sse.md | 189 ++
gcc/config/ia64/ia64.c | 9 +
gcc/config/mips/mips.c | 9 +
gcc/config/nios2/nios2.c | 51 +-
gcc/config/nios2/t-rtems | 146 +-
gcc/config/or1k/linux.h | 2 +
gcc/config/or1k/or1k.h | 21 +-
gcc/config/rs6000/aix71.h | 3 +
gcc/config/rs6000/aix72.h | 3 +
gcc/config/rs6000/altivec.h | 4 +
gcc/config/rs6000/altivec.md | 2 -
gcc/config/rs6000/rs6000-builtin.def | 21 +
gcc/config/rs6000/rs6000-call.c | 53 +
gcc/config/rs6000/rs6000.c | 10 +
gcc/config/rs6000/rs6000.md | 5 +-
gcc/config/rs6000/vsx.md | 211 +-
gcc/config/sh/sh.md | 3 +-
gcc/config/sparc/sparc.c | 6 +
gcc/configure | 7 +-
gcc/configure.ac | 7 +-
gcc/cp/ChangeLog | 90 +
gcc/cp/call.c | 145 +-
gcc/cp/cp-tree.h | 3 +-
gcc/cp/lang-specs.h | 40 +-
gcc/cp/module.cc | 4 +-
gcc/cp/name-lookup.c | 10 +
gcc/cp/name-lookup.h | 1 +
gcc/cp/parser.c | 53 +-
gcc/cp/pt.c | 4 +
gcc/cp/semantics.c | 61 +-
gcc/cp/tree.c | 27 +-
gcc/cp/typeck2.c | 46 +-
gcc/d/ChangeLog | 10 +
gcc/diagnostic.c | 189 +-
gcc/diagnostic.h | 23 +-
gcc/doc/extend.texi | 172 ++
gcc/doc/install.texi | 2 +-
gcc/doc/invoke.texi | 72 +-
gcc/doc/md.texi | 134 ++
gcc/doc/sourcebuild.texi | 4 +
gcc/doc/tree-ssa.texi | 16 +-
gcc/final.c | 1 +
gcc/fortran/ChangeLog | 52 +
gcc/fortran/dump-parse-tree.c | 6 +
gcc/fortran/frontend-passes.c | 1 +
gcc/fortran/gfortran.h | 3 +
gcc/fortran/openmp.c | 60 +-
gcc/fortran/primary.c | 55 +
gcc/fortran/resolve.c | 10 +-
gcc/fortran/trans-openmp.c | 16 +
gcc/fortran/trans-types.c | 3 +
gcc/fortran/types.def | 8 +-
gcc/function-abi.h | 2 +-
gcc/gcov.c | 43 +-
gcc/gimple-if-to-switch.cc | 11 +-
gcc/gimple-ssa-strength-reduction.c | 2 +-
gcc/gimplify.c | 14 +
gcc/go/ChangeLog | 4 +
gcc/go/Make-lang.in | 1 +
gcc/go/gofrontend/MERGE | 2 +-
gcc/go/gofrontend/embed.cc | 628 +++++
gcc/go/gofrontend/gogo.h | 4 +
gcc/graphite-scop-detection.c | 4 +-
gcc/internal-fn.def | 6 +
gcc/ipa-modref.c | 4 +-
gcc/ipa-pure-const.c | 8 +-
gcc/ipa-sra.c | 22 +-
gcc/jit/ChangeLog | 6 +
gcc/jit/docs/_build/texinfo/libgccjit.texi | 10 +-
gcc/jit/docs/cp/index.rst | 4 -
gcc/jit/docs/index.rst | 4 -
gcc/lra-eliminations.c | 28 +-
gcc/match.pd | 72 +-
gcc/omp-builtins.def | 2 +-
gcc/omp-expand.c | 19 +-
gcc/omp-low.c | 47 +
gcc/optabs.c | 8 +-
gcc/optabs.def | 6 +
gcc/optc-save-gen.awk | 6 +-
gcc/opts.c | 5 +-
gcc/passes.def | 8 +-
gcc/profile.c | 5 +
gcc/recog.h | 8 +-
gcc/rtl-ssa/accesses.h | 8 +-
gcc/rtl-ssa/functions.h | 2 +-
gcc/rtl-ssa/member-fns.inl | 2 +-
gcc/ssa-iterators.h | 39 +-
gcc/testsuite/ChangeLog | 553 +++++
gcc/testsuite/c-c++-common/gomp/task-detach-1.c | 37 +
gcc/testsuite/g++.dg/cpp0x/constexpr-52830.C | 1 +
gcc/testsuite/g++.dg/cpp0x/initlist-array13.C | 16 +
gcc/testsuite/g++.dg/cpp1z/elide4.C | 24 +
gcc/testsuite/g++.dg/cpp1z/elide5.C | 15 +
gcc/testsuite/g++.dg/cpp2a/concepts-ctad1.C | 16 +
gcc/testsuite/g++.dg/cpp2a/concepts-ctad2.C | 13 +
gcc/testsuite/g++.dg/debug/dwarf2/inline-ns-2.C | 1 +
gcc/testsuite/g++.dg/debug/dwarf2/inline-var-2.C | 1 +
gcc/testsuite/g++.dg/debug/dwarf2/inline-var-3.C | 1 +
gcc/testsuite/g++.dg/debug/dwarf2/lang-cpp11.C | 1 +
gcc/testsuite/g++.dg/debug/dwarf2/lang-cpp14.C | 1 +
gcc/testsuite/g++.dg/debug/dwarf2/lang-cpp17.C | 1 +
gcc/testsuite/g++.dg/debug/dwarf2/lang-cpp20.C | 1 +
gcc/testsuite/g++.dg/gcov/gcov-17.C | 40 +
gcc/testsuite/g++.dg/gcov/test-gcov-17.py | 37 +
gcc/testsuite/g++.dg/gomp/task-detach-1.C | 29 +
gcc/testsuite/g++.dg/lookup/using63.C | 17 +
gcc/testsuite/g++.dg/modules/dep-1_a.C | 4 +-
gcc/testsuite/g++.dg/modules/dep-1_b.C | 4 +-
gcc/testsuite/g++.dg/modules/dep-2.C | 6 +-
gcc/testsuite/g++.dg/modules/pr98591.H | 3 +
gcc/testsuite/g++.dg/opt/pr98550.C | 96 +
gcc/testsuite/g++.dg/template/pr98372.C | 28 +
gcc/testsuite/g++.dg/template/pr98538.C | 18 +
.../g++.dg/warn/Wmissing-field-initializers-2.C | 44 +
gcc/testsuite/g++.dg/warn/Wuninitialized-13.C | 28 +
gcc/testsuite/g++.target/aarch64/sve/cond_mla_1.C | 33 +
gcc/testsuite/g++.target/aarch64/sve/cond_mla_2.C | 33 +
gcc/testsuite/g++.target/aarch64/sve/cond_mla_3.C | 33 +
gcc/testsuite/g++.target/aarch64/sve/cond_mla_4.C | 36 +
gcc/testsuite/g++.target/aarch64/sve/cond_mla_5.C | 33 +
gcc/testsuite/g++.target/aarch64/sve/cond_mls_1.C | 33 +
gcc/testsuite/g++.target/aarch64/sve/cond_mls_2.C | 33 +
gcc/testsuite/g++.target/aarch64/sve/cond_mls_3.C | 33 +
gcc/testsuite/g++.target/aarch64/sve/cond_mls_4.C | 36 +
gcc/testsuite/g++.target/aarch64/sve/cond_mls_5.C | 33 +
gcc/testsuite/gcc.c-torture/compile/pr98629.c | 11 +
gcc/testsuite/gcc.c-torture/execute/pr95731.c | 40 +
gcc/testsuite/gcc.dg/analyzer/alloca-leak.c | 4 +-
gcc/testsuite/gcc.dg/analyzer/attr-malloc-1.c | 75 +
gcc/testsuite/gcc.dg/analyzer/attr-malloc-2.c | 24 +
gcc/testsuite/gcc.dg/analyzer/attr-malloc-4.c | 21 +
gcc/testsuite/gcc.dg/analyzer/attr-malloc-5.c | 12 +
gcc/testsuite/gcc.dg/analyzer/attr-malloc-6.c | 228 ++
.../analyzer/attr-malloc-CVE-2019-19078-usb-leak.c | 224 ++
.../gcc.dg/analyzer/attr-malloc-misuses.c | 18 +
gcc/testsuite/gcc.dg/analyzer/data-model-1.c | 5 +-
gcc/testsuite/gcc.dg/analyzer/malloc-1.c | 3 +-
gcc/testsuite/gcc.dg/analyzer/malloc-paths-8.c | 7 +-
gcc/testsuite/gcc.dg/analyzer/pr98628.c | 19 +
gcc/testsuite/gcc.dg/analyzer/sensitive-1.c | 5 +
gcc/testsuite/gcc.dg/analyzer/sigsetjmp-5.c | 2 +-
gcc/testsuite/gcc.dg/analyzer/sigsetjmp-6.c | 2 +-
gcc/testsuite/gcc.dg/debug/dwarf2/inline6.c | 3 +-
gcc/testsuite/gcc.dg/debug/dwarf2/lang-c11.c | 1 +
gcc/testsuite/gcc.dg/debug/dwarf2/pr41445-7.c | 1 +
gcc/testsuite/gcc.dg/debug/dwarf2/pr41445-8.c | 1 +
gcc/testsuite/gcc.dg/gomp/task-detach-1.c | 20 +
gcc/testsuite/gcc.dg/ipa/pr98222.c | 19 +
...w-locus-GCC_EXTRA_DIAGNOSTIC_OUTPUT-fixits-v1.c | 71 +
...w-locus-GCC_EXTRA_DIAGNOSTIC_OUTPUT-fixits-v2.c | 71 +
gcc/testsuite/gcc.dg/plugin/plugin.exp | 2 +
gcc/testsuite/gcc.dg/pr69047.c | 4 +-
gcc/testsuite/gcc.dg/torture/pr98640.c | 22 +
gcc/testsuite/gcc.dg/tree-ssa/pr95731.c | 22 +
gcc/testsuite/gcc.dg/tree-ssa/pr96669-1.c | 59 +
gcc/testsuite/gcc.dg/tree-ssa/pr96669-2.c | 30 +
gcc/testsuite/gcc.dg/tree-ssa/pr96671-1.c | 51 +
gcc/testsuite/gcc.dg/tree-ssa/pr96671-2.c | 51 +
gcc/testsuite/gcc.dg/tree-ssa/pr96681.c | 35 +
gcc/testsuite/gcc.dg/tree-ssa/pr96688.c | 24 +
gcc/testsuite/gcc.dg/tree-ssa/pr96691.c | 21 +
gcc/testsuite/gcc.dg/tree-ssa/pr98455.c | 19 +
gcc/testsuite/gcc.dg/tree-ssa/reassoc-37.c | 2 +-
gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-54.c | 6 +-
gcc/testsuite/gcc.dg/uninit-38.c | 80 +-
gcc/testsuite/gcc.dg/uninit-39.c | 47 +
gcc/testsuite/gcc.dg/uninit-40.c | 50 +
gcc/testsuite/gcc.dg/vect/bb-slp-32.c | 1 +
gcc/testsuite/gcc.dg/vect/bb-slp-9.c | 2 +-
gcc/testsuite/gcc.dg/vect/bb-slp-pr68892.c | 20 -
gcc/testsuite/gcc.dg/vect/bb-slp-pr98685.c | 15 +
.../gcc.dg/vect/complex/complex-mla-template.c | 101 +
.../gcc.dg/vect/complex/complex-mls-template.c | 101 +
.../gcc.dg/vect/complex/complex-mul-template.c | 71 +
.../complex/fast-math-bb-slp-complex-mla-double.c | 9 +
.../complex/fast-math-bb-slp-complex-mla-float.c | 8 +
.../fast-math-bb-slp-complex-mla-half-float.c | 9 +
.../complex/fast-math-bb-slp-complex-mls-double.c | 9 +
.../complex/fast-math-bb-slp-complex-mls-float.c | 8 +
.../fast-math-bb-slp-complex-mls-half-float.c | 9 +
.../complex/fast-math-bb-slp-complex-mul-double.c | 9 +
.../complex/fast-math-bb-slp-complex-mul-float.c | 8 +
.../fast-math-bb-slp-complex-mul-half-float.c | 9 +
.../vect/complex/fast-math-complex-mla-double.c | 8 +
.../vect/complex/fast-math-complex-mla-float.c | 8 +
.../complex/fast-math-complex-mla-half-float.c | 8 +
.../vect/complex/fast-math-complex-mls-double.c | 8 +
.../vect/complex/fast-math-complex-mls-float.c | 8 +
.../complex/fast-math-complex-mls-half-float.c | 8 +
.../vect/complex/fast-math-complex-mul-double.c | 8 +
.../vect/complex/fast-math-complex-mul-float.c | 8 +
.../complex/fast-math-complex-mul-half-float.c | 8 +
gcc/testsuite/gcc.dg/vect/pr98674.c | 16 +
gcc/testsuite/gcc.dg/vect/slp-11b.c | 12 +-
gcc/testsuite/gcc.dg/vect/slp-43.c | 4 +-
gcc/testsuite/gcc.dg/vect/slp-45.c | 2 +-
gcc/testsuite/gcc.dg/vect/slp-reduc-3.c | 3 +-
.../aarch64/advsimd-intrinsics/p64_p128.c | 46 +-
.../gcc.target/aarch64/narrow_high-intrinsics.c | 6 +-
.../gcc.target/aarch64/sve/acle/general/ldff1_8.c | 32 +
.../gcc.target/aarch64/sve/cost_model_11.c | 12 +
.../gcc.target/aarch64/sve/mask_struct_load_5.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/mla_2.c | 34 +
gcc/testsuite/gcc.target/aarch64/sve/mls_2.c | 34 +
gcc/testsuite/gcc.target/aarch64/sve/ptest_1.c | 10 +
gcc/testsuite/gcc.target/aarch64/sve/sel_1.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/sel_2.c | 2 +-
gcc/testsuite/gcc.target/aarch64/sve/sel_3.c | 2 +-
gcc/testsuite/gcc.target/arm/pr97969.c | 54 +
gcc/testsuite/gcc.target/arm/simd/mve-vneg.c | 3 +
gcc/testsuite/gcc.target/arm/simd/mve-vshl.c | 62 +
gcc/testsuite/gcc.target/arm/simd/mve-vshr.c | 59 +
gcc/testsuite/gcc.target/arm/simd/vceqz_p64.c | 18 +
gcc/testsuite/gcc.target/arm/simd/vceqzq_p64.c | 18 +
gcc/testsuite/gcc.target/gcn/fpdiv.c | 38 +
gcc/testsuite/gcc.target/i386/pr66821.c | 2 +-
gcc/testsuite/gcc.target/i386/pr92645-6.c | 34 +
gcc/testsuite/gcc.target/i386/pr92645-7.c | 24 +
gcc/testsuite/gcc.target/i386/pr95021-1.c | 2 +-
gcc/testsuite/gcc.target/i386/pr95021-3.c | 2 +-
gcc/testsuite/gcc.target/i386/pr95905-1.c | 26 +
gcc/testsuite/gcc.target/i386/pr95905-2.c | 82 +
gcc/testsuite/gcc.target/i386/pr95905-3.c | 82 +
gcc/testsuite/gcc.target/i386/pr95905-4.c | 82 +
gcc/testsuite/gcc.target/i386/pr96271.c | 11 +
gcc/testsuite/gcc.target/i386/pr96938.c | 66 +
gcc/testsuite/gcc.target/i386/pr98667-1.c | 9 +
gcc/testsuite/gcc.target/i386/pr98667-2.c | 9 +
gcc/testsuite/gcc.target/i386/pr98667-3.c | 7 +
gcc/testsuite/gcc.target/i386/pr98670.c | 16 +
.../gcc.target/powerpc/builtins-1-p10-runnable.c | 398 ++++
.../gcc.target/powerpc/fold-vec-extract-char.p7.c | 2 +-
.../powerpc/fold-vec-extract-double.p7.c | 3 +-
.../gcc.target/powerpc/fold-vec-extract-float.p7.c | 3 +-
.../gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +-
.../gcc.target/powerpc/fold-vec-extract-int.p7.c | 3 +-
.../gcc.target/powerpc/fold-vec-extract-int.p8.c | 2 +-
.../gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +-
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gcc/testsuite/gcc.target/powerpc/sse-andnps-1.c | 2 +-
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gcc/testsuite/gcc.target/powerpc/sse-movlps-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/sse2-andnpd-1.c | 2 +-
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gcc/testsuite/gcc.target/s390/s390.exp | 4 +
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gcc/tree-core.h | 29 +-
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gcc/tree-pretty-print.c | 6 +
gcc/tree-ssa-ccp.c | 2 +-
gcc/tree-ssa-dce.c | 17 +-
gcc/tree-ssa-dse.c | 8 +-
gcc/tree-ssa-loop-ivopts.c | 2 +-
gcc/tree-ssa-math-opts.c | 37 +-
gcc/tree-ssa-phiprop.c | 2 +-
gcc/tree-ssa-reassoc.c | 62 +-
gcc/tree-ssa-sccvn.c | 15 +-
gcc/tree-ssa.c | 2 +-
gcc/tree-vect-slp-patterns.c | 823 ++++++-
gcc/tree-vect-slp.c | 240 +-
gcc/tree-vect-stmts.c | 47 +-
gcc/tree.c | 15 +-
include/ChangeLog | 4 +
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libcody/Makesub.in | 49 -
libcody/build-aux/config.guess | 1476 ------------
libcody/build-aux/config.sub | 1833 ---------------
libcody/build-aux/install-sh | 518 ----
libcody/config.h.in | 5 +-
libcody/config.m4 | 182 --
libcody/configure | 209 +-
libcody/configure.ac | 15 +-
libcody/dox.cfg.in | 2478 --------------------
libcody/fatal.cc | 22 -
libcody/gdbinit.in | 11 -
libcody/internal.hh | 3 -
libcpp/ChangeLog | 5 +
libcpp/mkdeps.c | 1 -
libgcc/ChangeLog | 17 +
libgcc/config/i386/gnu-unwind.h | 60 +-
libgcc/config/or1k/sfp-machine.h | 41 +-
libgfortran/ChangeLog | 6 +
libgfortran/runtime/ISO_Fortran_binding.c | 3 +-
libgo/Makefile.am | 2 +-
libgo/Makefile.in | 2 +-
libgo/go/crypto/x509/root_hurd.go | 6 +
libgo/go/runtime/export_pipe2_test.go | 2 +-
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libgo/go/runtime/os_hurd.go | 18 +-
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libgo/misc/cgo/test/cthread_unix.c | 2 +-
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libgomp/config/accel/sem.h | 9 +
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libgomp/config/posix/sem.c | 20 +
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libgomp/configure | 86 +-
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libitm/ChangeLog | 7 +
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libstdc++-v3/doc/doxygen/user.cfg.in | 1 -
libstdc++-v3/include/bits/fs_path.h | 61 +-
libstdc++-v3/include/bits/hashtable_policy.h | 8 +-
libstdc++-v3/include/debug/macros.h | 5 +
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libstdc++-v3/include/debug/safe_iterator.tcc | 5 +-
libstdc++-v3/include/debug/safe_local_iterator.h | 4 +-
libstdc++-v3/include/std/barrier | 4 +-
libstdc++-v3/include/std/version | 4 +-
libstdc++-v3/src/c++11/Makefile.am | 4 +-
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libstdc++-v3/src/c++11/debug.cc | 5 +-
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libstdc++-v3/testsuite/30_threads/barrier/1.cc | 2 +-
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copy libstdc++-v3/testsuite/{30_threads/barrier/1.cc => 23_containers/unordered_ma [...]
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[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-Os updated (b4b6ea4680 -> 705989f19a)
by gitīŧ git.linaro.org
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-Os
in repository toolchain/ci/binutils-gdb.
from b4b6ea4680 libctf, ld: fix formatting of forwards to unions and enums
adds 70d3120f32 libctf, testsuite: don't run without a suitable compiler
adds 0814dbfbfc libctf, testsuite: adjust for real return type of ctf_member_count
adds 85dd67bd6d Automatic date update in version.in
adds 0c7f5bd08c sim: h8300: simplify testsuite runner
adds a2f8e947a8 sim: h8300: fix test mach markers
adds c004e77f7d sim: testsuite: delete unused Make-common.in file
adds 865288236d sim: fr30: delete unused testsuite
adds fbc09e7af7 RISC-V: Implement support for big endian targets.
adds f36ce378b4 RISC-V: Fix riscv gas/ld testsuites failures for big endian.
adds 286d2f2cd7 RISC-V: Mention -mbig-endian and -mlittle-endian in doc
adds 22206e847d gas APP macro tests
adds 73624512cf ld rgn-at10 and rgn-at11 test
adds 3677b72961 sparc-sun-solaris2 and sparc64-sun-solaris2 config
adds 85f55c2b75 sparc-elf ld test fails
adds 599c86c4a5 score-elf binutils-all/strip-13 fail
adds 4b186f88b8 gdbsupport: common-utils.h: fix typo in header
adds 3c55062cc1 gdb/testsuite: fix race in gdb.threads/signal-while-stepping [...]
adds b49180acf2 Fix fixed-point binary operation type handling
adds 1606216201 config.sub update broke powerpc-eabivle
adds 4018f4e0fc ld pr22471 test fails
adds f526791a6f Regen ld/po/BLD-POTFILES.in
adds e2ede46cb2 Automatic date update in version.in
adds 6987d5a1bb binutils/readelf.c: Correct grammar in comment
adds d4e57b87a3 bfin: Check bfd_link_hash_indirect
adds 2652cfad8d RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instructio [...]
adds 1861f7cfbf sim: cris: fix C tests with newer toolchains
adds 9446bcf6be fix paths in ChangeLog
adds 4d4490b8d7 ld: xfail riscv64*-*-* for ld-scripts/empty-address-2 tests.
adds aa881ecde4 RISC-V: Add pause hint instruction.
adds 78e4948694 [gdb/build] Fix gdbserver build with -fsanitize=address
adds 17d60030ae Fix another path length problem opening files on Win32 systems.
adds d4813f1046 Fix regression in Ada aggregate assignment
adds 8e604ff077 xfail more cases of complaints about relocs in read-only sections
adds dc20061339 sh-pe ld XPASSes
adds 959d6a673e Fix regression in Ada do_full_match
adds 3b288c8e2e m68k: Require m68020up rather than m68000up for CHK.L instruction.
adds d1bcae833b ELF: Don't generate unused section symbols
adds 1b0927db3c Updated French translation for the opcodes/ subdirectory.
adds f478212851 libtool.m4: update GNU/Hurd test from upstream. In upstream [...]
adds e904f56d02 gdb/sim: add support for exporting memory map
adds bfc7d04afb sim: h8300: delete opcode caching
adds a39487c668 sim: cris: use -sim with C tests for cris-elf targets
adds e6c1dbbfe8 sim: cris: disable test that crashes the linker
adds 0f8e278da2 sim: ChangeLog: move arch-specific entries into the arch dir
adds 9a50f40e82 Automatic date update in version.in
adds f4cfa91741 sim: ppc: stub out sim_memory_map
adds e343681375 gdb/fortran: Correct the lval type for array elements of int [...]
adds 1940319c0e [gdb] Fix internal-error in process_event_stop_test
adds fb932b57cb Treat the AArch64 register id_aa64mmfr2_el1 as a core system [...]
adds e84c871648 Fix places in the AArch64 opcodes library code where a call [...]
adds 3c8c6de21d gdb: user variables with components of dynamic type
adds ed20522215 Updated Swedish translation for the opcodes/ subdirectory
adds d00f086803 gdb: add missing test for completion of invalid /FMT strings
adds 6abd4cf281 gdb: check for empty strings in get_standard_cache_dir/get_s [...]
adds 8fc48b7961 Pass void_context_p to parse_expression
adds 46f900c065 sim: require a C11 compiler
adds a7e906e8f5 Automatic date update in version.in
adds 6430704567 configure regen
adds aae7fcb8d7 POWER10: Add Return-Oriented Programming instructions
adds b1b29aa51a elf: Verify section size for mixed ordered/unordered inputs
adds ba9e922fa0 ld/x86-64: Also set LAM_U57 when setting LAM_U48
adds ce0be4070f sim: common: add missing stdlib.h for abort()
adds 055bc77a80 Add Changelog entries and NEWS entries for 2.36 branch
adds 573fe3fbc1 Change version number to 2.36.50 and regenerate files
adds be2c78856d Update release howto with 2.37 numbers
adds b5a4a01af4 sim: hw: rework code to avoid gcc warnings
adds f41464416a sim: pru: fix include ordering with sim-main.h
adds 0a94990bf6 ld/x86-64: Properly Handle -z lam-u48/lam-u57
adds bf470982f9 sim: enable -Werror by default for some arches
adds 50df264dae sim: clean up stale AC_PREREQ refs
adds f8cab0b995 sim: sh64: delete port
adds f074c07d8d sim: common: clean up asprintf includes a bit
adds 7eb99e5e27 sim: cr16/d10v: move storage out of header
adds a9fd212a24 sim: replace rindex with strrchr
adds 50ad1254d5 GCC: Pass --plugin to AR and RANLIB
adds a4966cd965 Binutils: Pass --plugin to AR and RANLIB
adds af019bfde9 Support the PGO build for binutils+gdb
adds 66beed0227 Fix erroneous agent expression test
adds bc167b6b3e Remove a use of print_expression
adds 54585eee2e Avoid crash in compile_to_object
adds 5834526f4b Automatic date update in version.in
adds 46b1518d4c Automatic date update in version.in
adds a8aa72b913 Updated translations for multiple subdirectories
adds 68ed285428 sim: clean up C11 header includes
adds 933306703a sim: rl78: move storage out of header
adds 90e123dd60 sim: common: fix printf formats
adds a0c38f0d70 sim: or1k: fix include ordering with sim-main.h
adds 5c1008a41f sim: call SIM_AC_OPTION_WARNINGS(no) in remaining ports
adds 9c70334dee sim: always call SIM_AC_OPTION_WARNINGS
adds c0f6e439cc Add support for more MIPS variants to the linker command line.
adds 82c70b08df aarch64: Remove support for CSRE
adds 10dadadc5b [gdb/testsuite] Fix gdb.arch/amd64-stap-three-arg-disp.S
adds 062eaacbac gdb: change jit_debug to a bool
adds eef401dce1 gdb: convert solib-aix to new-style debug macros
adds c6185dce03 gdb: convert aarch64 to new-style debug macros
adds 254c3783fe sim: tests: get common tests working again
adds eabdd87b2e Automatic date update in version.in
adds 03c02f3116 GCC: Check if AR works with --plugin and rc
adds 83b33c6cb9 Binutils: Check if AR works with --plugin and rc
adds 44124a4683 binuitils: Check if AR is usable for LTO build
adds f631b79abe sim: or1k: delete redundant SIM_AC_OPTION_INLINE call
adds f220ef633c sim: common: use #error properly
adds 68895f7d7e sim: README-HACKING: clean up stale run references
adds 5e9e2f41eb sim: or1k: clean up stale build entries
adds e998918e98 sim: or1k: fix mixing of code & decl warning
adds 7c654b719d gdb/fortran: add symbol base comparison operators
adds ce38f5edf1 gdb: fix debug dump of OP_BOOL expressions
adds 6d104cac0a Updated translations for some subdirectories
adds c2e9a4a3ed elf/x86-64: Adjust R_AMD64_DIR64/R_AMD64_DIR32 for PE/x86-64 inputs
adds 18bfb5057f [gdb/testsuite] Require is_amd64_regs_target in gdb.base/dis [...]
adds d546b61084 Implement a workaround for GNU mak jobserver
adds 5291fe3cd1 aarch64: Add support for bfloat16 in gdb.
adds b2f2ae0d6f gdb: remove pre_init_ui_hook from top.c
adds 3f94e58859 [gdb/testsuite] Add have_mpx in lib/gdb.exp
adds 16e9019ef7 gdb: move baud_rate and serial_parity declarations to serial.h
adds fe7a351a8e gdb: move read{now,never}_symbol_files declarations to symfile.h
adds 24a7f1b548 gdb: fix indentation in infrun.c
adds 3034143dc6 src-release: fix indentation
adds 4180301e81 Automatic date update in version.in
adds 62fe7512a7 sim: watch: fix pc watchpoints on little endian host systems
adds c54f3efdc2 sim: watch: fix range expression processing
adds 2ce40d1a51 Add SEH support to code generated by dlltool.
adds 8c4645b488 Remove sflag_info param from wild callback functions
adds b209b5a6b8 SHF_LINK_ORDER fixup_link_order in ld
adds 5347ed60c5 Regen Makefile.in for jobserver.m4 aclocal.m4 dependency
adds 844bf810cf x86: Don't generate GOT_symbol for PLT relocations
adds b634d11d61 ld: Check for ELF input before accessing ELF section data
adds 54ca900277 gdb: convert jit to new-style debug macros
adds 5e12f48ffb gdb: bool-ify file_is_auto_load_safe
adds db972fce46 gdb: bool-ify ext_lang_auto_load_enabled and friends
adds 5bf7e91b2b gdb: bool-ify users of file_is_auto_load_safe
adds 506195754c gdb: bool-ify maybe_add_script_{text,file}
adds fb0f5031bb gdb: turn arc_debug into a bool
adds d8d1feb424 gdb: convert arc to new-style debug macros
adds 4120e4885b Re: SHF_LINK_ORDER fixup_link_order in ld
adds 3eeabe12c3 Automatic date update in version.in
adds c9d220893e gdb: make the remote target track its own thread resume state
adds bd497355ea gdb: remove target_ops::commit_resume implementation in reco [...]
adds 8f66807b98 gdb: better handling of 'S' packets
adds d9b1deff13 sim: watch: add basic default handler that traps
adds 54780889e9 sim: h8300: drop separate eightbit memory buffer
adds adb0bd8fda gas: bfin: fix build time warnings
adds abad28152e gas: bfin: build lexer with -Werror
adds 271bea6acd ld: tests: add -msim when testing bfin targets
adds 7e0d77ef5f Fix an illegal memory access parsing a win32pstatus note wit [...]
adds 116d0cf103 [gdb/testsuite] Fix gdb.base/style.exp with -m32
adds 5fae2a2c66 [gdb/breakpoint] Handle .plt.sec in in_plt_section
adds 5a10699ff3 Updated translations for some subdirectories
adds 8ca9c7eb67 bfin: Skip non SEC_ALLOC section for R_BFIN_FUNCDESC
adds 58eadc4b69 Fix building gdb with gcc-4.x
adds c14dee84dd Update my email address (long overdue!)
adds 17e8913732 Add myself to gdb/MAINTAINERS
adds 5aa06b1b14 Automatic date update in version.in
adds 5fda40b28f gas: make [248]byte directives available everywhere
adds 3624a6c15c PR26539, memory leak in inflate.c
adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status
adds 7cf91a2481 sim: m32r: clean up redundant test coverage
adds 89bfc2a429 sim: frv: clean up redundant test coverage
adds 137d6efd8a sim: mips: delete empty stub test dir
adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness
adds bb3eddb5bd sim: testsuite: delete configure script
adds dcd709e056 RISC-V: Comments tidy and improvement.
adds b800637e76 RISC-V: Error and warning messages tidy.
adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...]
adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...]
adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32
adds 5a11fff005 gdb/tui: compare pointer to nullptr, not 0
adds e403a898b5 Automatic date update in version.in
adds 1368b914e9 sim: testsuite: flatten tree
adds eb6e6af8c1 PR26002 undefined symbol VER_NDX_GLOBAL vs. VER_NDX_LOCAL
adds ad92f33d38 Tidy inflateEnd calls
adds 68b007788a ld/x86: Add -z report-relative-reloc
adds 75a933f399 ld/elf/x86: Don't compare IFUNC address in the shared object
adds 514fca98df Automatic date update in version.in
adds edf0f284b1 PR binutils/23460: Increase the max number of open files to 20
adds d46153313b Automatic date update in version.in
adds 25294ff049 gold: Remove the circular IFUNC dependency in ifuncmain6pie
adds 994b251328 ld/elf: Ignore section symbols when matching linkonce with comdat
adds 44365e88c0 PR27198, segv in S_IS_WEAK
adds cecb191290 gdb: const-ify unpack_* functions in remote.c
adds e3b2741b16 gdb: const-ify remote_target::add_current_inferior_and_threa [...]
adds b5c8f22d28 gdb: move remote_target::start_remote variable to narrower scope
adds aa2838ccc5 gdb: const-ify hostio methods parameter in remote.c
adds d3d7d1ba3b [gdb/tdep] Handle si_addr_bnd in compat_siginfo_from_siginfo
adds 326adec374 PR26378, sections initialised only by linker scripts are alw [...]
adds 6a9ad81c44 gdb/riscv: use a single regset supply function for riscv fbs [...]
adds 705989f19a as: Automatically enable DWARF5 support
No new revisions were added by this update.
Summary of changes:
ChangeLog | 62 +
Makefile.in | 68 +-
Makefile.tpl | 63 +-
bfd/ChangeLog | 286 +
bfd/Makefile.in | 1 +
bfd/aclocal.m4 | 1 +
bfd/aix386-core.c | 1 +
bfd/aout-target.h | 1 +
bfd/bfd-in2.h | 24 +-
bfd/bfdio.c | 23 +-
bfd/binary.c | 1 +
bfd/cisco-core.c | 2 +
bfd/coff-alpha.c | 1 +
bfd/coff-i386.c | 4 +-
bfd/coff-ia64.c | 1 +
bfd/coff-mips.c | 3 +
bfd/coff-rs6000.c | 2 +
bfd/coff-sh.c | 2 +
bfd/coff-tic30.c | 1 +
bfd/coff-tic54x.c | 26 +
bfd/coff-x86_64.c | 2 +
bfd/coff64-rs6000.c | 2 +
bfd/coffcode.h | 3 +
bfd/compress.c | 3 +-
bfd/config.bfd | 17 +-
bfd/configure | 87 +-
bfd/configure.ac | 4 +
bfd/doc/Makefile.in | 1 +
bfd/elf-linker-x86.h | 3 +
bfd/elf.c | 20 +-
bfd/elf32-bfin.c | 245 +-
bfd/elf32-i386.c | 36 +
bfd/elf32-score.c | 10 +-
bfd/elf32-score7.c | 10 +-
bfd/elf64-x86-64.c | 33 +
bfd/elfcode.h | 8 +-
bfd/elflink.c | 255 +-
bfd/elfnn-riscv.c | 416 +-
bfd/elfxx-riscv.c | 56 +-
bfd/elfxx-riscv.h | 4 +-
bfd/elfxx-target.h | 6 +
bfd/elfxx-x86.c | 72 +-
bfd/elfxx-x86.h | 7 +
bfd/hppabsd-core.c | 1 +
bfd/hpux-core.c | 1 +
bfd/i386msdos.c | 1 +
bfd/ihex.c | 1 +
bfd/irix-core.c | 1 +
bfd/mach-o-target.c | 1 +
bfd/mmo.c | 1 +
bfd/netbsd-core.c | 1 +
bfd/osf-core.c | 1 +
bfd/pdp11.c | 1 +
bfd/pef.c | 2 +
bfd/plugin.c | 1 +
bfd/po/bfd.pot | 2574 +--
bfd/po/fr.po | 2666 +--
bfd/po/pt.po | 2681 ++--
bfd/po/sr.po | 2687 ++--
bfd/po/uk.po | 2666 +--
bfd/ppcboot.c | 1 +
bfd/ptrace-core.c | 1 +
bfd/reloc.c | 7 +
bfd/sco5-core.c | 1 +
bfd/section.c | 7 +-
bfd/som.c | 1 +
bfd/srec.c | 2 +
bfd/syms.c | 3 +
bfd/targets.c | 18 +
bfd/tekhex.c | 1 +
bfd/trad-core.c | 1 +
bfd/verilog.c | 1 +
bfd/version.h | 2 +-
bfd/version.m4 | 2 +-
bfd/vms-alpha.c | 1 +
bfd/vms-lib.c | 1 +
bfd/wasm-module.c | 1 +
bfd/xsym.c | 1 +
binutils/BRANCHES | 1 +
binutils/ChangeLog | 97 +
binutils/MAINTAINERS | 6 +-
binutils/Makefile.in | 1 +
binutils/NEWS | 2 +
binutils/README-how-to-make-a-release | 40 +-
binutils/aclocal.m4 | 1 +
binutils/configure | 85 +-
binutils/configure.ac | 2 +
binutils/dlltool.c | 50 +-
binutils/doc/Makefile.in | 1 +
binutils/objcopy.c | 24 +
binutils/po/binutils.pot | 3317 ++--
binutils/po/fr.po | 3826 +++--
binutils/po/pt.po | 3943 ++---
binutils/po/sr.po | 3845 +++--
binutils/po/sv.po | 3804 +++--
binutils/po/uk.po | 3840 +++--
binutils/readelf.c | 10 +-
binutils/testsuite/binutils-all/readelf.exp | 6 +-
binutils/testsuite/binutils-all/readelf.s-64 | 2 +-
.../{readelf.s-64 => readelf.s-64-unused} | 0
binutils/testsuite/binutils-all/readelf.ss | 5 +-
binutils/testsuite/binutils-all/readelf.ss-64 | 5 +-
.../{readelf.ss-64 => readelf.ss-64-unused} | 0
.../binutils-all/{readelf.ss => readelf.ss-unused} | 0
binutils/testsuite/lib/binutils-common.exp | 31 +
config.sub | 4 +-
config/ChangeLog | 19 +
config/gcc-plugin.m4 | 40 +
config/jobserver.m4 | 24 +
configure | 246 +-
configure.ac | 84 +
cpu/ChangeLog | 4 +
elfcpp/ChangeLog | 4 +
gas/ChangeLog | 243 +
gas/Makefile.am | 4 +-
gas/Makefile.in | 5 +-
gas/NEWS | 10 +-
gas/aclocal.m4 | 1 +
gas/config/bfin-lex.l | 5 +-
gas/config/obj-elf.c | 7 +-
gas/config/tc-aarch64.c | 31 -
gas/config/tc-i386.c | 42 +-
gas/config/tc-riscv.c | 569 +-
gas/config/tc-riscv.h | 8 +-
gas/configure | 85 +-
gas/configure.ac | 2 +
gas/configure.tgt | 4 +-
gas/doc/Makefile.in | 1 +
gas/doc/as.texi | 8 +-
gas/doc/c-aarch64.texi | 2 -
gas/doc/c-riscv.texi | 8 +
gas/dwarf2dbg.c | 24 +-
gas/po/fr.po | 7239 ++++-----
gas/po/gas.pot | 2131 +--
gas/po/uk.po | 7237 ++++-----
gas/read.c | 6 +
gas/subsegs.c | 4 +
gas/testsuite/gas/aarch64/csre-invalid.d | 3 -
gas/testsuite/gas/aarch64/csre-invalid.s | 6 -
gas/testsuite/gas/aarch64/csre.d | 29 -
gas/testsuite/gas/aarch64/csre_csr-invalid.d | 3 -
gas/testsuite/gas/aarch64/csre_csr-invalid.l | 2 -
gas/testsuite/gas/aarch64/csre_csr-invalid.s | 4 -
gas/testsuite/gas/aarch64/csre_csr.d | 10 -
gas/testsuite/gas/aarch64/csre_csr.s | 4 -
gas/testsuite/gas/cfi/cfi-label.d | 4 +-
gas/testsuite/gas/elf/dwarf-5-file0.d | 2 +-
gas/testsuite/gas/elf/elf.exp | 6 +-
gas/testsuite/gas/elf/section2.e | 7 -
.../gas/elf/{section2.e => section2.e-unused} | 0
gas/testsuite/gas/elf/symver.d | 4 -
gas/testsuite/gas/i386/i386.exp | 5 +
gas/testsuite/gas/i386/ilp32/elf/symver.d | 4 -
gas/testsuite/gas/i386/ilp32/x86-64-size-1.d | 24 +-
gas/testsuite/gas/i386/ilp32/x86-64-size-3.d | 16 +-
gas/testsuite/gas/i386/ilp32/x86-64-size-5.d | 12 +-
gas/testsuite/gas/i386/ilp32/x86-64-unwind.d | 6 +-
gas/testsuite/gas/i386/no-got.d | 17 +
gas/testsuite/gas/i386/no-got.s | 5 +
gas/testsuite/gas/i386/pr27198.d | 2 +
gas/testsuite/gas/i386/pr27198.err | 5 +
gas/testsuite/gas/i386/pr27198.s | 1 +
gas/testsuite/gas/i386/size-1.d | 24 +-
gas/testsuite/gas/i386/size-3.d | 16 +-
gas/testsuite/gas/i386/svr4.d | 3 -
gas/testsuite/gas/i386/x86-64-no-got.d | 17 +
gas/testsuite/gas/i386/x86-64-no-got.s | 5 +
gas/testsuite/gas/i386/x86-64-size-1.d | 24 +-
gas/testsuite/gas/i386/x86-64-size-3.d | 16 +-
gas/testsuite/gas/i386/x86-64-size-5.d | 12 +-
gas/testsuite/gas/i386/x86-64-unwind.d | 10 +-
gas/testsuite/gas/lns/lns-diag-1.l | 2 -
gas/testsuite/gas/macros/app1.d | 1 +
gas/testsuite/gas/macros/app2.d | 1 +
gas/testsuite/gas/macros/app3.d | 1 +
gas/testsuite/gas/macros/app4.d | 1 +
gas/testsuite/gas/ppc/ppc.exp | 2 +
gas/testsuite/gas/ppc/rop-checks.d | 3 +
gas/testsuite/gas/ppc/rop-checks.l | 17 +
gas/testsuite/gas/ppc/rop-checks.s | 18 +
gas/testsuite/gas/ppc/rop.d | 27 +
gas/testsuite/gas/ppc/rop.s | 21 +
gas/testsuite/gas/riscv/bitmanip-insns-32.d | 37 +
gas/testsuite/gas/riscv/bitmanip-insns-64.d | 55 +
gas/testsuite/gas/riscv/bitmanip-insns.s | 58 +
gas/testsuite/gas/riscv/li32.d | 2 +-
gas/testsuite/gas/riscv/li64.d | 2 +-
gas/testsuite/gas/riscv/lla32.d | 2 +-
gas/testsuite/gas/riscv/lla64.d | 2 +-
gas/testsuite/gas/riscv/march-ok-g2.d | 2 +-
gas/testsuite/gas/riscv/march-ok-g2_p1.d | 2 +-
gas/testsuite/gas/riscv/march-ok-g2p0.d | 2 +-
gas/testsuite/gas/riscv/march-ok-i2p0.d | 2 +-
gas/testsuite/gas/riscv/march-ok-i2p0m2_a2f2.d | 2 +-
.../gas/riscv/march-ok-nse-with-version.d | 2 +-
gas/testsuite/gas/riscv/march-ok-two-nse.d | 2 +-
gas/testsuite/gas/riscv/pause.d | 10 +
gas/testsuite/gas/riscv/pause.s | 2 +
gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +-
.../gas/riscv/priv-reg-fail-read-only-01.l | 136 +-
.../gas/riscv/priv-reg-fail-read-only-02.l | 48 +-
gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +-
.../gas/riscv/priv-reg-fail-version-1p10.l | 48 +-
.../gas/riscv/priv-reg-fail-version-1p11.l | 46 +-
.../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +-
gas/testsuite/gas/sparc/sparc.exp | 34 +-
gas/write.c | 43 +-
gdb/ChangeLog | 284 +
gdb/MAINTAINERS | 1 +
gdb/aarch64-tdep.c | 94 +-
gdb/ada-lang.c | 70 +-
gdb/arc-linux-nat.c | 16 +-
gdb/arc-linux-tdep.c | 43 +-
gdb/arc-newlib-tdep.c | 11 +-
gdb/arc-tdep.c | 151 +-
gdb/arc-tdep.h | 7 +-
gdb/arch/aarch64-insn.c | 9 +-
gdb/arch/aarch64-insn.h | 5 +
gdb/auto-load.c | 82 +-
gdb/auto-load.h | 16 +-
gdb/breakpoint.c | 164 +-
gdb/compile/compile.c | 4 +-
gdb/expprint.c | 9 +-
gdb/expression.h | 3 +-
gdb/extension-priv.h | 2 +-
gdb/extension.c | 7 +-
gdb/extension.h | 5 +-
gdb/f-exp.y | 36 +-
gdb/f-lang.c | 6 +-
gdb/features/aarch64-fpu.c | 5 +
gdb/features/aarch64-fpu.xml | 2 +
gdb/guile/guile-internal.h | 5 +-
gdb/guile/scm-auto-load.c | 5 +-
gdb/infrun.c | 2 +-
gdb/jit.c | 80 +-
gdb/main.c | 1 +
gdb/nat/amd64-linux-siginfo.c | 13 +
gdb/objfiles.h | 3 +-
gdb/parse.c | 15 +-
gdb/printcmd.c | 10 +-
gdb/python/py-auto-load.c | 5 +-
gdb/python/python-internal.h | 5 +-
gdb/record-btrace.c | 11 -
gdb/record-full.c | 10 -
gdb/remote-sim.c | 18 +
gdb/remote.c | 412 +-
gdb/riscv-fbsd-tdep.c | 20 +-
gdb/riscv-linux-tdep.c | 4 +-
gdb/riscv-tdep.c | 50 +
gdb/riscv-tdep.h | 23 +
gdb/serial.c | 7 +-
gdb/serial.h | 8 +
gdb/solib-aix.c | 23 +-
gdb/symfile.c | 10 +-
gdb/symfile.h | 8 +
gdb/target.h | 6 -
gdb/testsuite/ChangeLog | 106 +
gdb/testsuite/gdb.ada/assign_arr.exp | 3 +
gdb/testsuite/gdb.ada/fixed_points.exp | 17 +
.../gdb.ada/fixed_points/fixed_points.adb | 1 +
gdb/testsuite/gdb.ada/fixed_points/pck.ads | 5 +
gdb/testsuite/gdb.ada/voidctx.exp | 40 +
gdb/testsuite/gdb.ada/voidctx/pck.adb | 27 +
gdb/testsuite/gdb.ada/voidctx/pck.ads | 23 +
gdb/testsuite/gdb.ada/voidctx/voidctx.adb | 31 +
gdb/testsuite/gdb.arch/aarch64-fp.exp | 25 +
gdb/testsuite/gdb.arch/amd64-stap-three-arg-disp.S | 5 +-
gdb/testsuite/gdb.arch/i386-mpx-call.c | 78 +-
gdb/testsuite/gdb.arch/i386-mpx-call.exp | 17 +-
gdb/testsuite/gdb.arch/i386-mpx-map.c | 45 +-
gdb/testsuite/gdb.arch/i386-mpx-map.exp | 23 +-
gdb/testsuite/gdb.arch/i386-mpx-sigsegv.c | 80 +-
gdb/testsuite/gdb.arch/i386-mpx-sigsegv.exp | 15 +-
gdb/testsuite/gdb.arch/i386-mpx-simple_segv.c | 40 +-
gdb/testsuite/gdb.arch/i386-mpx-simple_segv.exp | 15 +-
gdb/testsuite/gdb.arch/i386-mpx.c | 98 +-
gdb/testsuite/gdb.arch/i386-mpx.exp | 22 +-
gdb/testsuite/gdb.base/completion.exp | 5 +
gdb/testsuite/gdb.base/disasm-optim.exp | 2 +-
gdb/testsuite/gdb.base/empty-host-env-vars.exp | 72 +
gdb/testsuite/gdb.base/style.exp | 49 +-
gdb/testsuite/gdb.fortran/array-slices.exp | 2 +-
gdb/testsuite/gdb.fortran/debug-expr.exp | 8 +
gdb/testsuite/gdb.fortran/dot-ops.exp | 30 +
gdb/testsuite/gdb.fortran/intvar-array.exp | 59 +
gdb/testsuite/gdb.fortran/intvar-array.f90 | 28 +
gdb/testsuite/gdb.fortran/intvar-dynamic-types.exp | 97 +
gdb/testsuite/gdb.fortran/intvar-dynamic-types.f90 | 32 +
.../gdb.server/stop-reply-no-thread-multi.c | 77 +
.../gdb.server/stop-reply-no-thread-multi.exp | 136 +
.../signal-while-stepping-over-bp-other-thread.exp | 2 +-
gdb/testsuite/gdb.trace/ax.exp | 2 +-
gdb/testsuite/lib/gdb.exp | 75 +-
gdb/top.c | 5 -
gdb/top.h | 4 -
gdb/tracepoint.c | 17 +-
gdb/tracepoint.h | 2 +-
gdb/trad-frame.c | 5 +-
gdb/tui/tui.c | 4 +-
gdb/valarith.c | 46 +-
gdb/valops.c | 63 +-
gdb/value.c | 37 +-
gdb/value.h | 5 +
gdbserver/ChangeLog | 7 +
gdbserver/Makefile.in | 13 +-
gdbsupport/ChangeLog | 10 +
gdbsupport/common-utils.h | 2 +-
gdbsupport/pathstuff.cc | 14 +-
gold/ChangeLog | 19 +
gold/po/fr.po | 730 +-
gold/po/sr.po | 729 +-
gold/po/uk.po | 730 +-
gold/testsuite/ifuncmain6pie.c | 14 +-
gold/testsuite/ifuncmod6.c | 10 +-
gprof/ChangeLog | 37 +
gprof/Makefile.in | 1 +
gprof/aclocal.m4 | 1 +
gprof/configure | 85 +-
gprof/configure.ac | 2 +
gprof/po/gprof.pot | 4 +-
include/ChangeLog | 38 +
include/elf/riscv.h | 3 +-
include/gdb/ChangeLog | 4 +
include/gdb/remote-sim.h | 9 +
include/opcode/aarch64.h | 2 -
include/opcode/riscv-opc.h | 127 +-
include/opcode/riscv.h | 125 +-
ld/ChangeLog | 391 +
ld/Makefile.am | 12 +
ld/Makefile.in | 19 +
ld/NEWS | 5 +
ld/aclocal.m4 | 1 +
ld/configure | 97 +-
ld/configure.ac | 2 +
ld/configure.tgt | 25 +-
ld/emulparams/elf32_x86_64.sh | 1 +
ld/emulparams/elf32briscv.sh | 2 +
ld/emulparams/elf32briscv_ilp32.sh | 2 +
ld/emulparams/elf32briscv_ilp32f.sh | 2 +
ld/emulparams/elf64briscv.sh | 2 +
ld/emulparams/elf64briscv_lp64.sh | 2 +
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.../{sim => }/bfin/c_comp3op_pr_plus_pr_sh2.s | 0
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.../{sim => }/bfin/c_compi2opp_pr_eq_i7_p.s | 0
.../{sim => }/bfin/c_dagmodik_lnz_imgebl.s | 0
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.../{sim => }/bfin/c_dagmodim_lnz_imgebl.s | 0
.../{sim => }/bfin/c_dagmodim_lnz_imltbl.s | 0
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.../{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s | 0
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sim/testsuite/{sim => }/frv/fnop.cgs | 0
sim/testsuite/{sim => }/frv/fr400/addss.cgs | 0
sim/testsuite/{sim => }/frv/fr400/allinsn.exp | 0
sim/testsuite/{sim => }/frv/fr400/csdiv.cgs | 0
sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr400/masaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr400/maveh.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mclracc.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs | 0
sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs | 0
sim/testsuite/{sim => }/frv/fr400/movgs.cgs | 0
sim/testsuite/{sim => }/frv/fr400/movsg.cgs | 0
sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr400/scutss.cgs | 0
sim/testsuite/{sim => }/frv/fr400/sdiv.cgs | 0
sim/testsuite/{sim => }/frv/fr400/sdivi.cgs | 0
sim/testsuite/{sim => }/frv/fr400/slass.cgs | 0
sim/testsuite/{sim => }/frv/fr400/smass.cgs | 0
sim/testsuite/{sim => }/frv/fr400/smsss.cgs | 0
sim/testsuite/{sim => }/frv/fr400/smu.cgs | 0
sim/testsuite/{sim => }/frv/fr400/subss.cgs | 0
sim/testsuite/{sim => }/frv/fr400/udiv.cgs | 0
sim/testsuite/{sim => }/frv/fr400/udivi.cgs | 0
sim/testsuite/{sim => }/frv/fr500/allinsn.exp | 0
sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs | 0
sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs | 0
sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs | 0
sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs | 0
sim/testsuite/{sim => }/frv/fr500/dcpl.cgs | 0
sim/testsuite/{sim => }/frv/fr500/dcul.cgs | 0
sim/testsuite/{sim => }/frv/fr500/mclracc.cgs | 0
sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs | 0
sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs | 0
sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs | 0
sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/allinsn.exp | 0
sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmaddhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmcpxiu.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmcpxru.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmmachs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmmachu.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmqaddhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmqaddhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmqmachs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmqmachu.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmqsubhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmqsubhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmsubhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/dcpl.cgs | 0
sim/testsuite/{sim => }/frv/fr550/dcul.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mabshs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/maddhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/maddhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/masaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mmachs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mmachu.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs | 0
sim/testsuite/{sim => }/frv/fr550/msubhss.cgs | 0
sim/testsuite/{sim => }/frv/fr550/msubhus.cgs | 0
sim/testsuite/{sim => }/frv/fr550/mtrap.cgs | 0
sim/testsuite/{sim => }/frv/fr550/udiv.cgs | 0
sim/testsuite/{sim => }/frv/fr550/udivi.cgs | 0
sim/testsuite/{sim => }/frv/fsqrtd.cgs | 0
sim/testsuite/{sim => }/frv/fsqrts.cgs | 0
sim/testsuite/{sim => }/frv/fstoi.cgs | 0
sim/testsuite/{sim => }/frv/fsubd.cgs | 0
sim/testsuite/{sim => }/frv/fsubs.cgs | 0
sim/testsuite/{sim => }/frv/fteq.cgs | 0
sim/testsuite/{sim => }/frv/ftge.cgs | 0
sim/testsuite/{sim => }/frv/ftgt.cgs | 0
sim/testsuite/{sim => }/frv/ftieq.cgs | 0
sim/testsuite/{sim => }/frv/ftige.cgs | 0
sim/testsuite/{sim => }/frv/ftigt.cgs | 0
sim/testsuite/{sim => }/frv/ftile.cgs | 0
sim/testsuite/{sim => }/frv/ftilg.cgs | 0
sim/testsuite/{sim => }/frv/ftilt.cgs | 0
sim/testsuite/{sim => }/frv/ftine.cgs | 0
sim/testsuite/{sim => }/frv/ftino.cgs | 0
sim/testsuite/{sim => }/frv/ftio.cgs | 0
sim/testsuite/{sim => }/frv/ftira.cgs | 0
sim/testsuite/{sim => }/frv/ftiu.cgs | 0
sim/testsuite/{sim => }/frv/ftiue.cgs | 0
sim/testsuite/{sim => }/frv/ftiug.cgs | 0
sim/testsuite/{sim => }/frv/ftiuge.cgs | 0
sim/testsuite/{sim => }/frv/ftiul.cgs | 0
sim/testsuite/{sim => }/frv/ftle.cgs | 0
sim/testsuite/{sim => }/frv/ftlg.cgs | 0
sim/testsuite/{sim => }/frv/ftlt.cgs | 0
sim/testsuite/{sim => }/frv/ftne.cgs | 0
sim/testsuite/{sim => }/frv/ftno.cgs | 0
sim/testsuite/{sim => }/frv/fto.cgs | 0
sim/testsuite/{sim => }/frv/ftra.cgs | 0
sim/testsuite/{sim => }/frv/ftu.cgs | 0
sim/testsuite/{sim => }/frv/ftue.cgs | 0
sim/testsuite/{sim => }/frv/ftug.cgs | 0
sim/testsuite/{sim => }/frv/ftuge.cgs | 0
sim/testsuite/{sim => }/frv/ftul.cgs | 0
sim/testsuite/{sim => }/frv/ftule.cgs | 0
sim/testsuite/frv/grloop.ms | 13 +
sim/testsuite/frv/hello.ms | 19 +
sim/testsuite/{sim => }/frv/icei.cgs | 0
sim/testsuite/{sim => }/frv/ici.cgs | 0
sim/testsuite/{sim => }/frv/icpl.cgs | 0
sim/testsuite/{sim => }/frv/icul.cgs | 0
sim/testsuite/{sim => }/frv/interrupts.exp | 0
.../{sim => }/frv/interrupts/Ipipe-fr400.cgs | 0
.../{sim => }/frv/interrupts/Ipipe-fr500.cgs | 0
.../{sim => }/frv/interrupts/badalign-fr550.cgs | 0
.../{sim => }/frv/interrupts/badalign.cgs | 0
.../{sim => }/frv/interrupts/compound-fr550.cgs | 0
.../{sim => }/frv/interrupts/compound.cgs | 0
.../frv/interrupts/data_store_error-fr550.cgs | 0
.../{sim => }/frv/interrupts/data_store_error.cgs | 0
.../frv/interrupts/fp_exception-fr550.cgs | 0
.../{sim => }/frv/interrupts/fp_exception.cgs | 0
sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs | 0
.../frv/interrupts/insn_access_error-fr550.cgs | 0
.../{sim => }/frv/interrupts/insn_access_error.cgs | 0
.../{sim => }/frv/interrupts/mp_exception.cgs | 0
.../frv/interrupts/privileged_instruction.cgs | 0
.../{sim => }/frv/interrupts/regalign.cgs | 0
sim/testsuite/{sim => }/frv/interrupts/reset.cgs | 0
.../{sim => }/frv/interrupts/shadow_regs.cgs | 0
sim/testsuite/{sim => }/frv/interrupts/timer.cgs | 0
sim/testsuite/{sim => }/frv/jmpil.cgs | 0
sim/testsuite/{sim => }/frv/jmpl.cgs | 0
sim/testsuite/{sim => }/frv/jmpl.pcgs | 0
sim/testsuite/{sim => }/frv/ld.cgs | 0
sim/testsuite/{sim => }/frv/ldbf.cgs | 0
sim/testsuite/{sim => }/frv/ldbfi.cgs | 0
sim/testsuite/{sim => }/frv/ldbfu.cgs | 0
sim/testsuite/{sim => }/frv/ldc.cgs | 0
sim/testsuite/{sim => }/frv/ldcu.cgs | 0
sim/testsuite/{sim => }/frv/ldd.cgs | 0
sim/testsuite/{sim => }/frv/lddc.cgs | 0
sim/testsuite/{sim => }/frv/lddcu.cgs | 0
sim/testsuite/{sim => }/frv/lddf.cgs | 0
sim/testsuite/{sim => }/frv/lddfi.cgs | 0
sim/testsuite/{sim => }/frv/lddfu.cgs | 0
sim/testsuite/{sim => }/frv/lddi.cgs | 0
sim/testsuite/{sim => }/frv/lddu.cgs | 0
sim/testsuite/{sim => }/frv/ldf.cgs | 0
sim/testsuite/{sim => }/frv/ldfi.cgs | 0
sim/testsuite/{sim => }/frv/ldfu.cgs | 0
sim/testsuite/{sim => }/frv/ldhf.cgs | 0
sim/testsuite/{sim => }/frv/ldhfi.cgs | 0
sim/testsuite/{sim => }/frv/ldhfu.cgs | 0
sim/testsuite/{sim => }/frv/ldi.cgs | 0
sim/testsuite/{sim => }/frv/ldq.cgs | 0
sim/testsuite/{sim => }/frv/ldqc.cgs | 0
sim/testsuite/{sim => }/frv/ldqcu.cgs | 0
sim/testsuite/{sim => }/frv/ldqf.cgs | 0
sim/testsuite/{sim => }/frv/ldqfi.cgs | 0
sim/testsuite/{sim => }/frv/ldqfu.cgs | 0
sim/testsuite/{sim => }/frv/ldqi.cgs | 0
sim/testsuite/{sim => }/frv/ldqu.cgs | 0
sim/testsuite/{sim => }/frv/ldsb.cgs | 0
sim/testsuite/{sim => }/frv/ldsbi.cgs | 0
sim/testsuite/{sim => }/frv/ldsbu.cgs | 0
sim/testsuite/{sim => }/frv/ldsh.cgs | 0
sim/testsuite/{sim => }/frv/ldshi.cgs | 0
sim/testsuite/{sim => }/frv/ldshu.cgs | 0
sim/testsuite/{sim => }/frv/ldu.cgs | 0
sim/testsuite/{sim => }/frv/ldub.cgs | 0
sim/testsuite/{sim => }/frv/ldubi.cgs | 0
sim/testsuite/{sim => }/frv/ldubu.cgs | 0
sim/testsuite/{sim => }/frv/lduh.cgs | 0
sim/testsuite/{sim => }/frv/lduhi.cgs | 0
sim/testsuite/{sim => }/frv/lduhu.cgs | 0
sim/testsuite/{sim => }/frv/lrbranch.pcgs | 0
sim/testsuite/{sim => }/frv/mabshs.cgs | 0
sim/testsuite/{sim => }/frv/maddhss.cgs | 0
sim/testsuite/{sim => }/frv/maddhus.cgs | 0
sim/testsuite/{sim => }/frv/mand.cgs | 0
sim/testsuite/{sim => }/frv/maveh.cgs | 0
sim/testsuite/{sim => }/frv/mbtoh.cgs | 0
sim/testsuite/{sim => }/frv/mbtohe.cgs | 0
sim/testsuite/{sim => }/frv/mclracc.cgs | 0
sim/testsuite/{sim => }/frv/mcmpsh.cgs | 0
sim/testsuite/{sim => }/frv/mcmpuh.cgs | 0
sim/testsuite/{sim => }/frv/mcop1.cgs | 0
sim/testsuite/{sim => }/frv/mcop2.cgs | 0
sim/testsuite/{sim => }/frv/mcplhi.cgs | 0
sim/testsuite/{sim => }/frv/mcpli.cgs | 0
sim/testsuite/{sim => }/frv/mcpxis.cgs | 0
sim/testsuite/{sim => }/frv/mcpxiu.cgs | 0
sim/testsuite/{sim => }/frv/mcpxrs.cgs | 0
sim/testsuite/{sim => }/frv/mcpxru.cgs | 0
sim/testsuite/{sim => }/frv/mcut.cgs | 0
sim/testsuite/{sim => }/frv/mcuti.cgs | 0
sim/testsuite/{sim => }/frv/mcutss.cgs | 0
sim/testsuite/{sim => }/frv/mcutssi.cgs | 0
sim/testsuite/{sim => }/frv/mdaddaccs.cgs | 0
sim/testsuite/{sim => }/frv/mdasaccs.cgs | 0
sim/testsuite/{sim => }/frv/mdcutssi.cgs | 0
sim/testsuite/{sim => }/frv/mdpackh.cgs | 0
sim/testsuite/{sim => }/frv/mdrotli.cgs | 0
sim/testsuite/{sim => }/frv/mdsubaccs.cgs | 0
sim/testsuite/{sim => }/frv/mdunpackh.cgs | 0
sim/testsuite/{sim => }/frv/membar.cgs | 0
sim/testsuite/{sim => }/frv/mexpdhd.cgs | 0
sim/testsuite/{sim => }/frv/mexpdhw.cgs | 0
sim/testsuite/{sim => }/frv/mhdseth.cgs | 0
sim/testsuite/{sim => }/frv/mhdsets.cgs | 0
sim/testsuite/{sim => }/frv/mhsethih.cgs | 0
sim/testsuite/{sim => }/frv/mhsethis.cgs | 0
sim/testsuite/{sim => }/frv/mhsetloh.cgs | 0
sim/testsuite/{sim => }/frv/mhsetlos.cgs | 0
sim/testsuite/{sim => }/frv/mhtob.cgs | 0
sim/testsuite/frv/misc.exp | 19 +
sim/testsuite/{sim => }/frv/mmachs.cgs | 0
sim/testsuite/{sim => }/frv/mmachu.cgs | 0
sim/testsuite/{sim => }/frv/mmrdhs.cgs | 0
sim/testsuite/{sim => }/frv/mmrdhu.cgs | 0
sim/testsuite/{sim => }/frv/mmulhs.cgs | 0
sim/testsuite/{sim => }/frv/mmulhu.cgs | 0
sim/testsuite/{sim => }/frv/mmulxhs.cgs | 0
sim/testsuite/{sim => }/frv/mmulxhu.cgs | 0
sim/testsuite/{sim => }/frv/mnop.cgs | 0
sim/testsuite/{sim => }/frv/mnot.cgs | 0
sim/testsuite/{sim => }/frv/mor.cgs | 0
sim/testsuite/{sim => }/frv/mov.cgs | 0
sim/testsuite/{sim => }/frv/movfg.cgs | 0
sim/testsuite/{sim => }/frv/movfgd.cgs | 0
sim/testsuite/{sim => }/frv/movfgq.cgs | 0
sim/testsuite/{sim => }/frv/movgf.cgs | 0
sim/testsuite/{sim => }/frv/movgfd.cgs | 0
sim/testsuite/{sim => }/frv/movgfq.cgs | 0
sim/testsuite/{sim => }/frv/movgs.cgs | 0
sim/testsuite/{sim => }/frv/movsg.cgs | 0
sim/testsuite/{sim => }/frv/mpackh.cgs | 0
sim/testsuite/{sim => }/frv/mqcpxis.cgs | 0
sim/testsuite/{sim => }/frv/mqcpxiu.cgs | 0
sim/testsuite/{sim => }/frv/mqcpxrs.cgs | 0
sim/testsuite/{sim => }/frv/mqcpxru.cgs | 0
sim/testsuite/{sim => }/frv/mqlclrhs.cgs | 0
sim/testsuite/{sim => }/frv/mqlmths.cgs | 0
sim/testsuite/{sim => }/frv/mqmachs.cgs | 0
sim/testsuite/{sim => }/frv/mqmachu.cgs | 0
sim/testsuite/{sim => }/frv/mqmacxhs.cgs | 0
sim/testsuite/{sim => }/frv/mqmulhs.cgs | 0
sim/testsuite/{sim => }/frv/mqmulhu.cgs | 0
sim/testsuite/{sim => }/frv/mqmulxhs.cgs | 0
sim/testsuite/{sim => }/frv/mqmulxhu.cgs | 0
sim/testsuite/{sim => }/frv/mqsaths.cgs | 0
sim/testsuite/{sim => }/frv/mqsllhi.cgs | 0
sim/testsuite/{sim => }/frv/mqsrahi.cgs | 0
sim/testsuite/{sim => }/frv/mqxmachs.cgs | 0
sim/testsuite/{sim => }/frv/mqxmacxhs.cgs | 0
sim/testsuite/{sim => }/frv/mrdacc.cgs | 0
sim/testsuite/{sim => }/frv/mrdaccg.cgs | 0
sim/testsuite/{sim => }/frv/mrotli.cgs | 0
sim/testsuite/{sim => }/frv/mrotri.cgs | 0
sim/testsuite/{sim => }/frv/msaths.cgs | 0
sim/testsuite/{sim => }/frv/msathu.cgs | 0
sim/testsuite/{sim => }/frv/msllhi.cgs | 0
sim/testsuite/{sim => }/frv/msrahi.cgs | 0
sim/testsuite/{sim => }/frv/msrlhi.cgs | 0
sim/testsuite/{sim => }/frv/msubhss.cgs | 0
sim/testsuite/{sim => }/frv/msubhus.cgs | 0
sim/testsuite/{sim => }/frv/mtrap.cgs | 0
sim/testsuite/{sim => }/frv/munpackh.cgs | 0
sim/testsuite/{sim => }/frv/mwcut.cgs | 0
sim/testsuite/{sim => }/frv/mwcuti.cgs | 0
sim/testsuite/{sim => }/frv/mwtacc.cgs | 0
sim/testsuite/{sim => }/frv/mwtaccg.cgs | 0
sim/testsuite/{sim => }/frv/mxor.cgs | 0
sim/testsuite/{sim => }/frv/nandcr.cgs | 0
sim/testsuite/{sim => }/frv/nandncr.cgs | 0
sim/testsuite/{sim => }/frv/nfadds.cgs | 0
sim/testsuite/{sim => }/frv/nfdadds.cgs | 0
sim/testsuite/{sim => }/frv/nfdcmps.cgs | 0
sim/testsuite/{sim => }/frv/nfddivs.cgs | 0
sim/testsuite/{sim => }/frv/nfditos.cgs | 0
sim/testsuite/{sim => }/frv/nfdivs.cgs | 0
sim/testsuite/{sim => }/frv/nfdmadds.cgs | 0
sim/testsuite/{sim => }/frv/nfdmas.cgs | 0
sim/testsuite/{sim => }/frv/nfdmss.cgs | 0
sim/testsuite/{sim => }/frv/nfdmulcs.cgs | 0
sim/testsuite/{sim => }/frv/nfdmuls.cgs | 0
sim/testsuite/{sim => }/frv/nfdsads.cgs | 0
sim/testsuite/{sim => }/frv/nfdsqrts.cgs | 0
sim/testsuite/{sim => }/frv/nfdstoi.cgs | 0
sim/testsuite/{sim => }/frv/nfdsubs.cgs | 0
sim/testsuite/{sim => }/frv/nfitos.cgs | 0
sim/testsuite/{sim => }/frv/nfmadds.cgs | 0
sim/testsuite/{sim => }/frv/nfmas.cgs | 0
sim/testsuite/{sim => }/frv/nfmss.cgs | 0
sim/testsuite/{sim => }/frv/nfmsubs.cgs | 0
sim/testsuite/{sim => }/frv/nfmuls.cgs | 0
sim/testsuite/{sim => }/frv/nfsqrts.cgs | 0
sim/testsuite/{sim => }/frv/nfstoi.cgs | 0
sim/testsuite/{sim => }/frv/nfsubs.cgs | 0
sim/testsuite/{sim => }/frv/nld.cgs | 0
sim/testsuite/{sim => }/frv/nldbf.cgs | 0
sim/testsuite/{sim => }/frv/nldbfi.cgs | 0
sim/testsuite/{sim => }/frv/nldbfu.cgs | 0
sim/testsuite/{sim => }/frv/nldd.cgs | 0
sim/testsuite/{sim => }/frv/nlddf.cgs | 0
sim/testsuite/{sim => }/frv/nlddfi.cgs | 0
sim/testsuite/{sim => }/frv/nlddfu.cgs | 0
sim/testsuite/{sim => }/frv/nlddi.cgs | 0
sim/testsuite/{sim => }/frv/nlddu.cgs | 0
sim/testsuite/{sim => }/frv/nldf.cgs | 0
sim/testsuite/{sim => }/frv/nldfi.cgs | 0
sim/testsuite/{sim => }/frv/nldfu.cgs | 0
sim/testsuite/{sim => }/frv/nldhf.cgs | 0
sim/testsuite/{sim => }/frv/nldhfi.cgs | 0
sim/testsuite/{sim => }/frv/nldhfu.cgs | 0
sim/testsuite/{sim => }/frv/nldi.cgs | 0
sim/testsuite/{sim => }/frv/nldq.cgs | 0
sim/testsuite/{sim => }/frv/nldqf.cgs | 0
sim/testsuite/{sim => }/frv/nldqfi.cgs | 0
sim/testsuite/{sim => }/frv/nldqfu.cgs | 0
sim/testsuite/{sim => }/frv/nldqu.cgs | 0
sim/testsuite/{sim => }/frv/nldsb.cgs | 0
sim/testsuite/{sim => }/frv/nldsbi.cgs | 0
sim/testsuite/{sim => }/frv/nldsbu.cgs | 0
sim/testsuite/{sim => }/frv/nldsh.cgs | 0
sim/testsuite/{sim => }/frv/nldshi.cgs | 0
sim/testsuite/{sim => }/frv/nldshu.cgs | 0
sim/testsuite/{sim => }/frv/nldu.cgs | 0
sim/testsuite/{sim => }/frv/nldub.cgs | 0
sim/testsuite/{sim => }/frv/nldubi.cgs | 0
sim/testsuite/{sim => }/frv/nldubu.cgs | 0
sim/testsuite/{sim => }/frv/nlduh.cgs | 0
sim/testsuite/{sim => }/frv/nlduhi.cgs | 0
sim/testsuite/{sim => }/frv/nlduhu.cgs | 0
sim/testsuite/{sim => }/frv/nop.cgs | 0
sim/testsuite/{sim => }/frv/norcr.cgs | 0
sim/testsuite/{sim => }/frv/norncr.cgs | 0
sim/testsuite/{sim => }/frv/not.cgs | 0
sim/testsuite/{sim => }/frv/notcr.cgs | 0
sim/testsuite/{sim => }/frv/nsdiv.cgs | 0
sim/testsuite/{sim => }/frv/nsdivi.cgs | 0
sim/testsuite/{sim => }/frv/nudiv.cgs | 0
sim/testsuite/{sim => }/frv/nudivi.cgs | 0
sim/testsuite/{sim => }/frv/or.cgs | 0
sim/testsuite/{sim => }/frv/orcc.cgs | 0
sim/testsuite/{sim => }/frv/orcr.cgs | 0
sim/testsuite/{sim => }/frv/ori.cgs | 0
sim/testsuite/{sim => }/frv/oricc.cgs | 0
sim/testsuite/{sim => }/frv/orncr.cgs | 0
sim/testsuite/{sim => }/frv/parallel.exp | 0
sim/testsuite/{sim => }/frv/ret.cgs | 0
sim/testsuite/{sim => }/frv/rett.cgs | 0
sim/testsuite/{sim => }/frv/scan.cgs | 0
sim/testsuite/{sim => }/frv/scani.cgs | 0
sim/testsuite/{sim => }/frv/sdiv.cgs | 0
sim/testsuite/{sim => }/frv/sdivi.cgs | 0
sim/testsuite/{sim => }/frv/sethi.cgs | 0
sim/testsuite/{sim => }/frv/sethilo.pcgs | 0
sim/testsuite/{sim => }/frv/setlo.cgs | 0
sim/testsuite/{sim => }/frv/setlos.cgs | 0
sim/testsuite/{sim => }/frv/sll.cgs | 0
sim/testsuite/{sim => }/frv/sllcc.cgs | 0
sim/testsuite/{sim => }/frv/slli.cgs | 0
sim/testsuite/{sim => }/frv/sllicc.cgs | 0
sim/testsuite/{sim => }/frv/smul.cgs | 0
sim/testsuite/{sim => }/frv/smulcc.cgs | 0
sim/testsuite/{sim => }/frv/smuli.cgs | 0
sim/testsuite/{sim => }/frv/smulicc.cgs | 0
sim/testsuite/{sim => }/frv/sra.cgs | 0
sim/testsuite/{sim => }/frv/sracc.cgs | 0
sim/testsuite/{sim => }/frv/srai.cgs | 0
sim/testsuite/{sim => }/frv/sraicc.cgs | 0
sim/testsuite/{sim => }/frv/srl.cgs | 0
sim/testsuite/{sim => }/frv/srlcc.cgs | 0
sim/testsuite/{sim => }/frv/srli.cgs | 0
sim/testsuite/{sim => }/frv/srlicc.cgs | 0
sim/testsuite/{sim => }/frv/st.cgs | 0
sim/testsuite/{sim => }/frv/stb.cgs | 0
sim/testsuite/{sim => }/frv/stbf.cgs | 0
sim/testsuite/{sim => }/frv/stbfi.cgs | 0
sim/testsuite/{sim => }/frv/stbfu.cgs | 0
sim/testsuite/{sim => }/frv/stbi.cgs | 0
sim/testsuite/{sim => }/frv/stbu.cgs | 0
sim/testsuite/{sim => }/frv/stc.cgs | 0
sim/testsuite/{sim => }/frv/stcu.cgs | 0
sim/testsuite/{sim => }/frv/std.cgs | 0
sim/testsuite/{sim => }/frv/std.pcgs | 0
sim/testsuite/{sim => }/frv/stdc.cgs | 0
sim/testsuite/{sim => }/frv/stdc.pcgs | 0
sim/testsuite/{sim => }/frv/stdcu.cgs | 0
sim/testsuite/{sim => }/frv/stdf.cgs | 0
sim/testsuite/{sim => }/frv/stdf.pcgs | 0
sim/testsuite/{sim => }/frv/stdfi.cgs | 0
sim/testsuite/{sim => }/frv/stdfu.cgs | 0
sim/testsuite/{sim => }/frv/stdi.cgs | 0
sim/testsuite/{sim => }/frv/stdu.cgs | 0
sim/testsuite/{sim => }/frv/stf.cgs | 0
sim/testsuite/{sim => }/frv/stfi.cgs | 0
sim/testsuite/{sim => }/frv/stfu.cgs | 0
sim/testsuite/{sim => }/frv/sth.cgs | 0
sim/testsuite/{sim => }/frv/sthf.cgs | 0
sim/testsuite/{sim => }/frv/sthfi.cgs | 0
sim/testsuite/{sim => }/frv/sthfu.cgs | 0
sim/testsuite/{sim => }/frv/sthi.cgs | 0
sim/testsuite/{sim => }/frv/sthu.cgs | 0
sim/testsuite/{sim => }/frv/sti.cgs | 0
sim/testsuite/{sim => }/frv/stq.cgs | 0
sim/testsuite/{sim => }/frv/stq.pcgs | 0
sim/testsuite/{sim => }/frv/stqc.cgs | 0
sim/testsuite/{sim => }/frv/stqc.pcgs | 0
sim/testsuite/{sim => }/frv/stqcu.cgs | 0
sim/testsuite/{sim => }/frv/stqf.cgs | 0
sim/testsuite/{sim => }/frv/stqf.pcgs | 0
sim/testsuite/{sim => }/frv/stqfi.cgs | 0
sim/testsuite/{sim => }/frv/stqfu.cgs | 0
sim/testsuite/{sim => }/frv/stqi.cgs | 0
sim/testsuite/{sim => }/frv/stqu.cgs | 0
sim/testsuite/{sim => }/frv/stu.cgs | 0
sim/testsuite/{sim => }/frv/sub.cgs | 0
sim/testsuite/{sim => }/frv/subcc.cgs | 0
sim/testsuite/{sim => }/frv/subi.cgs | 0
sim/testsuite/{sim => }/frv/subicc.cgs | 0
sim/testsuite/{sim => }/frv/subx.cgs | 0
sim/testsuite/{sim => }/frv/subxcc.cgs | 0
sim/testsuite/{sim => }/frv/subxi.cgs | 0
sim/testsuite/{sim => }/frv/subxicc.cgs | 0
sim/testsuite/{sim => }/frv/swap.cgs | 0
sim/testsuite/{sim => }/frv/swapi.cgs | 0
sim/testsuite/{sim => }/frv/tc.cgs | 0
sim/testsuite/{sim => }/frv/teq.cgs | 0
sim/testsuite/{sim => }/frv/testutils.inc | 0
sim/testsuite/{sim => }/frv/tge.cgs | 0
sim/testsuite/{sim => }/frv/tgt.cgs | 0
sim/testsuite/{sim => }/frv/thi.cgs | 0
sim/testsuite/{sim => }/frv/tic.cgs | 0
sim/testsuite/{sim => }/frv/tieq.cgs | 0
sim/testsuite/{sim => }/frv/tige.cgs | 0
sim/testsuite/{sim => }/frv/tigt.cgs | 0
sim/testsuite/{sim => }/frv/tihi.cgs | 0
sim/testsuite/{sim => }/frv/tile.cgs | 0
sim/testsuite/{sim => }/frv/tils.cgs | 0
sim/testsuite/{sim => }/frv/tilt.cgs | 0
sim/testsuite/{sim => }/frv/tin.cgs | 0
sim/testsuite/{sim => }/frv/tinc.cgs | 0
sim/testsuite/{sim => }/frv/tine.cgs | 0
sim/testsuite/{sim => }/frv/tino.cgs | 0
sim/testsuite/{sim => }/frv/tinv.cgs | 0
sim/testsuite/{sim => }/frv/tip.cgs | 0
sim/testsuite/{sim => }/frv/tira.cgs | 0
sim/testsuite/{sim => }/frv/tiv.cgs | 0
sim/testsuite/{sim => }/frv/tle.cgs | 0
sim/testsuite/{sim => }/frv/tls.cgs | 0
sim/testsuite/{sim => }/frv/tlt.cgs | 0
sim/testsuite/{sim => }/frv/tn.cgs | 0
sim/testsuite/{sim => }/frv/tnc.cgs | 0
sim/testsuite/{sim => }/frv/tne.cgs | 0
sim/testsuite/{sim => }/frv/tno.cgs | 0
sim/testsuite/{sim => }/frv/tnv.cgs | 0
sim/testsuite/{sim => }/frv/tp.cgs | 0
sim/testsuite/{sim => }/frv/tra.cgs | 0
sim/testsuite/{sim => }/frv/tv.cgs | 0
sim/testsuite/{sim => }/frv/udiv.cgs | 0
sim/testsuite/{sim => }/frv/udivi.cgs | 0
sim/testsuite/{sim => }/frv/umul.cgs | 0
sim/testsuite/{sim => }/frv/umulcc.cgs | 0
sim/testsuite/{sim => }/frv/umuli.cgs | 0
sim/testsuite/{sim => }/frv/umulicc.cgs | 0
sim/testsuite/{sim => }/frv/xor.cgs | 0
sim/testsuite/{sim => }/frv/xorcc.cgs | 0
sim/testsuite/{sim => }/frv/xorcr.cgs | 0
sim/testsuite/{sim => }/frv/xori.cgs | 0
sim/testsuite/{sim => }/frv/xoricc.cgs | 0
sim/testsuite/{sim => }/ft32/ChangeLog | 0
sim/testsuite/{sim => }/ft32/allinsn.exp | 0
sim/testsuite/{sim => }/ft32/basic.s | 0
sim/testsuite/{sim => }/ft32/testutils.inc | 0
sim/testsuite/h8300/ChangeLog | 107 +
sim/testsuite/{sim => }/h8300/addb.s | 0
sim/testsuite/{sim => }/h8300/addl.s | 0
sim/testsuite/{sim => }/h8300/adds.s | 0
sim/testsuite/{sim => }/h8300/addw.s | 0
sim/testsuite/{sim => }/h8300/addx.s | 0
sim/testsuite/h8300/allinsn.exp | 15 +
sim/testsuite/{sim => }/h8300/andb.s | 0
sim/testsuite/{sim => }/h8300/andl.s | 0
sim/testsuite/{sim => }/h8300/andw.s | 0
sim/testsuite/{sim => }/h8300/band.s | 0
sim/testsuite/{sim => }/h8300/bfld.s | 0
sim/testsuite/{sim => }/h8300/biand.s | 0
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sim/testsuite/{sim => }/h8300/brabc.s | 0
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sim/testsuite/{sim => }/h8300/daa.s | 0
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sim/testsuite/{sim => }/h8300/movmd.s | 0
sim/testsuite/{sim => }/h8300/movsd.s | 0
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sim/testsuite/{sim => }/h8300/mul.s | 0
sim/testsuite/{sim => }/h8300/neg.s | 0
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sim/testsuite/{sim => }/h8300/orl.s | 0
sim/testsuite/{sim => }/h8300/orw.s | 0
sim/testsuite/h8300/rotl.s | 1212 ++
sim/testsuite/h8300/rotr.s | 1802 +++
sim/testsuite/h8300/rotxl.s | 167 +
sim/testsuite/h8300/rotxr.s | 2002 +++
sim/testsuite/h8300/shal.s | 167 +
sim/testsuite/h8300/shar.s | 2000 +++
sim/testsuite/h8300/shll.s | 375 +
sim/testsuite/h8300/shlr.s | 4085 +++++
sim/testsuite/{sim => }/h8300/stack.s | 0
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sim/testsuite/{sim => }/h8300/subx.s | 0
sim/testsuite/h8300/tas.s | 80 +
sim/testsuite/{sim => }/h8300/testutils.inc | 0
sim/testsuite/{sim => }/h8300/xorb.s | 0
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sim/testsuite/lib/sim-defs.exp | 23 +-
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sim/testsuite/{sim => }/m32c/fail.s | 0
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sim/testsuite/{sim => }/m32c/sample.ld | 0
sim/testsuite/{sim => }/m32c/sample.s | 0
sim/testsuite/{sim => }/m32c/sample2.c | 0
sim/testsuite/{sim => }/m32c/testutils.inc | 0
sim/testsuite/m32r-elf/ChangeLog | 18 -
sim/testsuite/m32r-elf/Makefile.in | 156 -
sim/testsuite/m32r-elf/configure | 2984 ----
sim/testsuite/m32r-elf/configure.ac | 18 -
sim/testsuite/m32r-elf/exit47.s | 7 -
sim/testsuite/m32r-elf/hello.s | 17 -
sim/testsuite/m32r-elf/loop.s | 2 -
sim/testsuite/m32r/ChangeLog | 126 +
sim/testsuite/{sim => }/m32r/add.cgs | 0
sim/testsuite/{sim => }/m32r/add3.cgs | 0
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sim/testsuite/{sim => }/m32r/addv3.cgs | 0
sim/testsuite/{sim => }/m32r/addx.cgs | 0
sim/testsuite/{sim => }/m32r/allinsn.exp | 0
sim/testsuite/{sim => }/m32r/and.cgs | 0
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sim/testsuite/{sim => }/m32r/bc24.cgs | 0
sim/testsuite/{sim => }/m32r/bc8.cgs | 0
sim/testsuite/{sim => }/m32r/beq.cgs | 0
sim/testsuite/{sim => }/m32r/beqz.cgs | 0
sim/testsuite/{sim => }/m32r/bgez.cgs | 0
sim/testsuite/{sim => }/m32r/bgtz.cgs | 0
sim/testsuite/{sim => }/m32r/bl24.cgs | 0
sim/testsuite/{sim => }/m32r/bl8.cgs | 0
sim/testsuite/{sim => }/m32r/blez.cgs | 0
sim/testsuite/{sim => }/m32r/bltz.cgs | 0
sim/testsuite/{sim => }/m32r/bnc24.cgs | 0
sim/testsuite/{sim => }/m32r/bnc8.cgs | 0
sim/testsuite/{sim => }/m32r/bne.cgs | 0
sim/testsuite/{sim => }/m32r/bnez.cgs | 0
sim/testsuite/{sim => }/m32r/bra24.cgs | 0
sim/testsuite/{sim => }/m32r/bra8.cgs | 0
sim/testsuite/{sim => }/m32r/cmp.cgs | 0
sim/testsuite/{sim => }/m32r/cmpi.cgs | 0
sim/testsuite/{sim => }/m32r/cmpu.cgs | 0
sim/testsuite/{sim => }/m32r/cmpui.cgs | 0
sim/testsuite/{sim => }/m32r/div.cgs | 0
sim/testsuite/{sim => }/m32r/divu.cgs | 0
sim/testsuite/m32r/exit47.ms | 11 +
sim/testsuite/{sim => }/m32r/hello.ms | 0
sim/testsuite/{sim => }/m32r/hw-trap.ms | 0
sim/testsuite/{sim => }/m32r/jl.cgs | 0
sim/testsuite/{sim => }/m32r/jmp.cgs | 0
sim/testsuite/{sim => }/m32r/ld-d.cgs | 0
sim/testsuite/{sim => }/m32r/ld-plus.cgs | 0
sim/testsuite/{sim => }/m32r/ld.cgs | 0
sim/testsuite/{sim => }/m32r/ld24.cgs | 0
sim/testsuite/{sim => }/m32r/ldb-d.cgs | 0
sim/testsuite/{sim => }/m32r/ldb.cgs | 0
sim/testsuite/{sim => }/m32r/ldh-d.cgs | 0
sim/testsuite/{sim => }/m32r/ldh.cgs | 0
sim/testsuite/{sim => }/m32r/ldi16.cgs | 0
sim/testsuite/{sim => }/m32r/ldi8.cgs | 0
sim/testsuite/{sim => }/m32r/ldub-d.cgs | 0
sim/testsuite/{sim => }/m32r/ldub.cgs | 0
sim/testsuite/{sim => }/m32r/lduh-d.cgs | 0
sim/testsuite/{sim => }/m32r/lduh.cgs | 0
sim/testsuite/{sim => }/m32r/lock.cgs | 0
sim/testsuite/{sim => }/m32r/machi.cgs | 0
sim/testsuite/{sim => }/m32r/maclo.cgs | 0
sim/testsuite/{sim => }/m32r/macwhi.cgs | 0
sim/testsuite/{sim => }/m32r/macwlo.cgs | 0
sim/testsuite/{sim => }/m32r/misc.exp | 0
sim/testsuite/{sim => }/m32r/mul.cgs | 0
sim/testsuite/{sim => }/m32r/mulhi.cgs | 0
sim/testsuite/{sim => }/m32r/mullo.cgs | 0
sim/testsuite/{sim => }/m32r/mulwhi.cgs | 0
sim/testsuite/{sim => }/m32r/mulwlo.cgs | 0
sim/testsuite/{sim => }/m32r/mv.cgs | 0
sim/testsuite/{sim => }/m32r/mvfachi.cgs | 0
sim/testsuite/{sim => }/m32r/mvfaclo.cgs | 0
sim/testsuite/{sim => }/m32r/mvfacmi.cgs | 0
sim/testsuite/{sim => }/m32r/mvfc.cgs | 0
sim/testsuite/{sim => }/m32r/mvtachi.cgs | 0
sim/testsuite/{sim => }/m32r/mvtaclo.cgs | 0
sim/testsuite/{sim => }/m32r/mvtc.cgs | 0
sim/testsuite/{sim => }/m32r/neg.cgs | 0
sim/testsuite/{sim => }/m32r/nop.cgs | 0
sim/testsuite/{sim => }/m32r/not.cgs | 0
sim/testsuite/{sim => }/m32r/or.cgs | 0
sim/testsuite/{sim => }/m32r/or3.cgs | 0
sim/testsuite/{sim => }/m32r/rac.cgs | 0
sim/testsuite/{sim => }/m32r/rach.cgs | 0
sim/testsuite/{sim => }/m32r/rem.cgs | 0
sim/testsuite/{sim => }/m32r/remu.cgs | 0
sim/testsuite/{sim => }/m32r/rte.cgs | 0
sim/testsuite/{sim => }/m32r/seth.cgs | 0
sim/testsuite/{sim => }/m32r/sll.cgs | 0
sim/testsuite/{sim => }/m32r/sll3.cgs | 0
sim/testsuite/{sim => }/m32r/slli.cgs | 0
sim/testsuite/{sim => }/m32r/sra.cgs | 0
sim/testsuite/{sim => }/m32r/sra3.cgs | 0
sim/testsuite/{sim => }/m32r/srai.cgs | 0
sim/testsuite/{sim => }/m32r/srl.cgs | 0
sim/testsuite/{sim => }/m32r/srl3.cgs | 0
sim/testsuite/{sim => }/m32r/srli.cgs | 0
sim/testsuite/{sim => }/m32r/st-d.cgs | 0
sim/testsuite/{sim => }/m32r/st-minus.cgs | 0
sim/testsuite/{sim => }/m32r/st-plus.cgs | 0
sim/testsuite/{sim => }/m32r/st.cgs | 0
sim/testsuite/{sim => }/m32r/stb-d.cgs | 0
sim/testsuite/{sim => }/m32r/stb.cgs | 0
sim/testsuite/{sim => }/m32r/sth-d.cgs | 0
sim/testsuite/{sim => }/m32r/sth.cgs | 0
sim/testsuite/{sim => }/m32r/sub.cgs | 0
sim/testsuite/{sim => }/m32r/subv.cgs | 0
sim/testsuite/{sim => }/m32r/subx.cgs | 0
sim/testsuite/{sim => }/m32r/testutils.inc | 0
sim/testsuite/{sim => }/m32r/trap.cgs | 0
sim/testsuite/{sim => }/m32r/unlock.cgs | 0
sim/testsuite/{sim => }/m32r/uread16.ms | 0
sim/testsuite/{sim => }/m32r/uread32.ms | 0
sim/testsuite/{sim => }/m32r/uwrite16.ms | 0
sim/testsuite/{sim => }/m32r/uwrite32.ms | 0
sim/testsuite/{sim => }/m32r/xor.cgs | 0
sim/testsuite/{sim => }/m32r/xor3.cgs | 0
sim/testsuite/{sim => }/m68hc11/ChangeLog | 0
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sim/testsuite/{sim => }/mips/basic.exp | 0
sim/testsuite/{sim => }/mips/fpu64-ps-sb1.s | 0
sim/testsuite/{sim => }/mips/fpu64-ps.s | 0
sim/testsuite/{sim => }/mips/hilo-hazard-1.s | 0
sim/testsuite/{sim => }/mips/hilo-hazard-2.s | 0
sim/testsuite/{sim => }/mips/hilo-hazard-3.s | 0
sim/testsuite/{sim => }/mips/hilo-hazard-4.s | 0
sim/testsuite/{sim => }/mips/mdmx-ob-sb1.s | 0
sim/testsuite/{sim => }/mips/mdmx-ob.s | 0
sim/testsuite/{sim => }/mips/mips32-dsp.s | 0
sim/testsuite/{sim => }/mips/mips32-dsp2.s | 0
sim/testsuite/{sim => }/mips/sanity.s | 0
sim/testsuite/{sim => }/mips/testutils.inc | 0
sim/testsuite/{sim => }/mips/utils-dsp.inc | 0
sim/testsuite/{sim => }/mips/utils-fpu.inc | 0
sim/testsuite/{sim => }/mips/utils-mdmx.inc | 0
sim/testsuite/mips64el-elf/ChangeLog | 19 -
sim/testsuite/mips64el-elf/Makefile.in | 170 -
sim/testsuite/mips64el-elf/configure | 2984 ----
sim/testsuite/mips64el-elf/configure.ac | 18 -
sim/testsuite/{sim => }/mn10300/ChangeLog | 0
sim/testsuite/{sim => }/mn10300/allinsn.exp | 0
sim/testsuite/{sim => }/mn10300/pass.s | 0
sim/testsuite/{sim => }/mn10300/testutils.inc | 0
sim/testsuite/{sim => }/moxie/ChangeLog | 0
sim/testsuite/{sim => }/moxie/allinsn.exp | 0
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sim/testsuite/{sim => }/moxie/testutils.inc | 0
sim/testsuite/{sim => }/msp430/ChangeLog | 0
sim/testsuite/{sim => }/msp430/add.s | 0
sim/testsuite/{sim => }/msp430/allinsn.exp | 0
sim/testsuite/{sim => }/msp430/mpyull_hwmult.s | 0
sim/testsuite/{sim => }/msp430/rrux.s | 0
sim/testsuite/{sim => }/msp430/testutils.inc | 0
sim/testsuite/{sim => }/or1k/ChangeLog | 0
sim/testsuite/{sim => }/or1k/add.S | 0
sim/testsuite/{sim => }/or1k/adrp.S | 0
sim/testsuite/{sim => }/or1k/alltests.exp | 0
sim/testsuite/{sim => }/or1k/and.S | 0
sim/testsuite/{sim => }/or1k/basic.S | 0
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sim/testsuite/sim/sh64/compact/shad.cgs | 58 -
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sim/testsuite/sim/sh64/interwork.exp | 20 -
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sim/testsuite/sim/sh64/media/ChangeLog | 102 -
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create mode 100644 gdb/testsuite/gdb.fortran/intvar-array.exp
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rename sim/testsuite/{sim => }/aarch64/ChangeLog (100%)
rename sim/testsuite/{sim => }/aarch64/adds.s (100%)
rename sim/testsuite/{sim => }/aarch64/addv.s (100%)
rename sim/testsuite/{sim => }/aarch64/allinsn.exp (100%)
rename sim/testsuite/{sim => }/aarch64/bit.s (100%)
rename sim/testsuite/{sim => }/aarch64/cmtst.s (100%)
rename sim/testsuite/{sim => }/aarch64/cnt.s (100%)
rename sim/testsuite/{sim => }/aarch64/fcmXX.s (100%)
rename sim/testsuite/{sim => }/aarch64/fcmp.s (100%)
rename sim/testsuite/{sim => }/aarch64/fcsel.s (100%)
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rename sim/testsuite/{sim => }/aarch64/fcvtz.s (100%)
rename sim/testsuite/{sim => }/aarch64/fminnm.s (100%)
rename sim/testsuite/{sim => }/aarch64/fstur.s (100%)
rename sim/testsuite/{sim => }/aarch64/ldn_multiple.s (100%)
rename sim/testsuite/{sim => }/aarch64/ldn_single.s (100%)
rename sim/testsuite/{sim => }/aarch64/ldnr.s (100%)
rename sim/testsuite/{sim => }/aarch64/mla.s (100%)
rename sim/testsuite/{sim => }/aarch64/mls.s (100%)
rename sim/testsuite/{sim => }/aarch64/mul.s (100%)
rename sim/testsuite/{sim => }/aarch64/pass.s (100%)
rename sim/testsuite/{sim => }/aarch64/stn_multiple.s (100%)
rename sim/testsuite/{sim => }/aarch64/stn_single.s (100%)
rename sim/testsuite/{sim => }/aarch64/sumov.s (100%)
rename sim/testsuite/{sim => }/aarch64/sumulh.s (100%)
rename sim/testsuite/{sim => }/aarch64/tbnz.s (100%)
rename sim/testsuite/{sim => }/aarch64/testutils.inc (100%)
rename sim/testsuite/{sim => }/aarch64/uzp.s (100%)
rename sim/testsuite/{sim => }/aarch64/xtl.s (100%)
rename sim/testsuite/{sim => }/aarch64/xtn.s (100%)
rename sim/testsuite/{sim => }/arm/ChangeLog (100%)
rename sim/testsuite/{sim => }/arm/adc.cgs (100%)
rename sim/testsuite/{sim => }/arm/add.cgs (100%)
rename sim/testsuite/{sim => }/arm/allinsn.exp (100%)
rename sim/testsuite/{sim => }/arm/and.cgs (100%)
rename sim/testsuite/{sim => }/arm/b.cgs (100%)
rename sim/testsuite/{sim => }/arm/bic.cgs (100%)
rename sim/testsuite/{sim => }/arm/bl.cgs (100%)
rename sim/testsuite/{sim => }/arm/bx.cgs (100%)
rename sim/testsuite/{sim => }/arm/cmn.cgs (100%)
rename sim/testsuite/{sim => }/arm/cmp.cgs (100%)
rename sim/testsuite/{sim => }/arm/eor.cgs (100%)
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rename sim/testsuite/{sim => }/arm/iwmmxt/iwmmxt.exp (100%)
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rename sim/testsuite/{sim => }/arm/misaligned1.ms (100%)
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rename sim/testsuite/{sim => }/arm/misc.exp (100%)
rename sim/testsuite/{sim => }/arm/mla.cgs (100%)
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rename sim/testsuite/{sim => }/arm/testutils.inc (100%)
rename sim/testsuite/{sim => }/arm/thumb/adc.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/add-hd-hs.cgs (100%)
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rename sim/testsuite/{sim => }/arm/thumb/add.cgs (100%)
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rename sim/testsuite/{sim => }/arm/thumb/allthumb.exp (100%)
rename sim/testsuite/{sim => }/arm/thumb/and.cgs (100%)
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rename sim/testsuite/{sim => }/arm/thumb/bhi.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bic.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bl-hi.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/bl-lo.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ble.cgs (100%)
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rename sim/testsuite/{sim => }/arm/thumb/bx-hs.cgs (100%)
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rename sim/testsuite/{sim => }/arm/thumb/cmn.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/cmp-hd-hs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/cmp-hd-rs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/cmp-rd-hs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/cmp.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/eor.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/lda-pc.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/lda-sp.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ldmia.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ldr-imm.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ldr-pc.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ldr-sprel.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ldr.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ldrb-imm.cgs (100%)
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rename sim/testsuite/{sim => }/arm/thumb/ldrh-imm.cgs (100%)
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rename sim/testsuite/{sim => }/arm/thumb/ldsb.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ldsh.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/lsl.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/lsr.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/mov-hd-hs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/mov-hd-rs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/mov-rd-hs.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/mov.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/mul.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/mvn.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/neg.cgs (100%)
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rename sim/testsuite/{sim => }/arm/thumb/pop-pc.cgs (100%)
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rename sim/testsuite/{sim => }/arm/thumb/push-lr.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/push.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/ror.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/sbc.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/stmia.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/str-imm.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/str-sprel.cgs (100%)
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rename sim/testsuite/{sim => }/arm/thumb/strb-imm.cgs (100%)
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rename sim/testsuite/{sim => }/arm/thumb/strh-imm.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/strh.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/sub-sp.cgs (100%)
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rename sim/testsuite/{sim => }/arm/thumb/subi.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/subi8.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/swi.cgs (100%)
rename sim/testsuite/{sim => }/arm/thumb/testutils.inc (100%)
rename sim/testsuite/{sim => }/arm/thumb/tst.cgs (100%)
rename sim/testsuite/{sim => }/arm/tst.cgs (100%)
rename sim/testsuite/{sim => }/arm/umlal.cgs (100%)
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rename sim/testsuite/{sim => }/arm/xscale/blx.cgs (100%)
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rename sim/testsuite/{sim => }/arm/xscale/miaxy.cgs (100%)
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rename sim/testsuite/{sim => }/arm/xscale/testutils.inc (100%)
rename sim/testsuite/{sim => }/arm/xscale/xscale.exp (100%)
rename sim/testsuite/{sim => }/avr/ChangeLog (100%)
rename sim/testsuite/{sim => }/avr/allinsn.exp (100%)
rename sim/testsuite/{sim => }/avr/pass.s (100%)
rename sim/testsuite/{sim => }/avr/testutils.inc (100%)
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rename sim/testsuite/{sim => }/bfin/ChangeLog (100%)
rename sim/testsuite/{sim => }/bfin/PN_generator.s (100%)
rename sim/testsuite/{sim => }/bfin/a0.s (100%)
rename sim/testsuite/{sim => }/bfin/a0shift.S (100%)
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rename sim/testsuite/{sim => }/bfin/abs_acc.s (100%)
rename sim/testsuite/{sim => }/bfin/acc-rot.s (100%)
rename sim/testsuite/{sim => }/bfin/acp5_19.s (100%)
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rename sim/testsuite/{sim => }/bfin/add_imm7.s (100%)
rename sim/testsuite/{sim => }/bfin/add_shift.S (100%)
rename sim/testsuite/{sim => }/bfin/add_sub_acc.s (100%)
rename sim/testsuite/{sim => }/bfin/addsub_flags.S (100%)
rename sim/testsuite/{sim => }/bfin/algnbug1.s (100%)
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rename sim/testsuite/{sim => }/bfin/allinsn.exp (100%)
rename sim/testsuite/{sim => }/bfin/argc.c (100%)
rename sim/testsuite/{sim => }/bfin/ashift.s (100%)
rename sim/testsuite/{sim => }/bfin/ashift_flags.s (100%)
rename sim/testsuite/{sim => }/bfin/ashift_left.s (100%)
rename sim/testsuite/{sim => }/bfin/b0.S (100%)
rename sim/testsuite/{sim => }/bfin/b1.s (100%)
rename sim/testsuite/{sim => }/bfin/b2.S (100%)
rename sim/testsuite/{sim => }/bfin/brcc.s (100%)
rename sim/testsuite/{sim => }/bfin/brevadd.s (100%)
rename sim/testsuite/{sim => }/bfin/byteop16m.s (100%)
rename sim/testsuite/{sim => }/bfin/byteop16p.s (100%)
rename sim/testsuite/{sim => }/bfin/byteop1p.s (100%)
rename sim/testsuite/{sim => }/bfin/byteop2p.s (100%)
rename sim/testsuite/{sim => }/bfin/byteop3p.s (100%)
rename sim/testsuite/{sim => }/bfin/byteunpack.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_arith_r_sft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_neg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_toggle.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_xb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_divq.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_divs.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_log_l_sft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_log_r_sft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_shadd_1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_alu2op_shadd_2.s (100%)
rename sim/testsuite/{sim => }/bfin/c_br_preg_killed_ac.s (100%)
rename sim/testsuite/{sim => }/bfin/c_br_preg_killed_ex1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_br_preg_stall_ac.s (100%)
rename sim/testsuite/{sim => }/bfin/c_br_preg_stall_ex1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_bp1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_bp2.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_bp3.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_bp4.s (100%)
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rename sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_bp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_nbp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brf_fbkwd.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brf_nbp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brt_bp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_brt_nbp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_kills_dhits.s (100%)
rename sim/testsuite/{sim => }/bfin/c_brcc_kills_dmiss.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr_pp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_calla_ljump.s (100%)
rename sim/testsuite/{sim => }/bfin/c_calla_subr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_ac.S (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_an.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_aq.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av0.S (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av1.S (100%)
rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_az.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_flag_ccmv_depend.S (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft_s1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft_sn.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_s1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_sn.S (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_a0a1.S (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr_uu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3_uu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3_uu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr_uu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_pr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_pr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_and_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_minus_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_or_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_plus_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_xor_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_pr_plus_pr_sh1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_comp3op_pr_plus_pr_sh2.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_add_i7_n.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_add_i7_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_eq_i7_n.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_eq_i7_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags.S (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags_2.S (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_n.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_n.s (100%)
rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imgebl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imltbl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dagmodik_lz_inc_dec.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imgebl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imltbl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dagmodim_lz_inc_dec.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0_pm_a1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0a1s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_abs_a.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_neg_a.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_absabs.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_negneg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_abs.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_absabs.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_alhwx.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_awx.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop1ew.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop2.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop3.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_bytepack.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteunpack.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_disalnexcpt.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_max.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_maxmax.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_min.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_minmin.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_r_lh_a0pa1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_r_negneg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd12_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd12_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd20_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd20_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd12_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd12_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd20_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd20_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rlh_rnd.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rr_lph_a1a0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm_aa.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft_x.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft_x.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_saa.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sat_aa.S (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_search.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sgn.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_iuw32.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_ih.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_iu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_t.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_tu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_ih.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_iu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_t.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_tu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_iutsh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_ih.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_iu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_iutsh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_t.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_t.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_tu.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_is.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_u.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_a0alr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align16.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align24.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_l.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_r.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expexp_r.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_ln.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_lp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rn.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_pack.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_r.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmax.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmaxvmax.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_a0alr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh_s.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ippm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_ipp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_ipp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ippm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_ipp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s (100%)
rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_ipp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_except_illopcode.S (100%)
rename sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S (100%)
rename sim/testsuite/{sim => }/bfin/c_except_user_mode.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_disable.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_disable_enable.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_excpt.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_loopsetup_stld.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_nested.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_nmi.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_pending.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_pending_2.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_timer.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_timer_reload.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_timer_tcount.S (100%)
rename sim/testsuite/{sim => }/bfin/c_interr_timer_tscale.S (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drlo.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_ibml.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_h_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_ibml.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_l_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_ibml.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lz_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_ibml.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_lzhi_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_pibml.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_mm_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_pp_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_ppmm_hbx.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_d_p_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_mm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_ld_p_p_pp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_mm_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_d_pp_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_mm.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldst_st_p_p_pp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dr_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_ld_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_b.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dr_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstidxl_st_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dr_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_ld_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dr_h.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_st_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstii_st_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstiifp_ld_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstiifp_st_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_hi.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dr_lo.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_h_xh.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_ld_lohi.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_hi.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dr_lo.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ldstpmod_st_lohi.s (100%)
rename sim/testsuite/{sim => }/bfin/c_linkage.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_alshft_mix.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_arith_shft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_bitclr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_bitset.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_bittgl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_bittst.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_log_l_shft_astat.S (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft.s (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_log_r_shft_astat.S (100%)
rename sim/testsuite/{sim => }/bfin/c_logi2op_nbittst.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_bot.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_prelc.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_nested_top.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_overlap.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_div2_lc1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc0.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_stld.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_prelc.s (100%)
rename sim/testsuite/{sim => }/bfin/c_loopsetup_topbotcntr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_mmr_interr_ctl.s (100%)
rename sim/testsuite/{sim => }/bfin/c_mmr_loop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mmr_loop_user_except.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mmr_ppop_illegal_adr.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mmr_ppopm_illegal_adr.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mmr_timer.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mode_supervisor.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mode_user.S (100%)
rename sim/testsuite/{sim => }/bfin/c_mode_user_superivsor.S (100%)
rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ld_ld.s (100%)
rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ldst_2.s (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pcpr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_call_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_clisti_interr.S (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_csync_mmr.S (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_except_rtx.S (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_excpt.S (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pcpr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_jump_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_nop.s (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_raise_rt_i_n.S (100%)
rename sim/testsuite/{sim => }/bfin/c_progctrl_rts.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_neg_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_sft_2_1.s (100%)
rename sim/testsuite/{sim => }/bfin/c_ptr2op_pr_shadd_1_2.s (100%)
rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp.s (100%)
rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dp_pair.s (100%)
rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_dreg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_pushpopmultiple_preg.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_acc_acc.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_dag_lz_dep.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_dr_acc_acc.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dep_nostall.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_dr_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_dr_imlb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_dr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dep_nostall.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dep_stall.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_imlb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_imlb_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dep_nostall.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dep_stall.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_pr_dr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_pr_imlb.s (100%)
rename sim/testsuite/{sim => }/bfin/c_regmv_pr_pr.s (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ac_raise_mv_ppop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ac_regmv_pushpop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_dec_raise_pushpop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex1_brcc_mv_pop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex1_call_mv_pop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex1_j_mv_pop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_brcc_mv_pop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_call_mv_pop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_j_mv_pop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex2_brcc_mp_mv_pop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex2_mmr_mvpop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex2_mmrj_mvpop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex2_raise_mmr_mvpop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex2_raise_mmrj_mvpop.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_brcc_mvp.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmr_mvp.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmrj_mvp.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_wb_cs_lsmmrj_mvp.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_wb_rti_lsmmrj_mvp.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_wb_rtn_lsmmrj_mvp.S (100%)
rename sim/testsuite/{sim => }/bfin/c_seq_wb_rtx_lsmmrj_mvp.S (100%)
rename sim/testsuite/{sim => }/bfin/c_ujump.s (100%)
rename sim/testsuite/{sim => }/bfin/cc-alu.S (100%)
rename sim/testsuite/{sim => }/bfin/cc-astat-bits.s (100%)
rename sim/testsuite/{sim => }/bfin/cc0.s (100%)
rename sim/testsuite/{sim => }/bfin/cc1.s (100%)
rename sim/testsuite/{sim => }/bfin/cc5.S (100%)
rename sim/testsuite/{sim => }/bfin/cec-exact-exception.S (100%)
rename sim/testsuite/{sim => }/bfin/cec-ifetch.S (100%)
rename sim/testsuite/{sim => }/bfin/cec-multi-pending.S (100%)
rename sim/testsuite/{sim => }/bfin/cec-no-snen-reti.S (100%)
rename sim/testsuite/{sim => }/bfin/cec-non-operating-env.s (100%)
rename sim/testsuite/{sim => }/bfin/cec-raise-reti.S (100%)
rename sim/testsuite/{sim => }/bfin/cec-snen-reti.S (100%)
rename sim/testsuite/{sim => }/bfin/cec-syscfg-ssstep.S (100%)
rename sim/testsuite/{sim => }/bfin/cec-system-call.S (100%)
rename sim/testsuite/{sim => }/bfin/cir.s (100%)
rename sim/testsuite/{sim => }/bfin/cir1.s (100%)
rename sim/testsuite/{sim => }/bfin/cli-sti.s (100%)
rename sim/testsuite/{sim => }/bfin/cmpacc.s (100%)
rename sim/testsuite/{sim => }/bfin/cmpdreg.S (100%)
rename sim/testsuite/{sim => }/bfin/compare.s (100%)
rename sim/testsuite/{sim => }/bfin/conv_enc_gen.s (100%)
rename sim/testsuite/{sim => }/bfin/cycles.s (100%)
rename sim/testsuite/{sim => }/bfin/d0.s (100%)
rename sim/testsuite/{sim => }/bfin/d1.s (100%)
rename sim/testsuite/{sim => }/bfin/d2.s (100%)
rename sim/testsuite/{sim => }/bfin/dbg_brprd_ntkn_src_kill.S (100%)
rename sim/testsuite/{sim => }/bfin/dbg_brtkn_nprd_src_kill.S (100%)
rename sim/testsuite/{sim => }/bfin/dbg_jmp_src_kill.S (100%)
rename sim/testsuite/{sim => }/bfin/dbg_tr_basic.S (100%)
rename sim/testsuite/{sim => }/bfin/dbg_tr_simplejp.S (100%)
rename sim/testsuite/{sim => }/bfin/dbg_tr_tbuf0.S (100%)
rename sim/testsuite/{sim => }/bfin/dbg_tr_umode.S (100%)
rename sim/testsuite/{sim => }/bfin/disalnexcpt_implicit.S (100%)
rename sim/testsuite/{sim => }/bfin/div0.s (100%)
rename sim/testsuite/{sim => }/bfin/divq.s (100%)
rename sim/testsuite/{sim => }/bfin/dotproduct.s (100%)
rename sim/testsuite/{sim => }/bfin/dotproduct2.s (100%)
rename sim/testsuite/{sim => }/bfin/double_prec_mult.s (100%)
rename sim/testsuite/{sim => }/bfin/dsp_a4.s (100%)
rename sim/testsuite/{sim => }/bfin/dsp_a7.s (100%)
rename sim/testsuite/{sim => }/bfin/dsp_a8.s (100%)
rename sim/testsuite/{sim => }/bfin/dsp_d0.s (100%)
rename sim/testsuite/{sim => }/bfin/dsp_d1.s (100%)
rename sim/testsuite/{sim => }/bfin/dsp_neg.S (100%)
rename sim/testsuite/{sim => }/bfin/dsp_s1.s (100%)
rename sim/testsuite/{sim => }/bfin/e0.s (100%)
rename sim/testsuite/{sim => }/bfin/edn_snafu.s (100%)
rename sim/testsuite/{sim => }/bfin/eu_dsp32mac_s.s (100%)
rename sim/testsuite/{sim => }/bfin/events.s (100%)
rename sim/testsuite/{sim => }/bfin/f221.s (100%)
rename sim/testsuite/{sim => }/bfin/fact.s (100%)
rename sim/testsuite/{sim => }/bfin/fir.s (100%)
rename sim/testsuite/{sim => }/bfin/fsm.s (100%)
rename sim/testsuite/{sim => }/bfin/greg2.s (100%)
rename sim/testsuite/{sim => }/bfin/hwloop-bits.S (100%)
rename sim/testsuite/{sim => }/bfin/hwloop-branch-in.s (100%)
rename sim/testsuite/{sim => }/bfin/hwloop-branch-out.s (100%)
rename sim/testsuite/{sim => }/bfin/hwloop-lt-bits.s (100%)
rename sim/testsuite/{sim => }/bfin/hwloop-nested.s (100%)
rename sim/testsuite/{sim => }/bfin/i0.s (100%)
rename sim/testsuite/{sim => }/bfin/iir.s (100%)
rename sim/testsuite/{sim => }/bfin/issue103.s (100%)
rename sim/testsuite/{sim => }/bfin/issue109.s (100%)
rename sim/testsuite/{sim => }/bfin/issue112.s (100%)
rename sim/testsuite/{sim => }/bfin/issue113.s (100%)
rename sim/testsuite/{sim => }/bfin/issue117.s (100%)
rename sim/testsuite/{sim => }/bfin/issue118.s (100%)
rename sim/testsuite/{sim => }/bfin/issue119.s (100%)
rename sim/testsuite/{sim => }/bfin/issue121.s (100%)
rename sim/testsuite/{sim => }/bfin/issue123.s (100%)
rename sim/testsuite/{sim => }/bfin/issue124.s (100%)
rename sim/testsuite/{sim => }/bfin/issue125.s (100%)
rename sim/testsuite/{sim => }/bfin/issue126.s (100%)
rename sim/testsuite/{sim => }/bfin/issue127.s (100%)
rename sim/testsuite/{sim => }/bfin/issue129.s (100%)
rename sim/testsuite/{sim => }/bfin/issue139.S (100%)
rename sim/testsuite/{sim => }/bfin/issue140.S (100%)
rename sim/testsuite/{sim => }/bfin/issue142.s (100%)
rename sim/testsuite/{sim => }/bfin/issue144.s (100%)
rename sim/testsuite/{sim => }/bfin/issue146.S (100%)
rename sim/testsuite/{sim => }/bfin/issue175.s (100%)
rename sim/testsuite/{sim => }/bfin/issue205.s (100%)
rename sim/testsuite/{sim => }/bfin/issue257.s (100%)
rename sim/testsuite/{sim => }/bfin/issue272.S (100%)
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rename sim/testsuite/{sim => }/cr16/pop3.cgs (100%)
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rename sim/testsuite/{sim => }/cr16/popret2.cgs (100%)
rename sim/testsuite/{sim => }/cr16/popret3.cgs (100%)
rename sim/testsuite/{sim => }/cr16/push1.cgs (100%)
rename sim/testsuite/{sim => }/cr16/push2.cgs (100%)
rename sim/testsuite/{sim => }/cr16/push3.cgs (100%)
rename sim/testsuite/{sim => }/cr16/sbitb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/sbitw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/scc.cgs (100%)
rename sim/testsuite/{sim => }/cr16/scs.cgs (100%)
rename sim/testsuite/{sim => }/cr16/seq.cgs (100%)
rename sim/testsuite/{sim => }/cr16/sfc.cgs (100%)
rename sim/testsuite/{sim => }/cr16/sfs.cgs (100%)
rename sim/testsuite/{sim => }/cr16/sge.cgs (100%)
rename sim/testsuite/{sim => }/cr16/sgt.cgs (100%)
rename sim/testsuite/{sim => }/cr16/shi.cgs (100%)
rename sim/testsuite/{sim => }/cr16/shs.cgs (100%)
rename sim/testsuite/{sim => }/cr16/slo.cgs (100%)
rename sim/testsuite/{sim => }/cr16/sls.cgs (100%)
rename sim/testsuite/{sim => }/cr16/slt.cgs (100%)
rename sim/testsuite/{sim => }/cr16/sne.cgs (100%)
rename sim/testsuite/{sim => }/cr16/storb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/stord.cgs (100%)
rename sim/testsuite/{sim => }/cr16/storw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/subb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/subd.cgs (100%)
rename sim/testsuite/{sim => }/cr16/subi.cgs (100%)
rename sim/testsuite/{sim => }/cr16/subw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/tbit.cgs (100%)
rename sim/testsuite/{sim => }/cr16/tbitb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/tbitw.cgs (100%)
rename sim/testsuite/{sim => }/cr16/testutils.inc (100%)
rename sim/testsuite/{sim => }/cr16/uread16.ms (100%)
rename sim/testsuite/{sim => }/cr16/uread32.ms (100%)
rename sim/testsuite/{sim => }/cr16/xorb.cgs (100%)
rename sim/testsuite/{sim => }/cr16/xord.cgs (100%)
rename sim/testsuite/{sim => }/cr16/xorw.cgs (100%)
create mode 100644 sim/testsuite/cris/ChangeLog
rename sim/testsuite/{sim => }/cris/asm/abs.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addcpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addcv32c.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addcv32m.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addcv32r.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addi.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addiv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addoc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addom.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addoq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addqpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addswpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addxc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addxm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/addxr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/andc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/andm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/andq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/andr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/asm.exp (100%)
rename sim/testsuite/{sim => }/cris/asm/asr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/ba.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/badarch1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bare1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bare2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bare3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bas.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bccb.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bdapc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bdapm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bdapq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/bdapqpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/biap.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/boundc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/boundm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/boundmv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/boundr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/break.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/btst.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/ccr-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/ccs-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/clearfv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/clearfv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/clrjmp1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/cmpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/cmpm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/cmpq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/cmpr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/cmpxc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/cmpxm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/dflags.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/dip.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/dstep.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/fidxd.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/fidxi.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/ftagd.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/ftagi.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/halt.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io4.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io5.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io6.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io7.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io8.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/io9.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/jsr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/jsrmv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/jumpmp.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/jumppv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/lapc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/lsl.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/lsr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/lz.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/mcp.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movdelsr1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movecpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movecr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movecrt10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movecrt32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movect10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movei.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movempc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movemr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movemrv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movemrv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movepcb.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movepcd.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movepcw.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moveq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moveqpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/mover.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverbpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverdpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverpcb.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverpcd.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverpcw.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/moverwpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movesmp.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movmp.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movmp8.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movpmv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movpmv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movppc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movpr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movprv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movprv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movrss.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movscpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movscr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movsm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movsmpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movsr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movsrpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movssr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movucpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movucr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movum.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movumpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movur.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/movurpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/mstep.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/msteppc1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/msteppc2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/msteppc3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/mulv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/mulv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/mulx.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/neg.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/nonvcv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/nopv10t.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/nopv32t.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/nopv32t2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/nopv32t3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/nopv32t4.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/not.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/op3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/opterr1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/opterr2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/opterr3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/opterr4.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/opterr5.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/option1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/option2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/option3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/option4.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/orc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/orm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/orq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/orr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/pcplus.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/pid1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw11.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw12.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw13.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw14.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw15.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw16.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw17.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw3.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw4.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw5.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw6.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw7.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw8.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/raw9.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/ret.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/rfe.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/rfg.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/rfn.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/sbfs.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/scc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/sfe.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/subc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/subm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/subq.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/subqpc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/subr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/subxc.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/subxm.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/subxr.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/swap.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tb.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/test.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/testutils.inc (100%)
rename sim/testsuite/{sim => }/cris/asm/tjmpsrv32-2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tjmpsrv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tjsrcv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tjsrcv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmemv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmemv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmulv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmulv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmvm1.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmvm2.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmvmrv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmvmrv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmvrmv10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/tmvrmv32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/user.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x0-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x0-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x1-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x1-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x10-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x2-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x2-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x3-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x3-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x4-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x5-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x5-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x6-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x6-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x7-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x7-v32.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x8-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/x9-v10.ms (100%)
rename sim/testsuite/{sim => }/cris/asm/xor.ms (100%)
rename sim/testsuite/{sim => }/cris/c/access1.c (100%)
rename sim/testsuite/{sim => }/cris/c/append1.c (100%)
rename sim/testsuite/{sim => }/cris/c/badldso1.c (100%)
rename sim/testsuite/{sim => }/cris/c/badldso2.c (100%)
rename sim/testsuite/{sim => }/cris/c/badldso3.c (100%)
create mode 100644 sim/testsuite/cris/c/c.exp
rename sim/testsuite/{sim => }/cris/c/clone1.c (100%)
rename sim/testsuite/{sim => }/cris/c/clone2.c (100%)
rename sim/testsuite/{sim => }/cris/c/clone3.c (100%)
rename sim/testsuite/{sim => }/cris/c/clone4.c (100%)
rename sim/testsuite/{sim => }/cris/c/clone5.c (100%)
rename sim/testsuite/{sim => }/cris/c/clone6.c (100%)
rename sim/testsuite/{sim => }/cris/c/ex1.c (100%)
rename sim/testsuite/{sim => }/cris/c/exitg1.c (100%)
rename sim/testsuite/{sim => }/cris/c/exitg2.c (100%)
rename sim/testsuite/{sim => }/cris/c/fcntl1.c (100%)
rename sim/testsuite/{sim => }/cris/c/fcntl2.c (100%)
rename sim/testsuite/{sim => }/cris/c/fdopen1.c (100%)
rename sim/testsuite/{sim => }/cris/c/fdopen2.c (100%)
rename sim/testsuite/{sim => }/cris/c/freopen1.c (100%)
rename sim/testsuite/{sim => }/cris/c/freopen2.c (100%)
rename sim/testsuite/{sim => }/cris/c/ftruncate1.c (100%)
rename sim/testsuite/{sim => }/cris/c/ftruncate2.c (100%)
rename sim/testsuite/{sim => }/cris/c/getcwd1.c (100%)
rename sim/testsuite/{sim => }/cris/c/gettod.c (100%)
rename sim/testsuite/{sim => }/cris/c/hello.c (100%)
create mode 100644 sim/testsuite/cris/c/helloaout.c
rename sim/testsuite/{sim => }/cris/c/hellodyn.c (100%)
rename sim/testsuite/{sim => }/cris/c/hellodyn2.c (100%)
rename sim/testsuite/{sim => }/cris/c/hellodyn3.c (100%)
rename sim/testsuite/{sim => }/cris/c/kill1.c (100%)
create mode 100644 sim/testsuite/cris/c/kill2.c
rename sim/testsuite/{sim => }/cris/c/kill3.c (100%)
rename sim/testsuite/{sim => }/cris/c/mapbrk.c (100%)
rename sim/testsuite/{sim => }/cris/c/mmap1.c (100%)
rename sim/testsuite/{sim => }/cris/c/mmap2.c (100%)
rename sim/testsuite/{sim => }/cris/c/mmap3.c (100%)
rename sim/testsuite/{sim => }/cris/c/mmap4.c (100%)
rename sim/testsuite/{sim => }/cris/c/mmap5.c (100%)
rename sim/testsuite/{sim => }/cris/c/mmap6.c (100%)
rename sim/testsuite/{sim => }/cris/c/mmap7.c (100%)
rename sim/testsuite/{sim => }/cris/c/mmap8.c (100%)
rename sim/testsuite/{sim => }/cris/c/mprotect1.c (100%)
rename sim/testsuite/{sim => }/cris/c/mprotect2.c (100%)
rename sim/testsuite/{sim => }/cris/c/mremap.c (100%)
create mode 100644 sim/testsuite/cris/c/openpf1.c
create mode 100644 sim/testsuite/cris/c/openpf2.c
rename sim/testsuite/{sim => }/cris/c/openpf3.c (100%)
rename sim/testsuite/{sim => }/cris/c/openpf4.c (100%)
rename sim/testsuite/{sim => }/cris/c/openpf5.c (100%)
create mode 100644 sim/testsuite/cris/c/pipe1.c
rename sim/testsuite/{sim => }/cris/c/pipe2.c (100%)
rename sim/testsuite/{sim => }/cris/c/pipe3.c (100%)
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rename sim/testsuite/{sim => }/frv/cfckug.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfckuge.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfckul.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfckule.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfcmps.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfdivs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfitos.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfmadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfmas.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfmovs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfmss.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfmsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfmuls.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfnegs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfsqrts.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfstoi.cgs (100%)
rename sim/testsuite/{sim => }/frv/cfsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cjmpl.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckc.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckeq.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckge.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckgt.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckle.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckls.cgs (100%)
rename sim/testsuite/{sim => }/frv/cklt.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckn.cgs (100%)
rename sim/testsuite/{sim => }/frv/cknc.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckne.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckno.cgs (100%)
rename sim/testsuite/{sim => }/frv/cknv.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckp.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckra.cgs (100%)
rename sim/testsuite/{sim => }/frv/ckv.cgs (100%)
rename sim/testsuite/{sim => }/frv/cld.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldbf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldbfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldd.cgs (100%)
rename sim/testsuite/{sim => }/frv/clddf.cgs (100%)
rename sim/testsuite/{sim => }/frv/clddfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/clddu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldhf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldhfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldq.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldqu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldsb.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldsbu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldsh.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldshu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldub.cgs (100%)
rename sim/testsuite/{sim => }/frv/cldubu.cgs (100%)
rename sim/testsuite/{sim => }/frv/clduh.cgs (100%)
rename sim/testsuite/{sim => }/frv/clduhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/clrfa.cgs (100%)
rename sim/testsuite/{sim => }/frv/clrfr.cgs (100%)
rename sim/testsuite/{sim => }/frv/clrga.cgs (100%)
rename sim/testsuite/{sim => }/frv/clrgr.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmaddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmaddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmand.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmbtoh.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmbtohe.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmcpxis.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmcpxiu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmcpxrs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmcpxru.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmexpdhd.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmexpdhw.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmhtob.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmmulhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmmulhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmnot.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmor.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmov.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmovfg.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmovfgd.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmovgf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmovgfd.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmp.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmpb.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmpba.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmpi.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmqmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmqmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmqmulhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmqmulhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmsubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmsubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/cmxor.cgs (100%)
rename sim/testsuite/{sim => }/frv/cnot.cgs (100%)
rename sim/testsuite/{sim => }/frv/commitfa.cgs (100%)
rename sim/testsuite/{sim => }/frv/commitfr.cgs (100%)
rename sim/testsuite/{sim => }/frv/commitga.cgs (100%)
rename sim/testsuite/{sim => }/frv/commitgr.cgs (100%)
rename sim/testsuite/{sim => }/frv/cop1.cgs (100%)
rename sim/testsuite/{sim => }/frv/cop2.cgs (100%)
rename sim/testsuite/{sim => }/frv/cor.cgs (100%)
rename sim/testsuite/{sim => }/frv/corcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/cscan.cgs (100%)
rename sim/testsuite/{sim => }/frv/csdiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/csll.cgs (100%)
rename sim/testsuite/{sim => }/frv/csllcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/csmul.cgs (100%)
rename sim/testsuite/{sim => }/frv/csmulcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/csra.cgs (100%)
rename sim/testsuite/{sim => }/frv/csracc.cgs (100%)
rename sim/testsuite/{sim => }/frv/csrl.cgs (100%)
rename sim/testsuite/{sim => }/frv/csrlcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/cst.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstb.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstbf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstbfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstbu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstd.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstdf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstdfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstdu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstf.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/csth.cgs (100%)
rename sim/testsuite/{sim => }/frv/csthf.cgs (100%)
rename sim/testsuite/{sim => }/frv/csthfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/csthu.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstq.cgs (100%)
rename sim/testsuite/{sim => }/frv/cstu.cgs (100%)
rename sim/testsuite/{sim => }/frv/csub.cgs (100%)
rename sim/testsuite/{sim => }/frv/csubcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/cswap.cgs (100%)
rename sim/testsuite/{sim => }/frv/cudiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/cxor.cgs (100%)
rename sim/testsuite/{sim => }/frv/cxorcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/dcef.cgs (100%)
rename sim/testsuite/{sim => }/frv/dcei.cgs (100%)
rename sim/testsuite/{sim => }/frv/dcf.cgs (100%)
rename sim/testsuite/{sim => }/frv/dci.cgs (100%)
create mode 100644 sim/testsuite/frv/exit47.ms
rename sim/testsuite/{sim => }/frv/fabsd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fabss.cgs (100%)
rename sim/testsuite/{sim => }/frv/faddd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbeq.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbeqlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbge.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbgelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbgt.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbgtlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fble.cgs (100%)
rename sim/testsuite/{sim => }/frv/fblelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fblg.cgs (100%)
rename sim/testsuite/{sim => }/frv/fblglr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fblt.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbltlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbne.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbnelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbno.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbnolr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbo.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbolr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbra.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbralr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbue.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbuelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbug.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbuge.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbugelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbuglr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbul.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbule.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbulelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbullr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fbulr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbeqlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbgelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbgtlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcblelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcblglr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbltlr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbnelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbnolr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbolr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbralr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbuelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbugelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbuglr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbulelr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbullr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcbulr.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckeq.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckge.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckgt.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckle.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcklg.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcklt.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckne.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckno.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcko.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckra.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcku.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckue.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckug.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckuge.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckul.cgs (100%)
rename sim/testsuite/{sim => }/frv/fckule.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcmpd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fcmps.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdabss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdcmps.cgs (100%)
rename sim/testsuite/{sim => }/frv/fddivs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fditos.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdivd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdivs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdmadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdmas.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdmovs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdmss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdmulcs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdmuls.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdnegs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdsads.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdsqrts.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdstoi.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fdtoi.cgs (100%)
rename sim/testsuite/{sim => }/frv/fitod.cgs (100%)
rename sim/testsuite/{sim => }/frv/fitos.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmad.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmaddd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmas.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmovd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmovs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmsd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmsubd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmuld.cgs (100%)
rename sim/testsuite/{sim => }/frv/fmuls.cgs (100%)
rename sim/testsuite/{sim => }/frv/fnegd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fnegs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fnop.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/addss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/allinsn.exp (100%)
rename sim/testsuite/{sim => }/frv/fr400/csdiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/maddaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/masaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/maveh.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mclracc.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mhdseth.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mhdsets.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mhsethih.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mhsethis.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mhsetloh.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/mhsetlos.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/movgs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/movsg.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/msubaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/scutss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/sdiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/sdivi.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/slass.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/smass.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/smsss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/smu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/subss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/udiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr400/udivi.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/allinsn.exp (100%)
rename sim/testsuite/{sim => }/frv/fr500/cmqaddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/cmqaddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/cmqsubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/cmqsubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/dcpl.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/dcul.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/mclracc.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/mqaddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/mqaddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/mqsubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr500/mqsubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/allinsn.exp (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmaddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmaddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmcpxiu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmcpxru.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmqaddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmqaddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmqmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmqmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmqsubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmqsubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmsubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/dcpl.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/dcul.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mabshs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/maddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/maddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/masaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mmrdhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mmrdhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqaddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqaddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqmacxhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqsubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqsubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqxmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mqxmacxhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/msubaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/msubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/msubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/mtrap.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/udiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/fr550/udivi.cgs (100%)
rename sim/testsuite/{sim => }/frv/fsqrtd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fsqrts.cgs (100%)
rename sim/testsuite/{sim => }/frv/fstoi.cgs (100%)
rename sim/testsuite/{sim => }/frv/fsubd.cgs (100%)
rename sim/testsuite/{sim => }/frv/fsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/fteq.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftge.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftgt.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftieq.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftige.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftigt.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftile.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftilg.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftilt.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftine.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftino.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftio.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftira.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftiu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftiue.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftiug.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftiuge.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftiul.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftle.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftlg.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftlt.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftne.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftno.cgs (100%)
rename sim/testsuite/{sim => }/frv/fto.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftra.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftue.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftug.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftuge.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftul.cgs (100%)
rename sim/testsuite/{sim => }/frv/ftule.cgs (100%)
create mode 100644 sim/testsuite/frv/grloop.ms
create mode 100644 sim/testsuite/frv/hello.ms
rename sim/testsuite/{sim => }/frv/icei.cgs (100%)
rename sim/testsuite/{sim => }/frv/ici.cgs (100%)
rename sim/testsuite/{sim => }/frv/icpl.cgs (100%)
rename sim/testsuite/{sim => }/frv/icul.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts.exp (100%)
rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr400.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr500.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/badalign-fr550.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/badalign.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/compound-fr550.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/compound.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/data_store_error-fr550.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/data_store_error.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/fp_exception-fr550.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/fp_exception.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error-fr550.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/mp_exception.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/privileged_instruction.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/regalign.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/reset.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/shadow_regs.cgs (100%)
rename sim/testsuite/{sim => }/frv/interrupts/timer.cgs (100%)
rename sim/testsuite/{sim => }/frv/jmpil.cgs (100%)
rename sim/testsuite/{sim => }/frv/jmpl.cgs (100%)
rename sim/testsuite/{sim => }/frv/jmpl.pcgs (100%)
rename sim/testsuite/{sim => }/frv/ld.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldbf.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldbfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldbfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldc.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldcu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldd.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddc.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddcu.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddf.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddi.cgs (100%)
rename sim/testsuite/{sim => }/frv/lddu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldf.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldhf.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldhfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldhfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldq.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqc.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqcu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqf.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldqu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldsb.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldsbi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldsbu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldsh.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldshi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldshu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldu.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldub.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldubi.cgs (100%)
rename sim/testsuite/{sim => }/frv/ldubu.cgs (100%)
rename sim/testsuite/{sim => }/frv/lduh.cgs (100%)
rename sim/testsuite/{sim => }/frv/lduhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/lduhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/lrbranch.pcgs (100%)
rename sim/testsuite/{sim => }/frv/mabshs.cgs (100%)
rename sim/testsuite/{sim => }/frv/maddhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/maddhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/mand.cgs (100%)
rename sim/testsuite/{sim => }/frv/maveh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mbtoh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mbtohe.cgs (100%)
rename sim/testsuite/{sim => }/frv/mclracc.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcmpsh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcmpuh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcop1.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcop2.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcplhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcpli.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcpxis.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcpxiu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcpxrs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcpxru.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcut.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcuti.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcutss.cgs (100%)
rename sim/testsuite/{sim => }/frv/mcutssi.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdaddaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdasaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdcutssi.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdpackh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdrotli.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdsubaccs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mdunpackh.cgs (100%)
rename sim/testsuite/{sim => }/frv/membar.cgs (100%)
rename sim/testsuite/{sim => }/frv/mexpdhd.cgs (100%)
rename sim/testsuite/{sim => }/frv/mexpdhw.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhdseth.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhdsets.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhsethih.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhsethis.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhsetloh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhsetlos.cgs (100%)
rename sim/testsuite/{sim => }/frv/mhtob.cgs (100%)
create mode 100644 sim/testsuite/frv/misc.exp
rename sim/testsuite/{sim => }/frv/mmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmrdhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmrdhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmulhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmulhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmulxhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mmulxhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mnop.cgs (100%)
rename sim/testsuite/{sim => }/frv/mnot.cgs (100%)
rename sim/testsuite/{sim => }/frv/mor.cgs (100%)
rename sim/testsuite/{sim => }/frv/mov.cgs (100%)
rename sim/testsuite/{sim => }/frv/movfg.cgs (100%)
rename sim/testsuite/{sim => }/frv/movfgd.cgs (100%)
rename sim/testsuite/{sim => }/frv/movfgq.cgs (100%)
rename sim/testsuite/{sim => }/frv/movgf.cgs (100%)
rename sim/testsuite/{sim => }/frv/movgfd.cgs (100%)
rename sim/testsuite/{sim => }/frv/movgfq.cgs (100%)
rename sim/testsuite/{sim => }/frv/movgs.cgs (100%)
rename sim/testsuite/{sim => }/frv/movsg.cgs (100%)
rename sim/testsuite/{sim => }/frv/mpackh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqcpxis.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqcpxiu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqcpxrs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqcpxru.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqlclrhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqlmths.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmachu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmacxhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmulhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmulhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmulxhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqmulxhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqsaths.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqsllhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqsrahi.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqxmachs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mqxmacxhs.cgs (100%)
rename sim/testsuite/{sim => }/frv/mrdacc.cgs (100%)
rename sim/testsuite/{sim => }/frv/mrdaccg.cgs (100%)
rename sim/testsuite/{sim => }/frv/mrotli.cgs (100%)
rename sim/testsuite/{sim => }/frv/mrotri.cgs (100%)
rename sim/testsuite/{sim => }/frv/msaths.cgs (100%)
rename sim/testsuite/{sim => }/frv/msathu.cgs (100%)
rename sim/testsuite/{sim => }/frv/msllhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/msrahi.cgs (100%)
rename sim/testsuite/{sim => }/frv/msrlhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/msubhss.cgs (100%)
rename sim/testsuite/{sim => }/frv/msubhus.cgs (100%)
rename sim/testsuite/{sim => }/frv/mtrap.cgs (100%)
rename sim/testsuite/{sim => }/frv/munpackh.cgs (100%)
rename sim/testsuite/{sim => }/frv/mwcut.cgs (100%)
rename sim/testsuite/{sim => }/frv/mwcuti.cgs (100%)
rename sim/testsuite/{sim => }/frv/mwtacc.cgs (100%)
rename sim/testsuite/{sim => }/frv/mwtaccg.cgs (100%)
rename sim/testsuite/{sim => }/frv/mxor.cgs (100%)
rename sim/testsuite/{sim => }/frv/nandcr.cgs (100%)
rename sim/testsuite/{sim => }/frv/nandncr.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdcmps.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfddivs.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfditos.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdivs.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdmadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdmas.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdmss.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdmulcs.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdmuls.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdsads.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdsqrts.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdstoi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfdsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfitos.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfmadds.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfmas.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfmss.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfmsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfmuls.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfsqrts.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfstoi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nfsubs.cgs (100%)
rename sim/testsuite/{sim => }/frv/nld.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldbf.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldbfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldbfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldd.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlddf.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlddfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlddfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlddi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlddu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldf.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldhf.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldhfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldhfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldq.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldqf.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldqfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldqfu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldqu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldsb.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldsbi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldsbu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldsh.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldshi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldshu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldub.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldubi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nldubu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlduh.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlduhi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nlduhu.cgs (100%)
rename sim/testsuite/{sim => }/frv/nop.cgs (100%)
rename sim/testsuite/{sim => }/frv/norcr.cgs (100%)
rename sim/testsuite/{sim => }/frv/norncr.cgs (100%)
rename sim/testsuite/{sim => }/frv/not.cgs (100%)
rename sim/testsuite/{sim => }/frv/notcr.cgs (100%)
rename sim/testsuite/{sim => }/frv/nsdiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/nsdivi.cgs (100%)
rename sim/testsuite/{sim => }/frv/nudiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/nudivi.cgs (100%)
rename sim/testsuite/{sim => }/frv/or.cgs (100%)
rename sim/testsuite/{sim => }/frv/orcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/orcr.cgs (100%)
rename sim/testsuite/{sim => }/frv/ori.cgs (100%)
rename sim/testsuite/{sim => }/frv/oricc.cgs (100%)
rename sim/testsuite/{sim => }/frv/orncr.cgs (100%)
rename sim/testsuite/{sim => }/frv/parallel.exp (100%)
rename sim/testsuite/{sim => }/frv/ret.cgs (100%)
rename sim/testsuite/{sim => }/frv/rett.cgs (100%)
rename sim/testsuite/{sim => }/frv/scan.cgs (100%)
rename sim/testsuite/{sim => }/frv/scani.cgs (100%)
rename sim/testsuite/{sim => }/frv/sdiv.cgs (100%)
rename sim/testsuite/{sim => }/frv/sdivi.cgs (100%)
rename sim/testsuite/{sim => }/frv/sethi.cgs (100%)
rename sim/testsuite/{sim => }/frv/sethilo.pcgs (100%)
rename sim/testsuite/{sim => }/frv/setlo.cgs (100%)
rename sim/testsuite/{sim => }/frv/setlos.cgs (100%)
rename sim/testsuite/{sim => }/frv/sll.cgs (100%)
rename sim/testsuite/{sim => }/frv/sllcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/slli.cgs (100%)
rename sim/testsuite/{sim => }/frv/sllicc.cgs (100%)
rename sim/testsuite/{sim => }/frv/smul.cgs (100%)
rename sim/testsuite/{sim => }/frv/smulcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/smuli.cgs (100%)
rename sim/testsuite/{sim => }/frv/smulicc.cgs (100%)
rename sim/testsuite/{sim => }/frv/sra.cgs (100%)
rename sim/testsuite/{sim => }/frv/sracc.cgs (100%)
rename sim/testsuite/{sim => }/frv/srai.cgs (100%)
rename sim/testsuite/{sim => }/frv/sraicc.cgs (100%)
rename sim/testsuite/{sim => }/frv/srl.cgs (100%)
rename sim/testsuite/{sim => }/frv/srlcc.cgs (100%)
rename sim/testsuite/{sim => }/frv/srli.cgs (100%)
rename sim/testsuite/{sim => }/frv/srlicc.cgs (100%)
rename sim/testsuite/{sim => }/frv/st.cgs (100%)
rename sim/testsuite/{sim => }/frv/stb.cgs (100%)
rename sim/testsuite/{sim => }/frv/stbf.cgs (100%)
rename sim/testsuite/{sim => }/frv/stbfi.cgs (100%)
rename sim/testsuite/{sim => }/frv/stbfu.cgs (100%)
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rename sim/testsuite/{sim => }/ft32/ChangeLog (100%)
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rename sim/testsuite/{sim => }/m32r/bc24.cgs (100%)
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rename sim/testsuite/{sim => }/m32r/beqz.cgs (100%)
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rename sim/testsuite/{sim => }/m32r/hello.ms (100%)
rename sim/testsuite/{sim => }/m32r/hw-trap.ms (100%)
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rename sim/testsuite/{sim => }/m32r/misc.exp (100%)
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rename sim/testsuite/{sim => }/m32r/mvtachi.cgs (100%)
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rename sim/testsuite/{sim => }/m32r/or.cgs (100%)
rename sim/testsuite/{sim => }/m32r/or3.cgs (100%)
rename sim/testsuite/{sim => }/m32r/rac.cgs (100%)
rename sim/testsuite/{sim => }/m32r/rach.cgs (100%)
rename sim/testsuite/{sim => }/m32r/rem.cgs (100%)
rename sim/testsuite/{sim => }/m32r/remu.cgs (100%)
rename sim/testsuite/{sim => }/m32r/rte.cgs (100%)
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rename sim/testsuite/{sim => }/m32r/slli.cgs (100%)
rename sim/testsuite/{sim => }/m32r/sra.cgs (100%)
rename sim/testsuite/{sim => }/m32r/sra3.cgs (100%)
rename sim/testsuite/{sim => }/m32r/srai.cgs (100%)
rename sim/testsuite/{sim => }/m32r/srl.cgs (100%)
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rename sim/testsuite/{sim => }/m32r/srli.cgs (100%)
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rename sim/testsuite/{sim => }/m32r/st-minus.cgs (100%)
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rename sim/testsuite/{sim => }/m32r/subv.cgs (100%)
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rename sim/testsuite/{sim => }/m32r/testutils.inc (100%)
rename sim/testsuite/{sim => }/m32r/trap.cgs (100%)
rename sim/testsuite/{sim => }/m32r/unlock.cgs (100%)
rename sim/testsuite/{sim => }/m32r/uread16.ms (100%)
rename sim/testsuite/{sim => }/m32r/uread32.ms (100%)
rename sim/testsuite/{sim => }/m32r/uwrite16.ms (100%)
rename sim/testsuite/{sim => }/m32r/uwrite32.ms (100%)
rename sim/testsuite/{sim => }/m32r/xor.cgs (100%)
rename sim/testsuite/{sim => }/m32r/xor3.cgs (100%)
rename sim/testsuite/{sim => }/m68hc11/ChangeLog (100%)
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rename sim/testsuite/{sim => }/m68hc11/pass.s (100%)
rename sim/testsuite/{sim => }/m68hc11/testutils.inc (100%)
rename sim/testsuite/{sim => }/mcore/ChangeLog (100%)
rename sim/testsuite/{sim => }/mcore/allinsn.exp (100%)
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rename sim/testsuite/{sim => }/mcore/pass.s (100%)
rename sim/testsuite/{sim => }/mcore/testutils.inc (100%)
rename sim/testsuite/{sim => }/microblaze/ChangeLog (100%)
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rename sim/testsuite/{sim => }/microblaze/pass.s (100%)
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rename sim/testsuite/{sim => }/mips/ChangeLog (100%)
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rename sim/testsuite/{sim => }/mips/fpu64-ps-sb1.s (100%)
rename sim/testsuite/{sim => }/mips/fpu64-ps.s (100%)
rename sim/testsuite/{sim => }/mips/hilo-hazard-1.s (100%)
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rename sim/testsuite/{sim => }/mips/mips32-dsp.s (100%)
rename sim/testsuite/{sim => }/mips/mips32-dsp2.s (100%)
rename sim/testsuite/{sim => }/mips/sanity.s (100%)
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rename sim/testsuite/{sim => }/mips/utils-dsp.inc (100%)
rename sim/testsuite/{sim => }/mips/utils-fpu.inc (100%)
rename sim/testsuite/{sim => }/mips/utils-mdmx.inc (100%)
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rename sim/testsuite/{sim => }/mn10300/ChangeLog (100%)
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rename sim/testsuite/{sim => }/mn10300/pass.s (100%)
rename sim/testsuite/{sim => }/mn10300/testutils.inc (100%)
rename sim/testsuite/{sim => }/moxie/ChangeLog (100%)
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rename sim/testsuite/{sim => }/moxie/pass.s (100%)
rename sim/testsuite/{sim => }/moxie/testutils.inc (100%)
rename sim/testsuite/{sim => }/msp430/ChangeLog (100%)
rename sim/testsuite/{sim => }/msp430/add.s (100%)
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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-Os updated (cba5cc34 -> 8a5dac06)
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01-reset_artifacts/console.log | 215 +-
02-prepare_abe/console.log | 238 +-
03-build_abe-binutils/console.log | 11625 +--
04-build_abe-stage1/console.log | 16522 ++--
05-build_abe-linux/console.log | 1998 +-
06-build_abe-glibc/console.log | 39997 ++++-----
07-build_abe-stage2/console.log | 33448 ++++----
08-build_llvm-true/console.log | 13721 ++--
10-benchmark--Os/benchmark-start.log | 2 +-
10-benchmark--Os/benchmark.log | 13 +-
10-benchmark--Os/console.log | 188 +-
11-check_regression/console.log | 2513 +-
11-check_regression/results-0.csv | 2276 +-
11-check_regression/results-1.csv | 2270 +-
11-check_regression/results-brief.csv | 38 +-
11-check_regression/results-compare.csv | 7 +-
11-check_regression/results-full.csv | 2408 +-
11-check_regression/results.csv | 163 +-
11-check_regression/results.log | 2598 +-
12-update_baseline/console.log | 5334 +-
12-update_baseline/results-1.csv | 2270 +-
12-update_baseline/results-brief.csv | 38 +-
12-update_baseline/results-compare.csv | 7 +-
12-update_baseline/results-full.csv | 2270 +-
12-update_baseline/results.csv | 161 +-
12-update_baseline/results.log | 1974 +-
console.log | 125799 +++++++++++++++--------------
jenkins/manifest.sh | 30 +-
results | 2 +-
results_id | 2 +-
30 files changed, 135522 insertions(+), 132605 deletions(-)
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[binutils-gdb] branch master updated (02baa133856 -> f89f33e57c6)
by gitīŧ git.linaro.org
This is an automated email from the git hooks/post-receive script.
unknown user pushed a change to branch master
in repository binutils-gdb.
from 02baa133856 gdb/testsuite: remove actual addresses from some test names
new 4cfcd3b3339 sim: common: modernize gennltvals.sh
new 5e25901fcc5 sim: common: delete configure & Makefile
new f89f33e57c6 sim: common: simplify version script
The 3 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
sim/ChangeLog | 15 +
sim/Makefile.in | 14 +
sim/README-HACKING | 6 +-
sim/common/ChangeLog | 10 +
sim/common/Make-common.in | 5 +-
sim/common/Makefile.in | 135 --
sim/common/configure | 3718 ------------------------------------------
sim/common/configure.ac | 34 -
sim/common/create-version.sh | 17 +-
sim/common/gennltvals.sh | 321 ++--
sim/common/gentvals.sh | 74 -
sim/common/nltvals.def | 7 +
sim/configure | 179 +-
sim/configure.ac | 1 +
14 files changed, 466 insertions(+), 4070 deletions(-)
delete mode 100644 sim/common/Makefile.in
delete mode 100755 sim/common/configure
delete mode 100644 sim/common/configure.ac
delete mode 100755 sim/common/gentvals.sh
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[toolchain/ci/qemu] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig updated (825a215c00 -> e43d564fa3)
by gitīŧ git.linaro.org
This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig
in repository toolchain/ci/qemu.
from 825a215c00 Merge remote-tracking branch 'remotes/kraxel/tags/audio-2021 [...]
adds 5d593bdf10 pci/shpc: don't push attention button when ejecting powered- [...]
adds 6da32fe5ef vhost-user-fs: add the "bootindex" property
adds 6f9ec653f3 acpi: Allow DSDT acpi table changes
adds 4c4465ff1c acpi: Fix unmatched expected DSDT.pxb file
adds e41ee85528 acpi: Add addr offset in build_crs
adds 0cf8882fd0 acpi/gpex: Inform os to keep firmware resource map
adds aee519c210 acpi/gpex: Exclude pxb's resources from PCI0
adds cc9346e4a9 Kconfig: Compile PXB for ARM_VIRT
adds f698a88a77 acpi: Enable pxb unit-test for ARM virt machine
adds ccee1a8140 acpi: Update _DSM method in expected files
adds e0cbcf1eea Merge remote-tracking branch 'remotes/mst/tags/for_upstream' [...]
new 1695854b37 hw/block: m25p80: Don't write to flash if write is disabled
new 465ef47abe hw/block: m25p80: Implement AAI-WP command support for SST flashes
new edf647864b gdb: riscv: Add target description
new 1a475d39ef RISC-V: Place DTB at 3GB boundary instead of 4GB
new d102f19a20 target/riscv/pmp: Raise exception if no PMP entry is configured
new 1eaada8ae1 hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type
new 29b5fe0dcd hw/misc/sifive_u_otp: handling the fails of blk_pread and bl [...]
new 56118ee88d target/riscv: Make csr_ops[CSR_TABLE_SIZE] external
new 8ceac5dc3d target/riscv: Add CSR name in the CSR function table
new b93777e1b4 target/riscv: Generate the GDB XML file for CSR registers dy [...]
new 138ca49a82 target/riscv: Remove built-in GDB XML files for CSRs
new a8259b5323 riscv: Pass RISCVHartArrayState by pointer
new 20b8016ed8 Merge remote-tracking branch 'remotes/alistair/tags/pull-ris [...]
new 8714e811a5 tests/docker: Remove Debian 9 remnant lines
new b8a322549b Makefile: add GNU global tags support
new 977cb99a15 shippable.yml: Remove jobs duplicated on Gitlab-CI
new e405a3ebf5 Add newline when generating Dockerfile
new f2c78150c3 Makefile: wrap ctags in quiet-command calls
new af5d5762f3 Makefile: wrap etags in quiet-command calls
new 3e6c147535 Makefile: wrap cscope in quiet-command calls
new ec9d7c38ec docker: expand debian-amd64 image to include tag tools
new a8a3abe0b3 gitlab: move docs and tools build across from Travis
new 228e3ec4e2 Fix build with new yank feature by adding stubs
new 22250a6ecd gitlab: migrate the minimal tools and unit tests from Travis
new 9e5acb373d scripts/checkpatch.pl: fix git-show invocation to include diffstat
new 5662ab11f6 test/guest-debug: echo QEMU command as well
new b1863ccc95 configure: gate our use of GDB to 8.3.1 or above
new 9559150e86 Revert "tests/tcg/multiarch/Makefile.target: Disable run-gdb [...]
new c00506aa26 gdbstub: implement a softmmu based test
new 51c623b0de gdbstub: add support to Xfer:auxv:read: packet
new ad9dcb207b gdbstub: drop CPUEnv from gdb_exit()
new 5ef0317f58 gdbstub: drop gdbserver_cleanup in favour of gdb_exit
new b9e10c6c75 gdbstub: ensure we clean-up when terminated
new 797920b952 target/arm: use official org.gnu.gdb.aarch64.sve layout for [...]
new 56b5170c87 semihosting: Move ARM semihosting code to shared directories
new 0bb446d8b0 semihosting: Change common-semi API to be architecture-independent
new 3c37cfe0b1 semihosting: Change internal common-semi interfaces to use C [...]
new 095f8c0293 semihosting: Support SYS_HEAPINFO when env->boot_info is not set
new a10b9d93ec riscv: Add semihosting support
new 6b80cb25b4 riscv: Add semihosting support for user mode
new 4d834039c2 semihosting: Implement SYS_ELAPSED and SYS_TICKFREQ
new 27e3b109d1 semihosting: Implement SYS_TMPNAM
new 767ba049b8 semihosting: Implement SYS_ISERROR
new 8814b1327c Merge remote-tracking branch 'remotes/stsquad/tags/pull-test [...]
new a82185880e hw/virtio-pci: Replace error_report() by qemu_log_mask(GUEST_ERROR)
new b026d4a6e6 pl031: Use timer_free() in the finalize function to avoid memleaks
new 3d64fdde67 misc/mos6522: Use timer_free() in the finalize function to a [...]
new 580e733321 hw/ide/ahci: Replace fprintf() by qemu_log_mask(GUEST_ERROR)
new e43d564fa3 Merge remote-tracking branch 'remotes/vivier2/tags/trivial-b [...]
The 49 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
.gitignore | 3 +
.gitlab-ci.yml | 30 +-
.shippable.yml | 14 +-
.travis.yml | 25 -
MAINTAINERS | 2 +
Makefile | 46 +-
bsd-user/syscall.c | 6 +-
configure | 7 +-
default-configs/devices/arm-softmmu.mak | 1 +
default-configs/devices/riscv32-softmmu.mak | 2 +
default-configs/devices/riscv64-softmmu.mak | 2 +
default-configs/targets/aarch64-linux-user.mak | 1 +
default-configs/targets/aarch64_be-linux-user.mak | 1 +
default-configs/targets/arm-linux-user.mak | 1 +
default-configs/targets/armeb-linux-user.mak | 1 +
default-configs/targets/riscv32-linux-user.mak | 3 +-
default-configs/targets/riscv32-softmmu.mak | 2 +-
default-configs/targets/riscv64-linux-user.mak | 3 +-
default-configs/targets/riscv64-softmmu.mak | 2 +-
gdb-xml/riscv-32bit-csr.xml | 250 ----------
gdb-xml/riscv-64bit-csr.xml | 250 ----------
gdbstub.c | 65 ++-
hw/acpi/aml-build.c | 18 +-
hw/block/m25p80.c | 74 +++
hw/i386/acpi-build.c | 3 +-
hw/ide/ahci.c | 8 +-
hw/misc/mos6522.c | 9 +
hw/misc/sifive_u_otp.c | 31 +-
hw/pci-bridge/Kconfig | 2 +-
hw/pci-host/gpex-acpi.c | 87 +++-
hw/pci/shpc.c | 4 +-
hw/riscv/boot.c | 18 +-
hw/riscv/sifive_u.c | 16 +-
hw/riscv/spike.c | 8 +-
hw/riscv/virt.c | 8 +-
hw/rtc/pl031.c | 8 +
hw/semihosting/Kconfig | 4 +
.../arm-semi.c => hw/semihosting/arm-compat-semi.c | 525 ++++++++++++++-------
hw/semihosting/common-semi.h | 39 ++
hw/semihosting/meson.build | 3 +
hw/virtio/vhost-user-fs-pci.c | 2 +
hw/virtio/vhost-user-fs.c | 10 +
hw/virtio/virtio-pci.c | 6 +-
include/exec/gdbstub.h | 14 +-
include/hw/acpi/aml-build.h | 4 +-
include/hw/riscv/boot.h | 6 +-
include/hw/virtio/vhost-user-fs.h | 1 +
include/qemu/timer.h | 2 +
linux-user/aarch64/cpu_loop.c | 3 +-
linux-user/arm/cpu_loop.c | 3 +-
linux-user/arm/meson.build | 3 -
linux-user/exit.c | 2 +-
linux-user/meson.build | 1 +
linux-user/qemu.h | 4 +-
linux-user/riscv/cpu_loop.c | 5 +
linux-user/{arm => }/semihost.c | 8 +-
qemu-options.hx | 10 +-
scripts/checkpatch.pl | 2 +-
softmmu/runstate.c | 2 +-
stubs/meson.build | 1 +
stubs/yank.c | 29 ++
target/arm/cpu.h | 8 -
target/arm/gdbstub.c | 75 ++-
target/arm/helper.c | 7 +-
target/arm/m_helper.c | 7 +-
target/arm/meson.build | 2 -
target/m68k/m68k-semi.c | 2 +-
target/nios2/nios2-semi.c | 2 +-
target/riscv/cpu.c | 25 +
target/riscv/cpu.h | 11 +
target/riscv/cpu_bits.h | 1 +
target/riscv/cpu_helper.c | 10 +
target/riscv/csr.c | 342 ++++++++++----
target/riscv/gdbstub.c | 308 ++----------
target/riscv/insn_trans/trans_privileged.c.inc | 37 +-
target/riscv/op_helper.c | 5 +
target/riscv/pmp.c | 4 +-
target/riscv/pmp.h | 1 +
target/riscv/translate.c | 11 +
tests/data/acpi/microvm/DSDT.pcie | Bin 3023 -> 3031 bytes
tests/data/acpi/virt/DSDT | Bin 5196 -> 5204 bytes
tests/data/acpi/virt/DSDT.memhp | Bin 6557 -> 6565 bytes
tests/data/acpi/virt/DSDT.numamem | Bin 5196 -> 5204 bytes
tests/data/acpi/virt/DSDT.pxb | Bin 7802 -> 7689 bytes
tests/docker/Makefile.include | 1 -
tests/docker/docker.py | 4 +-
tests/docker/dockerfiles/debian-amd64.docker | 5 +-
tests/guest-debug/run-test.py | 35 +-
tests/qtest/bios-tables-test.c | 4 -
tests/tcg/aarch64/Makefile.softmmu-target | 1 +
tests/tcg/aarch64/gdbstub/test-sve-ioctl.py | 11 +
tests/tcg/aarch64/system/boot.S | 1 +
tests/tcg/i386/Makefile.softmmu-target | 1 +
tests/tcg/i386/system/boot.S | 2 +-
tests/tcg/multiarch/Makefile.target | 13 +-
tests/tcg/multiarch/gdbstub/memory.py | 130 +++++
.../tcg/multiarch/gdbstub/test-qxfer-auxv-read.py | 57 +++
tests/tcg/multiarch/system/Makefile.softmmu-target | 19 +-
tests/tcg/x86_64/Makefile.softmmu-target | 1 +
tests/tcg/x86_64/system/boot.S | 2 +-
util/qemu-timer-common.c | 4 +
101 files changed, 1565 insertions(+), 1284 deletions(-)
delete mode 100644 gdb-xml/riscv-32bit-csr.xml
delete mode 100644 gdb-xml/riscv-64bit-csr.xml
rename target/arm/arm-semi.c => hw/semihosting/arm-compat-semi.c (66%)
create mode 100644 hw/semihosting/common-semi.h
rename linux-user/{arm => }/semihost.c (89%)
create mode 100644 stubs/yank.c
create mode 100644 tests/tcg/multiarch/gdbstub/memory.py
create mode 100644 tests/tcg/multiarch/gdbstub/test-qxfer-auxv-read.py
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[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig updated (a62f1b913cec -> aab255cd87bd)
by gitīŧ git.linaro.org
This is an automated email from the git hooks/post-receive script.
tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig
in repository toolchain/ci/linux.
from a62f1b913cec Merge v5.10.7
adds bca9ca5a603f powerpc/32s: Fix RTAS machine check with VMAP stack
adds 1d5e50da5cc7 io_uring: synchronise IOPOLL on task_submit fail
adds bc924dd21ecf io_uring: limit {io|sq}poll submit locking scope
adds 85e25e2370a2 io_uring: patch up IOPOLL overflow_flush sync
adds 85bbe2e64ab4 RDMA/hns: Avoid filling sl in high 3 bits of vlan_id
adds 9d7751a39a19 iommu/arm-smmu-qcom: Initialize SCTLR of the bypass context
adds 51495b719515 drm/panfrost: Don't corrupt the queue mutex on open/close
adds 458b40598dc0 io_uring: Fix return value from alloc_fixed_file_ref_node
adds e28ace868c1e scsi: ufs: Fix -Wsometimes-uninitialized warning
adds 87738164592f btrfs: skip unnecessary searches for xattrs when logging an inode
adds 17243f73ad74 btrfs: fix deadlock when cloning inline extent and low on [...]
adds e3b5252b5cdb btrfs: shrink delalloc pages instead of full inodes
adds b044a949a5c5 net: cdc_ncm: correct overhead in delayed_ndp_size
adds 799d8080f903 net: hns3: fix incorrect handling of sctp6 rss tuple
adds ed59d391ee5e net: hns3: fix the number of queues actually used by ARQ
adds 8d12c062ca99 net: hns3: fix a phy loopback fail issue
adds 413a79ccb98e net: stmmac: dwmac-sun8i: Fix probe error handling
adds 22e1ed2abc66 net: stmmac: dwmac-sun8i: Balance internal PHY resource re [...]
adds 35526a9c46b4 net: stmmac: dwmac-sun8i: Balance internal PHY power
adds 60de77165d0b net: stmmac: dwmac-sun8i: Balance syscon (de)initialization
adds 9591f32a630f net: vlan: avoid leaks on register_vlan_dev() failures
adds 2a432be9ba44 net/sonic: Fix some resource leaks in error handling paths
adds 210b9cdb3d5b net: bareudp: add missing error handling for bareudp_link_ [...]
adds 6d233d9501af ptp: ptp_ines: prevent build when HAS_IOMEM is not set
adds 69363e37d470 net: ipv6: fib: flush exceptions when purging route
adds 541c22aad368 tools: selftests: add test for changing routes with PTMU e [...]
adds d5fc41ebe260 net: fix pmtu check in nopmtudisc mode
adds b0ff6d00edac net: ip: always refragment ip defragmented packets
adds 694635a7b8cb chtls: Fix hardware tid leak
adds 2702758d42a4 chtls: Remove invalid set_tcb call
adds 523cea39aab2 chtls: Fix panic when route to peer not configured
adds d9297487df15 chtls: Avoid unnecessary freeing of oreq pointer
adds 5a1af38e06b6 chtls: Replace skb_dequeue with skb_peek
adds 23e696e2f382 chtls: Added a check to avoid NULL pointer dereference
adds ab8e7a1af3f2 chtls: Fix chtls resources release sequence
adds 2e7635299fbf octeontx2-af: fix memory leak of lmac and lmac->name
adds 6486bc0a3400 nexthop: Fix off-by-one error in error path
adds eaa7a6c39d10 nexthop: Unlink nexthop group entry in error path
adds 5fb8a3116cd0 nexthop: Bounce NHA_GATEWAY in FDB nexthop groups
adds 1214d69a2bfc s390/qeth: fix deadlock during recovery
adds af0c184ea106 s390/qeth: fix locking for discipline setup / removal
adds af9b4ab6ee6d s390/qeth: fix L2 header access in qeth_l3_osa_features_check()
adds d6d3f9de7a06 net: dsa: lantiq_gswip: Exclude RMII from modes that report 1 GbE
adds 39e86d3ca489 net/mlx5: Use port_num 1 instead of 0 when delete a RoCE address
adds dd7cce96dd37 net/mlx5e: ethtool, Fix restriction of autoneg with 56G
adds 1e5b0a2300bb net/mlx5e: In skb build skip setting mark in switchdev mode
adds 8543acf02563 net/mlx5: Check if lag is supported before creating one
adds 6aebfdacad97 scsi: lpfc: Fix variable 'vport' set but not used in lpfc_ [...]
adds bca9046c36d3 ionic: start queues before announcing link up
adds 797c128d3c7d HID: wacom: Fix memory leakage caused by kfifo_alloc
adds 797335659e58 fanotify: Fix sys_fanotify_mark() on native x86-32
adds 0a27398d8969 ARM: OMAP2+: omap_device: fix idling of devices during probe
adds 75dfd242b46a i2c: sprd: use a specific timeout to avoid system hang up issue
adds e095ac6bc3ea dmaengine: dw-edma: Fix use after free in dw_edma_alloc_chunk()
adds 4abc2dbd8822 selftests/bpf: Clarify build error if no vmlinux
adds 9b990788d84d can: tcan4x5x: fix bittiming const, use common bittiming f [...]
adds 9fc286ed3926 can: m_can: m_can_class_unregister(): remove erroneous m_c [...]
adds 175465cb6d87 can: kvaser_pciefd: select CONFIG_CRC32
adds a885713b0c03 spi: spi-geni-qcom: Fail new xfers if xfer/cancel/abort pending
adds 932e130e3dc8 cpufreq: powernow-k8: pass policy rather than use cpufreq_ [...]
adds c75a66726d7e spi: spi-geni-qcom: Fix geni_spi_isr() NULL dereference in [...]
adds 7a30d664c949 spi: stm32: FIFO threshold level - fix align packet size
adds d908dd5c1064 i2c: i801: Fix the i2c-mux gpiod_lookup_table not being pr [...]
adds 8f243682e5ed i2c: mediatek: Fix apdma and i2c hand-shake timeout
adds e5689d84ebd8 bcache: set bcache device into read-only mode for BCH_FEAT [...]
adds 6a0e580ded88 interconnect: imx: Add a missing of_node_put after of_devi [...]
adds fcd04aa9b52c interconnect: qcom: fix rpmh link failures
adds ceb97fbe4816 dmaengine: mediatek: mtk-hsdma: Fix a resource leak in the [...]
adds 41f95d84fcf5 dmaengine: milbeaut-xdmac: Fix a resource leak in the erro [...]
adds e72371fab4ea dmaengine: xilinx_dma: check dma_async_device_register ret [...]
adds c16e7cfc1baf dmaengine: xilinx_dma: fix incompatible param warning in _ [...]
adds d4a7eb9fbfcc dmaengine: xilinx_dma: fix mixed_enum_type coverity warning
adds 41dcfc0cb955 arm64: mm: Fix ARCH_LOW_ADDRESS_LIMIT when !CONFIG_ZONE_DMA
adds f03e2257df3c qed: select CONFIG_CRC32
adds e208085c82f7 phy: dp83640: select CONFIG_CRC32
adds 0d813da1bde0 wil6210: select CONFIG_CRC32
adds 432071f6af70 block: rsxx: select CONFIG_CRC32
adds 771865dc5a6e lightnvm: select CONFIG_CRC32
adds 2bbe923d7a84 zonefs: select CONFIG_CRC32
adds 39b3204e54c1 iommu/vt-d: Fix misuse of ALIGN in qi_flush_piotlb()
adds 2a21faa9c596 iommu/intel: Fix memleak in intel_irq_remapping_alloc
adds 31a3520409ff bpftool: Fix compilation failure for net.o with older glibc
adds b23accd11a89 nvme-tcp: Fix possible race of io_work and direct send
adds 699804e07641 net/mlx5e: Fix memleak in mlx5e_create_l2_table_groups
adds 6defee43fe54 net/mlx5e: Fix two double free cases
adds c9698380b01a regmap: debugfs: Fix a memory leak when calling regmap_attach_dev
adds 344f59a93151 wan: ds26522: select CONFIG_BITREVERSE
adds ae4db0bc5cde arm64: cpufeature: remove non-exist CONFIG_KVM_ARM_HOST
adds 734bd3f8256b regulator: qcom-rpmh-regulator: correct hfsmps515 definition
adds e7f0992529b2 net: mvpp2: disable force link UP during port init procedure
adds 729319e4f177 drm/i915/dp: Track pm_qos per connector
adds e336a772cdcb net: mvneta: fix error message when MTU too large for XDP
adds c5c22948f235 selftests: fib_nexthops: Fix wrong mausezahn invocation
adds 610e2c5699f8 KVM: arm64: Don't access PMCR_EL0 when no PMU is available
adds 9ad0375ed292 xsk: Fix race in SKB mode transmit with shared cq
adds be665727363f xsk: Rollback reservation at NETDEV_TX_BUSY
adds 6f7a362e1c6f block/rnbd-clt: avoid module unload race with close confirmation
adds 61e8c02ae6d6 can: isotp: isotp_getname(): fix kernel information leak
adds 481097d66174 block: fix use-after-free in disk_part_iter_next
adds 43f6ea41408b net: drop bogus skb with CHECKSUM_PARTIAL and offset beyon [...]
adds 75e5e51acf59 regmap: debugfs: Fix a reversed if statement in regmap_deb [...]
adds 27c6968cfb76 drm/panfrost: Remove unused variables in panfrost_job_close()
adds b77681d400f4 tools headers UAPI: Sync linux/fscrypt.h with the kernel sources
adds 7a1519a74f3d Linux 5.10.8
adds aab255cd87bd Merge v5.10.8
No new revisions were added by this update.
Summary of changes:
Makefile | 2 +-
arch/Kconfig | 6 +
arch/arm/mach-omap2/omap_device.c | 8 +-
arch/arm64/include/asm/processor.h | 3 +-
arch/arm64/kernel/cpufeature.c | 2 +-
arch/arm64/kvm/sys_regs.c | 4 +
arch/arm64/mm/init.c | 2 +-
arch/powerpc/kernel/head_book3s_32.S | 9 ++
arch/x86/Kconfig | 1 +
block/genhd.c | 9 +-
drivers/base/regmap/regmap-debugfs.c | 9 +-
drivers/block/Kconfig | 1 +
drivers/block/rnbd/rnbd-clt.c | 3 +-
drivers/cpufreq/powernow-k8.c | 9 +-
drivers/dma/dw-edma/dw-edma-core.c | 4 +-
drivers/dma/mediatek/mtk-hsdma.c | 1 +
drivers/dma/milbeaut-xdmac.c | 4 +-
drivers/dma/xilinx/xilinx_dma.c | 11 +-
drivers/gpu/drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/display/intel_dp.c | 8 +-
drivers/gpu/drm/i915/i915_drv.c | 5 -
drivers/gpu/drm/i915/i915_drv.h | 3 -
drivers/gpu/drm/panfrost/panfrost_job.c | 13 +--
drivers/hid/wacom_sys.c | 35 +++++-
drivers/i2c/busses/i2c-i801.c | 2 +-
drivers/i2c/busses/i2c-mt65xx.c | 27 ++++-
drivers/i2c/busses/i2c-sprd.c | 8 +-
drivers/infiniband/hw/hns/hns_roce_ah.c | 11 +-
drivers/interconnect/imx/imx.c | 1 +
drivers/interconnect/qcom/Kconfig | 23 ++--
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 2 +
drivers/iommu/intel/dmar.c | 4 +-
drivers/iommu/intel/irq_remapping.c | 2 +
drivers/lightnvm/Kconfig | 1 +
drivers/md/bcache/super.c | 15 +++
drivers/net/bareudp.c | 22 ++--
drivers/net/can/Kconfig | 1 +
drivers/net/can/m_can/m_can.c | 2 -
drivers/net/can/m_can/tcan4x5x.c | 26 -----
drivers/net/dsa/lantiq_gswip.c | 7 +-
.../chelsio/inline_crypto/chtls/chtls_cm.c | 71 ++++--------
drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h | 4 +-
.../ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 9 +-
.../ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 2 +
.../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 9 +-
.../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h | 2 +
drivers/net/ethernet/marvell/mvneta.c | 2 +-
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 14 ++-
drivers/net/ethernet/marvell/octeontx2/af/cgx.c | 14 ++-
.../net/ethernet/mellanox/mlx5/core/en/rep/tc.c | 5 +
.../net/ethernet/mellanox/mlx5/core/en_ethtool.c | 24 +++-
drivers/net/ethernet/mellanox/mlx5/core/en_fs.c | 3 +
drivers/net/ethernet/mellanox/mlx5/core/lag.c | 11 +-
drivers/net/ethernet/mellanox/mlx5/core/rdma.c | 2 +-
drivers/net/ethernet/natsemi/macsonic.c | 12 +-
drivers/net/ethernet/natsemi/xtsonic.c | 7 +-
drivers/net/ethernet/pensando/ionic/ionic_lif.c | 12 +-
drivers/net/ethernet/qlogic/Kconfig | 1 +
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 129 +++++++++++++--------
drivers/net/usb/cdc_ncm.c | 8 +-
drivers/net/wan/Kconfig | 1 +
drivers/net/wireless/ath/wil6210/Kconfig | 1 +
drivers/nvme/host/tcp.c | 12 +-
drivers/ptp/Kconfig | 2 +
drivers/regulator/qcom-rpmh-regulator.c | 2 +-
drivers/s390/net/qeth_core.h | 3 +-
drivers/s390/net/qeth_core_main.c | 38 +++---
drivers/s390/net/qeth_l2_main.c | 2 +-
drivers/s390/net/qeth_l3_main.c | 4 +-
drivers/scsi/lpfc/lpfc_sli.c | 2 -
drivers/scsi/ufs/ufshcd.c | 2 +-
drivers/spi/spi-geni-qcom.c | 73 +++++++++++-
drivers/spi/spi-stm32.c | 4 +-
fs/btrfs/btrfs_inode.h | 16 +++
fs/btrfs/ctree.h | 3 +-
fs/btrfs/dev-replace.c | 2 +-
fs/btrfs/inode.c | 69 ++++++++---
fs/btrfs/ioctl.c | 2 +-
fs/btrfs/reflink.c | 15 +++
fs/btrfs/space-info.c | 4 +-
fs/btrfs/tree-log.c | 8 ++
fs/btrfs/xattr.c | 4 +-
fs/io_uring.c | 100 ++++++++--------
fs/notify/fanotify/fanotify_user.c | 17 ++-
fs/zonefs/Kconfig | 1 +
include/linux/syscalls.h | 24 ++++
include/net/xdp_sock.h | 4 -
include/net/xsk_buff_pool.h | 5 +
net/8021q/vlan.c | 3 +-
net/can/isotp.c | 1 +
net/core/skbuff.c | 6 +
net/ipv4/ip_output.c | 2 +-
net/ipv4/ip_tunnel.c | 11 +-
net/ipv4/nexthop.c | 6 +-
net/ipv6/ip6_fib.c | 5 +-
net/xdp/xsk.c | 12 +-
net/xdp/xsk_buff_pool.c | 1 +
net/xdp/xsk_queue.h | 5 +
tools/bpf/bpftool/net.c | 1 -
tools/include/uapi/linux/fscrypt.h | 5 +-
tools/testing/selftests/bpf/Makefile | 3 +
tools/testing/selftests/net/fib_nexthops.sh | 2 +-
tools/testing/selftests/net/pmtu.sh | 71 +++++++++++-
103 files changed, 829 insertions(+), 375 deletions(-)
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[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig updated (e2559c3945a -> 76c1dd15e4a)
by gitīŧ git.linaro.org
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig
in repository toolchain/ci/gcc.
from e2559c3945a match.pd: Optimize ((cst << x) & 1) [PR96669]
adds 7e02426ba0c nios2: Remove custom instruction warnings
adds 42f4e239924 nios2: Add -mcustom-fpu-cfg=fph2
adds 5e5d56919dd RTEMS: Add -mcustom-fpu-cfg=fph2 multilib
adds a6d22fb21c6 openmp: Add support for the OpenMP 5.0 task detach clause
adds a2960a04d51 testsuite: Fix up a testcase to find the right ISO_Fortran_ [...]
adds 59cf67d1cf7 Daily bump.
adds 3804e937b0e Default to DWARF5
adds 0f4c8f517b7 ipa: Adjust cgraph verifier to materialization on demand (P [...]
adds 192105b6a2a Avoid assuming SSA_NAME_IDENTIFIER is nonnull.
adds 56b5d13e278 aix: default to DWARF 4.
adds b654d23a470 testsuite: Skip DWARF 5 testcases on AIX.
adds 4c9bcd5c81a Daily bump.
adds 4905f404018 Fix ChangeLog entries.
adds 994fb69ac1b testsuite: powerpc fold-vec and sse updates.
adds d3b41bde961 libgomp: Don't access gomp_sem_t as int using atomics uncon [...]
adds 0f951b3dd34 RTEMS: Fix libgomp build
new 2e43880dbd4 libstd++: : Add workaround for as Error: file number less t [...]
new a81d2f1e414 libstdc++: Fix narrow char test to use stringbuf not wstringbuf
new 104304cd246 testsuite/97299 - fix test condition of gcc.dg/vect/slp-reduc-3.c
new acdc49fabf0 [arm,testsuite]: Fix options for vceqz_p64.c and vceqzq_p64.c
new b8c3f5196e1 libgomp: enable linux-futex on riscv64
new e393f03b1a7 testsuite/97494 - adjust gcc.dg/vect/slp-11b.c
new ec153f96f89 libstdc++: Only test writing to wostream if supported [PR 98725]
new c7e276b869b analyzer: use "malloc" attribute
new 66cbe54960c Avoid no-stack-protector-attr fails on hppa*-*-*.
new 76c1dd15e4a Skip asm goto tests on hppa*-*-*.
The 10 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
gcc/ChangeLog | 86 +++
gcc/DATESTAMP | 2 +-
gcc/analyzer/analyzer.h | 1 +
gcc/analyzer/diagnostic-manager.cc | 15 +-
gcc/analyzer/region-model-impl-calls.cc | 9 +
gcc/analyzer/region-model.cc | 9 +
gcc/analyzer/region-model.h | 1 +
gcc/analyzer/sm-malloc.cc | 767 +++++++++++++++++----
gcc/attribs.h | 2 +
gcc/builtin-types.def | 8 +-
gcc/builtins.c | 10 +
gcc/c-family/ChangeLog | 10 +
gcc/c-family/c-pragma.h | 3 +-
gcc/c-family/c-pretty-print.c | 27 +-
gcc/c/ChangeLog | 9 +
gcc/c/c-parser.c | 57 +-
gcc/c/c-typeck.c | 58 +-
gcc/cgraph.c | 4 +-
gcc/common.opt | 2 +-
gcc/config/nios2/nios2.c | 51 +-
gcc/config/nios2/t-rtems | 146 +---
gcc/config/rs6000/aix71.h | 3 +
gcc/config/rs6000/aix72.h | 3 +
gcc/cp/ChangeLog | 10 +
gcc/cp/parser.c | 53 +-
gcc/cp/pt.c | 1 +
gcc/cp/semantics.c | 61 +-
gcc/doc/extend.texi | 52 ++
gcc/doc/invoke.texi | 49 +-
gcc/fortran/ChangeLog | 23 +
gcc/fortran/dump-parse-tree.c | 6 +
gcc/fortran/frontend-passes.c | 1 +
gcc/fortran/gfortran.h | 2 +
gcc/fortran/openmp.c | 60 +-
gcc/fortran/trans-openmp.c | 16 +
gcc/fortran/trans-types.c | 3 +
gcc/fortran/types.def | 8 +-
gcc/gimplify.c | 14 +
gcc/omp-builtins.def | 2 +-
gcc/omp-expand.c | 19 +-
gcc/omp-low.c | 47 ++
gcc/testsuite/ChangeLog | 45 +-
gcc/testsuite/c-c++-common/gomp/task-detach-1.c | 37 +
gcc/testsuite/g++.dg/debug/dwarf2/inline-ns-2.C | 1 +
gcc/testsuite/g++.dg/debug/dwarf2/inline-var-2.C | 1 +
gcc/testsuite/g++.dg/debug/dwarf2/inline-var-3.C | 1 +
gcc/testsuite/g++.dg/debug/dwarf2/lang-cpp11.C | 1 +
gcc/testsuite/g++.dg/debug/dwarf2/lang-cpp14.C | 1 +
gcc/testsuite/g++.dg/debug/dwarf2/lang-cpp17.C | 1 +
gcc/testsuite/g++.dg/debug/dwarf2/lang-cpp20.C | 1 +
gcc/testsuite/g++.dg/gomp/task-detach-1.C | 29 +
gcc/testsuite/g++.dg/no-stack-protector-attr-3.C | 2 +-
gcc/testsuite/g++.dg/no-stack-protector-attr.C | 2 +-
gcc/testsuite/gcc.c-torture/compile/asmgoto-2.c | 1 +
gcc/testsuite/gcc.c-torture/compile/asmgoto-5.c | 1 +
gcc/testsuite/gcc.dg/analyzer/attr-malloc-1.c | 75 ++
gcc/testsuite/gcc.dg/analyzer/attr-malloc-2.c | 24 +
gcc/testsuite/gcc.dg/analyzer/attr-malloc-4.c | 21 +
gcc/testsuite/gcc.dg/analyzer/attr-malloc-5.c | 12 +
gcc/testsuite/gcc.dg/analyzer/attr-malloc-6.c | 228 ++++++
.../analyzer/attr-malloc-CVE-2019-19078-usb-leak.c | 224 ++++++
.../gcc.dg/analyzer/attr-malloc-misuses.c | 18 +
gcc/testsuite/gcc.dg/debug/dwarf2/inline6.c | 3 +-
gcc/testsuite/gcc.dg/debug/dwarf2/lang-c11.c | 1 +
gcc/testsuite/gcc.dg/debug/dwarf2/pr41445-7.c | 1 +
gcc/testsuite/gcc.dg/debug/dwarf2/pr41445-8.c | 1 +
gcc/testsuite/gcc.dg/gomp/task-detach-1.c | 20 +
gcc/testsuite/gcc.dg/ipa/pr98222.c | 19 +
gcc/testsuite/gcc.dg/vect/slp-11b.c | 12 +-
gcc/testsuite/gcc.dg/vect/slp-reduc-3.c | 3 +-
gcc/testsuite/gcc.target/arm/simd/vceqz_p64.c | 3 +-
gcc/testsuite/gcc.target/arm/simd/vceqzq_p64.c | 3 +-
.../gcc.target/powerpc/fold-vec-extract-char.p7.c | 2 +-
.../powerpc/fold-vec-extract-double.p7.c | 3 +-
.../gcc.target/powerpc/fold-vec-extract-float.p7.c | 3 +-
.../gcc.target/powerpc/fold-vec-extract-float.p8.c | 2 +-
.../gcc.target/powerpc/fold-vec-extract-int.p7.c | 3 +-
.../gcc.target/powerpc/fold-vec-extract-int.p8.c | 2 +-
.../gcc.target/powerpc/fold-vec-extract-short.p7.c | 3 +-
.../gcc.target/powerpc/fold-vec-extract-short.p8.c | 2 +-
gcc/testsuite/gcc.target/powerpc/sse-andnps-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/sse-movhps-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/sse-movlps-1.c | 2 +-
gcc/testsuite/gcc.target/powerpc/sse2-andnpd-1.c | 2 +-
gcc/testsuite/gfortran.dg/gomp/task-detach-1.f90 | 29 +
.../iso_fortran_binding_uint8_array_driver.c | 2 +-
gcc/tree-core.h | 29 +-
gcc/tree-nested.c | 2 +
gcc/tree-pretty-print.c | 6 +
gcc/tree.c | 15 +-
include/ChangeLog | 4 +
include/gomp-constants.h | 1 +
libgfortran/ChangeLog | 2 +-
libgomp/ChangeLog | 45 ++
libgomp/config/accel/sem.h | 9 +
libgomp/config/linux/sem.h | 9 +
libgomp/config/posix/sem.c | 20 +
libgomp/config/posix/sem.h | 10 +
libgomp/config/rtems/sem.h | 5 +
libgomp/configure.tgt | 4 +
libgomp/fortran.c | 6 +
libgomp/libgomp.h | 7 +
libgomp/libgomp.map | 2 +
libgomp/libgomp_g.h | 2 +-
libgomp/omp.h.in | 7 +
libgomp/omp_lib.f90.in | 9 +
libgomp/omp_lib.h.in | 4 +
libgomp/priority_queue.c | 57 ++
libgomp/priority_queue.h | 5 +
libgomp/task.c | 132 +++-
libgomp/team.c | 4 +
.../testsuite/libgomp.c-c++-common/task-detach-1.c | 36 +
.../testsuite/libgomp.c-c++-common/task-detach-2.c | 37 +
.../testsuite/libgomp.c-c++-common/task-detach-3.c | 33 +
.../testsuite/libgomp.c-c++-common/task-detach-4.c | 24 +
.../testsuite/libgomp.c-c++-common/task-detach-5.c | 42 ++
.../testsuite/libgomp.c-c++-common/task-detach-6.c | 46 ++
.../testsuite/libgomp.fortran/task-detach-1.f90 | 33 +
.../testsuite/libgomp.fortran/task-detach-2.f90 | 34 +
.../testsuite/libgomp.fortran/task-detach-3.f90 | 33 +
.../testsuite/libgomp.fortran/task-detach-4.f90 | 22 +
.../testsuite/libgomp.fortran/task-detach-5.f90 | 39 ++
.../testsuite/libgomp.fortran/task-detach-6.f90 | 44 ++
libstdc++-v3/ChangeLog | 5 +
libstdc++-v3/src/c++11/Makefile.am | 4 +-
libstdc++-v3/src/c++11/Makefile.in | 4 +-
.../testsuite/20_util/unique_ptr/io/lwg2948.cc | 2 +
.../27_io/basic_stringstream/cons/char/1.cc | 2 +-
128 files changed, 3000 insertions(+), 397 deletions(-)
create mode 100644 gcc/testsuite/c-c++-common/gomp/task-detach-1.c
create mode 100644 gcc/testsuite/g++.dg/gomp/task-detach-1.C
create mode 100644 gcc/testsuite/gcc.dg/analyzer/attr-malloc-1.c
create mode 100644 gcc/testsuite/gcc.dg/analyzer/attr-malloc-2.c
create mode 100644 gcc/testsuite/gcc.dg/analyzer/attr-malloc-4.c
create mode 100644 gcc/testsuite/gcc.dg/analyzer/attr-malloc-5.c
create mode 100644 gcc/testsuite/gcc.dg/analyzer/attr-malloc-6.c
create mode 100644 gcc/testsuite/gcc.dg/analyzer/attr-malloc-CVE-2019-19078-usb-leak.c
create mode 100644 gcc/testsuite/gcc.dg/analyzer/attr-malloc-misuses.c
create mode 100644 gcc/testsuite/gcc.dg/gomp/task-detach-1.c
create mode 100644 gcc/testsuite/gcc.dg/ipa/pr98222.c
create mode 100644 gcc/testsuite/gfortran.dg/gomp/task-detach-1.f90
create mode 100644 libgomp/testsuite/libgomp.c-c++-common/task-detach-1.c
create mode 100644 libgomp/testsuite/libgomp.c-c++-common/task-detach-2.c
create mode 100644 libgomp/testsuite/libgomp.c-c++-common/task-detach-3.c
create mode 100644 libgomp/testsuite/libgomp.c-c++-common/task-detach-4.c
create mode 100644 libgomp/testsuite/libgomp.c-c++-common/task-detach-5.c
create mode 100644 libgomp/testsuite/libgomp.c-c++-common/task-detach-6.c
create mode 100644 libgomp/testsuite/libgomp.fortran/task-detach-1.f90
create mode 100644 libgomp/testsuite/libgomp.fortran/task-detach-2.f90
create mode 100644 libgomp/testsuite/libgomp.fortran/task-detach-3.f90
create mode 100644 libgomp/testsuite/libgomp.fortran/task-detach-4.f90
create mode 100644 libgomp/testsuite/libgomp.fortran/task-detach-5.f90
create mode 100644 libgomp/testsuite/libgomp.fortran/task-detach-6.f90
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[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig updated (75a933f399 -> 705989f19a)
by gitīŧ git.linaro.org
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig
in repository toolchain/ci/binutils-gdb.
from 75a933f399 ld/elf/x86: Don't compare IFUNC address in the shared object
adds 514fca98df Automatic date update in version.in
adds edf0f284b1 PR binutils/23460: Increase the max number of open files to 20
adds d46153313b Automatic date update in version.in
adds 25294ff049 gold: Remove the circular IFUNC dependency in ifuncmain6pie
adds 994b251328 ld/elf: Ignore section symbols when matching linkonce with comdat
adds 44365e88c0 PR27198, segv in S_IS_WEAK
adds cecb191290 gdb: const-ify unpack_* functions in remote.c
adds e3b2741b16 gdb: const-ify remote_target::add_current_inferior_and_threa [...]
adds b5c8f22d28 gdb: move remote_target::start_remote variable to narrower scope
adds aa2838ccc5 gdb: const-ify hostio methods parameter in remote.c
adds d3d7d1ba3b [gdb/tdep] Handle si_addr_bnd in compat_siginfo_from_siginfo
new 326adec374 PR26378, sections initialised only by linker scripts are alw [...]
new 6a9ad81c44 gdb/riscv: use a single regset supply function for riscv fbs [...]
new 705989f19a as: Automatically enable DWARF5 support
The 3 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.
Summary of changes:
bfd/ChangeLog | 5 +++
bfd/elflink.c | 6 ++-
bfd/version.h | 2 +-
gas/ChangeLog | 20 +++++++++
gas/config/tc-i386.c | 3 ++
gas/dwarf2dbg.c | 24 +++++++---
gas/testsuite/gas/elf/dwarf-5-file0.d | 2 +-
gas/testsuite/gas/i386/i386.exp | 1 +
gas/testsuite/gas/i386/pr27198.d | 2 +
gas/testsuite/gas/i386/pr27198.err | 5 +++
gas/testsuite/gas/i386/pr27198.s | 1 +
gas/testsuite/gas/lns/lns-diag-1.l | 2 -
gdb/ChangeLog | 56 +++++++++++++++++++++++
gdb/nat/amd64-linux-siginfo.c | 13 ++++++
gdb/remote.c | 82 ++++++++++++++++------------------
gdb/riscv-fbsd-tdep.c | 20 +--------
gdb/riscv-linux-tdep.c | 4 +-
gdb/riscv-tdep.c | 50 +++++++++++++++++++++
gdb/riscv-tdep.h | 23 ++++++++++
gold/ChangeLog | 6 +++
gold/testsuite/ifuncmain6pie.c | 14 ++----
gold/testsuite/ifuncmod6.c | 10 ++---
ld/ChangeLog | 21 +++++++++
ld/ldlang.c | 2 +-
ld/testsuite/ld-elf/size-2.d | 2 +-
ld/testsuite/ld-i386/i386.exp | 5 +++
ld/testsuite/ld-i386/pr27193.dd | 5 +++
ld/testsuite/ld-i386/pr27193a.o.bz2 | Bin 0 -> 468 bytes
ld/testsuite/ld-i386/pr27193b.s | 8 ++++
ld/testsuite/ld-plugin/lto.exp | 2 +-
30 files changed, 303 insertions(+), 93 deletions(-)
create mode 100644 gas/testsuite/gas/i386/pr27198.d
create mode 100644 gas/testsuite/gas/i386/pr27198.err
create mode 100644 gas/testsuite/gas/i386/pr27198.s
create mode 100644 ld/testsuite/ld-i386/pr27193.dd
create mode 100644 ld/testsuite/ld-i386/pr27193a.o.bz2
create mode 100644 ld/testsuite/ld-i386/pr27193b.s
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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig updated (b40ea5d0 -> 3b6dc987)
by gitīŧ git.linaro.org
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-allmodconfig
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discards b40ea5d0 2: update: binutils-gcc-linux-qemu: 21061
new 3b6dc987 2: update: binutils-gcc-linux-qemu: 21061
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N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-lt [...]
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Summary of changes:
01-reset_artifacts/console.log | 123 +-
02-prepare_abe/console.log | 432 +-
03-build_abe-binutils/console.log | 11854 +++++----
04-build_abe-stage1/console.log | 20868 ++++++++-------
05-build_linux/console.log | 9630 +++----
08-check_regression/console.log | 2 +-
08-check_regression/results.regressions | 20 +-
09-update_baseline/console.log | 54 +-
09-update_baseline/results.regressions | 20 +-
console.log | 42757 +++++++++++++++---------------
jenkins/manifest.sh | 22 +-
11 files changed, 42884 insertions(+), 42898 deletions(-)
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