Tcwg-commits January 2021

tcwg-commits@lists.linaro.org

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9360 discussions

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_tk1/llvm-release-arm-spec2k6-Os updated (8e4642602b0 -> 26b0c76ef8b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/llvm-release-arm-spec2k6-Os in repository toolchain/ci/gcc. from 8e4642602b0 Daily bump. adds 390ecc23210 Daily bump. adds 403feb626fe libstdc++: Remove accidental -std=gnu++17 from test adds b1dba8a228e libstdc++: improve how pretty printers find node types (PR 91997) adds af0dd3ec611 libstdc++: Fix pretty printers script and tests adds 94a665fcc68 libstdc++: Fix unique_ptr pretty printer for empty classes adds 01f53867189 libstdc++: Fix compatibility support in unique_ptr pretty printer adds 3613228af82 libstdc++: Fix std::any pretty printer [PR 68735] adds 78ba8511aca libstdc++: Only use __builtin_sprintf if supported [PR 96083] adds 49e4535f983 libstdc++: Fix filesystem::path pretty printer test failure adds 00e948106cc libstdc++: Fix misnamed configure option in manual adds cae446efd7c Daily bump. adds 1bf384c36a7 Daily bump. adds 23b1bb7b22a hurd: libgcc unwinding over signal trampolines with SIGINFO adds 0313ce139f4 Hurd: Enable ifunc by default adds 4aeae11db66 libstdc++: Fix clang analyzer suppression [PR 98605] adds f3c2cc8eaa0 Daily bump. adds 0f1e1069a75 [nvptx libgomp plugin] Build only in supported configurations adds 8d491db06a6 libgomp_g.h: Include stdint.h instead of gstdint.h. adds 669f3c7bc02 Daily bump. adds 891c4f6f4d3 Daily bump. adds ed0b8379792 Daily bump. adds 26b0c76ef8b Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 8 + gcc/DATESTAMP | 2 +- gcc/config.gcc | 4 +- libgcc/ChangeLog | 10 ++ libgcc/config/i386/gnu-unwind.h | 60 +++++-- libgomp/ChangeLog | 19 ++ libgomp/configure | 85 +++++---- libgomp/libgomp_g.h | 2 +- libgomp/plugin/configfrag.ac | 91 ++++++---- libgomp/plugin/plugin-nvptx.c | 9 - libstdc++-v3/ChangeLog | 115 ++++++++++++ libstdc++-v3/doc/html/manual/configure.html | 3 +- libstdc++-v3/doc/xml/manual/configure.xml | 3 +- libstdc++-v3/include/ext/throw_allocator.h | 21 +++ libstdc++-v3/include/std/mutex | 8 +- libstdc++-v3/python/libstdcxx/v6/printers.py | 196 +++++++++++++++------ .../filesystem/filesystem_error/cons.cc | 2 +- .../testsuite/libstdc++-prettyprinters/59161.cc | 2 - .../testsuite/libstdc++-prettyprinters/80276.cc | 3 + .../testsuite/libstdc++-prettyprinters/91997.cc | 53 ++++++ .../testsuite/libstdc++-prettyprinters/compat.cc | 28 ++- .../testsuite/libstdc++-prettyprinters/cxx11.cc | 20 +++ .../libstdc++-prettyprinters/filesystem-ts.cc | 39 ++++ 23 files changed, 619 insertions(+), 164 deletions(-) create mode 100644 libstdc++-v3/testsuite/libstdc++-prettyprinters/91997.cc create mode 100644 libstdc++-v3/testsuite/libstdc++-prettyprinters/filesystem-ts.cc -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_tk1/llvm-release-arm-spec2k6-Os updated (0aca14de -> 9d938ec1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/llvm-release-arm-spec2k6-Os in repository toolchain/ci/base-artifacts. discards 0aca14de 1: update: binutils-gcc-glibc-llvm: 1 new 9d938ec1 1: update: binutils-gcc-glibc-llvm: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (0aca14de) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk_tk1/llvm-release-arm [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 160 +- 02-prepare_abe/console.log | 204 +- 03-build_abe-binutils/console.log | 11133 +-- 04-build_abe-stage1/console.log | 18046 ++-- 05-build_abe-linux/console.log | 1998 +- 06-build_abe-glibc/console.log | 38308 ++++---- 07-build_abe-stage2/console.log | 38982 ++++---- 08-build_llvm-true/console.log | 12757 +-- 10-benchmark--Os_mthumb/benchmark-start.log | 2 +- 10-benchmark--Os_mthumb/benchmark.log | 13 +- 10-benchmark--Os_mthumb/console.log | 242 +- 11-check_regression/console.log | 2545 +- 11-check_regression/results-0.csv | 2229 +- 11-check_regression/results-1.csv | 2229 +- 11-check_regression/results-brief.csv | 38 +- 11-check_regression/results-compare.csv | 5 +- 11-check_regression/results-full.csv | 2411 +- 11-check_regression/results.csv | 167 +- 11-check_regression/results.log | 2554 +- 12-update_baseline/console.log | 5184 +- 12-update_baseline/results-1.csv | 2229 +- 12-update_baseline/results-brief.csv | 38 +- 12-update_baseline/results-compare.csv | 5 +- 12-update_baseline/results-full.csv | 2229 +- 12-update_baseline/results.csv | 167 +- 12-update_baseline/results.log | 1914 +- console.log | 129643 ++++++++++++------------- jenkins/manifest.sh | 20 +- results_id | 2 +- 29 files changed, 137674 insertions(+), 137780 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/jenkins-scripts] branch tested updated (55fa597a -> f7e8218a)

by tcwg-buildslave

This is an automated email from the git hooks/post-receive script. "tcwg-buildslave pushed a change to branch tested in repository toolchain/jenkins-scripts. from 55fa597a tcwg-dev-build.sh: Fix thinko adds f7e8218a tcwg_kernel-build.sh: Use GNU Binutils for LLVM builds No new revisions were added by this update. Summary of changes: tcwg_kernel-build.sh | 28 +++++++++++++++++----------- 1 file changed, 17 insertions(+), 11 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_ubsan updated (5d201f32885 -> a7c7dd708aa)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_ubsan in repository toolchain/ci/gcc. from 5d201f32885 Daily bump. adds 8f2ed3fe616 Daily bump. adds 05318fb8a89 testsuite: i386: Require ifunc support in gcc.target/i386/p [...] adds a7c7dd708aa Daily bump. No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.target/i386/pr98100.c | 1 + 3 files changed, 6 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_ubsan updated (fea00984 -> 0707ce06)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_ubsan in repository toolchain/ci/base-artifacts. discards fea00984 0: update: gcc-5d201f32885d0fd22db1e61394eceb0915b647af: 1 new 0707ce06 0: update: gcc-a7c7dd708aaa22101cfc1725f4bc676b8e75e990: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (fea00984) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-release-arm-boot [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 128 +- 02-prepare_abe/console.log | 260 +- 04-build_abe-bootstrap_ubsan/console.log | 99230 ++++++++++++++-------------- 05-check_regression/console.log | 6 +- 06-update_baseline/console.log | 6 +- console.log | 99624 ++++++++++++++--------------- jenkins/manifest.sh | 12 +- 7 files changed, 99627 insertions(+), 99639 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-Os_LTO updated (f430293d84 -> 202586f73e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-Os_LTO in repository toolchain/ci/glibc. from f430293d84 posix: consume less entropy on tempname adds 2ef23b5205 x86: Set header.feature_1 in TCB for always-on CET [BZ #27177] adds 86a4d3fa7d elf: work around a gcc bug in elf_get_dynamic_info adds efbbd9c33a ldconfig/x86: Store ISA level in cache and aux cache adds cf12900645 Use the right argument code in unnormal tests adds 7137d682eb ifuncmain6pie: Remove the circular IFUNC dependency [BZ #20019] adds d18f59bf92 Fix x86 build with --enable-tunable=no adds 2d651eb926 x86: Move x86 processor cache info to cpu_features adds cc528f9a7e math/test-tgmath2: Fix fabs failure when no long double adds 86f65dffc2 ld.so: Add --list-tunables to print tunable values adds 96f17e6e63 ARC: nofpu: Regenerate ulps adds f678099de9 Update hppa libm-test-ulps new a031b3abad Update powerpc-nofpu libm-test-ulps. new 07169fcac7 Update arm libm-test-ulps. new 202586f73e Update MIPS libm-test-ulps. The 3 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: NEWS | 4 + elf/Makefile | 13 + elf/cache.c | 39 +- elf/dl-cache.c | 4 + elf/dl-main.h | 2 +- elf/dl-tunables.c | 43 ++ elf/dl-tunables.h | 2 + elf/dl-usage.c | 7 +- elf/get-dynamic-info.h | 41 +- elf/ifuncmain6pie.c | 14 +- elf/ifuncmod6.c | 8 +- elf/ldconfig.c | 18 +- elf/readelflib.c | 81 +++- elf/readlib.c | 7 +- elf/rtld.c | 19 + elf/tst-glibc-hwcaps-2-cache.c | 45 ++ .../etc/ld.so.conf | 0 .../postclean.req | 0 elf/tst-glibc-hwcaps-2-cache.script | 8 + elf/tst-rtld-list-tunables.exp | 14 + elf/tst-rtld-list-tunables.sh | 34 ++ manual/tunables.texi | 38 ++ math/libm-test-driver.c | 12 +- math/libm-test-fpclassify.inc | 14 +- math/libm-test-isinf.inc | 14 +- math/libm-test-isnan.inc | 14 +- math/libm-test-issignaling.inc | 14 +- math/test-tgmath2.c | 4 +- sysdeps/arc/nofpu/libm-test-ulps | 11 +- sysdeps/arm/libm-test-ulps | 23 +- sysdeps/generic/dl-cache.h | 16 +- sysdeps/generic/dl-isa-level.h | 25 ++ sysdeps/generic/elf-read-prop.h | 34 ++ sysdeps/generic/ldconfig.h | 22 +- sysdeps/hppa/fpu/libm-test-ulps | 23 +- sysdeps/mips/mips32/libm-test-ulps | 23 +- sysdeps/mips/mips64/libm-test-ulps | 23 +- sysdeps/powerpc/nofpu/libm-test-ulps | 33 +- sysdeps/unix/sysv/linux/arm/readelflib.c | 22 +- sysdeps/unix/sysv/linux/ia64/readelflib.c | 22 +- sysdeps/unix/sysv/linux/mips/readelflib.c | 22 +- sysdeps/unix/sysv/linux/powerpc/readelflib.c | 22 +- sysdeps/unix/sysv/linux/riscv/readelflib.c | 22 +- sysdeps/unix/sysv/linux/s390/readelflib.c | 22 +- sysdeps/unix/sysv/linux/sparc/readelflib.c | 22 +- sysdeps/unix/sysv/linux/x86/elf-read-prop.h | 60 +++ sysdeps/unix/sysv/linux/x86/readelflib.c | 23 +- sysdeps/unix/sysv/linux/x86_64/Makefile | 51 +++ .../unix/sysv/linux/x86_64/tst-glibc-hwcaps-2.c | 84 ++++ .../sysv/linux/x86_64/x86-64-isa-level-VALUE.c | 4 + sysdeps/x86/Makefile | 6 + sysdeps/x86/cacheinfo.c | 46 ++- sysdeps/x86/cacheinfo.h | 400 ++---------------- sysdeps/x86/cpu-features.c | 35 +- sysdeps/x86/dl-cacheinfo.h | 460 +++++++++++++++++++++ sysdeps/x86/dl-cet.c | 5 +- sysdeps/x86/dl-isa-level.h | 31 ++ sysdeps/x86/get-isa-level.h | 1 + sysdeps/x86/include/cpu-features.h | 22 + sysdeps/x86/tst-setjmp-cet.c | 1 + sysdeps/x86_64/dl-hwcaps-subdirs.c | 1 + 61 files changed, 1467 insertions(+), 663 deletions(-) create mode 100644 elf/tst-glibc-hwcaps-2-cache.c copy elf/{tst-glibc-hwcaps-cache.root => tst-glibc-hwcaps-2-cache.root}/etc/ld.so. [...] copy elf/{tst-glibc-hwcaps-cache.root => tst-glibc-hwcaps-2-cache.root}/postclean. [...] create mode 100644 elf/tst-glibc-hwcaps-2-cache.script create mode 100644 elf/tst-rtld-list-tunables.exp create mode 100755 elf/tst-rtld-list-tunables.sh create mode 100644 sysdeps/generic/dl-isa-level.h create mode 100644 sysdeps/generic/elf-read-prop.h create mode 100644 sysdeps/unix/sysv/linux/x86/elf-read-prop.h create mode 100644 sysdeps/unix/sysv/linux/x86_64/tst-glibc-hwcaps-2.c create mode 100644 sysdeps/unix/sysv/linux/x86_64/x86-64-isa-level-VALUE.c create mode 100644 sysdeps/x86/dl-isa-level.h create mode 100644 sysdeps/x86/tst-setjmp-cet.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-Os_LTO updated (4180301e81 -> f89f33e57c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-Os_LTO in repository toolchain/ci/binutils-gdb. from 4180301e81 Automatic date update in version.in adds 62fe7512a7 sim: watch: fix pc watchpoints on little endian host systems adds c54f3efdc2 sim: watch: fix range expression processing adds 2ce40d1a51 Add SEH support to code generated by dlltool. adds 8c4645b488 Remove sflag_info param from wild callback functions adds b209b5a6b8 SHF_LINK_ORDER fixup_link_order in ld adds 5347ed60c5 Regen Makefile.in for jobserver.m4 aclocal.m4 dependency adds 844bf810cf x86: Don't generate GOT_symbol for PLT relocations adds b634d11d61 ld: Check for ELF input before accessing ELF section data adds 54ca900277 gdb: convert jit to new-style debug macros adds 5e12f48ffb gdb: bool-ify file_is_auto_load_safe adds db972fce46 gdb: bool-ify ext_lang_auto_load_enabled and friends adds 5bf7e91b2b gdb: bool-ify users of file_is_auto_load_safe adds 506195754c gdb: bool-ify maybe_add_script_{text,file} adds fb0f5031bb gdb: turn arc_debug into a bool adds d8d1feb424 gdb: convert arc to new-style debug macros adds 4120e4885b Re: SHF_LINK_ORDER fixup_link_order in ld adds 3eeabe12c3 Automatic date update in version.in adds c9d220893e gdb: make the remote target track its own thread resume state adds bd497355ea gdb: remove target_ops::commit_resume implementation in reco [...] adds 8f66807b98 gdb: better handling of 'S' packets adds d9b1deff13 sim: watch: add basic default handler that traps adds 54780889e9 sim: h8300: drop separate eightbit memory buffer adds adb0bd8fda gas: bfin: fix build time warnings adds abad28152e gas: bfin: build lexer with -Werror adds 271bea6acd ld: tests: add -msim when testing bfin targets adds 7e0d77ef5f Fix an illegal memory access parsing a win32pstatus note wit [...] adds 116d0cf103 [gdb/testsuite] Fix gdb.base/style.exp with -m32 adds 5fae2a2c66 [gdb/breakpoint] Handle .plt.sec in in_plt_section adds 5a10699ff3 Updated translations for some subdirectories adds 8ca9c7eb67 bfin: Skip non SEC_ALLOC section for R_BFIN_FUNCDESC adds 58eadc4b69 Fix building gdb with gcc-4.x adds c14dee84dd Update my email address (long overdue!) adds 17e8913732 Add myself to gdb/MAINTAINERS adds 5aa06b1b14 Automatic date update in version.in adds 5fda40b28f gas: make [248]byte directives available everywhere adds 3624a6c15c PR26539, memory leak in inflate.c adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status adds 7cf91a2481 sim: m32r: clean up redundant test coverage adds 89bfc2a429 sim: frv: clean up redundant test coverage adds 137d6efd8a sim: mips: delete empty stub test dir adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness adds bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 adds 5a11fff005 gdb/tui: compare pointer to nullptr, not 0 adds e403a898b5 Automatic date update in version.in adds 1368b914e9 sim: testsuite: flatten tree adds eb6e6af8c1 PR26002 undefined symbol VER_NDX_GLOBAL vs. VER_NDX_LOCAL adds ad92f33d38 Tidy inflateEnd calls adds 68b007788a ld/x86: Add -z report-relative-reloc adds 75a933f399 ld/elf/x86: Don't compare IFUNC address in the shared object adds 514fca98df Automatic date update in version.in adds edf0f284b1 PR binutils/23460: Increase the max number of open files to 20 adds d46153313b Automatic date update in version.in adds 25294ff049 gold: Remove the circular IFUNC dependency in ifuncmain6pie adds 994b251328 ld/elf: Ignore section symbols when matching linkonce with comdat adds 44365e88c0 PR27198, segv in S_IS_WEAK adds cecb191290 gdb: const-ify unpack_* functions in remote.c adds e3b2741b16 gdb: const-ify remote_target::add_current_inferior_and_threa [...] adds b5c8f22d28 gdb: move remote_target::start_remote variable to narrower scope adds aa2838ccc5 gdb: const-ify hostio methods parameter in remote.c adds d3d7d1ba3b [gdb/tdep] Handle si_addr_bnd in compat_siginfo_from_siginfo adds 326adec374 PR26378, sections initialised only by linker scripts are alw [...] adds 6a9ad81c44 gdb/riscv: use a single regset supply function for riscv fbs [...] adds 705989f19a as: Automatically enable DWARF5 support adds 02baa13385 gdb/testsuite: remove actual addresses from some test names adds 4cfcd3b333 sim: common: modernize gennltvals.sh adds 5e25901fcc sim: common: delete configure & Makefile adds f89f33e57c sim: common: simplify version script No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 80 + bfd/Makefile.in | 1 + bfd/bfd-in2.h | 7 +- bfd/compress.c | 3 +- bfd/doc/Makefile.in | 1 + bfd/elf-linker-x86.h | 3 + bfd/elf.c | 5 +- bfd/elf32-bfin.c | 235 +- bfd/elf32-i386.c | 36 + bfd/elf64-x86-64.c | 33 + bfd/elflink.c | 202 +- bfd/elfnn-riscv.c | 319 +- bfd/elfxx-riscv.c | 54 +- bfd/elfxx-riscv.h | 4 +- bfd/elfxx-x86.c | 50 +- bfd/elfxx-x86.h | 4 + bfd/section.c | 7 +- bfd/version.h | 2 +- binutils/ChangeLog | 31 + binutils/MAINTAINERS | 6 +- binutils/Makefile.in | 1 + binutils/dlltool.c | 50 +- binutils/doc/Makefile.in | 1 + binutils/po/sv.po | 3804 +++++++++++--------- binutils/readelf.c | 8 +- gas/ChangeLog | 76 + gas/Makefile.am | 4 +- gas/Makefile.in | 5 +- gas/config/bfin-lex.l | 5 +- gas/config/obj-elf.c | 4 - gas/config/tc-i386.c | 42 +- gas/config/tc-riscv.c | 521 ++- gas/config/tc-riscv.h | 6 +- gas/doc/Makefile.in | 1 + gas/doc/as.texi | 7 - gas/dwarf2dbg.c | 24 +- gas/read.c | 3 + gas/testsuite/gas/elf/dwarf-5-file0.d | 2 +- gas/testsuite/gas/i386/i386.exp | 5 + gas/testsuite/gas/i386/no-got.d | 17 + gas/testsuite/gas/i386/no-got.s | 5 + gas/testsuite/gas/i386/pr27198.d | 2 + gas/testsuite/gas/i386/pr27198.err | 5 + gas/testsuite/gas/i386/pr27198.s | 1 + gas/testsuite/gas/i386/x86-64-no-got.d | 17 + gas/testsuite/gas/i386/x86-64-no-got.s | 5 + gas/testsuite/gas/lns/lns-diag-1.l | 2 - gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +- .../gas/riscv/priv-reg-fail-read-only-01.l | 136 +- .../gas/riscv/priv-reg-fail-read-only-02.l | 48 +- gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +- .../gas/riscv/priv-reg-fail-version-1p10.l | 48 +- .../gas/riscv/priv-reg-fail-version-1p11.l | 46 +- .../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +- gdb/ChangeLog | 160 + gdb/MAINTAINERS | 1 + gdb/arc-linux-nat.c | 16 +- gdb/arc-linux-tdep.c | 43 +- gdb/arc-newlib-tdep.c | 11 +- gdb/arc-tdep.c | 151 +- gdb/arc-tdep.h | 7 +- gdb/auto-load.c | 82 +- gdb/auto-load.h | 16 +- gdb/extension-priv.h | 2 +- gdb/extension.c | 7 +- gdb/extension.h | 5 +- gdb/guile/guile-internal.h | 5 +- gdb/guile/scm-auto-load.c | 5 +- gdb/jit.c | 64 +- gdb/nat/amd64-linux-siginfo.c | 13 + gdb/objfiles.h | 3 +- gdb/python/py-auto-load.c | 5 +- gdb/python/python-internal.h | 5 +- gdb/record-btrace.c | 11 - gdb/record-full.c | 10 - gdb/remote.c | 412 ++- gdb/riscv-fbsd-tdep.c | 20 +- gdb/riscv-linux-tdep.c | 4 +- gdb/riscv-tdep.c | 50 + gdb/riscv-tdep.h | 23 + gdb/testsuite/ChangeLog | 22 + gdb/testsuite/gdb.base/style.exp | 49 +- gdb/testsuite/gdb.fortran/array-slices.exp | 5 +- .../gdb.server/stop-reply-no-thread-multi.c | 77 + .../gdb.server/stop-reply-no-thread-multi.exp | 136 + gdb/trad-frame.c | 5 +- gdb/tui/tui.c | 4 +- gold/ChangeLog | 10 + gold/po/fr.po | 730 ++-- gold/testsuite/ifuncmain6pie.c | 14 +- gold/testsuite/ifuncmod6.c | 10 +- gprof/ChangeLog | 4 + gprof/Makefile.in | 1 + include/ChangeLog | 11 + include/elf/riscv.h | 3 +- include/opcode/riscv-opc.h | 16 +- include/opcode/riscv.h | 127 +- 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=> }/bfin/c_alu2op_conv_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_neg.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_toggle.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_xb.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_conv_xh.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_divq.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_divs.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_log_l_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_log_r_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_shadd_1.s (100%) rename sim/testsuite/{sim => }/bfin/c_alu2op_shadd_2.s (100%) rename sim/testsuite/{sim => }/bfin/c_br_preg_killed_ac.s (100%) rename sim/testsuite/{sim => }/bfin/c_br_preg_killed_ex1.s (100%) rename sim/testsuite/{sim => }/bfin/c_br_preg_stall_ac.s (100%) rename sim/testsuite/{sim => }/bfin/c_br_preg_stall_ex1.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_bp1.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_bp2.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_bp3.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_bp4.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_bp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_bp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_brt_nbp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_fbkwd.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brf_nbp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brt_bp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_brt_nbp.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_kills_dhits.s (100%) rename sim/testsuite/{sim => }/bfin/c_brcc_kills_dmiss.s (100%) rename sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_cactrl_iflush_pr_pp.s (100%) rename sim/testsuite/{sim => }/bfin/c_calla_ljump.s (100%) rename sim/testsuite/{sim => }/bfin/c_calla_subr.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc2dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_ac.S (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_an.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_aq.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av0.S (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_av1.S (100%) rename sim/testsuite/{sim => }/bfin/c_cc2stat_cc_az.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_flag_ccmv_depend.S (100%) rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft_s1.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_flagdreg_mvbrsft_sn.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_s1.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_sn.S (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_a0a1.S (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_and_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_minus_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_or_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_plus_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_dr_xor_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_pr_plus_pr_sh1.s (100%) rename sim/testsuite/{sim => }/bfin/c_comp3op_pr_plus_pr_sh2.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_add_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_add_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_eq_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_dr_eq_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags.S (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opd_flags_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imgebl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imltbl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lz_inc_dec.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imgebl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imltbl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lz_inc_dec.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0_pm_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0a1s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_abs_a.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_neg_a.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_absabs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_negneg.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_abs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_absabs.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_alhwx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_awx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop1ew.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop2.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteop3.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_bytepack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_byteunpack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_disalnexcpt.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_max.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_maxmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_min.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_minmin.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_r_lh_a0pa1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_r_negneg.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd12_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd12_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd20_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd20_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd12_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd12_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd20_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd20_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rlh_rnd.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rr_lph_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm_aa.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft_x.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft_x.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_saa.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sat_aa.S (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_search.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sgn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_iuw32.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_iutsh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_a1a0_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_pair_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_iutsh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_m_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_tu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_dr_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_m_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mult_pair_u.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_a0alr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align16.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align24.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_align8.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_l.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expexp_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_ones.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_pack.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_rot_mix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_signbits_rl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_vmaxvmax.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_a0alr.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_af_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_ln_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_lp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rn_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahalf_rp_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_ahh_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_amix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_lmix.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shiftim_rot.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_ld_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_dr_ippm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drhi_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dspldst_st_drlo_ipp.s (100%) rename sim/testsuite/{sim => }/bfin/c_except_illopcode.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_user_mode.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable_enable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_loopsetup_stld.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nested.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nmi.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_reload.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tcount.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tscale.S (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drhi.s (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_drlo.s (100%) rename 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=> }/bfin/c_loopsetup_preg_lc0.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_lc1.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_preg_stld.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_prelc.s (100%) rename sim/testsuite/{sim => }/bfin/c_loopsetup_topbotcntr.s (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_interr_ctl.s (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_loop.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_loop_user_except.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_ppop_illegal_adr.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_ppopm_illegal_adr.S (100%) rename sim/testsuite/{sim => }/bfin/c_mmr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_supervisor.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user.S (100%) rename sim/testsuite/{sim => }/bfin/c_mode_user_superivsor.S (100%) rename sim/testsuite/{sim => }/bfin/c_multi_issue_dsp_ld_ld.s (100%) rename sim/testsuite/{sim => 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=> }/cr16/subd.cgs (100%) rename sim/testsuite/{sim => }/cr16/subi.cgs (100%) rename sim/testsuite/{sim => }/cr16/subw.cgs (100%) rename sim/testsuite/{sim => }/cr16/tbit.cgs (100%) rename sim/testsuite/{sim => }/cr16/tbitb.cgs (100%) rename sim/testsuite/{sim => }/cr16/tbitw.cgs (100%) rename sim/testsuite/{sim => }/cr16/testutils.inc (100%) rename sim/testsuite/{sim => }/cr16/uread16.ms (100%) rename sim/testsuite/{sim => }/cr16/uread32.ms (100%) rename sim/testsuite/{sim => }/cr16/xorb.cgs (100%) rename sim/testsuite/{sim => }/cr16/xord.cgs (100%) rename sim/testsuite/{sim => }/cr16/xorw.cgs (100%) create mode 100644 sim/testsuite/cris/ChangeLog rename sim/testsuite/{sim => }/cris/asm/abs.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addcpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addcv32c.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addcv32m.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addcv32r.ms (100%) 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}/frv/bvlr.cgs (100%) create mode 100644 sim/testsuite/frv/cache.ms rename sim/testsuite/{sim => }/frv/cadd.cgs (100%) rename sim/testsuite/{sim => }/frv/caddcc.cgs (100%) rename sim/testsuite/{sim => }/frv/call.cgs (100%) rename sim/testsuite/{sim => }/frv/call.pcgs (100%) rename sim/testsuite/{sim => }/frv/callil.cgs (100%) rename sim/testsuite/{sim => }/frv/calll.cgs (100%) rename sim/testsuite/{sim => }/frv/cand.cgs (100%) rename sim/testsuite/{sim => }/frv/candcc.cgs (100%) rename sim/testsuite/{sim => }/frv/ccalll.cgs (100%) rename sim/testsuite/{sim => }/frv/cckc.cgs (100%) rename sim/testsuite/{sim => }/frv/cckeq.cgs (100%) rename sim/testsuite/{sim => }/frv/cckge.cgs (100%) rename sim/testsuite/{sim => }/frv/cckgt.cgs (100%) rename sim/testsuite/{sim => }/frv/cckhi.cgs (100%) rename sim/testsuite/{sim => }/frv/cckle.cgs (100%) rename sim/testsuite/{sim => }/frv/cckls.cgs (100%) rename sim/testsuite/{sim => }/frv/ccklt.cgs (100%) rename sim/testsuite/{sim => }/frv/cckn.cgs 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sim/testsuite/{sim => }/frv/cldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/cldbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldd.cgs (100%) rename sim/testsuite/{sim => }/frv/clddf.cgs (100%) rename sim/testsuite/{sim => }/frv/clddfu.cgs (100%) rename sim/testsuite/{sim => }/frv/clddu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldf.cgs (100%) rename sim/testsuite/{sim => }/frv/cldfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldhf.cgs (100%) rename sim/testsuite/{sim => }/frv/cldhfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldq.cgs (100%) rename sim/testsuite/{sim => }/frv/cldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/cldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/cldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldu.cgs (100%) rename sim/testsuite/{sim => }/frv/cldub.cgs (100%) rename sim/testsuite/{sim => }/frv/cldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/clduh.cgs (100%) rename sim/testsuite/{sim => }/frv/clduhu.cgs (100%) rename sim/testsuite/{sim => }/frv/clrfa.cgs (100%) rename sim/testsuite/{sim => }/frv/clrfr.cgs (100%) rename sim/testsuite/{sim => }/frv/clrga.cgs (100%) rename sim/testsuite/{sim => }/frv/clrgr.cgs (100%) rename sim/testsuite/{sim => }/frv/cmaddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/cmaddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/cmand.cgs (100%) rename sim/testsuite/{sim => }/frv/cmbtoh.cgs (100%) rename sim/testsuite/{sim => }/frv/cmbtohe.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxis.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxiu.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxrs.cgs (100%) rename sim/testsuite/{sim => }/frv/cmcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/cmexpdhd.cgs (100%) rename sim/testsuite/{sim => }/frv/cmexpdhw.cgs (100%) rename sim/testsuite/{sim => }/frv/cmhtob.cgs (100%) rename sim/testsuite/{sim => }/frv/cmmachs.cgs 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=> }/frv/csracc.cgs (100%) rename sim/testsuite/{sim => }/frv/csrl.cgs (100%) rename sim/testsuite/{sim => }/frv/csrlcc.cgs (100%) rename sim/testsuite/{sim => }/frv/cst.cgs (100%) rename sim/testsuite/{sim => }/frv/cstb.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstbu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstd.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdfu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstdu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstf.cgs (100%) rename sim/testsuite/{sim => }/frv/cstfu.cgs (100%) rename sim/testsuite/{sim => }/frv/csth.cgs (100%) rename sim/testsuite/{sim => }/frv/csthf.cgs (100%) rename sim/testsuite/{sim => }/frv/csthfu.cgs (100%) rename sim/testsuite/{sim => }/frv/csthu.cgs (100%) rename sim/testsuite/{sim => }/frv/cstq.cgs (100%) rename sim/testsuite/{sim => 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rename sim/testsuite/{sim => }/frv/fbgt.cgs (100%) rename sim/testsuite/{sim => }/frv/fbgtlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fble.cgs (100%) rename sim/testsuite/{sim => }/frv/fblelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fblg.cgs (100%) rename sim/testsuite/{sim => }/frv/fblglr.cgs (100%) rename sim/testsuite/{sim => }/frv/fblt.cgs (100%) rename sim/testsuite/{sim => }/frv/fbltlr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbne.cgs (100%) rename sim/testsuite/{sim => }/frv/fbnelr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbno.cgs (100%) rename sim/testsuite/{sim => }/frv/fbnolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbo.cgs (100%) rename sim/testsuite/{sim => }/frv/fbolr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbra.cgs (100%) rename sim/testsuite/{sim => }/frv/fbralr.cgs (100%) rename sim/testsuite/{sim => }/frv/fbu.cgs (100%) rename sim/testsuite/{sim => }/frv/fbue.cgs (100%) rename sim/testsuite/{sim => }/frv/fbuelr.cgs (100%) rename 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rename sim/testsuite/{sim => }/frv/fr550/cmqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/dcpl.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/dcul.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mabshs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/frv/fr550/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrtd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/fstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fteq.cgs (100%) rename sim/testsuite/{sim => }/frv/ftge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftgt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftieq.cgs (100%) rename sim/testsuite/{sim => }/frv/ftige.cgs (100%) rename sim/testsuite/{sim => }/frv/ftigt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftile.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftine.cgs (100%) rename sim/testsuite/{sim => }/frv/ftino.cgs (100%) rename sim/testsuite/{sim => }/frv/ftio.cgs (100%) rename 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sim/testsuite/frv/grloop.ms create mode 100644 sim/testsuite/frv/hello.ms rename sim/testsuite/{sim => }/frv/icei.cgs (100%) rename sim/testsuite/{sim => }/frv/ici.cgs (100%) rename sim/testsuite/{sim => }/frv/icpl.cgs (100%) rename sim/testsuite/{sim => }/frv/icul.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts.exp (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr400.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr500.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/mp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/privileged_instruction.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/regalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/reset.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/shadow_regs.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/timer.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpil.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.pcgs (100%) rename sim/testsuite/{sim => }/frv/ld.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfi.cgs 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sim/testsuite/{sim => }/frv/ldqc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/ldshi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldub.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/lduh.cgs (100%) rename sim/testsuite/{sim => }/frv/lduhi.cgs (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/frv/mcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutss.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mdrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdunpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/membar.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhd.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhw.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethih.cgs (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/frv/mqmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsaths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotri.cgs (100%) rename sim/testsuite/{sim => }/frv/msaths.cgs (100%) rename sim/testsuite/{sim => }/frv/msathu.cgs (100%) rename sim/testsuite/{sim => }/frv/msllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrlhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mtrap.cgs (100%) rename sim/testsuite/{sim => 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=> }/v850/satsubi.cgs (100%) rename sim/testsuite/{sim => }/v850/satsubr.cgs (100%) rename sim/testsuite/{sim => }/v850/shl.cgs (100%) rename sim/testsuite/{sim => }/v850/shr.cgs (100%) rename sim/testsuite/{sim => }/v850/testutils.cgs (100%) rename sim/testsuite/{sim => }/v850/testutils.inc (100%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-Os_LTO updated (14c0e041 -> aed374ee)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch64-spec2k6-Os_LTO in repository toolchain/ci/base-artifacts. discards 14c0e041 6: update: binutils-gcc-glibc: 1 new aed374ee 6: update: binutils-glibc: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (14c0e041) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk_tx1/gnu-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 181 +- 02-prepare_abe/console.log | 410 +- 03-build_abe-binutils/console.log | 11868 +-- 04-build_abe-stage1/console.log | 16288 ++--- 05-build_abe-linux/console.log | 1994 +- 06-build_abe-glibc/console.log | 40896 +++++------ 07-build_abe-stage2/console.log | 33156 +++++---- 09-benchmark--Os_LTO/benchmark-start.log | 2 +- 09-benchmark--Os_LTO/benchmark.log | 12 +- 09-benchmark--Os_LTO/console.log | 155 +- 10-check_regression/console.log | 1126 +- 10-check_regression/results-0.csv | 230 +- 10-check_regression/results-1.csv | 226 +- 10-check_regression/results-brief.csv | 58 +- 10-check_regression/results-full.csv | 238 +- 10-check_regression/results.csv | 72 +- 10-check_regression/results.log | 4692 +- 11-update_baseline/console.log | 3550 +- 11-update_baseline/results-1.csv | 226 +- 11-update_baseline/results-brief.csv | 58 +- 11-update_baseline/results-full.csv | 222 +- 11-update_baseline/results.csv | 72 +- 11-update_baseline/results.log | 3274 +- console.log | 109662 ++++++++++++++-------------- jenkins/manifest.sh | 22 +- results_id | 2 +- 26 files changed, 114085 insertions(+), 114607 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[gcc] branch master updated (ef1f8ee67d4 -> c907e439413)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from ef1f8ee67d4 Daily bump. new c907e439413 compiler: read embedcfg files, parse go:embed directives The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/go/gofrontend/MERGE | 2 +- gcc/go/gofrontend/embed.cc | 15 +++++++ gcc/go/gofrontend/go.cc | 2 + gcc/go/gofrontend/gogo.cc | 4 +- gcc/go/gofrontend/gogo.h | 16 ++++++++ gcc/go/gofrontend/lex.cc | 94 +++++++++++++++++++++++++++++++++++++++++++ gcc/go/gofrontend/lex.h | 20 ++++++++++ gcc/go/gofrontend/parse.cc | 99 +++++++++++++++++++++++++++++++++++----------- gcc/go/gofrontend/parse.h | 15 +++---- 9 files changed, 234 insertions(+), 33 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[gcc] branch releases/gcc-9 updated (26b0c76ef8b -> af7f0399252)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch releases/gcc-9 in repository gcc. from 26b0c76ef8b Daily bump. new af7f0399252 Daily bump. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

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