Tcwg-commits January 2021

tcwg-commits@lists.linaro.org

5 participants
9360 discussions

[glibc] branch nsz/bug27072 updated (4b93918115 -> 84877b5e3f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch nsz/bug27072 in repository glibc. discards 4b93918115 Make libc symbols hidden in static PIE discards 9d9d859c0e x86: Check ifunc resolver with CPU_FEATURE_USABLE [BZ #27072] discards 4224b7c042 csu: Move static pie self relocation later [BZ #27072] discards be1b797ea8 Use <startup.h> in __libc_init_secure discards 3ed8c627e3 elf: Avoid RELATIVE relocation for _dl_sysinfo discards 78d3bf1bc9 Use hidden visibility for early static PIE code discards 13b7b31869 elf: Avoid RELATIVE relocs in __tunables_init discards 58d4e6b794 elf: Make the tunable struct definition internal only discards 7bd28c328f libmvec: Add extra-test-objs to test-extras discards 9c7e869002 configure: Require PI_STATIC_AND_HIDDEN for static pie adds f678099de9 Update hppa libm-test-ulps adds a031b3abad Update powerpc-nofpu libm-test-ulps. adds 07169fcac7 Update arm libm-test-ulps. adds 202586f73e Update MIPS libm-test-ulps. adds 0887fff0b0 Hurd: Add rtld-strncpy-c.c adds 0ec583d926 libmvec: Add extra-test-objs to test-extras adds cabc8a2916 elf: Avoid RELATIVE relocation for _dl_sysinfo new 5790f6b21a configure: Require PI_STATIC_AND_HIDDEN for static pie new 0d5328b83b elf: Make the tunable struct definition internal only new 2da1722fe0 elf: Avoid RELATIVE relocs in __tunables_init new a16cb63d41 Use hidden visibility for early static PIE code new a14c2bc43c Use <startup.h> in __libc_init_secure new 6b468d65b6 csu: Move static pie self relocation later [BZ #27072] new 84877b5e3f Make libc symbols hidden in static PIE This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (4b93918115) \ N -- N -- N refs/heads/nsz/bug27072 (84877b5e3f) You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 7 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: csu/libc-start.c | 16 +-- elf/dl-support.c | 12 +-- sysdeps/arm/libm-test-ulps | 23 ++-- sysdeps/hppa/fpu/libm-test-ulps | 23 ++-- .../mach/hurd/i386/i686/multiarch/rtld-strncpy-c.c | 1 + sysdeps/mips/mips32/libm-test-ulps | 23 ++-- sysdeps/mips/mips64/libm-test-ulps | 23 ++-- sysdeps/powerpc/nofpu/libm-test-ulps | 33 +++--- sysdeps/x86/Makefile | 14 --- sysdeps/x86/tst-ifunc-isa-1-static.c | 1 - sysdeps/x86/tst-ifunc-isa-1.c | 115 -------------------- sysdeps/x86/tst-ifunc-isa-2-static.c | 1 - sysdeps/x86/tst-ifunc-isa-2.c | 119 --------------------- 13 files changed, 78 insertions(+), 326 deletions(-) create mode 100644 sysdeps/mach/hurd/i386/i686/multiarch/rtld-strncpy-c.c delete mode 100644 sysdeps/x86/tst-ifunc-isa-1-static.c delete mode 100644 sysdeps/x86/tst-ifunc-isa-1.c delete mode 100644 sysdeps/x86/tst-ifunc-isa-2-static.c delete mode 100644 sysdeps/x86/tst-ifunc-isa-2.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[gcc] branch master updated (66dd412feea -> 8227106f566)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 66dd412feea ipa/98330 - avoid ICEing on call indirect call new 8227106f566 [committed] Fix dwarf-float.c test in testsuite The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/testsuite/gcc.dg/debug/dwarf2/dwarf-float.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/interesting-commits] branch linaro-local/ci/tcwg_bmk_tx1 updated (fb36674 -> 007ffba)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1 in repository toolchain/ci/interesting-commits. from fb36674 Add last-good 5c046034e3ea61dd68965154a398f8f813daf8f2 from h [...] new 007ffba Add regression 0425f4c1b63107bf3bc4778d1fe53c91ace7838d from [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc | 1 + 1 file changed, 1 insertion(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/interesting-commits] branch linaro-local/ci/tcwg_bmk_tx1 updated (7e20ffd -> fb36674)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1 in repository toolchain/ci/interesting-commits. from 7e20ffd Add regression 4a369d199bf2f34e037030b18d0da923e8a24997 from [...] new fb36674 Add last-good 5c046034e3ea61dd68965154a398f8f813daf8f2 from h [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc | 1 + 1 file changed, 1 insertion(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[binutils-gdb] branch binutils-2_36-branch updated (d235291c819 -> 296ffb5ad60)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch binutils-2_36-branch in repository binutils-gdb. from d235291c819 [GOLD] powerpc assertion failure new b7540e2b88b libctf: lookup_by_name: do not return success for nonexiste [...] new 296ffb5ad60 libctf, create: fix ctf_type_add of structs with unnamed members The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: libctf/ChangeLog | 12 ++++ libctf/ctf-create.c | 6 ++ libctf/ctf-lookup.c | 34 +++++++--- libctf/testsuite/libctf-regression/pptrtab-a.c | 2 + libctf/testsuite/libctf-regression/pptrtab-b.c | 3 +- libctf/testsuite/libctf-regression/pptrtab.c | 10 ++- .../type-add-unnamed-struct-ctf.c | 19 ++++++ .../libctf-regression/type-add-unnamed-struct.c | 72 ++++++++++++++++++++++ .../libctf-regression/type-add-unnamed-struct.lk | 3 + 9 files changed, 151 insertions(+), 10 deletions(-) create mode 100644 libctf/testsuite/libctf-regression/type-add-unnamed-struct-ctf.c create mode 100644 libctf/testsuite/libctf-regression/type-add-unnamed-struct.c create mode 100644 libctf/testsuite/libctf-regression/type-add-unnamed-struct.lk -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig updated (1d94330a437a -> 1e2a199f6ccd)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig in repository toolchain/ci/linux. from 1d94330a437a Merge tag 'for-5.11/dm-fixes-1' of git://git.kernel.org/pu [...] adds 29a951dfb3c3 mm: fix clear_refs_write locking adds 9348b73c2e1b mm: don't play games with pinned pages in clear_page_refs adds cf7b2ae4d704 riscv: return -ENOSYS for syscall -1 adds 11f4c2e940e2 riscv: Fix kernel time_init() adds 1f1496a923b6 riscv: Fix sifive serial driver adds 643437b996ba riscv: Enable interrupts during syscalls with M-Mode adds 0ea02c737752 riscv: Drop a duplicated PAGE_KERNEL_EXEC adds 7cd1af107a92 riscv: Trace irq on only interrupt is enabled adds 80709af7325d riscv: cacheinfo: Fix using smp_processor_id() in preemptible adds 0aa2ec8a475f riscv: Fixup CONFIG_GENERIC_TIME_VSYSCALL adds c25a053e1577 riscv: Fix KASAN memory mapping. adds be969b7cfbcf dts: phy: fix missing mdio device and probe failure of vsc [...] adds a0fa9d727043 dts: phy: add GPIO number and active state used for phy reset adds 0983834a8393 riscv: defconfig: enable gpio support for HiFive Unleashed adds dec822771b01 riscv: stacktrace: Move register keyword to beginning of d [...] adds 797f0375dd2e RISC-V: Do not allocate memblock while iterating reserved [...] adds abb8e86b2696 RISC-V: Set current memblock limit adds e557793799c5 RISC-V: Fix maximum allowed phsyical memory for RV32 adds acda701bf1e8 Merge tag 'riscv-for-linus-5.11-rc4' of git://git.kernel.o [...] adds d434ab6db524 io_uring: drop mm and files after task_work_run adds 621fadc22365 io_uring: don't take files/mm for a dead task adds b4411616c26f io_uring: fix null-deref in io_disable_sqo_submit adds 06585c497b55 io_uring: do sqo disable on install_fd error adds f010505b78a4 io_uring: flush timeouts that should already have expired adds a8d13dbccb13 io_uring: ensure finish_wait() is always called in __io_ur [...] adds 11c0239ae264 Merge tag 'io_uring-5.11-2021-01-16' of git://git.kernel.d [...] adds 7a84665619bb nvmet-rdma: Fix NULL deref when setting pi_enable and trad [...] adds ada831772188 nvme-tcp: Fix warning with CONFIG_DEBUG_PREEMPT adds ca1ff67d0fb1 nvme-tcp: fix possible data corruption with bio merges adds 5ab25a32cd90 nvme: don't intialize hwmon for discovery controllers adds b4f664252f51 Merge tag 'nvme-5.11-2021-01-14' of git://git.infradead.or [...] adds 54c6247d06f1 Merge tag 'block-5.11-2021-01-16' of git://git.kernel.dk/l [...] adds 1d53864c3617 scsi: ufs: Fix possible power drain during system suspend adds 21acf4601cc6 scsi: ufs: Relax the condition of UFSHCI_QUIRK_SKIP_MANUAL [...] adds 6948a96a0d69 scsi: ufs: Relocate flush of exceptional event adds 35fc4cd34426 scsi: ufs: Correct the LUN used in eh_device_reset_handler [...] adds d50c7986fbf0 scsi: qedi: Correct max length of CHAP secret adds 39718fe7adb1 scsi: mpt3sas: Fix spelling mistake in Kconfig "compatibli [...] adds 3b01d7ea4dae scsi: scsi_debug: Fix memleak in scsi_debug_init() adds e5cc9002caaf scsi: sd: Suppress spurious errors when WRITE SAME is bein [...] adds be2553358cd4 scsi: sd: Remove obsolete variable in sd_remove() adds 0da0a8a0a0e1 Merge tag 'scsi-fixes' of git://git.kernel.org/pub/scm/lin [...] adds feb889fb40fa mm: don't put pinned pages into the swap cache adds a0a6df9afcaf umount(2): move the flag validity checks first adds a959a9782fa8 iov_iter: fix the uaccess area in copy_compat_iovec_from_user adds d36a1dd9f77a dump_common_audit_data(): fix racy accesses to ->d_name adds a527a2b32d20 Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux [...] adds 2225a8dda263 powerpc: Fix alignment bug within the init sections adds 41131a5e54ae powerpc/vdso: Fix clock_gettime_fallback for vdso32 adds a1339d6355ac Merge tag 'powerpc-5.11-4' of git://git.kernel.org/pub/scm [...] adds 301f0203e042 perf bpf examples: Fix bpf.h header include directive in 5 [...] adds 38c53947a7dc tools headers UAPI: Sync kvm.h headers with the kernel sources adds addbdff24293 tools headers: Syncronize linux/build_bug.h with the kerne [...] adds a042a82ddbb3 perf test: Fix shadow stat test for non-bash shells adds be82fddca81e libperf tests: Avoid uninitialized variable warning adds bba2ea17ef55 libperf tests: If a test fails return non-zero adds 66dd86b2a2be libperf tests: Fail when failing to get a tracepoint id adds 3ff1e7180abc perf stat: Introduce struct runtime_stat_data adds a1bf23052bdf perf stat: Take cgroups into account for shadow stats adds 5501e9229a80 perf intel-pt: Fix 'CPU too large' error adds 648b054a4647 perf inject: Correct event attribute sizes adds e2da783614bb Merge tag 'perf-tools-fixes-2021-01-17' of git://git.kerne [...] adds 19c329f68089 Linux 5.11-rc4 adds 3c02e04fd4f5 crypto: xor - Fix divide error in do_xor_speed() adds 382811940303 crypto: omap-sham - Fix link error without crypto-engine adds fd3958eac387 Merge branch 'linus' of git://git.kernel.org/pub/scm/linux [...] adds 32c2bc8f2d85 ia64: fix build failure caused by memory model changes adds b4459f4413c8 Merge tag 'fixes-2021-01-18' of git://git.kernel.org/pub/s [...] adds 7a2da5d7960a spi: fsl: Fix driver breakage when SPI_CS_HIGH is not set [...] adds 4d163ad79b15 spi: cadence: cache reference clock rate during probe adds 1e2a199f6ccd Merge tag 'spi-fix-v5.11-rc4' of git://git.kernel.org/pub/ [...] No new revisions were added by this update. Summary of changes: Makefile | 2 +- arch/ia64/include/asm/sparsemem.h | 1 + arch/powerpc/include/asm/vdso/gettimeofday.h | 16 +- arch/powerpc/kernel/vmlinux.lds.S | 8 + arch/riscv/Kconfig | 6 +- .../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 2 + arch/riscv/configs/defconfig | 2 + arch/riscv/include/asm/pgtable.h | 1 - arch/riscv/include/asm/vdso.h | 2 +- arch/riscv/kernel/cacheinfo.c | 11 +- arch/riscv/kernel/entry.S | 24 +- arch/riscv/kernel/setup.c | 24 +- arch/riscv/kernel/stacktrace.c | 5 +- arch/riscv/kernel/time.c | 3 + arch/riscv/kernel/vdso.c | 2 +- arch/riscv/mm/init.c | 16 +- arch/riscv/mm/kasan_init.c | 4 +- crypto/xor.c | 2 + drivers/crypto/Kconfig | 1 + drivers/nvme/host/core.c | 11 +- drivers/nvme/host/tcp.c | 4 +- drivers/nvme/target/rdma.c | 16 +- drivers/scsi/mpt3sas/Kconfig | 2 +- drivers/scsi/qedi/qedi_main.c | 4 +- drivers/scsi/scsi_debug.c | 5 +- drivers/scsi/sd.c | 6 +- drivers/scsi/ufs/ufshcd.c | 24 +- drivers/spi/spi-cadence.c | 6 +- drivers/spi/spi-fsl-spi.c | 5 +- drivers/tty/serial/sifive.c | 1 + fs/io_uring.c | 46 ++- fs/namespace.c | 7 +- fs/proc/task_mmu.c | 53 +-- lib/iov_iter.c | 2 +- mm/vmscan.c | 2 + security/lsm_audit.c | 7 +- tools/include/linux/build_bug.h | 5 - tools/include/uapi/linux/kvm.h | 2 + tools/lib/perf/tests/test-cpumap.c | 2 +- tools/lib/perf/tests/test-evlist.c | 7 +- tools/lib/perf/tests/test-evsel.c | 2 +- tools/lib/perf/tests/test-threadmap.c | 2 +- tools/perf/examples/bpf/5sec.c | 2 +- tools/perf/tests/shell/stat+shadow_stat.sh | 30 +- tools/perf/util/header.c | 8 + tools/perf/util/machine.c | 4 +- tools/perf/util/session.c | 2 +- tools/perf/util/stat-shadow.c | 366 +++++++++++---------- 48 files changed, 447 insertions(+), 318 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig updated (5d201f32885 -> 1aed3f059eb)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig in repository toolchain/ci/gcc. from 5d201f32885 Daily bump. adds 8f2ed3fe616 Daily bump. adds 05318fb8a89 testsuite: i386: Require ifunc support in gcc.target/i386/p [...] adds a7c7dd708aa Daily bump. adds 4fdb9c83408 Daily bump. new 4779ef35735 Fix PR ada/98740 new 1aed3f059eb sparc,rtems: add __FIX_LEON3FT_TN0018 for affected targets The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/DATESTAMP | 2 +- gcc/ada/gcc-interface/trans.c | 11 ++++++----- gcc/config/sparc/rtemself.h | 2 ++ gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.target/i386/pr98100.c | 1 + 5 files changed, 14 insertions(+), 6 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig updated (a7921f82 -> c3ba16a2)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig in repository toolchain/ci/base-artifacts. discards a7921f82 0: update: binutils-gcc-linux-qemu: boot new c3ba16a2 0: update: binutils-gcc-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (a7921f82) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-m [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 183 +- 02-prepare_abe/console.log | 434 +- 03-build_abe-binutils/console.log | 11517 +++++----- 04-build_abe-stage1/console.log | 18517 +++++++-------- 05-build_linux/console.log | 562 +- 06-build_abe-qemu/console.log | 4468 ++-- 07-boot_linux/console.log | 494 +- 08-check_regression/console.log | 12 +- 08-check_regression/results.regressions | 2 +- 09-update_baseline/console.log | 12 +- 09-update_baseline/results.regressions | 2 +- console.log | 36255 +++++++++++++++--------------- jenkins/manifest.sh | 16 +- 13 files changed, 36240 insertions(+), 36234 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-Os updated (eeaa19f75e -> 202586f73e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-Os in repository toolchain/ci/glibc. from eeaa19f75e mntent: Use __putc_unlocked instead of fputc_unlocked adds 1b5c9dfeb2 ARC: Regenerate ulps adds c6e2ca2c3f POSIX locale: Fix typo in comment adds a7e9dbb774 Add xchdir to libsupport. adds 7a72265436 Add xfchmod to libsupport adds 2cd361b511 posix: Correct attribute access mode on readlinkat [BZ #27024]. adds c31b1f5231 riscv: support GNU indirect function adds 313bfd505e riscv: Initialize $gp before resolving the IRELATIVE relocation adds 1c426b1d59 Update STATX_ATTR_DAX value from Linux 5.10. adds 7b9c3260bc support: Add xchmod wrapper adds 42dda89dcb posix: Fix return value of system if shell can not be execut [...] adds 4dddd7e9cb posix: Sync tempname with gnulib [BZ #26648] adds bf7db6d369 math: Add BZ#18980 fix back on dbl-64 cosh adds 87d583c6e8 install: Replace scripts/output-format.sed with objdump -f [ [...] adds 0400f92833 Makerules: Do not require startup files for format.lds probe object adds f430293d84 posix: consume less entropy on tempname adds 2ef23b5205 x86: Set header.feature_1 in TCB for always-on CET [BZ #27177] adds 86a4d3fa7d elf: work around a gcc bug in elf_get_dynamic_info adds efbbd9c33a ldconfig/x86: Store ISA level in cache and aux cache adds cf12900645 Use the right argument code in unnormal tests adds 7137d682eb ifuncmain6pie: Remove the circular IFUNC dependency [BZ #20019] adds d18f59bf92 Fix x86 build with --enable-tunable=no adds 2d651eb926 x86: Move x86 processor cache info to cpu_features adds cc528f9a7e math/test-tgmath2: Fix fabs failure when no long double adds 86f65dffc2 ld.so: Add --list-tunables to print tunable values adds 96f17e6e63 ARC: nofpu: Regenerate ulps adds f678099de9 Update hppa libm-test-ulps adds a031b3abad Update powerpc-nofpu libm-test-ulps. adds 07169fcac7 Update arm libm-test-ulps. adds 202586f73e Update MIPS libm-test-ulps. No new revisions were added by this update. Summary of changes: Makerules | 16 +- NEWS | 4 + benchtests/strcoll-inputs/filelist#en_US.UTF-8 | 1 - config.make.in | 1 - configure | 19 - configure.ac | 11 - elf/Makefile | 13 + elf/cache.c | 39 +- elf/dl-cache.c | 4 + elf/dl-main.h | 2 +- elf/dl-tunables.c | 43 ++ elf/dl-tunables.h | 2 + elf/dl-usage.c | 7 +- elf/get-dynamic-info.h | 41 +- elf/ifuncmain6pie.c | 14 +- elf/ifuncmod6.c | 8 +- elf/ldconfig.c | 18 +- elf/readelflib.c | 81 +++- elf/readlib.c | 7 +- elf/rtld.c | 19 + elf/tst-glibc-hwcaps-2-cache.c | 45 ++ .../etc/ld.so.conf | 0 .../postclean.req | 0 elf/tst-glibc-hwcaps-2-cache.script | 8 + elf/tst-rtld-list-tunables.exp | 14 + elf/tst-rtld-list-tunables.sh | 34 ++ io/bits/statx-generic.h | 2 +- libc-abis | 1 + localedata/locales/POSIX | 2 +- manual/tunables.texi | 38 ++ math/libm-test-driver.c | 12 +- math/libm-test-fpclassify.inc | 14 +- math/libm-test-isinf.inc | 14 +- math/libm-test-isnan.inc | 14 +- math/libm-test-issignaling.inc | 14 +- math/test-tgmath2.c | 4 +- posix/unistd.h | 2 +- scripts/output-format.sed | 35 -- stdlib/tst-system.c | 17 + support/Makefile | 3 + support/xchdir.c | 28 ++ support/xchmod.c | 30 ++ support/xfchmod.c | 28 ++ support/xunistd.h | 3 + sysdeps/arc/fpu/libm-test-ulps | 8 +- sysdeps/arc/nofpu/libm-test-ulps | 11 +- sysdeps/arm/libm-test-ulps | 23 +- sysdeps/generic/dl-cache.h | 16 +- sysdeps/generic/dl-isa-level.h | 25 ++ sysdeps/generic/elf-read-prop.h | 34 ++ sysdeps/generic/ldconfig.h | 22 +- sysdeps/hppa/fpu/libm-test-ulps | 23 +- sysdeps/ieee754/dbl-64/e_cosh.c | 3 +- sysdeps/mips/mips32/libm-test-ulps | 23 +- sysdeps/mips/mips64/libm-test-ulps | 23 +- sysdeps/posix/system.c | 4 + sysdeps/posix/tempname.c | 291 +++++++------ sysdeps/powerpc/nofpu/libm-test-ulps | 33 +- sysdeps/riscv/dl-irel.h | 56 +++ sysdeps/riscv/dl-machine.h | 44 +- sysdeps/unix/sysv/linux/arm/readelflib.c | 22 +- sysdeps/unix/sysv/linux/ia64/readelflib.c | 22 +- sysdeps/unix/sysv/linux/mips/readelflib.c | 22 +- sysdeps/unix/sysv/linux/powerpc/readelflib.c | 22 +- sysdeps/unix/sysv/linux/riscv/readelflib.c | 22 +- sysdeps/unix/sysv/linux/s390/readelflib.c | 22 +- sysdeps/unix/sysv/linux/sparc/readelflib.c | 22 +- sysdeps/unix/sysv/linux/x86/elf-read-prop.h | 60 +++ sysdeps/unix/sysv/linux/x86/readelflib.c | 23 +- sysdeps/unix/sysv/linux/x86_64/Makefile | 51 +++ .../unix/sysv/linux/x86_64/tst-glibc-hwcaps-2.c | 84 ++++ .../sysv/linux/x86_64/x86-64-isa-level-VALUE.c | 4 + sysdeps/x86/Makefile | 6 + sysdeps/x86/cacheinfo.c | 46 ++- sysdeps/x86/cacheinfo.h | 400 ++---------------- sysdeps/x86/cpu-features.c | 35 +- sysdeps/x86/dl-cacheinfo.h | 460 +++++++++++++++++++++ sysdeps/x86/dl-cet.c | 5 +- sysdeps/x86/dl-isa-level.h | 31 ++ sysdeps/x86/get-isa-level.h | 1 + sysdeps/x86/include/cpu-features.h | 22 + sysdeps/x86/tst-setjmp-cet.c | 1 + sysdeps/x86_64/dl-hwcaps-subdirs.c | 1 + 83 files changed, 1868 insertions(+), 867 deletions(-) create mode 100644 elf/tst-glibc-hwcaps-2-cache.c copy elf/{tst-glibc-hwcaps-cache.root => tst-glibc-hwcaps-2-cache.root}/etc/ld.so. [...] copy elf/{tst-glibc-hwcaps-cache.root => tst-glibc-hwcaps-2-cache.root}/postclean. [...] create mode 100644 elf/tst-glibc-hwcaps-2-cache.script create mode 100644 elf/tst-rtld-list-tunables.exp create mode 100755 elf/tst-rtld-list-tunables.sh delete mode 100644 scripts/output-format.sed create mode 100644 support/xchdir.c create mode 100644 support/xchmod.c create mode 100644 support/xfchmod.c create mode 100644 sysdeps/generic/dl-isa-level.h create mode 100644 sysdeps/generic/elf-read-prop.h create mode 100644 sysdeps/riscv/dl-irel.h create mode 100644 sysdeps/unix/sysv/linux/x86/elf-read-prop.h create mode 100644 sysdeps/unix/sysv/linux/x86_64/tst-glibc-hwcaps-2.c create mode 100644 sysdeps/unix/sysv/linux/x86_64/x86-64-isa-level-VALUE.c create mode 100644 sysdeps/x86/dl-isa-level.h create mode 100644 sysdeps/x86/tst-setjmp-cet.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

3 years, 10 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-Os updated (d00f086803 -> a75a6a4164)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-Os in repository toolchain/ci/binutils-gdb. from d00f086803 gdb: add missing test for completion of invalid /FMT strings adds 6abd4cf281 gdb: check for empty strings in get_standard_cache_dir/get_s [...] adds 8fc48b7961 Pass void_context_p to parse_expression adds 46f900c065 sim: require a C11 compiler adds a7e906e8f5 Automatic date update in version.in adds 6430704567 configure regen adds aae7fcb8d7 POWER10: Add Return-Oriented Programming instructions adds b1b29aa51a elf: Verify section size for mixed ordered/unordered inputs adds ba9e922fa0 ld/x86-64: Also set LAM_U57 when setting LAM_U48 adds ce0be4070f sim: common: add missing stdlib.h for abort() adds 055bc77a80 Add Changelog entries and NEWS entries for 2.36 branch adds 573fe3fbc1 Change version number to 2.36.50 and regenerate files adds be2c78856d Update release howto with 2.37 numbers adds b5a4a01af4 sim: hw: rework code to avoid gcc warnings adds f41464416a sim: pru: fix include ordering with sim-main.h adds 0a94990bf6 ld/x86-64: Properly Handle -z lam-u48/lam-u57 adds bf470982f9 sim: enable -Werror by default for some arches adds 50df264dae sim: clean up stale AC_PREREQ refs adds f8cab0b995 sim: sh64: delete port adds f074c07d8d sim: common: clean up asprintf includes a bit adds 7eb99e5e27 sim: cr16/d10v: move storage out of header adds a9fd212a24 sim: replace rindex with strrchr adds 50ad1254d5 GCC: Pass --plugin to AR and RANLIB adds a4966cd965 Binutils: Pass --plugin to AR and RANLIB adds af019bfde9 Support the PGO build for binutils+gdb adds 66beed0227 Fix erroneous agent expression test adds bc167b6b3e Remove a use of print_expression adds 54585eee2e Avoid crash in compile_to_object adds 5834526f4b Automatic date update in version.in adds 46b1518d4c Automatic date update in version.in adds a8aa72b913 Updated translations for multiple subdirectories adds 68ed285428 sim: clean up C11 header includes adds 933306703a sim: rl78: move storage out of header adds 90e123dd60 sim: common: fix printf formats adds a0c38f0d70 sim: or1k: fix include ordering with sim-main.h adds 5c1008a41f sim: call SIM_AC_OPTION_WARNINGS(no) in remaining ports adds 9c70334dee sim: always call SIM_AC_OPTION_WARNINGS adds c0f6e439cc Add support for more MIPS variants to the linker command line. adds 82c70b08df aarch64: Remove support for CSRE adds 10dadadc5b [gdb/testsuite] Fix gdb.arch/amd64-stap-three-arg-disp.S adds 062eaacbac gdb: change jit_debug to a bool adds eef401dce1 gdb: convert solib-aix to new-style debug macros adds c6185dce03 gdb: convert aarch64 to new-style debug macros adds 254c3783fe sim: tests: get common tests working again adds eabdd87b2e Automatic date update in version.in adds 03c02f3116 GCC: Check if AR works with --plugin and rc adds 83b33c6cb9 Binutils: Check if AR works with --plugin and rc adds 44124a4683 binuitils: Check if AR is usable for LTO build adds f631b79abe sim: or1k: delete redundant SIM_AC_OPTION_INLINE call adds f220ef633c sim: common: use #error properly adds 68895f7d7e sim: README-HACKING: clean up stale run references adds 5e9e2f41eb sim: or1k: clean up stale build entries adds e998918e98 sim: or1k: fix mixing of code & decl warning adds 7c654b719d gdb/fortran: add symbol base comparison operators adds ce38f5edf1 gdb: fix debug dump of OP_BOOL expressions adds 6d104cac0a Updated translations for some subdirectories adds c2e9a4a3ed elf/x86-64: Adjust R_AMD64_DIR64/R_AMD64_DIR32 for PE/x86-64 inputs adds 18bfb5057f [gdb/testsuite] Require is_amd64_regs_target in gdb.base/dis [...] adds d546b61084 Implement a workaround for GNU mak jobserver adds 5291fe3cd1 aarch64: Add support for bfloat16 in gdb. adds b2f2ae0d6f gdb: remove pre_init_ui_hook from top.c adds 3f94e58859 [gdb/testsuite] Add have_mpx in lib/gdb.exp adds 16e9019ef7 gdb: move baud_rate and serial_parity declarations to serial.h adds fe7a351a8e gdb: move read{now,never}_symbol_files declarations to symfile.h adds 24a7f1b548 gdb: fix indentation in infrun.c adds 3034143dc6 src-release: fix indentation adds 4180301e81 Automatic date update in version.in adds 62fe7512a7 sim: watch: fix pc watchpoints on little endian host systems adds c54f3efdc2 sim: watch: fix range expression processing adds 2ce40d1a51 Add SEH support to code generated by dlltool. adds 8c4645b488 Remove sflag_info param from wild callback functions adds b209b5a6b8 SHF_LINK_ORDER fixup_link_order in ld adds 5347ed60c5 Regen Makefile.in for jobserver.m4 aclocal.m4 dependency adds 844bf810cf x86: Don't generate GOT_symbol for PLT relocations adds b634d11d61 ld: Check for ELF input before accessing ELF section data adds 54ca900277 gdb: convert jit to new-style debug macros adds 5e12f48ffb gdb: bool-ify file_is_auto_load_safe adds db972fce46 gdb: bool-ify ext_lang_auto_load_enabled and friends adds 5bf7e91b2b gdb: bool-ify users of file_is_auto_load_safe adds 506195754c gdb: bool-ify maybe_add_script_{text,file} adds fb0f5031bb gdb: turn arc_debug into a bool adds d8d1feb424 gdb: convert arc to new-style debug macros adds 4120e4885b Re: SHF_LINK_ORDER fixup_link_order in ld adds 3eeabe12c3 Automatic date update in version.in adds c9d220893e gdb: make the remote target track its own thread resume state adds bd497355ea gdb: remove target_ops::commit_resume implementation in reco [...] adds 8f66807b98 gdb: better handling of 'S' packets adds d9b1deff13 sim: watch: add basic default handler that traps adds 54780889e9 sim: h8300: drop separate eightbit memory buffer adds adb0bd8fda gas: bfin: fix build time warnings adds abad28152e gas: bfin: build lexer with -Werror adds 271bea6acd ld: tests: add -msim when testing bfin targets adds 7e0d77ef5f Fix an illegal memory access parsing a win32pstatus note wit [...] adds 116d0cf103 [gdb/testsuite] Fix gdb.base/style.exp with -m32 adds 5fae2a2c66 [gdb/breakpoint] Handle .plt.sec in in_plt_section adds 5a10699ff3 Updated translations for some subdirectories adds 8ca9c7eb67 bfin: Skip non SEC_ALLOC section for R_BFIN_FUNCDESC adds 58eadc4b69 Fix building gdb with gcc-4.x adds c14dee84dd Update my email address (long overdue!) adds 17e8913732 Add myself to gdb/MAINTAINERS adds 5aa06b1b14 Automatic date update in version.in adds 5fda40b28f gas: make [248]byte directives available everywhere adds 3624a6c15c PR26539, memory leak in inflate.c adds 37a9c3a53e sim: testsuite: allow tests to declare expected exit status adds 7cf91a2481 sim: m32r: clean up redundant test coverage adds 89bfc2a429 sim: frv: clean up redundant test coverage adds 137d6efd8a sim: mips: delete empty stub test dir adds 29fd199ed8 sim: d10v: relocate tests & clean up test harness adds bb3eddb5bd sim: testsuite: delete configure script adds dcd709e056 RISC-V: Comments tidy and improvement. adds b800637e76 RISC-V: Error and warning messages tidy. adds 1942a04836 RISC-V: Indent and GNU coding standards tidy, also aligned t [...] adds 4bb5732e27 RISC-V: Fixed the indent that caused by the previous commits [...] adds 10f92414d6 [gdb/testsuite] Fix gdb.fortran/array-slices.exp with -m32 adds 5a11fff005 gdb/tui: compare pointer to nullptr, not 0 adds e403a898b5 Automatic date update in version.in adds 1368b914e9 sim: testsuite: flatten tree adds eb6e6af8c1 PR26002 undefined symbol VER_NDX_GLOBAL vs. VER_NDX_LOCAL adds ad92f33d38 Tidy inflateEnd calls adds 68b007788a ld/x86: Add -z report-relative-reloc adds 75a933f399 ld/elf/x86: Don't compare IFUNC address in the shared object adds 514fca98df Automatic date update in version.in adds edf0f284b1 PR binutils/23460: Increase the max number of open files to 20 adds d46153313b Automatic date update in version.in adds 25294ff049 gold: Remove the circular IFUNC dependency in ifuncmain6pie adds 994b251328 ld/elf: Ignore section symbols when matching linkonce with comdat adds 44365e88c0 PR27198, segv in S_IS_WEAK adds cecb191290 gdb: const-ify unpack_* functions in remote.c adds e3b2741b16 gdb: const-ify remote_target::add_current_inferior_and_threa [...] adds b5c8f22d28 gdb: move remote_target::start_remote variable to narrower scope adds aa2838ccc5 gdb: const-ify hostio methods parameter in remote.c adds d3d7d1ba3b [gdb/tdep] Handle si_addr_bnd in compat_siginfo_from_siginfo adds 326adec374 PR26378, sections initialised only by linker scripts are alw [...] adds 6a9ad81c44 gdb/riscv: use a single regset supply function for riscv fbs [...] adds 705989f19a as: Automatically enable DWARF5 support adds 02baa13385 gdb/testsuite: remove actual addresses from some test names adds 4cfcd3b333 sim: common: modernize gennltvals.sh adds 5e25901fcc sim: common: delete configure & Makefile adds f89f33e57c sim: common: simplify version script adds f0c1efa53d Automatic date update in version.in adds 85e963f185 ld: Just xfail riscv little endian targets for compressed1d.d test. adds 0e7620dcdc sim: bfin: delete accidental ADI copyright adds a75a6a4164 [GOLD] powerpc assertion failure No new revisions were added by this update. Summary of changes: ChangeLog | 54 + Makefile.in | 68 +- Makefile.tpl | 63 +- bfd/ChangeLog | 141 + bfd/Makefile.in | 1 + bfd/aclocal.m4 | 1 + bfd/bfd-in2.h | 7 +- bfd/compress.c | 3 +- bfd/configure | 73 +- bfd/configure.ac | 2 + bfd/doc/Makefile.in | 1 + bfd/elf-linker-x86.h | 3 + bfd/elf.c | 5 +- bfd/elf32-bfin.c | 235 +- bfd/elf32-i386.c | 36 + bfd/elf64-x86-64.c | 33 + bfd/elflink.c | 194 +- bfd/elfnn-riscv.c | 319 +- bfd/elfxx-riscv.c | 54 +- bfd/elfxx-riscv.h | 4 +- bfd/elfxx-x86.c | 72 +- bfd/elfxx-x86.h | 4 + bfd/po/bfd.pot | 2574 +-- bfd/po/fr.po | 2666 +-- bfd/po/pt.po | 2681 ++-- bfd/po/sr.po | 2687 ++-- bfd/po/uk.po | 2666 +-- bfd/reloc.c | 7 + bfd/section.c | 7 +- bfd/version.h | 2 +- bfd/version.m4 | 2 +- binutils/BRANCHES | 1 + binutils/ChangeLog | 73 + binutils/MAINTAINERS | 6 +- binutils/Makefile.in | 1 + binutils/NEWS | 2 + binutils/README-how-to-make-a-release | 40 +- binutils/aclocal.m4 | 1 + binutils/configure | 73 +- binutils/configure.ac | 2 + binutils/dlltool.c | 50 +- binutils/doc/Makefile.in | 1 + binutils/po/binutils.pot | 3317 ++-- binutils/po/fr.po | 3826 +++-- binutils/po/pt.po | 3943 ++--- binutils/po/sr.po | 3845 +++-- binutils/po/sv.po | 3804 +++-- binutils/po/uk.po | 3840 +++-- binutils/readelf.c | 8 +- config/ChangeLog | 19 + config/gcc-plugin.m4 | 40 + config/jobserver.m4 | 24 + configure | 246 +- configure.ac | 84 + cpu/ChangeLog | 4 + elfcpp/ChangeLog | 4 + gas/ChangeLog | 139 + gas/Makefile.am | 4 +- gas/Makefile.in | 5 +- gas/NEWS | 10 +- gas/aclocal.m4 | 1 + gas/config/bfin-lex.l | 5 +- gas/config/obj-elf.c | 4 - gas/config/tc-aarch64.c | 31 - gas/config/tc-i386.c | 42 +- gas/config/tc-riscv.c | 521 +- gas/config/tc-riscv.h | 6 +- gas/configure | 73 +- gas/configure.ac | 2 + gas/doc/Makefile.in | 1 + gas/doc/as.texi | 7 - gas/doc/c-aarch64.texi | 2 - gas/dwarf2dbg.c | 24 +- gas/po/fr.po | 7239 ++++----- gas/po/gas.pot | 2131 +-- gas/po/uk.po | 7237 ++++----- gas/read.c | 3 + gas/testsuite/gas/aarch64/csre-invalid.d | 3 - gas/testsuite/gas/aarch64/csre-invalid.s | 6 - gas/testsuite/gas/aarch64/csre.d | 29 - gas/testsuite/gas/aarch64/csre_csr-invalid.d | 3 - gas/testsuite/gas/aarch64/csre_csr-invalid.l | 2 - gas/testsuite/gas/aarch64/csre_csr-invalid.s | 4 - gas/testsuite/gas/aarch64/csre_csr.d | 10 - gas/testsuite/gas/aarch64/csre_csr.s | 4 - gas/testsuite/gas/elf/dwarf-5-file0.d | 2 +- gas/testsuite/gas/i386/i386.exp | 5 + gas/testsuite/gas/i386/no-got.d | 17 + gas/testsuite/gas/i386/no-got.s | 5 + gas/testsuite/gas/i386/pr27198.d | 2 + gas/testsuite/gas/i386/pr27198.err | 5 + gas/testsuite/gas/i386/pr27198.s | 1 + gas/testsuite/gas/i386/x86-64-no-got.d | 17 + gas/testsuite/gas/i386/x86-64-no-got.s | 5 + gas/testsuite/gas/lns/lns-diag-1.l | 2 - gas/testsuite/gas/ppc/ppc.exp | 2 + gas/testsuite/gas/ppc/rop-checks.d | 3 + gas/testsuite/gas/ppc/rop-checks.l | 17 + gas/testsuite/gas/ppc/rop-checks.s | 18 + gas/testsuite/gas/ppc/rop.d | 27 + gas/testsuite/gas/ppc/rop.s | 21 + gas/testsuite/gas/riscv/priv-reg-fail-fext.l | 6 +- .../gas/riscv/priv-reg-fail-read-only-01.l | 136 +- .../gas/riscv/priv-reg-fail-read-only-02.l | 48 +- gas/testsuite/gas/riscv/priv-reg-fail-rv32-only.l | 130 +- .../gas/riscv/priv-reg-fail-version-1p10.l | 48 +- .../gas/riscv/priv-reg-fail-version-1p11.l | 46 +- .../gas/riscv/priv-reg-fail-version-1p9p1.l | 54 +- gdb/ChangeLog | 244 + gdb/MAINTAINERS | 1 + gdb/aarch64-tdep.c | 94 +- gdb/arc-linux-nat.c | 16 +- gdb/arc-linux-tdep.c | 43 +- gdb/arc-newlib-tdep.c | 11 +- gdb/arc-tdep.c | 151 +- gdb/arc-tdep.h | 7 +- gdb/arch/aarch64-insn.c | 9 +- gdb/arch/aarch64-insn.h | 5 + gdb/auto-load.c | 82 +- gdb/auto-load.h | 16 +- gdb/compile/compile.c | 4 +- gdb/copyright.py | 2 +- gdb/expprint.c | 9 +- gdb/expression.h | 3 +- gdb/extension-priv.h | 2 +- gdb/extension.c | 7 +- gdb/extension.h | 5 +- gdb/f-exp.y | 36 +- gdb/features/aarch64-fpu.c | 5 + gdb/features/aarch64-fpu.xml | 2 + gdb/guile/guile-internal.h | 5 +- gdb/guile/scm-auto-load.c | 5 +- gdb/infrun.c | 2 +- gdb/jit.c | 80 +- gdb/main.c | 1 + gdb/nat/amd64-linux-siginfo.c | 13 + gdb/objfiles.h | 3 +- gdb/parse.c | 15 +- gdb/printcmd.c | 10 +- gdb/python/py-auto-load.c | 5 +- gdb/python/python-internal.h | 5 +- gdb/record-btrace.c | 11 - gdb/record-full.c | 10 - gdb/remote.c | 412 +- gdb/riscv-fbsd-tdep.c | 20 +- gdb/riscv-linux-tdep.c | 4 +- gdb/riscv-tdep.c | 50 + gdb/riscv-tdep.h | 23 + gdb/serial.c | 7 +- gdb/serial.h | 8 + gdb/solib-aix.c | 23 +- gdb/symfile.c | 10 +- gdb/symfile.h | 8 + gdb/target.h | 6 - gdb/testsuite/ChangeLog | 79 + gdb/testsuite/gdb.ada/voidctx.exp | 40 + gdb/testsuite/gdb.ada/voidctx/pck.adb | 27 + gdb/testsuite/gdb.ada/voidctx/pck.ads | 23 + gdb/testsuite/gdb.ada/voidctx/voidctx.adb | 31 + gdb/testsuite/gdb.arch/aarch64-fp.exp | 25 + gdb/testsuite/gdb.arch/amd64-stap-three-arg-disp.S | 5 +- gdb/testsuite/gdb.arch/i386-mpx-call.c | 78 +- gdb/testsuite/gdb.arch/i386-mpx-call.exp | 17 +- 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sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_s1.s (100%) rename sim/testsuite/{sim => }/bfin/c_cc_regmvlogi_mvbrsft_sn.S (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_a0a1.S (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_dr_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_dr_imm3_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_imm3_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccflag_pr_pr_uu.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_dr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_cc_pr_pr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_dr.s (100%) rename sim/testsuite/{sim => }/bfin/c_ccmv_ncc_dr_pr.s (100%) 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sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_add_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_n.s (100%) rename sim/testsuite/{sim => }/bfin/c_compi2opp_pr_eq_i7_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imgebl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lnz_imltbl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodik_lz_inc_dec.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imgebl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lnz_imltbl.s (100%) rename sim/testsuite/{sim => }/bfin/c_dagmodim_lz_inc_dec.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0_pm_a1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a0a1s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_abs_a.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_a_neg_a.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_aa_absabs.s (100%) rename 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(100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_r_lh_a0pa1.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_r_negneg.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd12_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd12_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd20_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rh_rnd20_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd12_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd12_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd20_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rl_rnd20_p.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rlh_rnd.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rmp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rpp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rr_lph_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpm_aa.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrpmmp_sft_x.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_rrppmm_sft_x.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_saa.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sat_aa.S (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_search.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32alu_sgn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_iuw32.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_a1a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_i.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_ih.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_is.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_iu.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_m.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_s.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_t.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32mac_dr_a0_tu.s (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/bfin/c_dsp32shift_bitmux.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_bxor.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_h.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_l.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expadj_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_expexp_r.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fdepx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_fextx.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lf.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_ln.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_lp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rn.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhalf_rp.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lhh.s (100%) rename sim/testsuite/{sim => }/bfin/c_dsp32shift_lmix.s (100%) rename sim/testsuite/{sim => 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=> }/bfin/c_except_illopcode.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_sys_sstep.S (100%) rename sim/testsuite/{sim => }/bfin/c_except_user_mode.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_disable_enable.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_excpt.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_loopsetup_stld.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nested.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_nmi.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_pending_2.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_reload.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tcount.S (100%) rename sim/testsuite/{sim => }/bfin/c_interr_timer_tscale.S (100%) rename sim/testsuite/{sim => }/bfin/c_ldimmhalf_dreg.s (100%) rename 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(100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_brcc_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_call_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex1_raise_j_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_brcc_mp_mv_pop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_mmr_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_mmrj_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_raise_mmr_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex2_raise_mmrj_mvpop.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_brcc_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmr_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_ls_mmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_ex3_raise_ls_mmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_cs_lsmmrj_mvp.S (100%) rename sim/testsuite/{sim => }/bfin/c_seq_wb_raisecs_lsmmrj_mvp.S (100%) rename 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(100%) rename sim/testsuite/{sim => }/cr16/loadmp.cgs (100%) rename sim/testsuite/{sim => }/cr16/loadw.cgs (100%) rename sim/testsuite/{sim => }/cr16/lpr-spr.cgs (100%) rename sim/testsuite/{sim => }/cr16/lprd-sprd.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshb.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshb_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshd.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshd_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshw.cgs (100%) rename sim/testsuite/{sim => }/cr16/lshw_i.cgs (100%) rename sim/testsuite/{sim => }/cr16/macqw.cgs (100%) rename sim/testsuite/{sim => }/cr16/macsw.cgs (100%) rename sim/testsuite/{sim => }/cr16/macuw.cgs (100%) rename sim/testsuite/{sim => }/cr16/misc.exp (100%) rename sim/testsuite/{sim => }/cr16/movb.cgs (100%) rename sim/testsuite/{sim => }/cr16/movd.cgs (100%) rename sim/testsuite/{sim => }/cr16/movw.cgs (100%) rename sim/testsuite/{sim => }/cr16/movxb.cgs (100%) rename sim/testsuite/{sim => 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(100%) rename sim/testsuite/{sim => }/cr16/subb.cgs (100%) rename sim/testsuite/{sim => }/cr16/subd.cgs (100%) rename sim/testsuite/{sim => }/cr16/subi.cgs (100%) rename sim/testsuite/{sim => }/cr16/subw.cgs (100%) rename sim/testsuite/{sim => }/cr16/tbit.cgs (100%) rename sim/testsuite/{sim => }/cr16/tbitb.cgs (100%) rename sim/testsuite/{sim => }/cr16/tbitw.cgs (100%) rename sim/testsuite/{sim => }/cr16/testutils.inc (100%) rename sim/testsuite/{sim => }/cr16/uread16.ms (100%) rename sim/testsuite/{sim => }/cr16/uread32.ms (100%) rename sim/testsuite/{sim => }/cr16/xorb.cgs (100%) rename sim/testsuite/{sim => }/cr16/xord.cgs (100%) rename sim/testsuite/{sim => }/cr16/xorw.cgs (100%) create mode 100644 sim/testsuite/cris/ChangeLog rename sim/testsuite/{sim => }/cris/asm/abs.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addcpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/addcv32c.ms (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/cris/asm/andr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/asm.exp (100%) rename sim/testsuite/{sim => }/cris/asm/asr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ba.ms (100%) rename sim/testsuite/{sim => }/cris/asm/badarch1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bare1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bare2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bare3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bas.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bccb.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bdapc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bdapm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bdapq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/bdapqpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/biap.ms (100%) rename sim/testsuite/{sim => }/cris/asm/boundc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/boundm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/boundmv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/boundr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/break.ms (100%) rename sim/testsuite/{sim => }/cris/asm/btst.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ccr-v10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ccs-v32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/clearfv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/clearfv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/clrjmp1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpxc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/cmpxm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/dflags.ms (100%) rename sim/testsuite/{sim => }/cris/asm/dip.ms (100%) rename sim/testsuite/{sim => }/cris/asm/dstep.ms (100%) rename sim/testsuite/{sim => }/cris/asm/fidxd.ms (100%) rename sim/testsuite/{sim => }/cris/asm/fidxi.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ftagd.ms (100%) rename sim/testsuite/{sim => }/cris/asm/ftagi.ms (100%) rename sim/testsuite/{sim => }/cris/asm/halt.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io4.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io5.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io6.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io7.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io8.ms (100%) rename sim/testsuite/{sim => }/cris/asm/io9.ms (100%) rename sim/testsuite/{sim => }/cris/asm/jsr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/jsrmv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/jumpmp.ms (100%) rename sim/testsuite/{sim => }/cris/asm/jumppv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/lapc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/lsl.ms (100%) rename sim/testsuite/{sim => }/cris/asm/lsr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/lz.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mcp.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movdelsr1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movecpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movecr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movecrt10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movecrt32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movect10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movei.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movempc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movemr.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movemrv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movemrv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movepcb.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movepcd.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movepcw.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moveq.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moveqpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mover.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverbpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverdpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverm.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverpcb.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverpcd.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverpcw.ms (100%) rename sim/testsuite/{sim => }/cris/asm/moverwpc.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movesmp.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movmp.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movmp8.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movpmv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movpmv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/movppc.ms (100%) rename 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}/cris/asm/mstep.ms (100%) rename sim/testsuite/{sim => }/cris/asm/msteppc1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/msteppc2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/msteppc3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mulv10.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mulv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/mulx.ms (100%) rename sim/testsuite/{sim => }/cris/asm/neg.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nonvcv32.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv10t.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv32t.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv32t2.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv32t3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/nopv32t4.ms (100%) rename sim/testsuite/{sim => }/cris/asm/not.ms (100%) rename sim/testsuite/{sim => }/cris/asm/op3.ms (100%) rename sim/testsuite/{sim => }/cris/asm/opterr1.ms (100%) rename sim/testsuite/{sim => }/cris/asm/opterr2.ms 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rename sim/testsuite/{sim => }/frv/fr550/cmqmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqmachu.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmqsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmsubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/cmsubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/dcpl.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/dcul.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mabshs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhss.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/maddhus.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/masaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/frv/fr550/udiv.cgs (100%) rename sim/testsuite/{sim => }/frv/fr550/udivi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrtd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsqrts.cgs (100%) rename sim/testsuite/{sim => }/frv/fstoi.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubd.cgs (100%) rename sim/testsuite/{sim => }/frv/fsubs.cgs (100%) rename sim/testsuite/{sim => }/frv/fteq.cgs (100%) rename sim/testsuite/{sim => }/frv/ftge.cgs (100%) rename sim/testsuite/{sim => }/frv/ftgt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftieq.cgs (100%) rename sim/testsuite/{sim => }/frv/ftige.cgs (100%) rename sim/testsuite/{sim => }/frv/ftigt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftile.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilg.cgs (100%) rename sim/testsuite/{sim => }/frv/ftilt.cgs (100%) rename sim/testsuite/{sim => }/frv/ftine.cgs (100%) rename sim/testsuite/{sim => }/frv/ftino.cgs (100%) rename sim/testsuite/{sim => }/frv/ftio.cgs (100%) rename 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sim/testsuite/frv/grloop.ms create mode 100644 sim/testsuite/frv/hello.ms rename sim/testsuite/{sim => }/frv/icei.cgs (100%) rename sim/testsuite/{sim => }/frv/ici.cgs (100%) rename sim/testsuite/{sim => }/frv/icpl.cgs (100%) rename sim/testsuite/{sim => }/frv/icul.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts.exp (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr400.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/Ipipe-fr500.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/badalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/compound.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/data_store_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/fp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/illinsn.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error-fr550.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/insn_access_error.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/mp_exception.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/privileged_instruction.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/regalign.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/reset.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/shadow_regs.cgs (100%) rename sim/testsuite/{sim => }/frv/interrupts/timer.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpil.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.cgs (100%) rename sim/testsuite/{sim => }/frv/jmpl.pcgs (100%) rename sim/testsuite/{sim => }/frv/ld.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldbfi.cgs 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sim/testsuite/{sim => }/frv/ldqc.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqcu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqf.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqfu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldqu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsb.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsbu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldsh.cgs (100%) rename sim/testsuite/{sim => }/frv/ldshi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldshu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldu.cgs (100%) rename sim/testsuite/{sim => }/frv/ldub.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubi.cgs (100%) rename sim/testsuite/{sim => }/frv/ldubu.cgs (100%) rename sim/testsuite/{sim => }/frv/lduh.cgs (100%) rename sim/testsuite/{sim => }/frv/lduhi.cgs (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/frv/mcpxru.cgs (100%) rename sim/testsuite/{sim => }/frv/mcut.cgs (100%) rename sim/testsuite/{sim => }/frv/mcuti.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutss.cgs (100%) rename sim/testsuite/{sim => }/frv/mcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdaddaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdasaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdcutssi.cgs (100%) rename sim/testsuite/{sim => }/frv/mdpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/mdrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mdsubaccs.cgs (100%) rename sim/testsuite/{sim => }/frv/mdunpackh.cgs (100%) rename sim/testsuite/{sim => }/frv/membar.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhd.cgs (100%) rename sim/testsuite/{sim => }/frv/mexpdhw.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdseth.cgs (100%) rename sim/testsuite/{sim => }/frv/mhdsets.cgs (100%) rename sim/testsuite/{sim => }/frv/mhsethih.cgs (100%) rename sim/testsuite/{sim => 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sim/testsuite/{sim => }/frv/mqmulxhu.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsaths.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqsrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmachs.cgs (100%) rename sim/testsuite/{sim => }/frv/mqxmacxhs.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdacc.cgs (100%) rename sim/testsuite/{sim => }/frv/mrdaccg.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotli.cgs (100%) rename sim/testsuite/{sim => }/frv/mrotri.cgs (100%) rename sim/testsuite/{sim => }/frv/msaths.cgs (100%) rename sim/testsuite/{sim => }/frv/msathu.cgs (100%) rename sim/testsuite/{sim => }/frv/msllhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrahi.cgs (100%) rename sim/testsuite/{sim => }/frv/msrlhi.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhss.cgs (100%) rename sim/testsuite/{sim => }/frv/msubhus.cgs (100%) rename sim/testsuite/{sim => }/frv/mtrap.cgs (100%) rename sim/testsuite/{sim => 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