Tcwg-commits August 2020

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[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3 updated (47251582f5c -> 466590192b4)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3 in repository toolchain/ci/llvm-project. from 47251582f5c [SimplifyCFG] Cost required selects adds 33bb80bc7a6 [X86] ia32intrin.h - pull out common attributes into define [...] adds 18bc400f97a [NewPM][PassInstrumentation] Add PreservedAnalyses paramete [...] adds 90e0a021291 [Attributor][NFC] run update_test_checks with --check-attributes. adds 98de0d22f57 [AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy adds f7e4e87df34 [DSE,MemorySSA] Regenerate check lines for atomic.ll tests. adds c6863a4ab8b [X86] Enable constexpr on POPCNT intrinsics (PR31446) adds 0819a6416fd [SelectionDAG] Better legalization for FSHL and FSHR adds 5d7c5a5e997 [NFC] Port InstCount pass to new pass manager adds 9f7350672e3 [DSE,MemorySSA] Handle atomicrmw/cmpxchg conservatively. adds c8e6bf0a65f [X86] Enable constexpr on BSWAP intrinsics (PR31446) adds c66b82f14cc [llvm-readelf] - Start recognizing 'PT_OPENBSD_*' segment types. adds 5bd1febe214 [AMDGPU] Fix alignment requirements for 96bit and 128bit lo [...] adds f5cd7ec9f3f [AMDGPU] Reorganize GCN subtarget features for unaligned access adds d17ea67b92f [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores adds 0654ff703d4 [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag adds 9e6c09c0d99 [RISCV] Fix inaccurate annotations on PseudoBRIND adds 9ffc412e1af [X86] Enable constexpr on BITSCAN intrinsics (PR31446) adds 1dd85e9d0e0 [NFC] Add SimplifyCFG for ARM adds f5643dc3dce Recommit: [DWARFYAML] Add support for referencing different [...] adds b4889353207 [clangd] Discard diagnostics from another SourceManager. adds 3f7985e6ec2 [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax des [...] adds 519b0e3e9d6 [PowerPC] Pre-commit FISel with PC-Rel test adds aa456a6df49 [llvm-readobj/elf] - Refine the code for broken PT_DYNAMIC [...] adds 57903cf0933 [compiler-rt][RISCV] Use muldi3 builtin assembly implementation adds 88dd7c85497 [llvm-readelf][test] - Refine the merged.test adds bfc6d8b59b7 [NFC][SimplifyCFG] Formatting and variable rename adds 88818491b9d [LoopIdiom,LSR] Add additional tests for SCEVExpander cleanups. adds a4c3ed42ba5 Correctly emit dwoIDs after ASTFileSignature refactoring (D81347) adds 466590192b4 [AST][RecoveryExpr] Fix a bogus unused diagnostic when the [...] No new revisions were added by this update. Summary of changes: clang-tools-extra/clangd/Diagnostics.cpp | 16 +- clang-tools-extra/clangd/Diagnostics.h | 4 +- .../clangd/unittests/ModulesTests.cpp | 28 + clang/docs/ReleaseNotes.rst | 14 +- clang/include/clang/Basic/Module.h | 9 + clang/lib/AST/Expr.cpp | 2 + clang/lib/CodeGen/CGDebugInfo.cpp | 9 +- .../CodeGen/ObjectFilePCHContainerOperations.cpp | 6 +- clang/lib/Headers/ia32intrin.h | 70 +- clang/test/CodeGen/bitscan-builtins.c | 41 +- clang/test/CodeGen/popcnt-builtins.c | 14 + clang/test/CodeGen/x86-bswap.c | 26 +- clang/test/Modules/Inputs/DebugDwoId.h | 4 + clang/test/Modules/Inputs/module.map | 4 + clang/test/Modules/ModuleDebugInfoDwoId.cpp | 20 + clang/test/SemaCXX/recovery-expr-type.cpp | 11 + compiler-rt/lib/builtins/CMakeLists.txt | 5 +- llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst | 1569 +++++----- llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst | 6 +- llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst | 272 +- llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst | 926 +++--- llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst | 1065 ++++--- llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst | 6 +- llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst | 6 +- .../{gfx10_src32_3.rst => gfx1011_src32_2.rst} | 4 +- .../{gfx10_src32_2.rst => gfx1011_src32_3.rst} | 4 +- llvm/docs/AMDGPU/gfx10_addr_mimg.rst | 2 +- llvm/docs/AMDGPU/gfx10_attr.rst | 1 - llvm/docs/AMDGPU/gfx10_bimm16.rst | 1 - llvm/docs/AMDGPU/gfx10_bimm32.rst | 1 - llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst | 2 +- llvm/docs/AMDGPU/gfx10_fimm16.rst | 1 - llvm/docs/AMDGPU/gfx10_fimm32.rst | 1 - llvm/docs/AMDGPU/gfx10_hwreg.rst | 1 - llvm/docs/AMDGPU/gfx10_label.rst | 1 - llvm/docs/AMDGPU/gfx10_mad_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst | 1 - llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx10_opt.rst | 1 - llvm/docs/AMDGPU/gfx10_param.rst | 1 - llvm/docs/AMDGPU/gfx10_perm_smem.rst | 1 - llvm/docs/AMDGPU/gfx10_ret.rst | 1 - llvm/docs/AMDGPU/gfx10_sdata64_0.rst | 2 +- llvm/docs/AMDGPU/gfx10_sdst64_0.rst | 2 +- llvm/docs/AMDGPU/gfx10_sdst64_1.rst | 2 +- llvm/docs/AMDGPU/gfx10_simm16.rst | 1 - llvm/docs/AMDGPU/gfx10_src32_1.rst | 2 +- llvm/docs/AMDGPU/gfx10_src32_2.rst | 2 +- llvm/docs/AMDGPU/gfx10_src32_3.rst | 2 +- .../{gfx10_src32_2.rst => gfx10_src32_4.rst} | 2 +- .../{gfx10_src32_2.rst => gfx10_src32_5.rst} | 4 +- .../{gfx10_src32_3.rst => gfx10_src32_6.rst} | 2 +- llvm/docs/AMDGPU/gfx10_ssrc64_0.rst | 2 +- llvm/docs/AMDGPU/gfx10_ssrc64_1.rst | 2 +- llvm/docs/AMDGPU/gfx10_tgt.rst | 1 - llvm/docs/AMDGPU/gfx10_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx10_uimm16.rst | 1 - llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst | 2 - llvm/docs/AMDGPU/gfx10_vcc_32.rst | 1 - llvm/docs/AMDGPU/gfx10_waitcnt.rst | 1 - llvm/docs/AMDGPU/gfx7_attr.rst | 1 - llvm/docs/AMDGPU/gfx7_bimm16.rst | 1 - llvm/docs/AMDGPU/gfx7_bimm32.rst | 1 - .../{gfx10_sdata64_0.rst => gfx7_dst_buf_32.rst} | 10 +- llvm/docs/AMDGPU/gfx7_fimm32.rst | 1 - llvm/docs/AMDGPU/gfx7_hwreg.rst | 1 - llvm/docs/AMDGPU/gfx7_label.rst | 1 - llvm/docs/AMDGPU/gfx7_mod.rst | 1 - llvm/docs/AMDGPU/gfx7_opt.rst | 1 - llvm/docs/AMDGPU/gfx7_param.rst | 1 - llvm/docs/AMDGPU/gfx7_ret.rst | 1 - llvm/docs/AMDGPU/gfx7_simm16.rst | 1 - llvm/docs/AMDGPU/gfx7_tgt.rst | 1 - llvm/docs/AMDGPU/gfx7_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx7_uimm16.rst | 1 - llvm/docs/AMDGPU/gfx7_waitcnt.rst | 1 - llvm/docs/AMDGPU/gfx8_attr.rst | 1 - llvm/docs/AMDGPU/gfx8_bimm16.rst | 1 - llvm/docs/AMDGPU/gfx8_bimm32.rst | 1 - .../{gfx10_sdata64_0.rst => gfx8_dst_buf_32.rst} | 10 +- llvm/docs/AMDGPU/gfx8_fimm16.rst | 1 - llvm/docs/AMDGPU/gfx8_fimm32.rst | 1 - llvm/docs/AMDGPU/gfx8_hwreg.rst | 1 - llvm/docs/AMDGPU/gfx8_imask.rst | 1 - llvm/docs/AMDGPU/gfx8_label.rst | 1 - llvm/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx8_mod_sdwa_sext.rst | 1 - llvm/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx8_opt.rst | 1 - llvm/docs/AMDGPU/gfx8_param.rst | 1 - llvm/docs/AMDGPU/gfx8_perm_smem.rst | 1 - llvm/docs/AMDGPU/gfx8_ret.rst | 1 - llvm/docs/AMDGPU/gfx8_simm16.rst | 1 - llvm/docs/AMDGPU/gfx8_src32_1.rst | 2 +- llvm/docs/AMDGPU/gfx8_src32_2.rst | 2 +- llvm/docs/AMDGPU/gfx8_src32_3.rst | 2 +- .../AMDGPU/{gfx8_src32_2.rst => gfx8_src32_4.rst} | 2 +- .../AMDGPU/{gfx8_src32_3.rst => gfx8_src32_5.rst} | 2 +- .../AMDGPU/{gfx8_src32_2.rst => gfx8_src32_6.rst} | 4 +- .../AMDGPU/{gfx8_src32_3.rst => gfx8_src32_7.rst} | 4 +- llvm/docs/AMDGPU/gfx8_tgt.rst | 1 - llvm/docs/AMDGPU/gfx8_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx8_uimm16.rst | 1 - llvm/docs/AMDGPU/gfx8_waitcnt.rst | 1 - llvm/docs/AMDGPU/gfx900_mad_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx900_mod_vop3_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx900_src32_0.rst | 2 +- llvm/docs/AMDGPU/gfx900_src32_1.rst | 2 +- llvm/docs/AMDGPU/gfx904_mad_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx904_mod_vop3_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx904_src32_0.rst | 2 +- llvm/docs/AMDGPU/gfx904_src32_1.rst | 2 +- llvm/docs/AMDGPU/gfx906_mad_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx906_mod_dpp_sdwa_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx906_mod_sdwa_sext.rst | 1 - llvm/docs/AMDGPU/gfx906_mod_vop3_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx906_src32_0.rst | 2 +- llvm/docs/AMDGPU/gfx906_src32_1.rst | 2 +- llvm/docs/AMDGPU/gfx906_src32_2.rst | 2 +- .../{gfx9_src32_2.rst => gfx906_src32_3.rst} | 4 +- .../{gfx9_src32_3.rst => gfx906_src32_4.rst} | 4 +- llvm/docs/AMDGPU/gfx906_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx908_mad_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx908_mod_dpp_sdwa_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx908_mod_sdwa_sext.rst | 1 - llvm/docs/AMDGPU/gfx908_mod_vop3_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx908_offset_buf.rst | 2 +- llvm/docs/AMDGPU/gfx908_opt.rst | 1 - llvm/docs/AMDGPU/gfx908_ret.rst | 1 - llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst | 2 +- llvm/docs/AMDGPU/gfx908_src32_0.rst | 2 +- llvm/docs/AMDGPU/gfx908_src32_1.rst | 2 +- llvm/docs/AMDGPU/gfx908_src32_2.rst | 2 +- llvm/docs/AMDGPU/gfx908_src32_3.rst | 2 +- .../{gfx9_src32_2.rst => gfx908_src32_4.rst} | 4 +- .../{gfx9_src32_3.rst => gfx908_src32_5.rst} | 4 +- llvm/docs/AMDGPU/gfx908_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst | 2 - llvm/docs/AMDGPU/gfx9_attr.rst | 1 - llvm/docs/AMDGPU/gfx9_bimm16.rst | 1 - llvm/docs/AMDGPU/gfx9_bimm32.rst | 1 - llvm/docs/AMDGPU/gfx9_fimm16.rst | 1 - llvm/docs/AMDGPU/gfx9_fimm32.rst | 1 - llvm/docs/AMDGPU/gfx9_hwreg.rst | 1 - llvm/docs/AMDGPU/gfx9_imask.rst | 1 - llvm/docs/AMDGPU/gfx9_label.rst | 1 - llvm/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx9_mod_sdwa_sext.rst | 1 - llvm/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx9_opt.rst | 1 - llvm/docs/AMDGPU/gfx9_param.rst | 1 - llvm/docs/AMDGPU/gfx9_perm_smem.rst | 1 - llvm/docs/AMDGPU/gfx9_ret.rst | 1 - llvm/docs/AMDGPU/gfx9_simm16.rst | 1 - llvm/docs/AMDGPU/gfx9_src32_1.rst | 2 +- llvm/docs/AMDGPU/gfx9_src32_2.rst | 2 +- llvm/docs/AMDGPU/gfx9_src32_3.rst | 2 +- .../AMDGPU/{gfx9_src32_2.rst => gfx9_src32_4.rst} | 2 +- .../AMDGPU/{gfx9_src32_3.rst => gfx9_src32_5.rst} | 2 +- .../AMDGPU/{gfx9_src32_2.rst => gfx9_src32_6.rst} | 4 +- .../AMDGPU/{gfx9_src32_3.rst => gfx9_src32_7.rst} | 4 +- llvm/docs/AMDGPU/gfx9_tgt.rst | 1 - llvm/docs/AMDGPU/gfx9_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx9_uimm16.rst | 1 - llvm/docs/AMDGPU/gfx9_vaddr_flat_global.rst | 2 - llvm/docs/AMDGPU/gfx9_waitcnt.rst | 1 - llvm/docs/AMDGPUInstructionNotation.rst | 2 +- llvm/docs/AMDGPUInstructionSyntax.rst | 6 +- llvm/docs/AMDGPUModifierSyntax.rst | 211 +- llvm/docs/AMDGPUOperandSyntax.rst | 17 +- llvm/include/llvm/Analysis/CGSCCPassManager.h | 10 +- llvm/include/llvm/Analysis/InstCount.h | 28 + llvm/include/llvm/IR/PassInstrumentation.h | 14 +- llvm/include/llvm/IR/PassManager.h | 9 +- llvm/include/llvm/InitializePasses.h | 2 +- llvm/include/llvm/ObjectYAML/DWARFYAML.h | 7 + .../llvm/Transforms/Scalar/LoopPassManager.h | 6 +- llvm/lib/Analysis/Analysis.cpp | 2 +- llvm/lib/Analysis/CGSCCPassManager.cpp | 4 +- llvm/lib/Analysis/InstCount.cpp | 87 +- llvm/lib/CodeGen/MachinePassManager.cpp | 2 +- .../CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp | 73 + llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 5 + .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 8 + .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 58 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 12 + llvm/lib/IR/PassTimingInfo.cpp | 8 +- llvm/lib/ObjectYAML/DWARFEmitter.cpp | 26 +- llvm/lib/ObjectYAML/DWARFYAML.cpp | 29 + llvm/lib/Passes/PassBuilder.cpp | 1 + llvm/lib/Passes/PassRegistry.def | 1 + llvm/lib/Passes/StandardInstrumentations.cpp | 8 +- llvm/lib/Target/AMDGPU/AMDGPU.td | 34 +- llvm/lib/Target/AMDGPU/AMDGPUGISel.td | 4 + llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 67 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 24 +- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 10 +- llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 9 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 6 +- .../Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp | 6 +- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 6 +- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h | 25 +- llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h | 2 +- llvm/lib/Target/AMDGPU/DSInstructions.td | 76 +- llvm/lib/Target/AMDGPU/R600ISelLowering.cpp | 2 +- llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 6 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 90 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 10 +- llvm/lib/Target/AMDGPU/SIInstrInfo.h | 2 +- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 22 +- llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 2 +- llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp | 2 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 2 +- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 73 +- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 1 - llvm/lib/Target/RISCV/RISCVInstrInfo.td | 1 - llvm/lib/Target/RISCV/RISCVInstrInfoB.td | 42 +- .../lib/Transforms/Scalar/DeadStoreElimination.cpp | 5 + llvm/lib/Transforms/Scalar/LoopPassManager.cpp | 4 +- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 13 +- llvm/test/CodeGen/AArch64/funnel-shift-rot.ll | 24 +- llvm/test/CodeGen/AArch64/funnel-shift.ll | 80 +- llvm/test/CodeGen/AArch64/shift-by-signext.ll | 20 +- .../GlobalISel/inst-select-load-local-128.mir | 147 +- .../AMDGPU/GlobalISel/legalize-load-local.mir | 226 +- .../CodeGen/AMDGPU/GlobalISel/load-constant.96.ll | 8 +- .../CodeGen/AMDGPU/GlobalISel/load-local.128.ll | 300 ++ .../CodeGen/AMDGPU/GlobalISel/load-local.96.ll | 260 ++ .../CodeGen/AMDGPU/GlobalISel/load-unaligned.ll | 252 ++ .../CodeGen/AMDGPU/GlobalISel/store-local.128.ll | 301 ++ .../CodeGen/AMDGPU/GlobalISel/store-local.96.ll | 262 ++ llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll | 10 +- llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll | 2 +- .../CodeGen/AMDGPU/ds-combine-with-dependence.ll | 6 +- llvm/test/CodeGen/AMDGPU/ds_read2.ll | 5 +- llvm/test/CodeGen/AMDGPU/ds_write2.ll | 11 +- .../AMDGPU/fast-unaligned-load-store.global.ll | 6 +- llvm/test/CodeGen/AMDGPU/fshl.ll | 274 +- llvm/test/CodeGen/AMDGPU/fshr.ll | 968 +++--- .../AMDGPU/insert-subvector-unused-scratch.ll | 6 +- llvm/test/CodeGen/AMDGPU/lds-misaligned-bug.ll | 22 +- llvm/test/CodeGen/AMDGPU/load-local-f32.ll | 10 +- llvm/test/CodeGen/AMDGPU/load-local-i16.ll | 12 +- llvm/test/CodeGen/AMDGPU/load-local-i32.ll | 5 +- llvm/test/CodeGen/AMDGPU/load-local-i8.ll | 6 +- llvm/test/CodeGen/AMDGPU/load-local.128.ll | 378 +++ llvm/test/CodeGen/AMDGPU/load-local.96.ll | 331 ++ llvm/test/CodeGen/AMDGPU/store-local.128.ll | 422 +++ llvm/test/CodeGen/AMDGPU/store-local.96.ll | 370 +++ llvm/test/CodeGen/AMDGPU/store-local.ll | 5 +- llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll | 2 +- .../AMDGPU/llc-target-cpu-attr-from-cmdline-ir.mir | 6 +- .../AMDGPU/llc-target-cpu-attr-from-cmdline.mir | 4 +- llvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll | 73 + llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll | 2 +- llvm/test/CodeGen/PowerPC/funnel-shift.ll | 29 +- llvm/test/CodeGen/RISCV/blockaddress.ll | 4 - llvm/test/CodeGen/RISCV/codemodel-lowering.ll | 16 +- llvm/test/CodeGen/RISCV/indirectbr.ll | 8 - llvm/test/CodeGen/RISCV/rv32Zbbp.ll | 34 +- llvm/test/CodeGen/RISCV/rv32Zbt.ll | 467 ++- llvm/test/CodeGen/RISCV/rv64Zbbp.ll | 6 +- llvm/test/CodeGen/RISCV/rv64Zbt.ll | 53 +- llvm/test/CodeGen/X86/fshl.ll | 137 +- llvm/test/CodeGen/X86/fshr.ll | 118 +- llvm/test/CodeGen/X86/funnel-shift.ll | 175 +- llvm/test/CodeGen/X86/vector-fshl-128.ll | 3301 ++++++++++---------- llvm/test/CodeGen/X86/vector-fshl-256.ll | 2543 ++++++++------- llvm/test/CodeGen/X86/vector-fshl-512.ll | 1550 ++++----- llvm/test/CodeGen/X86/vector-fshl-rot-128.ll | 28 +- llvm/test/CodeGen/X86/vector-fshr-128.ll | 3231 +++++++++---------- llvm/test/CodeGen/X86/vector-fshr-256.ll | 2417 +++++++------- llvm/test/CodeGen/X86/vector-fshr-512.ll | 1390 +++++---- llvm/test/CodeGen/X86/vector-fshr-rot-128.ll | 126 +- llvm/test/CodeGen/X86/vector-fshr-rot-256.ll | 94 +- llvm/test/CodeGen/X86/vector-fshr-rot-512.ll | 148 +- llvm/test/ObjectYAML/MachO/DWARF-debug_abbrev.yaml | 71 +- llvm/test/ObjectYAML/MachO/DWARF-debug_info.yaml | 227 ++ llvm/test/ObjectYAML/MachO/DWARF5-debug_info.yaml | 3 + .../Attributor/ArgumentPromotion/X86/attributes.ll | 14 +- .../X86/min-legal-vector-width.ll | 50 +- .../Attributor/ArgumentPromotion/X86/thiscall.ll | 2 +- .../Transforms/DeadStoreElimination/MSSA/atomic.ll | 228 +- .../AMDGPU/adjust-alloca-alignment.ll | 8 +- .../LoadStoreVectorizer/AMDGPU/merge-stores.ll | 5 +- .../LoadStoreVectorizer/AMDGPU/multiple_tails.ll | 34 +- .../expander-do-not-delete-reused-values.ll | 64 + .../X86/expander-reused-value-insert-point.ll | 65 + .../Transforms/SimplifyCFG/ARM/phi-eliminate.ll | 453 +++ .../llvm-readobj/ELF/malformed-pt-dynamic.test | 65 +- llvm/test/tools/llvm-readobj/ELF/merged.test | 52 +- .../tools/llvm-readobj/ELF/program-headers.test | 12 +- .../tools/yaml2obj/ELF/DWARF/debug-abbrev.yaml | 25 + llvm/test/tools/yaml2obj/ELF/DWARF/debug-info.yaml | 101 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 15 +- llvm/tools/obj2yaml/dwarf2yaml.cpp | 10 + .../DebugInfo/DWARF/DWARFDebugInfoTest.cpp | 1 + llvm/unittests/IR/PassBuilderCallbacksTest.cpp | 76 +- llvm/unittests/IR/TimePassesTest.cpp | 6 +- 300 files changed, 16050 insertions(+), 11775 deletions(-) create mode 100644 clang/test/Modules/Inputs/DebugDwoId.h create mode 100644 clang/test/Modules/ModuleDebugInfoDwoId.cpp copy llvm/docs/AMDGPU/{gfx10_src32_3.rst => gfx1011_src32_2.rst} (86%) copy llvm/docs/AMDGPU/{gfx10_src32_2.rst => gfx1011_src32_3.rst} (82%) copy llvm/docs/AMDGPU/{gfx10_src32_2.rst => gfx10_src32_4.rst} (96%) copy llvm/docs/AMDGPU/{gfx10_src32_2.rst => gfx10_src32_5.rst} (82%) copy llvm/docs/AMDGPU/{gfx10_src32_3.rst => gfx10_src32_6.rst} (96%) copy llvm/docs/AMDGPU/{gfx10_sdata64_0.rst => gfx7_dst_buf_32.rst} (59%) copy llvm/docs/AMDGPU/{gfx10_sdata64_0.rst => gfx8_dst_buf_32.rst} (59%) copy llvm/docs/AMDGPU/{gfx8_src32_2.rst => gfx8_src32_4.rst} (96%) copy llvm/docs/AMDGPU/{gfx8_src32_3.rst => gfx8_src32_5.rst} (96%) copy llvm/docs/AMDGPU/{gfx8_src32_2.rst => gfx8_src32_6.rst} (89%) copy llvm/docs/AMDGPU/{gfx8_src32_3.rst => gfx8_src32_7.rst} (85%) copy llvm/docs/AMDGPU/{gfx9_src32_2.rst => gfx906_src32_3.rst} (89%) copy llvm/docs/AMDGPU/{gfx9_src32_3.rst => gfx906_src32_4.rst} (85%) copy llvm/docs/AMDGPU/{gfx9_src32_2.rst => gfx908_src32_4.rst} (89%) copy llvm/docs/AMDGPU/{gfx9_src32_3.rst => gfx908_src32_5.rst} (85%) copy llvm/docs/AMDGPU/{gfx9_src32_2.rst => gfx9_src32_4.rst} (96%) copy llvm/docs/AMDGPU/{gfx9_src32_3.rst => gfx9_src32_5.rst} (96%) copy llvm/docs/AMDGPU/{gfx9_src32_2.rst => gfx9_src32_6.rst} (89%) copy llvm/docs/AMDGPU/{gfx9_src32_3.rst => gfx9_src32_7.rst} (85%) create mode 100644 llvm/include/llvm/Analysis/InstCount.h create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.128.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/load-local.96.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/load-unaligned.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll create mode 100644 llvm/test/CodeGen/AMDGPU/load-local.128.ll create mode 100644 llvm/test/CodeGen/AMDGPU/load-local.96.ll create mode 100644 llvm/test/CodeGen/AMDGPU/store-local.128.ll create mode 100644 llvm/test/CodeGen/AMDGPU/store-local.96.ll create mode 100644 llvm/test/CodeGen/PowerPC/fast-isel-pcrel.ll create mode 100644 llvm/test/Transforms/LoopIdiom/expander-do-not-delete-reused-values.ll create mode 100644 llvm/test/Transforms/LoopStrengthReduce/X86/expander-reused-val [...] create mode 100644 llvm/test/Transforms/SimplifyCFG/ARM/phi-eliminate.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3 updated (ee4f7cf5 -> 871e8bd9)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3 in repository toolchain/ci/base-artifacts. from ee4f7cf5 3: reset: llvm-47251582f5c2ac5962f52bc6ddd3d612c56ab83d: 1 new 871e8bd9 4: update: llvm-466590192b4202ceb294eb82f881193d013dc90c: 1 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 97 +- 02-prepare_abe/console.log | 48 +- 03-build_abe-binutils/console.log | 10105 +-- 04-build_abe-stage1/console.log | 15325 ++-- 05-build_abe-linux/console.log | 92 +- 06-build_abe-glibc/console.log | 34594 ++++----- 07-build_abe-stage2/console.log | 35538 ++++----- 08-build_llvm-true/console.log | 13159 ++-- 10-benchmark--O3/benchmark-start.log | 2 +- 10-benchmark--O3/benchmark.log | 4 +- 10-benchmark--O3/console.log | 500 +- 11-check_regression/console.log | 2518 +- 11-check_regression/extra-bisect-params | 2 +- 11-check_regression/results-0.csv | 2163 +- 11-check_regression/results-1.csv | 2161 +- 11-check_regression/results-brief.csv | 38 +- 11-check_regression/results-compare.csv | 10 +- 11-check_regression/results-full.csv | 2299 +- 11-check_regression/results.csv | 160 +- 11-check_regression/results.log | 2496 +- 11-check_regression/results.regressions | 2 - 11-check_regression/trigger-bisect | 4 - 12-update_baseline/console.log | 3751 +- 12-update_baseline/results-1.csv | 2161 +- 12-update_baseline/results-brief.csv | 38 +- 12-update_baseline/results-compare.csv | 6 +- 12-update_baseline/results-full.csv | 2161 +- 12-update_baseline/results.csv | 160 +- 12-update_baseline/results.log | 1828 +- 12-update_baseline/results.regressions | 2 +- console.log | 115717 +++++++++++++++-------------- jenkins/manifest.sh | 10 +- reset-baseline | 0 results | 2 - results_id | 2 +- 35 files changed, 124784 insertions(+), 122371 deletions(-) delete mode 100644 11-check_regression/results.regressions delete mode 100644 11-check_regression/trigger-bisect delete mode 100644 reset-baseline -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[gcc] branch releases/gcc-10 updated (ac4f77d2563 -> 2cbd82044b2)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch releases/gcc-10 in repository gcc. from ac4f77d2563 Fortran: Fix absent-optional handling for nondescriptor arr [...] new 2cbd82044b2 Refine expander vec_unpacku_float_hi_v16si/vec_unpacku_floa [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/i386/sse.md | 4 +-- gcc/testsuite/gcc.target/i386/avx512f-pr96551-1.c | 18 +++++++++++++ gcc/testsuite/gcc.target/i386/avx512f-pr96551-2.c | 33 +++++++++++++++++++++++ 3 files changed, 53 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-pr96551-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-pr96551-2.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 2 months

[gcc] branch master updated (39f5b724844 -> 1aa71af0935)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 39f5b724844 tree-cfg: Improve gimple switch verification new 1aa71af0935 Refine expander vec_unpacku_float_hi_v16si/vec_unpacku_floa [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/config/i386/sse.md | 4 +-- gcc/testsuite/gcc.target/i386/avx512f-pr96551-1.c | 18 +++++++++++++ gcc/testsuite/gcc.target/i386/avx512f-pr96551-2.c | 33 +++++++++++++++++++++++ 3 files changed, 53 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-pr96551-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx512f-pr96551-2.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[gcc] branch master updated (e11c4b7f837 -> 39f5b724844)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from e11c4b7f837 ipa/96806 - Fix ICE in ipa-cp due to integer addition overflow new 39f5b724844 tree-cfg: Improve gimple switch verification The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/tree-cfg.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[binutils-gdb] branch master updated (e2e82b115cc -> e840f2e3e2f)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from e2e82b115cc CSKY: Refine operand format error reporting. new e840f2e3e2f [gdb/testsuite] Add nopie to gdb.base/eh_return.exp The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/testsuite/ChangeLog | 4 ++++ gdb/testsuite/gdb.base/eh_return.exp | 3 ++- 2 files changed, 6 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[gcc] branch master updated (d0939f42dd8 -> e11c4b7f837)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from d0939f42dd8 testsuite: Update some vect cases for partial vectors new 0106300f6c3 varasm: Optimize memory broadcast for constant vector under [...] new e11c4b7f837 ipa/96806 - Fix ICE in ipa-cp due to integer addition overflow The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ipa-cp.c | 8 +- gcc/testsuite/g++.dg/ipa/pr96806.C | 53 +++++++++++ gcc/varasm.c | 181 ++++++++++++++++++++++++++++++++++++- 3 files changed, 237 insertions(+), 5 deletions(-) create mode 100644 gcc/testsuite/g++.dg/ipa/pr96806.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 2 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3_LTO updated (21f8d414689 -> 503deec2183)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3_LTO in repository toolchain/ci/llvm-project. from 21f8d414689 Refactor Reduction Tree Pass adds a54eb9b7c50 [Polly] Update isl to isl-0.22.1-416-g61d6dc75. adds c1bc4fb95e3 [lldb] Simplify CMake logic with LLVM's append_if function adds e0b220d22ee [lldb] Remove redundant call to FindBacktrace (NFC) adds 6ad3de350c4 [lldb] Fix a new -Wdocumetnation issues (NFC) adds 927da43ade1 Allow multiple calls to InitLLVM() (NFC) adds df9a9bb7beb [X86] Correct the implementation of the testFeature macro i [...] adds 91039784b3c [PowerPC] Add readflm/setflm intrinsics to Clang adds 2b69efded0d [ARM][LV] Add a preferPredicatedReductionSelect target hook adds acf0bb41e45 [ARM][CostModel] Select instruction costs. adds 85c15f17cc6 [SyntaxTree] Add support for `this` adds a0e92ffd0d6 [DSE,MemorySSA] Split off partial tracking from isOverwite. adds 80e9dd08784 [llvm-readobj] - Change how we create DynRegionInfo objects. NFCI. adds e1cd7cac8a3 [lldb] Tab completion for process load/unload adds 47251582f5c [SimplifyCFG] Cost required selects adds 33bb80bc7a6 [X86] ia32intrin.h - pull out common attributes into define [...] adds 18bc400f97a [NewPM][PassInstrumentation] Add PreservedAnalyses paramete [...] adds 90e0a021291 [Attributor][NFC] run update_test_checks with --check-attributes. adds 98de0d22f57 [AMDGPU] Apply llvm-prefer-register-over-unsigned from clang-tidy adds f7e4e87df34 [DSE,MemorySSA] Regenerate check lines for atomic.ll tests. adds c6863a4ab8b [X86] Enable constexpr on POPCNT intrinsics (PR31446) adds 0819a6416fd [SelectionDAG] Better legalization for FSHL and FSHR adds 5d7c5a5e997 [NFC] Port InstCount pass to new pass manager adds 9f7350672e3 [DSE,MemorySSA] Handle atomicrmw/cmpxchg conservatively. adds c8e6bf0a65f [X86] Enable constexpr on BSWAP intrinsics (PR31446) adds c66b82f14cc [llvm-readelf] - Start recognizing 'PT_OPENBSD_*' segment types. adds 5bd1febe214 [AMDGPU] Fix alignment requirements for 96bit and 128bit lo [...] adds f5cd7ec9f3f [AMDGPU] Reorganize GCN subtarget features for unaligned access adds d17ea67b92f [AMDGPU][GlobalISel] Fix 96 and 128 local loads and stores adds 0654ff703d4 [AMDGPU] Use ds_read/write_b96/b128 when possible for SDag adds 9e6c09c0d99 [RISCV] Fix inaccurate annotations on PseudoBRIND adds 9ffc412e1af [X86] Enable constexpr on BITSCAN intrinsics (PR31446) adds 1dd85e9d0e0 [NFC] Add SimplifyCFG for ARM adds f5643dc3dce Recommit: [DWARFYAML] Add support for referencing different [...] adds b4889353207 [clangd] Discard diagnostics from another SourceManager. adds 3f7985e6ec2 [AMDGPU][MC][NFC][DOC] Updated AMD GPU assembler syntax des [...] adds 519b0e3e9d6 [PowerPC] Pre-commit FISel with PC-Rel test adds aa456a6df49 [llvm-readobj/elf] - Refine the code for broken PT_DYNAMIC [...] adds 57903cf0933 [compiler-rt][RISCV] Use muldi3 builtin assembly implementation adds 88dd7c85497 [llvm-readelf][test] - Refine the merged.test adds bfc6d8b59b7 [NFC][SimplifyCFG] Formatting and variable rename adds 88818491b9d [LoopIdiom,LSR] Add additional tests for SCEVExpander cleanups. adds a4c3ed42ba5 Correctly emit dwoIDs after ASTFileSignature refactoring (D81347) adds 466590192b4 [AST][RecoveryExpr] Fix a bogus unused diagnostic when the [...] adds 36dbb8fc972 [SVE] Lower fixed length UDIV to scalable adds 8eded24bf46 Recommit "[SCEVExpander] Add helper to clean up instrs inse [...] adds c1dd5df4255 Revert "Correctly emit dwoIDs after ASTFileSignature refact [...] adds 1beb11c61ae [SyntaxTree] Use annotations in Statement tests adds a0818689213 [AIX][XCOFF] emit symbol visibility for xcoff object file. adds 365f861c45b [PowerPC][PCRelative] Thread Local Storage Support for Init [...] adds bc72a3ab949 [Constants] Handle FNeg in getWithOperands. adds 72d0f094898 [gn build] Port 57903cf0933 -- https://reviews.llvm.org/rG5 [...] adds 7a527f17776 Teach AttachPreviousImpl to inherit MSInheritanceAttr attribute adds 2799031a143 [lldb] Skip PDB and NativePDB tests with reproducers adds 7ed3286a512 [LibFuzzer] [tests] [Darwin] Use the pthread library from the SDK adds 58c305f466d Revert "Teach AttachPreviousImpl to inherit MSInheritanceAt [...] adds 63d9d56a554 [InstCombine] Move handling of gc.relocate in a gc.statepoint adds 8831e34771f Revert "[libFuzzer] Fix arguments of InsertPartOf/CopyPartO [...] adds 50aae463315 Update my email address. adds 08249d7f72f [lldb] Fix TestAPILog.py for reproducer replay adds 36ee9a322a4 [mlir][GPUToVulkan] Fix signature of bindMemRef function for f16 adds 02e02f5398d [LLD][PowerPC] Add check in LLD to produce an error for mis [...] adds 670063eb220 Preserve the error message when MemoryBuffer creation fails adds a5b7b8cce02 [PowerPC] Support constrained scalar sitofp/uitofp adds cc62373915f [ASan][Darwin] Enable test on additional platforms adds 57e0ef131b6 [lldb] Make it a fatal error when %lldb cannot be substituted adds 0cadd162b7c Forgot to update the test case for ppc64-tls-missing-gdld.s [...] adds 06cad825cdd PrintStackTrace: don't symbolize if LLVM_DISABLE_SYMBOLIZAT [...] adds cf6adecd6a8 [llvm-mca][NFC] Refactor views to separate data collection [...] adds 9e362bb0eb5 [InstCombine] Remove unused entries in gc-live bundle of st [...] adds aca191cce1c Re-land 7a527f17776be78ec44b88e82b39afb65fc148e4 with fixes. adds 9a9a092e61d [AMDGPU] Avoid sorting stalls in regbank-reassign adds c0ec37ee65d [docs] Move the label for __builtin_shufflevector below __b [...] adds 5e3fd471acb [Cloning] Fix to cloning DISubprograms. adds e21a22a7a8b [Attributor] fix AANoUndef initialization adds 52e758f352e [lldb] Fix build error in TestSimulatorPlatform.py adds 7ea0ee30588 [DomTree] Avoid creating an empty GD to reduce compile time. adds 65fcc0ee318 [Attributor] Function seed allow list adds b37db11d95d MachineSSAUpdater: Allow initialization with just a register class adds b79889c2b14 [opt][NewPM] Add basic-aa in legacy PM compatibility mode adds e0c01e6cb07 New TableGen Programmer's Reference document adds 17cd34409a3 Fix two bugs in TGParser::ParseValue adds d3a49b03a57 [lldb] Remove --rerun-all-issues as its functionality no lo [...] adds 5eff21c8ff2 [NFC][documentation] clarify comment in test adds 503deec2183 Temporairly revert "[SimplifyCFG][LoopRotate] SimplifyCFG: [...] No new revisions were added by this update. Summary of changes: clang-tools-extra/clangd/Diagnostics.cpp | 16 +- clang-tools-extra/clangd/Diagnostics.h | 4 +- .../clangd/unittests/ModulesTests.cpp | 28 + clang/docs/LanguageExtensions.rst | 4 +- clang/docs/ReleaseNotes.rst | 14 +- clang/include/clang/Basic/BuiltinsPPC.def | 6 + clang/include/clang/Tooling/Syntax/Nodes.h | 11 + clang/lib/AST/Expr.cpp | 2 + clang/lib/Headers/ia32intrin.h | 70 +- clang/lib/Serialization/ASTReaderDecl.cpp | 22 + clang/lib/Tooling/Syntax/BuildTree.cpp | 10 + clang/lib/Tooling/Syntax/Nodes.cpp | 7 + clang/test/CodeGen/bitscan-builtins.c | 41 +- clang/test/CodeGen/builtins-ppc.c | 9 + clang/test/CodeGen/constantexpr-fneg.c | 20 + clang/test/CodeGen/popcnt-builtins.c | 14 + clang/test/CodeGen/x86-bswap.c | 26 +- clang/test/Modules/Inputs/inherit-attribute/a.h | 10 + clang/test/Modules/Inputs/inherit-attribute/b.h | 5 + .../cycle => Modules/Inputs/inherit-attribute}/c.h | 0 .../Inputs/inherit-attribute/module.modulemap | 3 + clang/test/Modules/inherit-attribute.cpp | 20 + clang/test/SemaCXX/recovery-expr-type.cpp | 11 + clang/unittests/Tooling/Syntax/BuildTreeTest.cpp | 439 +- compiler-rt/lib/builtins/CMakeLists.txt | 5 +- compiler-rt/lib/builtins/cpu_model.c | 2 +- compiler-rt/lib/fuzzer/FuzzerMutate.cpp | 14 +- compiler-rt/lib/fuzzer/tests/CMakeLists.txt | 4 + .../test/asan/TestCases/Darwin/dead-strip.c | 4 +- compiler-rt/test/fuzzer/CrossOverTest.cpp | 15 +- compiler-rt/test/fuzzer/cross_over.test | 4 +- compiler-rt/test/fuzzer/cross_over_copy.test | 20 - compiler-rt/test/fuzzer/cross_over_insert.test | 20 - lld/ELF/Relocations.cpp | 26 +- lld/test/ELF/ppc64-tls-missing-gdld.s | 53 + lldb/cmake/modules/LLDBConfig.cmake | 36 +- lldb/include/lldb/Target/Process.h | 20 +- .../Python/lldbsuite/test/configuration.py | 3 - lldb/packages/Python/lldbsuite/test/dotest.py | 4 - lldb/packages/Python/lldbsuite/test/dotest_args.py | 10 - lldb/source/Commands/CommandObjectProcess.cpp | 29 + .../Plugins/TypeSystem/Clang/TypeSystemClang.h | 2 +- lldb/test/API/api/log/TestAPILog.py | 11 +- lldb/test/API/functionalities/completion/Makefile | 7 + .../functionalities/completion/TestCompletion.py | 25 + .../test/API/functionalities/completion/shared.cpp | 3 + .../API/macosx/simulator/TestSimulatorPlatform.py | 13 +- lldb/test/Shell/SymbolFile/NativePDB/lit.local.cfg | 2 + lldb/test/Shell/SymbolFile/PDB/lit.local.cfg | 2 + lldb/test/Shell/helper/toolchain.py | 6 +- llvm/CODE_OWNERS.TXT | 2 +- llvm/CREDITS.TXT | 2 +- llvm/docs/AMDGPU/AMDGPUAsmGFX10.rst | 1569 +- llvm/docs/AMDGPU/AMDGPUAsmGFX1011.rst | 6 +- llvm/docs/AMDGPU/AMDGPUAsmGFX7.rst | 272 +- llvm/docs/AMDGPU/AMDGPUAsmGFX8.rst | 926 +- llvm/docs/AMDGPU/AMDGPUAsmGFX9.rst | 1065 +- llvm/docs/AMDGPU/AMDGPUAsmGFX906.rst | 6 +- llvm/docs/AMDGPU/AMDGPUAsmGFX908.rst | 6 +- .../{gfx10_src32_3.rst => gfx1011_src32_2.rst} | 4 +- .../{gfx10_src32_2.rst => gfx1011_src32_3.rst} | 4 +- llvm/docs/AMDGPU/gfx10_addr_mimg.rst | 2 +- llvm/docs/AMDGPU/gfx10_attr.rst | 1 - llvm/docs/AMDGPU/gfx10_bimm16.rst | 1 - llvm/docs/AMDGPU/gfx10_bimm32.rst | 1 - llvm/docs/AMDGPU/gfx10_data_smem_atomic64.rst | 2 +- llvm/docs/AMDGPU/gfx10_fimm16.rst | 1 - llvm/docs/AMDGPU/gfx10_fimm32.rst | 1 - llvm/docs/AMDGPU/gfx10_hwreg.rst | 1 - llvm/docs/AMDGPU/gfx10_label.rst | 1 - llvm/docs/AMDGPU/gfx10_mad_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx10_mod_dpp_sdwa_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx10_mod_sdwa_sext.rst | 1 - llvm/docs/AMDGPU/gfx10_mod_vop3_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx10_opt.rst | 1 - llvm/docs/AMDGPU/gfx10_param.rst | 1 - llvm/docs/AMDGPU/gfx10_perm_smem.rst | 1 - llvm/docs/AMDGPU/gfx10_ret.rst | 1 - llvm/docs/AMDGPU/gfx10_sdata64_0.rst | 2 +- llvm/docs/AMDGPU/gfx10_sdst64_0.rst | 2 +- llvm/docs/AMDGPU/gfx10_sdst64_1.rst | 2 +- llvm/docs/AMDGPU/gfx10_simm16.rst | 1 - llvm/docs/AMDGPU/gfx10_src32_1.rst | 2 +- llvm/docs/AMDGPU/gfx10_src32_2.rst | 2 +- llvm/docs/AMDGPU/gfx10_src32_3.rst | 2 +- .../{gfx10_src32_2.rst => gfx10_src32_4.rst} | 2 +- .../{gfx10_src32_2.rst => gfx10_src32_5.rst} | 4 +- .../{gfx10_src32_3.rst => gfx10_src32_6.rst} | 2 +- llvm/docs/AMDGPU/gfx10_ssrc64_0.rst | 2 +- llvm/docs/AMDGPU/gfx10_ssrc64_1.rst | 2 +- llvm/docs/AMDGPU/gfx10_tgt.rst | 1 - llvm/docs/AMDGPU/gfx10_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx10_uimm16.rst | 1 - llvm/docs/AMDGPU/gfx10_vaddr_flat_global.rst | 2 - llvm/docs/AMDGPU/gfx10_vcc_32.rst | 1 - llvm/docs/AMDGPU/gfx10_waitcnt.rst | 1 - llvm/docs/AMDGPU/gfx7_attr.rst | 1 - llvm/docs/AMDGPU/gfx7_bimm16.rst | 1 - llvm/docs/AMDGPU/gfx7_bimm32.rst | 1 - .../{gfx10_sdata64_0.rst => gfx7_dst_buf_32.rst} | 10 +- llvm/docs/AMDGPU/gfx7_fimm32.rst | 1 - llvm/docs/AMDGPU/gfx7_hwreg.rst | 1 - llvm/docs/AMDGPU/gfx7_label.rst | 1 - llvm/docs/AMDGPU/gfx7_mod.rst | 1 - llvm/docs/AMDGPU/gfx7_opt.rst | 1 - llvm/docs/AMDGPU/gfx7_param.rst | 1 - llvm/docs/AMDGPU/gfx7_ret.rst | 1 - llvm/docs/AMDGPU/gfx7_simm16.rst | 1 - llvm/docs/AMDGPU/gfx7_tgt.rst | 1 - llvm/docs/AMDGPU/gfx7_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx7_uimm16.rst | 1 - llvm/docs/AMDGPU/gfx7_waitcnt.rst | 1 - llvm/docs/AMDGPU/gfx8_attr.rst | 1 - llvm/docs/AMDGPU/gfx8_bimm16.rst | 1 - llvm/docs/AMDGPU/gfx8_bimm32.rst | 1 - .../{gfx10_sdata64_0.rst => gfx8_dst_buf_32.rst} | 10 +- llvm/docs/AMDGPU/gfx8_fimm16.rst | 1 - llvm/docs/AMDGPU/gfx8_fimm32.rst | 1 - llvm/docs/AMDGPU/gfx8_hwreg.rst | 1 - llvm/docs/AMDGPU/gfx8_imask.rst | 1 - llvm/docs/AMDGPU/gfx8_label.rst | 1 - llvm/docs/AMDGPU/gfx8_mod_dpp_sdwa_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx8_mod_sdwa_sext.rst | 1 - llvm/docs/AMDGPU/gfx8_mod_vop3_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx8_opt.rst | 1 - llvm/docs/AMDGPU/gfx8_param.rst | 1 - llvm/docs/AMDGPU/gfx8_perm_smem.rst | 1 - llvm/docs/AMDGPU/gfx8_ret.rst | 1 - llvm/docs/AMDGPU/gfx8_simm16.rst | 1 - llvm/docs/AMDGPU/gfx8_src32_1.rst | 2 +- llvm/docs/AMDGPU/gfx8_src32_2.rst | 2 +- llvm/docs/AMDGPU/gfx8_src32_3.rst | 2 +- .../AMDGPU/{gfx8_src32_2.rst => gfx8_src32_4.rst} | 2 +- .../AMDGPU/{gfx8_src32_3.rst => gfx8_src32_5.rst} | 2 +- .../AMDGPU/{gfx8_src32_2.rst => gfx8_src32_6.rst} | 4 +- .../AMDGPU/{gfx8_src32_3.rst => gfx8_src32_7.rst} | 4 +- llvm/docs/AMDGPU/gfx8_tgt.rst | 1 - llvm/docs/AMDGPU/gfx8_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx8_uimm16.rst | 1 - llvm/docs/AMDGPU/gfx8_waitcnt.rst | 1 - llvm/docs/AMDGPU/gfx900_mad_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx900_mod_vop3_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx900_src32_0.rst | 2 +- llvm/docs/AMDGPU/gfx900_src32_1.rst | 2 +- llvm/docs/AMDGPU/gfx904_mad_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx904_mod_vop3_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx904_src32_0.rst | 2 +- llvm/docs/AMDGPU/gfx904_src32_1.rst | 2 +- llvm/docs/AMDGPU/gfx906_mad_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx906_mod_dpp_sdwa_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx906_mod_sdwa_sext.rst | 1 - llvm/docs/AMDGPU/gfx906_mod_vop3_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx906_src32_0.rst | 2 +- llvm/docs/AMDGPU/gfx906_src32_1.rst | 2 +- llvm/docs/AMDGPU/gfx906_src32_2.rst | 2 +- .../{gfx9_src32_2.rst => gfx906_src32_3.rst} | 4 +- .../{gfx9_src32_3.rst => gfx906_src32_4.rst} | 4 +- llvm/docs/AMDGPU/gfx906_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx908_mad_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx908_mod_dpp_sdwa_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx908_mod_sdwa_sext.rst | 1 - llvm/docs/AMDGPU/gfx908_mod_vop3_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx908_offset_buf.rst | 2 +- llvm/docs/AMDGPU/gfx908_opt.rst | 1 - llvm/docs/AMDGPU/gfx908_ret.rst | 1 - llvm/docs/AMDGPU/gfx908_saddr_flat_global.rst | 2 +- llvm/docs/AMDGPU/gfx908_src32_0.rst | 2 +- llvm/docs/AMDGPU/gfx908_src32_1.rst | 2 +- llvm/docs/AMDGPU/gfx908_src32_2.rst | 2 +- llvm/docs/AMDGPU/gfx908_src32_3.rst | 2 +- .../{gfx9_src32_2.rst => gfx908_src32_4.rst} | 4 +- .../{gfx9_src32_3.rst => gfx908_src32_5.rst} | 4 +- llvm/docs/AMDGPU/gfx908_type_dev.rst | 1 - llvm/docs/AMDGPU/gfx908_vaddr_flat_global.rst | 2 - llvm/docs/AMDGPU/gfx9_attr.rst | 1 - llvm/docs/AMDGPU/gfx9_bimm16.rst | 1 - llvm/docs/AMDGPU/gfx9_bimm32.rst | 1 - llvm/docs/AMDGPU/gfx9_fimm16.rst | 1 - llvm/docs/AMDGPU/gfx9_fimm32.rst | 1 - llvm/docs/AMDGPU/gfx9_hwreg.rst | 1 - llvm/docs/AMDGPU/gfx9_imask.rst | 1 - llvm/docs/AMDGPU/gfx9_label.rst | 1 - llvm/docs/AMDGPU/gfx9_mod_dpp_sdwa_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx9_mod_sdwa_sext.rst | 1 - llvm/docs/AMDGPU/gfx9_mod_vop3_abs_neg.rst | 1 - llvm/docs/AMDGPU/gfx9_opt.rst | 1 - llvm/docs/AMDGPU/gfx9_param.rst | 1 - llvm/docs/AMDGPU/gfx9_perm_smem.rst | 1 - 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polly/lib/External/isl/isl_pw_insert_domain_templ.c create mode 100644 polly/lib/External/isl/isl_pw_locals_templ.c create mode 100644 polly/lib/External/isl/isl_unbind_params_templ.c create mode 100644 polly/lib/External/isl/isl_union_locals_templ.c create mode 100644 polly/lib/External/isl/isl_union_pw_templ.c create mode 100644 polly/lib/External/isl/m4/ax_prog_cc_for_build.m4 create mode 100644 polly/lib/External/isl/m4/ax_prog_cxx_for_build.m4 create mode 100644 polly/lib/External/isl/test_inputs/schedule/niewang.sc create mode 100644 polly/lib/External/isl/test_inputs/schedule/niewang.st -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3_LTO updated (83dbf952 -> abd99bf0)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3_LTO in repository toolchain/ci/base-artifacts. from 83dbf952 4: update: binutils-gcc-glibc: 1 new abd99bf0 5: reset: llvm-503deec2183d466dad64b763bab4e15fd8804239: 1 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 132 +- 02-prepare_abe/console.log | 240 +- 03-build_abe-binutils/console.log | 11702 ++- 04-build_abe-stage1/console.log | 16004 ++-- 05-build_abe-linux/console.log | 226 +- 06-build_abe-glibc/console.log | 40278 +++++---- 07-build_abe-stage2/console.log | 38110 +++++---- 08-build_llvm-true/console.log | 13214 +-- 10-benchmark--O3_LTO/benchmark-start.log | 2 +- 10-benchmark--O3_LTO/benchmark.log | 6 +- 10-benchmark--O3_LTO/console.log | 172 +- 11-check_regression/console.log | 836 +- 11-check_regression/extra-bisect-params | 2 +- 11-check_regression/results-0.csv | 107 +- 11-check_regression/results-1.csv | 102 +- 11-check_regression/results-brief.csv | 38 +- 11-check_regression/results-compare.csv | 4 +- 11-check_regression/results-full.csv | 108 +- 11-check_regression/results.csv | 48 +- 11-check_regression/results.log | 2360 +- 11-check_regression/results.regressions | 2 + 11-check_regression/trigger-bisect | 4 + 12-update_baseline/console.log | 1589 +- 12-update_baseline/extra-bisect-params | 2 +- 12-update_baseline/results-0.csv | 106 +- 12-update_baseline/results-1.csv | 102 +- 12-update_baseline/results-brief.csv | 38 +- 12-update_baseline/results-compare.csv | 10 +- 12-update_baseline/results-full.csv | 112 +- 12-update_baseline/results.csv | 48 +- 12-update_baseline/results.log | 2504 +- 12-update_baseline/results.regressions | 3 +- console.log | 122573 ++++++++++++++-------------- jenkins/manifest.sh | 18 +- reset-baseline | 0 results | 2 + results_id | 2 +- 37 files changed, 123705 insertions(+), 127101 deletions(-) create mode 100644 11-check_regression/results.regressions create mode 100644 11-check_regression/trigger-bisect create mode 100644 reset-baseline -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 2 months

[toolchain/jenkins-scripts] branch master updated (73ab5ac9 -> 70b59f1a)

by Diana Picus

This is an automated email from the git hooks/post-receive script. "Diana Picus pushed a change to branch master in repository toolchain/jenkins-scripts. from 73ab5ac9 Increase memory allocation for build containers new 70b59f1a tcwg-llvm-release: Deal with flang and mlir The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: tcwg-llvm-release.sh | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 2 months

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