Tcwg-commits March 2020

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[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3 updated (083d644d42 -> 28b4928b1b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3 in repository toolchain/ci/glibc. from 083d644d42 test-container: print errno when execvp fails adds b7176cc2af ldconfig: trace origin paths with -v adds 2de7fe6253 parse_tunables: Fix typo in comment adds dcf46d3fe5 nscd: add cache dumper adds 4315f45c93 manual: Fix inconsistent declaration of wcsrchr [BZ #24655] adds 28b4928b1b Fix nscd/cachedumper.c compile errors No new revisions were added by this update. Summary of changes: elf/dl-tunables.c | 2 +- elf/ldconfig.c | 30 ++++- manual/string.texi | 2 +- nscd/Makefile | 2 +- nscd/cachedumper.c | 375 +++++++++++++++++++++++++++++++++++++++++++++++++++++ nscd/nscd.c | 13 ++ nscd/nscd.h | 2 + 7 files changed, 417 insertions(+), 9 deletions(-) create mode 100644 nscd/cachedumper.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 4 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3 updated (a0ae4cbe9d1 -> a475f153431)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3 in repository toolchain/ci/gcc. from a0ae4cbe9d1 maintainer-scripts: Fix jit documentation build with update [...] adds c56871dd15a maintainer-scripts: Fix up gcc_release without -l, where mk [...] adds daf2852b883 Support for the CPEN control register was removed in rev .5 [...] adds 4aded535ea6 Remove no-op register to register copies in CSE just like w [...] adds 54e69cb00da Daily bump. adds 82f620e2ba4 Fix unaligned load with small memcpy on the ARM adds 3e6ab5cefa8 Fix incorrect filling of delay slots in branchy code at -O2 adds dbf3dc75888 aarch64: Add --params to control the number of recip steps [...] adds fd8679974b2 i386: Use ix86_output_ssemov for DFmode TYPE_SSEMOV adds 7aa605c9d46 aarch64: Fix another bug in aarch64_add_offset_1 [PR94121] adds 43d513af3f2 [testsuite] Fix PR93935 to guard case under vect_hw_misalign adds 98ff89d1ac5 Do not strcat to result of getenv. adds 3604480a6fe tree-optimization/94163 constrain alignment set by PRE adds 80a13af724a c++: Redundant -Wdeprecated-declarations warning in build_o [...] adds 5c7e6d4bdf8 df: Don't abuse bb->aux (PR94148, PR94042) adds 9ae8bc02774 testsuite: Assorted x32 testsuite fixes adds f2e9fe5f97d PR c/94040 - ICE on a call to an invalid redeclaration of strftime adds 3b515f74841 Fix wrong year in ChangeLog. adds 45ee7a35f34 PR c/94040 - ICE on a call to an invalid redeclaration of strftime adds a4504f32c05 PR92303: Try to simplify memory subreg. adds db3fa3476e9 testsuite: Fix misquoted string in bfcvt-nosimd.c adds 5b74dd0a227 d/dmd: Merge upstream dmd e9420cfbf adds 5c048755ec9 analyzer: handle NOP_EXPR in get_lvalue [PR94099,PR94105] adds 50c96067c8e Fix UBSAN error, shifting 64 bit value by 64. adds 0034955eb16 Daily bump. adds 53b28abf8e4 Fix doubled indefinite articles, mostly in comments. adds 9a6408bd18f rs6000/test: Fix selector in fold-vec-mule-misc.c adds 6e5084b4401 libphobos: Merge upstream druntime 7915b6a3 adds c393c99d3dc c++: Fix CTAD with multiple-arg ctor template [93248]. adds b3b0c671cc3 c++: Find parameter pack in typedef in lambda [92909]. adds 3a285529ee3 c++: Fix ICE-after-error on partial spec [92068] adds 824722e45f8 i386: Use ix86_output_ssemov for DImode TYPE_SSEMOV adds 89769d70af2 Daily bump. adds 9c3cdb43c2b tree-nested: Fix handling of *reduction clauses with C arra [...] adds b408e010ccf driver: Fix redundant descriptions in options adds ced66da3135 coroutines: Fix indentation (NFC). adds 9d74caf21be i386: Use ix86_output_ssemov for SFmode TYPE_SSEMOV adds 5e5ce5371f6 Daily bump. adds e4e9a59105a Update post order number for merged SCC. adds 5ba25b2ef17 tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167] adds 6d44c881286 tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167] adds f2d3807f580 libphobos: Merge upstream druntime 6c45dd3a, phobos 68cc18adb. adds e41d4a0a567 d/dmd: Merge upstream dmd b061bd744 adds 5a3c42b227b i386: Use ix86_output_ssemov for SImode TYPE_SSEMOV adds 136fec1e27f x32 does not support MS ABI, skip testcases that require it. adds f19b40bd377 Fix ChangeLog formatting from my commit last friday. adds bc093503d74 libphobos: Reset libtool_VERSION to 1:0:0 adds 63c8f7d6a08 [ARM][GCC][1/x]: MVE ACLE intrinsics framework patch. adds c7be0832b54 [ARM][GCC][2/x]: MVE ACLE intrinsics framework patch. adds 5dee500b359 [ARM][GCC][3/x]: MVE ACLE intrinsics framework patch. adds f522810d2b5 [testsuite] Avoid duplicate test names in sizeless tests adds bae7b38cf8a Fix PR94185: Do not reuse insn alternative after changing m [...] adds c015ff8ccaf c: Handle MEM_REF in c_fully_fold* [PR94179] adds 447d196e75d d: Fix multiple definition error when using mixins and interfaces. adds c62f5e6e1f4 libstdc++: Add default constructor to net::service_already_ [...] adds 2691ffe6dba d: Fix assignment to anonymous union member corrupts siblin [...] adds b3f246f12b2 Daily bump. adds 950183c7741 Update gcc sv.po. adds 57e7ad5a8fd c++: Add test for PR 93901. adds ecf2b69a629 Filter a test-case with gas. adds 7afa3b82918 expand: Don't depend on warning flags in code generation of [...] adds 741ff2a263f strlen: Punt on UB reads past end of string literal [PR94187] adds fd857de8070 c: ignore initializers for elements of variable-size types [...] adds 994d4862062 testsuite: Fix pr94185.C testcase on i686-linux with C++98 [...] adds 14782c8123e [ARM][GCC][4/x]: MVE ACLE vector interleaving store intrinsics. adds a50f6abffc3 [ARM][GCC][1/1x]: Patch to support MVE ACLE intrinsics with [...] adds 5db0eb95c34 [ARM][GCC][2/1x]: MVE intrinsics with unary operand. adds a9a437ffc42 tree-ssa-strlen: Fix up count_nonzero_bytes* [PR94015] adds f582ca0fd70 [GCC][PATCH][ARM] Add multilib mapping for Armv8.1-M+MVE wi [...] adds 700d4cb08c8 Fix up duplicated duplicated words mostly in comments adds 6df4618cac9 [ARM][GCC][3/1x]: MVE intrinsics with unary operand. adds a475f153431 [ARM][GCC][4/1x]: MVE intrinsics with unary operand. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 865 +++++++++++ gcc/DATESTAMP | 2 +- gcc/analyzer/ChangeLog | 10 + gcc/analyzer/diagnostic-manager.cc | 5 +- gcc/analyzer/region-model.cc | 14 +- gcc/builtins.c | 22 +- gcc/c-family/ChangeLog | 9 + gcc/c-family/c-common.c | 2 +- gcc/c-family/c.opt | 22 +- gcc/c/ChangeLog | 13 + gcc/c/c-decl.c | 66 +- gcc/c/c-fold.c | 9 + gcc/c/c-typeck.c | 2 +- gcc/cfgexpand.c | 2 +- gcc/common.opt | 20 +- gcc/common/config/arm/arm-common.c | 3 +- gcc/config.gcc | 2 +- gcc/config/aarch64/aarch64-sve.md | 2 +- gcc/config/aarch64/aarch64.c | 13 +- gcc/config/aarch64/aarch64.opt | 9 + .../aarch64/falkor-tag-collision-avoidance.c | 2 +- gcc/config/arc/arc.c | 2 +- gcc/config/arc/arc.opt | 4 +- gcc/config/arm/aout.h | 6 +- gcc/config/arm/arm-builtins.c | 290 +++- gcc/config/arm/arm-c.c | 10 + gcc/config/arm/arm-cpus.in | 14 +- gcc/config/arm/arm-protos.h | 2 +- gcc/config/arm/arm.c | 294 +++- gcc/config/arm/arm.h | 69 +- gcc/config/arm/arm.md | 27 +- gcc/config/arm/arm_mve.h | 1585 ++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 78 + gcc/config/arm/constraints.md | 11 +- gcc/config/arm/iterators.md | 13 +- gcc/config/arm/mve.md | 689 +++++++++ gcc/config/arm/neon.md | 22 +- gcc/config/arm/predicates.md | 10 +- gcc/config/arm/t-arm | 5 +- gcc/config/arm/t-rmprofile | 13 +- gcc/config/arm/thumb2.md | 2 +- gcc/config/arm/types.md | 18 +- gcc/config/arm/unspecs.md | 2 +- gcc/config/arm/vec-common.md | 41 +- gcc/config/arm/vfp.md | 129 +- gcc/config/cr16/cr16.opt | 2 +- gcc/config/fr30/fr30.c | 2 +- gcc/config/gcn/gcn-run.c | 2 +- gcc/config/i386/i386-features.c | 2 +- gcc/config/i386/i386.c | 17 +- gcc/config/i386/i386.md | 126 +- gcc/config/i386/predicates.md | 5 - gcc/config/i386/x86-tune.def | 2 +- gcc/config/msp430/msp430.c | 2 +- gcc/config/nds32/nds32-md-auxiliary.c | 12 +- gcc/config/nvptx/nvptx.c | 2 +- gcc/config/rs6000/rs6000-c.c | 2 +- gcc/config/rs6000/rs6000-logue.c | 2 +- gcc/config/rs6000/rs6000-p8swap.c | 2 +- gcc/config/rs6000/rs6000-string.c | 2 +- gcc/config/rs6000/rs6000.c | 7 +- gcc/config/rx/rx.c | 1 - gcc/config/rx/rx.md | 1 - gcc/config/s390/s390.c | 2 +- gcc/cp/ChangeLog | 44 + gcc/cp/call.c | 5 + gcc/cp/coroutines.cc | 8 +- gcc/cp/logic.cc | 2 +- gcc/cp/name-lookup.c | 2 +- gcc/cp/parser.c | 12 +- gcc/cp/pt.c | 36 +- gcc/cse.c | 14 +- gcc/d/ChangeLog | 12 + gcc/d/decl.cc | 7 +- gcc/d/dmd/MERGE | 2 +- gcc/d/dmd/attrib.c | 189 ++- gcc/d/dmd/attrib.h | 9 +- gcc/d/dmd/cond.c | 333 +++- gcc/d/dmd/cond.h | 5 +- gcc/d/dmd/cppmangle.c | 2 +- gcc/d/dmd/declaration.c | 9 + gcc/d/dmd/dinterpret.c | 4 + gcc/d/dmd/dmangle.c | 1 + gcc/d/dmd/dsymbol.c | 100 +- gcc/d/dmd/dsymbol.h | 2 + gcc/d/dmd/expression.c | 10 + gcc/d/dmd/expression.h | 2 + gcc/d/dmd/expressionsem.c | 27 +- gcc/d/dmd/func.c | 4 +- gcc/d/dmd/hdrgen.c | 68 +- gcc/d/dmd/iasmgcc.c | 30 +- gcc/d/dmd/init.c | 2 +- gcc/d/dmd/intrange.c | 2 +- gcc/d/dmd/json.c | 4 + gcc/d/dmd/mtype.c | 152 +- gcc/d/dmd/mtype.h | 18 + gcc/d/dmd/parse.c | 304 ++-- gcc/d/dmd/parse.h | 3 + gcc/d/dmd/scope.h | 3 +- gcc/d/dmd/statement.c | 120 ++ gcc/d/dmd/statement.h | 9 +- gcc/d/dmd/statementsem.c | 581 ++++--- gcc/d/dmd/traits.c | 34 +- gcc/d/dmd/visitor.h | 4 + gcc/d/types.cc | 10 +- gcc/df-core.c | 35 +- gcc/doc/invoke.texi | 11 + gcc/doc/tm.texi | 4 +- gcc/dwarf2out.c | 2 +- gcc/expmed.c | 55 +- gcc/fortran/ChangeLog | 14 + gcc/fortran/arith.c | 2 +- gcc/fortran/array.c | 2 +- gcc/fortran/frontend-passes.c | 2 +- gcc/fortran/lang.opt | 2 +- gcc/fortran/module.c | 4 +- gcc/fortran/resolve.c | 2 +- gcc/fortran/trans-expr.c | 2 +- gcc/gimple-fold.c | 2 +- gcc/gimple-ssa-sprintf.c | 6 +- gcc/gimple-ssa-store-merging.c | 2 +- gcc/gimple-ssa-warn-restrict.c | 4 +- gcc/hsa-common.c | 2 +- gcc/hsa-common.h | 2 +- gcc/input.c | 4 +- gcc/ipa-param-manipulation.h | 2 +- gcc/ipa-prop.h | 2 +- gcc/ira-costs.c | 2 +- gcc/langhooks.h | 2 +- gcc/lra-spills.c | 21 +- gcc/lto-wrapper.c | 3 +- gcc/omp-grid.c | 2 +- gcc/po/ChangeLog | 4 + gcc/po/sv.po | 162 +- gcc/read-rtl-function.c | 6 +- gcc/reorg.c | 26 +- gcc/resource.c | 21 +- gcc/resource.h | 1 + gcc/rtl.c | 2 +- gcc/selftest.c | 2 +- gcc/shrink-wrap.c | 2 +- gcc/spellcheck.c | 2 +- gcc/target.def | 6 +- gcc/testsuite/ChangeLog | 364 +++++ .../g++.dg/cpp0x/lambda/lambda-variadic10.C | 12 + gcc/testsuite/g++.dg/cpp0x/noexcept57.C | 40 + gcc/testsuite/g++.dg/cpp0x/variadic178.C | 6 + gcc/testsuite/g++.dg/cpp1z/class-deduction71.C | 6 + gcc/testsuite/g++.dg/diagnostic/pr67960-2.C | 13 + gcc/testsuite/g++.dg/diagnostic/pr67960.C | 13 + gcc/testsuite/g++.target/i386/pr94185.C | 33 + gcc/testsuite/gcc.c-torture/compile/20200313-1.c | 14 + gcc/testsuite/gcc.c-torture/compile/pr90275.c | 27 + gcc/testsuite/gcc.c-torture/compile/pr94179.c | 9 + .../gcc.dg/Wbuiltin-declaration-mismatch-12.c | 4 +- .../gcc.dg/Wbuiltin-declaration-mismatch-14.c | 77 + .../gcc.dg/Wbuiltin-declaration-mismatch-15.c | 56 + gcc/testsuite/gcc.dg/analyzer/pr94099.c | 27 + gcc/testsuite/gcc.dg/analyzer/pr94105.c | 3 + gcc/testsuite/gcc.dg/lto/pr94157_0.c | 7 + gcc/testsuite/gcc.dg/pr62090.c | 2 + gcc/testsuite/gcc.dg/pr89314.c | 2 +- gcc/testsuite/gcc.dg/pr94015.c | 107 ++ gcc/testsuite/gcc.dg/pr94166.c | 24 + gcc/testsuite/gcc.dg/pr94167.c | 33 + gcc/testsuite/gcc.dg/pr94189.c | 11 + gcc/testsuite/gcc.dg/torture/pr54261-1.c | 14 +- gcc/testsuite/gcc.dg/tree-ssa/pr94125.c | 41 + gcc/testsuite/gcc.dg/vect/bb-slp-over-widen-2.c | 2 +- gcc/testsuite/gcc.misc-tests/help.exp | 2 +- .../aarch64/advsimd-intrinsics/bfcvt-nosimd.c | 2 +- .../aarch64/sve/acle/general-c/sizeless-1.c | 3 +- .../aarch64/sve/acle/general-c/sizeless-2.c | 3 +- gcc/testsuite/gcc.target/arm/multilib.exp | 3 + .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 14 + .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 14 + .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 14 + .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 14 + .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 12 + .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 67 + .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 67 + .../arm/mve/intrinsics/mve_vector_float.c | 27 + .../arm/mve/intrinsics/mve_vector_float1.c | 31 + .../arm/mve/intrinsics/mve_vector_float2.c | 27 + .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 49 + .../arm/mve/intrinsics/mve_vector_int1.c | 54 + .../arm/mve/intrinsics/mve_vector_int2.c | 49 + .../arm/mve/intrinsics/mve_vector_uint.c | 49 + .../arm/mve/intrinsics/mve_vector_uint1.c | 54 + .../arm/mve/intrinsics/mve_vector_uint2.c | 49 + .../gcc.target/arm/mve/intrinsics/vabsq_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vabsq_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vabsq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabsq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddlvq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddvq_s16.c | 22 + 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+ .../gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c | 14 + .../gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c | 14 + 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gcc/testsuite/gcc.target/i386/pr89229-6c.c | 6 + gcc/testsuite/gcc.target/i386/pr89229-7a.c | 17 + gcc/testsuite/gcc.target/i386/pr89229-7b.c | 6 + gcc/testsuite/gcc.target/i386/pr89229-7c.c | 7 + gcc/testsuite/gcc.target/i386/pr90096.c | 2 +- .../gcc.target/powerpc/fold-vec-mule-misc.c | 2 +- gcc/testsuite/gdc.dg/asm1.d | 9 + gcc/testsuite/gdc.dg/asm5.d | 12 + gcc/testsuite/gdc.dg/imports/pr92216.d | 22 + gcc/testsuite/gdc.dg/pr92216.d | 13 + gcc/testsuite/gdc.dg/pr92309.d | 25 + gcc/testsuite/gdc.test/compilable/b12001.d | 9 + gcc/testsuite/gdc.test/compilable/json.d | 21 + gcc/testsuite/gdc.test/compilable/staticforeach.d | 842 +++++++++++ gcc/testsuite/gdc.test/compilable/test11169.d | 15 + gcc/testsuite/gdc.test/compilable/test17819.d | 17 + gcc/testsuite/gdc.test/compilable/test18871.d | 15 + .../fail7815.d => compilable/test7815.d} | 6 +- gcc/testsuite/gdc.test/compilable/test7886.d | 5 + gcc/testsuite/gdc.test/fail_compilation/e7804_1.d | 11 + gcc/testsuite/gdc.test/fail_compilation/e7804_2.d | 19 + .../gdc.test/fail_compilation/fail11169.d | 28 - .../gdc.test/fail_compilation/fail19182.d | 18 + .../gdc.test/fail_compilation/fail19336.d | 17 + .../gdc.test/fail_compilation/fail19520.d | 21 + gcc/testsuite/gdc.test/fail_compilation/fail2195.d | 18 + gcc/testsuite/gdc.test/fail_compilation/fail7886.d | 5 - .../gdc.test/fail_compilation/staticforeach1.d | 13 + .../gdc.test/fail_compilation/staticforeach2.d | 13 + .../gdc.test/fail_compilation/staticforeach3.d | 7 + .../gdc.test/fail_compilation/test17307.d | 12 + .../gdc.test/fail_compilation/traits_alone.d | 10 + gcc/testsuite/gdc.test/runnable/arrayop.d | 3 +- gcc/testsuite/gdc.test/runnable/constfold.d | 18 +- gcc/testsuite/gdc.test/runnable/e7804.d | 179 +++ .../gdc.test/runnable/imports/template13478a.d | 5 +- gcc/testsuite/gdc.test/runnable/staticforeach.d | 45 + gcc/testsuite/gdc.test/runnable/test42.d | 60 +- gcc/testsuite/gdc.test/runnable/traits.d | 38 +- gcc/testsuite/lib/target-supports.exp | 45 +- gcc/tree-call-cdce.c | 2 +- gcc/tree-data-ref.c | 2 +- gcc/tree-inline.c | 4 +- gcc/tree-loop-distribution.c | 13 +- gcc/tree-nested.c | 37 +- gcc/tree-sra.c | 2 +- gcc/tree-ssa-dom.c | 2 +- gcc/tree-ssa-dse.c | 4 +- gcc/tree-ssa-loop-split.c | 2 +- gcc/tree-ssa-math-opts.c | 2 +- gcc/tree-ssa-pre.c | 3 +- gcc/tree-ssa-reassoc.c | 9 +- gcc/tree-ssa-strlen.c | 242 +-- gcc/tree-vect-loop.c | 2 +- gcc/tree.c | 2 +- gcc/tree.def | 2 +- libgcc/ChangeLog | 4 + libgcc/config/arm/t-arm | 3 + libgomp/ChangeLog | 5 + libgomp/testsuite/libgomp.c/pr93566.c | 113 ++ libphobos/ChangeLog | 8 + libphobos/Makefile.in | 2 +- libphobos/configure | 2 +- libphobos/configure.ac | 2 +- libphobos/libdruntime/MERGE | 2 +- libphobos/libdruntime/Makefile.in | 2 +- libphobos/libdruntime/core/cpuid.d | 36 +- libphobos/libdruntime/core/stdc/errno.d | 328 ++++ libphobos/libdruntime/core/stdc/fenv.d | 2 + libphobos/libdruntime/core/sys/posix/config.d | 8 +- libphobos/libdruntime/core/sys/posix/fcntl.d | 112 +- libphobos/libdruntime/core/sys/posix/semaphore.d | 4 +- libphobos/libdruntime/core/sys/posix/sys/socket.d | 62 +- libphobos/libdruntime/core/sys/posix/sys/stat.d | 236 ++- libphobos/libdruntime/core/sys/posix/sys/types.d | 22 +- libphobos/src/MERGE | 2 +- libphobos/src/std/algorithm/iteration.d | 2 +- libphobos/src/std/math.d | 20 +- libstdc++-v3/ChangeLog | 8 + libstdc++-v3/include/experimental/executor | 9 +- libstdc++-v3/testsuite/20_util/bind/91371.cc | 2 +- .../testsuite/20_util/is_function/91371.cc | 2 +- .../20_util/is_member_function_pointer/91371.cc | 2 +- libstdc++-v3/testsuite/20_util/is_object/91371.cc | 2 +- .../net/execution_context/make_service.cc} | 31 +- maintainer-scripts/ChangeLog | 3 + maintainer-scripts/gcc_release | 2 +- 412 files changed, 12982 insertions(+), 1355 deletions(-) create mode 100644 gcc/config/arm/arm_mve.h create mode 100644 gcc/config/arm/arm_mve_builtins.def create mode 100644 gcc/config/arm/mve.md create mode 100644 gcc/testsuite/g++.dg/cpp0x/lambda/lambda-variadic10.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/noexcept57.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/variadic178.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction71.C create mode 100644 gcc/testsuite/g++.dg/diagnostic/pr67960-2.C create mode 100644 gcc/testsuite/g++.dg/diagnostic/pr67960.C create mode 100644 gcc/testsuite/g++.target/i386/pr94185.C create mode 100644 gcc/testsuite/gcc.c-torture/compile/20200313-1.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr90275.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr94179.c create mode 100644 gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-14.c create mode 100644 gcc/testsuite/gcc.dg/Wbuiltin-declaration-mismatch-15.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr94099.c create mode 100644 gcc/testsuite/gcc.dg/analyzer/pr94105.c create mode 100644 gcc/testsuite/gcc.dg/lto/pr94157_0.c create mode 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5 years, 4 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3 updated (0925214029 -> 946ffddcae)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3 in repository toolchain/ci/binutils-gdb. from 0925214029 [gdb/testsuite] Fix internal buffer full error in gdb.base/i [...] adds 607c693210 sim: ppc: netbsd: Sync errno codes with NetBSD 9.99.49 adds 7a20f753ef sim: ppc: netbsd: Sync signal names with NetBSD 9.99.49 adds 8dd8e1c722 Remove use of deprecated core functions (in NetBSD/ARM) adds 4d696a5c68 gdb/selftest.m4: ensure $development is set adds db6878ac55 Move sourcing of development.sh to GDB_AC_COMMON adds 74cd3f9d7e Don't include selftests objects in build when unit tests are [...] adds 272cd5a31e Move gdb/selftest.m4 to gdbsupport/selftest.m4 adds 40310f30a5 gdb: make gdb.arch/amd64-disp-step-avx.exp actually test dis [...] adds 3f512721a8 gdb: use foreach_with_prefix in gdb.base/break-interp.exp adds 64f251023b Fix CORE_ADDR size assertion in symfile-mem.c adds 53807e9f3d Don't use sprintf_vma for CORE_ADDR adds 227031b2bf Cast to bfd_vma in arm-tdep.c adds 9a665d6226 Fix gdbserver build when intl already built adds 213291361b Change gdbsupport not to rely on BFD adds 4635ff9753 Change gdbserver to use existing gdbsupport adds 6ba0a32103 Remove deprecated core file functions adds 301b21e0df [gdb/testsuite] Fix check-read1 FAIL in gdb.tui/corefile-run.exp adds 49ba92c0a6 [gdb/testsuite] Fix mi-sym-info.exp matching FAILs adds fd486f32d1 asan: more readelf leaks adds 502794d432 Fix several mix up between octets and bytes in ELF program headers adds 666318230c Fix several mix up between octets and bytes in ELF program headers adds 96c7f87394 [gdb/symtab] Fix partial unit psymtabs adds 1673df3278 x86-64: correct mis-named X86_64_0D enumerator adds 015ec493d8 Recognize aarch64 PT_GETREGS and PT_GETFPREGS notes on NetBSD adds 66d1f7cc12 gas, arm: PR25660L Fix vadd/vsub with lt and le condition co [...] adds 2e9145ace2 [gdb/testsuite] Fix mi-sym-info.exp matching FAILs (2) adds 2d61316c32 [gdb/testsuite] Fix buffer full errors in gdb.mi/mi-sym-info.exp adds 74e10d1742 x86: Check static link of dynamic objects adds abf874aafe Add support for non-contiguous memory regions adds 9fcbd8a90a Register NT_NETBSDCORE_AUXV (NetBSD-Core) adds 06d949ec31 Implement NT_NETBSDCORE_LWPSTATUS (NetBSD-Core) adds 1b83d09cd5 gdb/testsuite: Remove paths and make test names unique adds ce3acbe9fa Use scoped_value_mark in value_print adds b0c26e99f5 Refactor val_print and common_val_print adds c2a44efee1 Introduce common_val_print_checked adds 3444c526a3 Use common_val_print in infcmd.c adds a6e05a6c3a Use common_val_print in mi-main.c adds 040f66bd2d Use common_val_print in riscv-tdep.c adds 72a45c9384 Use common_val_print in f-valprint.c adds 410cf31501 Use common_val_print in cp-valprint.c adds a1f6a07c3d Use common_val_print in c-valprint.c adds 2b4e573d62 Introduce la_value_print_inner adds 156bfec999 Introduce generic_value_print adds 4f9ae81013 Introduce value_print_scalar_formatted adds 4dba70eee1 Two simple uses of value_print_scalar_formatted adds d121c6ce89 Introduce value_print_array_elements adds 7fe471e9ae Simplify c_val_print_array adds 1e592a8ae0 Make pascal_object_print_value_fields static adds 6218219002 Introduce c_value_print_inner adds 62c4663d3c Introduce m2_value_print_inner adds c0941be613 Introduce pascal_value_print_inner adds 24051bbe84 Introduce f_value_print_innner adds 26792ee034 Introduce ada_value_print_inner adds 5f56f7cbd2 Convert Rust printing to value-based API adds 23b0f06be4 Convert Go printing to value-based API adds d133c3e1a8 Convert D printing to value-based API adds 59fcdac646 Convert Modula-2 printing to value-based API adds 6a95a1f58d Convert Fortran printing to value-based API adds 64d64d3a76 Rewrite pascal_value_print_inner adds 07a328583d Convert Pascal to value-based API adds abc66ce95e Initial rewrite of generic_value_print adds 2a5b130bcb Introduce generic_value_print_ptr adds 40f3ce189e Fix generic_val_print_enum for value-based printing adds 65786af626 Remove generic_val_print_flags adds 4112d2e602 Simplify generic_val_print_func adds 6dde752183 Introduce generic_value_print_bool adds fdddfccba1 Introduce generic_value_print_int adds 3eec3b05b9 Introduce generic_value_print_char adds f535400886 Simplify generic_val_print_float adds 4f412b6e31 Introduce generic_value_print_complex adds 5083623134 Rewrite c_value_print_inner adds da3e2c2923 Introduce c_value_print_ptr adds 2faac269d5 Introduce c_value_print_int adds ce80b8bd37 Introduce c_value_print_memberptr adds 6999f067c1 Introduce c_value_print_array adds 64b653ca70 Introduce cp_print_value_fields and c_value_print_struct adds fbf54e7554 Introduce cp_print_value adds 5b5e15ecdd Rewrite ada_value_print_inner adds 416595d640 Introduce ada_value_print_ptr adds b9fa6e0798 Rewrite ada_value_print_1 floating point case adds 39ef85a896 Introduce ada_value_print_num adds 2e088f8b6e Convert ada_val_print_ref to value-based API adds 0337112903 Convert ada_value_print to value-based API adds b59eac3732 Introduce ada_value_print_array adds 3a916a9757 Change print_field_values to use value-based API adds 42331a1ea2 Change extension language pretty-printers to use value API adds 426a9c18dd Remove val_print adds 48e81d7f63 BFD_FAKE_SECTIONS formatting adds 02a8180e6f non-contiguous elf test adds f761cb13a9 asan: readelf: memory leaks adds 780f96aed2 readelf large memory allocation adds 09546b56ed [gdb/testsuite] Fix FAIL in gdb.base/printcmds.exp adds 2ac70237d2 [gdb/testsuite] Fix unrecognized debug output level 'stateme [...] adds 1bd6175ae7 Re: asan: more readelf leaks adds 8b5d0a4f6f Include netbsd-core.lo for all arm/mips NetBSD targets adds 25567eeece Define _KERNTYPES in vax-bsd-nat.c adds 52feded778 Define _KERNTYPES in ppc-nbsd-nat.c adds 8110f842bc Define _KERNTYPES in mips-nbsd-nat.c adds d5be5fa420 Inherit vax_bsd_nat_target from nbsd_nat_target adds 1275307303 Add explicit cast to fix build of vax-bsd-nat.c adds 6227b330d5 Add support for threads in vax_bsd_nat_target adds 013f99f035 Add support for NetBSD threads in x86-bsd-nat.c adds 6018d381a0 Inherit arm_netbsd_nat_target from nbsd_nat_target adds 75c56d3d12 Add support for NetBSD threads in arm-nbsd-nat.c adds 54c4382534 [gdb/testsuite] Fix check-read1 FAIL in attach-many-short-li [...] adds 2190cf067b Define _KERNTYPES in alpha-bsd-nat.c adds 4fed520be2 Inherit alpha_netbsd_nat_target from nbsd_nat_target adds 66eaca97eb Remove unused code from alpha-bsd-nat.c adds 6def66f140 Add support for NetBSD threads in alpha-bsd-nat.c adds f90280caf5 Define _KERNTYPES in m68k-bsd-nat.c adds 01a801176e Inherit m68k_bsd_nat_target from nbsd_nat_target adds bc10778499 m68k: bsd: Change type from char * to gdb_byte * adds 154151a6e3 Add support for NetBSD threads in m68k-bsd-nat.c adds ab44624cea [gdb/testsuite] Fix check-read1 FAILs in mi-fortran-modules.exp adds 3293bbaffa Add C parser support for "restrict" and "_Atomic" adds eaeaf44cfd [gdb/testsuite] Fix check-read1 FAIL with gdb.base/maint.exp adds 6b9374f1e0 [gdb/testsuite] Fix solib-list.exp test-case for exec with d [...] adds 7bac4137d7 asan: alpha-vms: null dereference adds 60e63c3e97 ubsan: shift exponent 70 is too large adds 28d1356774 asan: readelf leak in hppa_process_unwind adds 4b3ecb3b91 PR25675: SIGSEGV in bfd_octets_per_byte adds 2f89101fe8 [gdb/testsuite] Add cache_verify option for gdb_caching_procs adds cb9b645d3e gdb: recognize 64 bits Windows executables as Cygwin osabi adds fe4b2ee65c gdb: move enum gdb_osabi to osabi.h adds 053205cc40 gdb: add Windows OS ABI adds 7a1998dffb gdb: rename i386-cygwin-tdep.c to i386-windows-tdep.c adds 5982a56ab9 gdb: rename content of i386-windows-tdep.c, cygwin to windows adds 8db5243724 gdb: select "Cygwin" OS ABI for Cygwin binaries adds 30efb6c7af gdb: define builtin long type to be 64 bits on amd64 Cygwin adds 67430cd00a Fix dwarf2_name caching bug adds 817a758576 arc: Migrate to new target features adds 771dd3a88b Initialize base_value in pascal_object_print_value adds 7325b16ba4 [gdb/testsuite] Give up after consecutive timeouts in comple [...] adds 589902954d [gdb] Skip imports of c++ CUs adds a2ecbe9fb7 Rewrite nbsd_nat_target::pid_to_exec_file to sysctl(3) adds 9e38d61910 Include missing header to get missing declarations adds 946ffddcae Automatic date update in version.in No new revisions were added by this update. Summary of changes: ChangeLog | 15 + Makefile.def | 5 +- Makefile.in | 5 +- bfd/ChangeLog | 126 ++ bfd/bfd-in2.h | 29 +- bfd/bfd.c | 5 +- bfd/configure | 4 +- bfd/configure.ac | 4 +- bfd/ecoff.c | 6 +- bfd/elf-bfd.h | 2 +- bfd/elf-linker-x86.h | 6 + bfd/elf.c | 194 +-- bfd/elf32-arm.c | 11 + bfd/elf32-csky.c | 11 + bfd/elf32-hppa.c | 31 + bfd/elf32-m68hc11.c | 11 + bfd/elf32-m68hc12.c | 11 + bfd/elf32-metag.c | 15 +- bfd/elf32-nios2.c | 13 + bfd/elf64-ppc.c | 50 + bfd/elfcode.h | 28 +- bfd/elflink.c | 55 +- bfd/elfnn-aarch64.c | 16 +- bfd/elfxx-x86.c | 17 + bfd/merge.c | 22 +- bfd/section.c | 31 +- bfd/version.h | 2 +- bfd/vms-alpha.c | 38 +- binutils/ChangeLog | 51 + binutils/elfcomm.c | 20 +- binutils/elfcomm.h | 2 +- binutils/elfedit.c | 14 +- binutils/readelf.c | 318 +++-- binutils/unwind-ia64.c | 21 +- gas/ChangeLog | 14 + gas/config/tc-arm.c | 15 +- gas/testsuite/gas/arm/mve-vaddsub-it-bad.d | 6 + gas/testsuite/gas/arm/mve-vaddsub-it-bad.l | 7 + gas/testsuite/gas/arm/mve-vaddsub-it-bad.s | 11 + gas/testsuite/gas/arm/mve-vaddsub-it.d | 23 + gas/testsuite/gas/arm/mve-vaddsub-it.s | 17 + gas/testsuite/gas/arm/nomve-vaddsub-it.d | 24 + gdb/ChangeLog | 752 +++++++++++ gdb/Makefile.in | 16 +- gdb/acinclude.m4 | 2 +- gdb/ada-lang.c | 2 +- gdb/ada-lang.h | 8 +- gdb/ada-valprint.c | 297 ++--- gdb/alpha-bsd-nat.c | 63 +- gdb/amd64-bsd-nat.c | 1 + gdb/amd64-windows-tdep.c | 41 +- gdb/arc-tdep.c | 59 +- gdb/arc-tdep.h | 4 + gdb/arch/arc.c | 58 + gdb/arch/arc.h | 48 + gdb/arm-nbsd-nat.c | 154 +-- gdb/arm-nbsd-tdep.c | 75 +- .../gdb.mi/mi-sym-info-2.c => arm-nbsd-tdep.h} | 34 +- gdb/arm-tdep.c | 4 +- gdb/breakpoint.c | 5 +- gdb/c-exp.y | 56 +- gdb/c-lang.c | 8 +- gdb/c-lang.h | 20 +- gdb/c-typeprint.c | 27 +- gdb/c-valprint.c | 268 ++-- gdb/configure | 18 +- gdb/configure.ac | 7 +- gdb/configure.tgt | 12 +- gdb/corelow.c | 170 +-- gdb/cp-valprint.c | 141 +-- gdb/d-lang.c | 2 +- gdb/d-lang.h | 10 +- gdb/d-valprint.c | 22 +- gdb/defs.h | 31 - gdb/disasm-selftests.c | 5 - gdb/dwarf2/read.c | 40 +- gdb/dwarf2/read.h | 6 + gdb/extension-priv.h | 17 +- gdb/extension.c | 19 +- gdb/extension.h | 6 +- gdb/f-lang.c | 2 +- gdb/f-lang.h | 9 +- gdb/f-valprint.c | 62 +- gdb/features/Makefile | 6 +- gdb/features/arc-arcompact.c | 74 -- gdb/features/arc-arcompact.xml | 85 -- gdb/features/arc-v2.c | 78 -- gdb/features/arc-v2.xml | 92 -- gdb/features/arc/aux-arcompact.c | 31 + gdb/features/arc/aux-arcompact.xml | 28 + gdb/features/arc/aux-v2.c | 35 + gdb/features/arc/aux-v2.xml | 32 + gdb/features/arc/core-arcompact.c | 47 + gdb/features/arc/core-arcompact.xml | 58 + gdb/features/arc/core-v2.c | 47 + gdb/features/arc/core-v2.xml | 61 + gdb/gdbarch-selftests.c | 4 - gdb/gdbarch.h | 1 + gdb/gdbarch.sh | 1 + gdb/gdbcore.h | 68 - gdb/go-lang.c | 2 +- gdb/go-lang.h | 10 +- gdb/go-valprint.c | 16 +- gdb/guile/guile-internal.h | 5 +- gdb/guile/scm-pretty-print.c | 16 +- gdb/guile/scm-value.c | 18 + gdb/{i386-cygwin-tdep.c => i386-windows-tdep.c} | 45 +- gdb/infcmd.c | 12 +- gdb/language.c | 14 +- gdb/language.h | 25 +- gdb/m2-lang.c | 2 +- gdb/m2-lang.h | 8 +- gdb/m2-valprint.c | 95 +- gdb/m68k-bsd-nat.c | 27 +- gdb/mi/mi-main.c | 4 +- gdb/mips-nbsd-nat.c | 2 + gdb/mips-tdep.c | 5 +- gdb/nbsd-nat.c | 22 +- gdb/objc-lang.c | 2 +- gdb/opencl-lang.c | 2 +- gdb/osabi.c | 1 + gdb/osabi.h | 32 + gdb/p-lang.c | 2 +- gdb/p-lang.h | 16 +- gdb/p-valprint.c | 161 +-- gdb/ppc-nbsd-nat.c | 2 + gdb/printcmd.c | 5 +- gdb/psymtab.c | 44 +- gdb/psymtab.h | 6 + gdb/python/py-prettyprint.c | 17 +- gdb/python/py-value.c | 21 + gdb/python/python-internal.h | 5 +- gdb/remote.c | 12 +- gdb/riscv-tdep.c | 12 +- gdb/rust-lang.c | 120 +- gdb/stack.c | 2 +- gdb/symfile-mem.c | 2 +- gdb/target-descriptions.c | 3 +- gdb/testsuite/ChangeLog | 92 ++ gdb/testsuite/gdb.arch/amd64-disp-step-avx.S | 5 + gdb/testsuite/gdb.arch/amd64-disp-step-avx.exp | 8 +- gdb/testsuite/gdb.base/break-interp.exp | 286 ++--- gdb/testsuite/gdb.base/cvexpr.exp | 11 + gdb/testsuite/gdb.base/maint.exp | 45 +- gdb/testsuite/gdb.base/printcmds.c | 3 + gdb/testsuite/gdb.base/printcmds.exp | 3 + gdb/testsuite/gdb.cp/step-and-next-inline.exp | 4 + gdb/testsuite/gdb.dwarf2/imported-unit.exp | 13 + gdb/testsuite/gdb.mi/mi-fortran-modules.exp | 116 +- gdb/testsuite/gdb.mi/mi-sym-info-2.c | 5 + gdb/testsuite/gdb.mi/mi-sym-info.exp | 190 ++- gdb/testsuite/gdb.server/solib-list.exp | 17 +- .../attach-many-short-lived-threads.exp | 16 +- .../gdb.tui/tui-layout-asm-short-prog.exp | 2 +- gdb/testsuite/gdb.tui/tui-layout-asm.exp | 2 +- gdb/testsuite/lib/cache.exp | 37 +- gdb/testsuite/lib/completion-support.exp | 27 +- gdb/testsuite/lib/gdb.exp | 11 + gdb/testsuite/lib/tuiterm.exp | 15 +- gdb/type-stack.c | 76 +- gdb/type-stack.h | 2 + gdb/valprint.c | 457 +++---- gdb/valprint.h | 50 +- gdb/value.h | 7 - gdb/vax-bsd-nat.c | 17 +- gdb/windows-tdep.c | 99 ++ gdb/windows-tdep.h | 6 + gdb/x86-bsd-nat.c | 20 +- gdbserver/ChangeLog | 38 + gdbserver/Makefile.in | 100 +- gdbserver/acinclude.m4 | 5 +- gdbserver/config.in | 4 + gdbserver/configure | 1308 +++++++++++--------- gdbserver/configure.ac | 16 +- gdbsupport/ChangeLog | 21 + gdbsupport/Makefile.in | 3 +- gdbsupport/acinclude.m4 | 2 +- gdbsupport/common-defs.h | 16 - gdbsupport/common-types.h | 32 +- gdbsupport/common.m4 | 3 + gdbsupport/configure | 14 +- gdbsupport/configure.ac | 3 - {gdb => gdbsupport}/selftest.m4 | 7 +- include/ChangeLog | 28 + include/bfdlink.h | 12 +- include/elf/common.h | 2 + include/elf/internal.h | 30 +- ld/ChangeLog | 64 + ld/NEWS | 3 + ld/emulparams/elf32_x86_64.sh | 1 + ld/emulparams/elf_i386.sh | 1 + ld/emulparams/elf_x86_64.sh | 1 + ld/emulparams/static.sh | 12 + ld/emultempl/armelf.em | 3 +- ld/emultempl/elf-x86.em | 1 + ld/emultempl/xtensaelf.em | 6 + ld/ld.texi | 42 + ld/ldexp.c | 3 +- ld/ldlang.c | 145 ++- ld/ldlex.h | 2 + ld/lexsup.c | 10 + ld/testsuite/ld-arm/arm-elf.exp | 7 + ld/testsuite/ld-arm/non-contiguous-arm.d | 4 + ld/testsuite/ld-arm/non-contiguous-arm.ld | 34 + ld/testsuite/ld-arm/non-contiguous-arm.s | 35 + ld/testsuite/ld-arm/non-contiguous-arm2.d | 77 ++ ld/testsuite/ld-arm/non-contiguous-arm2.ld | 33 + ld/testsuite/ld-arm/non-contiguous-arm3.d | 83 ++ ld/testsuite/ld-arm/non-contiguous-arm3.ld | 33 + ld/testsuite/ld-arm/non-contiguous-arm4.d | 4 + ld/testsuite/ld-arm/non-contiguous-arm4.ld | 34 + ld/testsuite/ld-arm/non-contiguous-arm5.d | 77 ++ ld/testsuite/ld-arm/non-contiguous-arm5.ld | 34 + ld/testsuite/ld-arm/non-contiguous-arm6.d | 77 ++ ld/testsuite/ld-arm/non-contiguous-arm6.ld | 33 + ld/testsuite/ld-elf/linux-x86.exp | 33 +- ld/testsuite/ld-elf/non-contiguous.d | 28 + ld/testsuite/ld-elf/non-contiguous.ld | 47 + ld/testsuite/ld-elf/non-contiguous.s | 21 + ld/testsuite/ld-elf/pr24920.err | 1 + ld/testsuite/ld-powerpc/non-contiguous-powerpc.d | 5 + ld/testsuite/ld-powerpc/non-contiguous-powerpc.ld | 22 + ld/testsuite/ld-powerpc/non-contiguous-powerpc.s | 8 + ld/testsuite/ld-powerpc/non-contiguous-powerpc64.d | 5 + ld/testsuite/ld-powerpc/powerpc.exp | 3 + opcodes/ChangeLog | 5 + opcodes/i386-dis.c | 6 +- sim/ppc/ChangeLog | 8 + sim/ppc/emul_netbsd.c | 51 +- 229 files changed, 6255 insertions(+), 3563 deletions(-) create mode 100644 gas/testsuite/gas/arm/mve-vaddsub-it-bad.d create mode 100644 gas/testsuite/gas/arm/mve-vaddsub-it-bad.l create mode 100644 gas/testsuite/gas/arm/mve-vaddsub-it-bad.s create mode 100644 gas/testsuite/gas/arm/mve-vaddsub-it.d create mode 100644 gas/testsuite/gas/arm/mve-vaddsub-it.s create mode 100644 gas/testsuite/gas/arm/nomve-vaddsub-it.d create mode 100644 gdb/arch/arc.c create mode 100644 gdb/arch/arc.h copy gdb/{testsuite/gdb.mi/mi-sym-info-2.c => arm-nbsd-tdep.h} (65%) delete mode 100644 gdb/features/arc-arcompact.c delete mode 100644 gdb/features/arc-arcompact.xml delete mode 100644 gdb/features/arc-v2.c delete mode 100644 gdb/features/arc-v2.xml create mode 100644 gdb/features/arc/aux-arcompact.c create mode 100644 gdb/features/arc/aux-arcompact.xml create mode 100644 gdb/features/arc/aux-v2.c create mode 100644 gdb/features/arc/aux-v2.xml create mode 100644 gdb/features/arc/core-arcompact.c create mode 100644 gdb/features/arc/core-arcompact.xml create mode 100644 gdb/features/arc/core-v2.c create mode 100644 gdb/features/arc/core-v2.xml rename gdb/{i386-cygwin-tdep.c => i386-windows-tdep.c} (83%) rename {gdb => gdbsupport}/selftest.m4 (84%) create mode 100644 ld/emulparams/static.sh create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm.d create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm.ld create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm.s create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm2.d create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm2.ld create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm3.d create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm3.ld create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm4.d create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm4.ld create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm5.d create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm5.ld create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm6.d create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm6.ld create mode 100644 ld/testsuite/ld-elf/non-contiguous.d create mode 100644 ld/testsuite/ld-elf/non-contiguous.ld create mode 100644 ld/testsuite/ld-elf/non-contiguous.s create mode 100644 ld/testsuite/ld-elf/pr24920.err create mode 100644 ld/testsuite/ld-powerpc/non-contiguous-powerpc.d create mode 100644 ld/testsuite/ld-powerpc/non-contiguous-powerpc.ld create mode 100644 ld/testsuite/ld-powerpc/non-contiguous-powerpc.s create mode 100644 ld/testsuite/ld-powerpc/non-contiguous-powerpc64.d -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 4 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3 updated (d3c309fe0 -> 24fbc5f28)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarch64-spec2k6-O3 in repository toolchain/ci/base-artifacts. discards d3c309fe0 1: update: binutils-gcc-glibc-llvm: 1 new 24fbc5f28 1: update: binutils-gcc-glibc-llvm: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (d3c309fe0) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk_tx1/llvm-master-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 128 +- 02-prepare_abe/console.log | 408 +- 03-build_abe-binutils/console.log | 11723 ++- 04-build_abe-stage1/console.log | 15379 ++-- 05-build_abe-linux/console.log | 388 +- 06-build_abe-glibc/console.log | 28769 ++++---- 07-build_abe-stage2/console.log | 36861 +++++----- 08-build_llvm-true/console.log | 12777 ++-- 10-benchmark--O3/benchmark-start.log | 2 +- 10-benchmark--O3/benchmark.log | 5 +- 10-benchmark--O3/console.log | 221 +- 11-check_regression/console.log | 2916 +- 11-check_regression/results-0.csv | 2215 +- 11-check_regression/results-1.csv | 2147 +- 11-check_regression/results-brief.csv | 38 +- 11-check_regression/results-compare.csv | 11 +- 11-check_regression/results-full.csv | 2332 +- 11-check_regression/results.csv | 159 +- 11-check_regression/results.log | 2594 +- 12-update_baseline/console.log | 1072 +- 12-update_baseline/extra-bisect-params | 2 +- 12-update_baseline/results-1.csv | 2147 +- 12-update_baseline/results-brief.csv | 38 +- 12-update_baseline/results-compare.csv | 9 +- 12-update_baseline/results-full.csv | 2146 +- 12-update_baseline/results.csv | 155 +- 12-update_baseline/results.log | 1764 +- console.log | 110692 +++++++++++++++-------------- jenkins/manifest.sh | 22 +- regressions.txt | 2 + results | 6 +- results_id | 2 +- 32 files changed, 118869 insertions(+), 118261 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 4 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allmodconfig updated (a81912b0740 -> 05409a1edd8)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allmodconfig in repository toolchain/ci/gcc. from a81912b0740 Daily bump. adds 31b204ace29 libstdc++: Add default constructor to net::service_already_ [...] adds 9a532a94e35 Daily bump. adds 62960ccdefe [testsuite] Fix PR94023 to guard case under vect_hw_misalign adds 05409a1edd8 [testsuite] Fix PR94019 to check vector char when vect_hw_misalign No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- gcc/testsuite/ChangeLog | 18 +++++++++++++++++ gcc/testsuite/gcc.dg/vect/slp-perm-12.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-over-widen-17.c | 5 ++++- libstdc++-v3/ChangeLog | 11 +++++++++++ libstdc++-v3/include/experimental/executor | 9 ++++++++- .../1.cc => net/execution_context/make_service.cc} | 23 +++++++++++++--------- 7 files changed, 57 insertions(+), 13 deletions(-) copy libstdc++-v3/testsuite/experimental/{optional/constexpr/observers/1.cc => net [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 4 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allmodconfig updated (ee9faa0dd -> 64c09064b)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allmodconfig in repository toolchain/ci/base-artifacts. discards ee9faa0dd 0: update: binutils-gcc-linux: all new 64c09064b 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (ee9faa0dd) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 68 +- 02-prepare_abe/console.log | 430 +- 03-build_abe-binutils/console.log | 11426 ++++++------- 04-build_abe-stage1/console.log | 18232 ++++++++++----------- 05-build_linux/console.log | 876 +- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 2 +- console.log | 31042 ++++++++++++++++++------------------ jenkins/manifest.sh | 8 +- regressions.txt | 2 +- 11 files changed, 31079 insertions(+), 31011 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 4 months

[gcc] branch master updated (1fef0148be4 -> 58a703f0726)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 1fef0148be4 Fix the ChangeLog after the __is_assignable/__is_constructible fix new cf9c3bff39c aarch64: Fix bf16_v(ld|st)n.c failures for big-endian new 58a703f0726 testsuite: Fix gcc.target/aarch64/advsimd-intrinsics/bfcvt- [...] The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 4 ++++ gcc/config/aarch64/iterators.md | 3 ++- gcc/testsuite/ChangeLog | 6 ++++++ gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/bfcvt-nosimd.c | 5 +++-- 4 files changed, 15 insertions(+), 3 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 4 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allnoconfig updated (39930d67fff -> 135744ce689)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allnoconfig in repository toolchain/ci/llvm-project. from 39930d67fff Add new website to release notes. adds 9e0bd5ec03c [Concepts] Fix incorrect DeclContext for transformed Requir [...] adds 135744ce689 [Concepts] Fix incorrect control flow when TryAnnotateTypeC [...] No new revisions were added by this update. Summary of changes: clang/include/clang/Sema/Sema.h | 6 ++++-- clang/lib/Parse/ParseDecl.cpp | 6 ++++++ clang/lib/Parse/ParseTemplate.cpp | 3 ++- clang/lib/Sema/SemaTemplate.cpp | 13 ++++++++----- clang/lib/Sema/TreeTransform.h | 2 +- clang/test/SemaCXX/invalid-member-expr.cpp | 1 + clang/test/SemaCXX/typo-correction.cpp | 5 +++-- clang/test/SemaTemplate/instantiate-requires-expr.cpp | 13 +++++++++++++ clang/test/SemaTemplate/ms-lookup-template-base-classes.cpp | 1 + 9 files changed, 39 insertions(+), 11 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 4 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allnoconfig updated (fbba5b7ec -> 0ce47103d)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allnoconfig in repository toolchain/ci/base-artifacts. discards fbba5b7ec 0: update: llvm-linux: boot new 0ce47103d 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (fbba5b7ec) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 216 +- 02-build_llvm/console.log | 12646 ++++++++++++++++++----------------- 03-build_linux/console.log | 856 ++- 04-boot_linux/console.log | 4 +- 05-check_regression/console.log | 12 +- 06-update_baseline/console.log | 13 +- console.log | 13734 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 13732 insertions(+), 13757 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 4 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig updated (5dee500b359 -> 1fef0148be4)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig in repository toolchain/ci/gcc. from 5dee500b359 [ARM][GCC][3/x]: MVE ACLE intrinsics framework patch. adds f522810d2b5 [testsuite] Avoid duplicate test names in sizeless tests adds bae7b38cf8a Fix PR94185: Do not reuse insn alternative after changing m [...] adds c015ff8ccaf c: Handle MEM_REF in c_fully_fold* [PR94179] adds 447d196e75d d: Fix multiple definition error when using mixins and interfaces. adds c62f5e6e1f4 libstdc++: Add default constructor to net::service_already_ [...] adds 2691ffe6dba d: Fix assignment to anonymous union member corrupts siblin [...] adds b3f246f12b2 Daily bump. adds 950183c7741 Update gcc sv.po. adds 57e7ad5a8fd c++: Add test for PR 93901. adds ecf2b69a629 Filter a test-case with gas. adds 7afa3b82918 expand: Don't depend on warning flags in code generation of [...] adds 741ff2a263f strlen: Punt on UB reads past end of string literal [PR94187] adds fd857de8070 c: ignore initializers for elements of variable-size types [...] adds 994d4862062 testsuite: Fix pr94185.C testcase on i686-linux with C++98 [...] adds 14782c8123e [ARM][GCC][4/x]: MVE ACLE vector interleaving store intrinsics. adds a50f6abffc3 [ARM][GCC][1/1x]: Patch to support MVE ACLE intrinsics with [...] adds 5db0eb95c34 [ARM][GCC][2/1x]: MVE intrinsics with unary operand. adds a9a437ffc42 tree-ssa-strlen: Fix up count_nonzero_bytes* [PR94015] adds f582ca0fd70 [GCC][PATCH][ARM] Add multilib mapping for Armv8.1-M+MVE wi [...] adds 700d4cb08c8 Fix up duplicated duplicated words mostly in comments adds 6df4618cac9 [ARM][GCC][3/1x]: MVE intrinsics with unary operand. adds a475f153431 [ARM][GCC][4/1x]: MVE intrinsics with unary operand. adds 4be8cf77026 [ARM][GCC][1/2x]: MVE intrinsics with binary operands. adds 887085be635 c++: Fix access checks for __is_assignable and __is_constructible adds f166a8cdf48 [ARM][GCC][2/2x]: MVE intrinsics with binary operands. adds d71dba7b611 [ARM][GCC][3/2x]: MVE intrinsics with binary operands. adds 33203b4c27d [ARM][GCC][4/2x]: MVE intrinsics with binary operands. adds f9355dee93f [ARM][GCC][5/2x]: MVE intrinsics with binary operands. adds 0dad5b33687 [ARM][GCC][1/3x]: MVE intrinsics with ternary operands. adds e4596b66710 coroutines, testsuite: Fix single test execution. adds 1fef0148be4 Fix the ChangeLog after the __is_assignable/__is_constructible fix No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 2143 ++++++ gcc/DATESTAMP | 2 +- gcc/builtins.c | 22 +- gcc/c-family/ChangeLog | 5 + gcc/c-family/c-common.c | 2 +- gcc/c/ChangeLog | 5 + gcc/c/c-fold.c | 9 + gcc/c/c-typeck.c | 2 +- gcc/cfgexpand.c | 2 +- gcc/config/aarch64/aarch64-sve.md | 2 +- gcc/config/aarch64/aarch64.c | 2 +- .../aarch64/falkor-tag-collision-avoidance.c | 2 +- gcc/config/arm/arm-builtins.c | 276 +- gcc/config/arm/arm.h | 3 + gcc/config/arm/arm_mve.h | 8012 ++++++++++++++++++++ gcc/config/arm/arm_mve_builtins.def | 311 + gcc/config/arm/constraints.md | 33 +- gcc/config/arm/iterators.md | 3 +- gcc/config/arm/mve.md | 3159 +++++++- gcc/config/arm/neon.md | 8 +- gcc/config/arm/predicates.md | 20 + gcc/config/arm/t-arm | 4 +- gcc/config/arm/t-rmprofile | 13 +- gcc/config/fr30/fr30.c | 2 +- gcc/config/gcn/gcn-run.c | 2 +- gcc/config/i386/i386-features.c | 2 +- gcc/config/i386/i386.c | 2 +- gcc/config/i386/x86-tune.def | 2 +- gcc/config/msp430/msp430.c | 2 +- gcc/config/nds32/nds32-md-auxiliary.c | 12 +- gcc/config/nvptx/nvptx.c | 2 +- gcc/config/rs6000/rs6000-c.c | 2 +- gcc/config/rs6000/rs6000-logue.c | 2 +- gcc/config/rs6000/rs6000-p8swap.c | 2 +- gcc/config/rs6000/rs6000-string.c | 2 +- gcc/config/rs6000/rs6000.c | 2 +- gcc/cp/ChangeLog | 17 + gcc/cp/method.c | 4 +- gcc/cp/name-lookup.c | 2 +- gcc/cp/parser.c | 10 +- gcc/cp/pt.c | 6 +- gcc/d/ChangeLog | 12 + gcc/d/decl.cc | 7 +- gcc/d/types.cc | 10 +- gcc/doc/tm.texi | 4 +- gcc/dwarf2out.c | 2 +- gcc/fortran/ChangeLog | 10 + gcc/fortran/arith.c | 2 +- gcc/fortran/array.c | 2 +- gcc/fortran/frontend-passes.c | 2 +- gcc/fortran/module.c | 4 +- gcc/fortran/resolve.c | 2 +- gcc/fortran/trans-expr.c | 2 +- gcc/gimple-ssa-sprintf.c | 6 +- gcc/gimple-ssa-store-merging.c | 2 +- gcc/gimple-ssa-warn-restrict.c | 4 +- gcc/hsa-common.c | 2 +- gcc/input.c | 4 +- gcc/ipa-param-manipulation.h | 2 +- gcc/ipa-prop.h | 2 +- gcc/ira-costs.c | 2 +- gcc/langhooks.h | 2 +- gcc/lra-spills.c | 12 +- gcc/omp-grid.c | 2 +- gcc/po/ChangeLog | 4 + gcc/po/sv.po | 162 +- gcc/read-rtl-function.c | 6 +- gcc/rtl.c | 2 +- gcc/selftest.c | 2 +- gcc/shrink-wrap.c | 2 +- gcc/spellcheck.c | 2 +- gcc/target.def | 6 +- gcc/testsuite/ChangeLog | 824 ++ .../g++.dg/coroutines/torture/coro-torture.exp | 14 +- gcc/testsuite/g++.dg/cpp0x/noexcept57.C | 40 + gcc/testsuite/g++.dg/ext/pr94197.C | 74 + gcc/testsuite/g++.target/i386/pr94185.C | 33 + gcc/testsuite/gcc.c-torture/compile/pr94179.c | 9 + gcc/testsuite/gcc.dg/lto/pr94157_0.c | 1 + gcc/testsuite/gcc.dg/pr94015.c | 107 + gcc/testsuite/gcc.dg/pr94189.c | 11 + .../aarch64/sve/acle/general-c/sizeless-1.c | 3 +- .../aarch64/sve/acle/general-c/sizeless-2.c | 3 +- gcc/testsuite/gcc.target/arm/multilib.exp | 3 + .../gcc.target/arm/mve/intrinsics/vabavq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vabavq_u16.c | 22 + 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcreateq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp16q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp32q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp64q_m.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vctp8q.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_m_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_n_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_n_s32.c create mode 100644 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mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_s32.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovnbq_s16.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_u16.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vqrshlq_s8.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_r_s32.c create mode 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_u8.c create mode 100644 gcc/testsuite/gdc.dg/imports/pr92216.d create mode 100644 gcc/testsuite/gdc.dg/pr92216.d create mode 100644 gcc/testsuite/gdc.dg/pr92309.d create mode 100644 libstdc++-v3/testsuite/experimental/net/execution_context/make_ [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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