Tcwg-commits March 2020

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[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allmodconfig updated (3fb7f2fbd5f -> c76df72f1a9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allmodconfig in repository toolchain/ci/gcc. from 3fb7f2fbd5f [Fortran] Fix result-variable handling of MODULE PROCEDURE [...] adds 7d57570b065 Patch for PR94246 adds 946a444df34 testsuite: adjust modulo-sched compare-debug tests adds 42cda3ba45f libstdc++: Fix std::reverse_iterator relational operators adds f6b2b79040d libstdc++: Fix two tests that fail in C++20 mode adds 673bb288e62 Daily bump. new c76df72f1a9 testsuite: Split up gdc-test.exp into each subdirectory The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/DATESTAMP | 2 +- gcc/fortran/ChangeLog | 8 ++ gcc/fortran/arith.c | 10 +- gcc/fortran/expr.c | 47 +++----- gcc/testsuite/ChangeLog | 18 +++ .../pr87197-debug-sms.c => sms-compare-debug-1.c} | 2 +- .../sms-compare-debug-2.c} | 3 +- gcc/testsuite/gdc.test/compilable/compilable.exp | 30 +++++ .../gdc.test/fail_compilation/fail_compilation.exp | 30 +++++ gcc/testsuite/gdc.test/runnable/runnable.exp | 35 ++++++ gcc/testsuite/gfortran.dg/bessel_5_redux.f90 | 85 ++++++++++++++ .../{gdc.test/gdc-test.exp => lib/gdc-utils.exp} | 41 ++----- libstdc++-v3/ChangeLog | 19 ++++ libstdc++-v3/include/bits/stl_iterator.h | 126 +++++++++++---------- .../testsuite/20_util/is_constructible/value-2.cc | 4 + .../testsuite/20_util/time_point/cons/81468.cc | 8 +- .../24_iterators/move_iterator/greedy_ops.cc | 8 +- .../24_iterators/move_iterator/rel_ops_c++20.cc | 34 ++++++ .../24_iterators/reverse_iterator/greedy_ops.cc | 8 +- .../24_iterators/reverse_iterator/rel_ops_c++20.cc | 61 ++++++++-- 20 files changed, 422 insertions(+), 157 deletions(-) rename gcc/testsuite/gcc.dg/{torture/pr87197-debug-sms.c => sms-compare-debug-1.c} (81%) rename gcc/testsuite/{gcc.c-torture/execute/pr70127-debug-sms.c => gcc.dg/sms-comp [...] create mode 100644 gcc/testsuite/gdc.test/compilable/compilable.exp create mode 100644 gcc/testsuite/gdc.test/fail_compilation/fail_compilation.exp create mode 100644 gcc/testsuite/gdc.test/runnable/runnable.exp create mode 100644 gcc/testsuite/gfortran.dg/bessel_5_redux.f90 rename gcc/testsuite/{gdc.test/gdc-test.exp => lib/gdc-utils.exp} (94%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allmodconfig updated (4d1b9ab645 -> 37d59eacfe)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allmodconfig in repository toolchain/ci/binutils-gdb. from 4d1b9ab645 Fix comment in dwarf2/attribute.h adds 37d59eacfe Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allmodconfig updated (cd9bc6ca -> f08ab4fc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allmodconfig in repository toolchain/ci/base-artifacts. discards cd9bc6ca 0: update: binutils-gcc-linux: all new f08ab4fc 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (cd9bc6ca) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-st [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 182 +- 02-prepare_abe/console.log | 376 +- 03-build_abe-binutils/console.log | 10212 +++++---- 04-build_abe-stage1/console.log | 19980 ++++++++-------- 05-build_linux/console.log | 6058 ++--- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 12 +- 07-check_regression/results.regressions | 2 +- 08-update_baseline/console.log | 12 +- 08-update_baseline/results.regressions | 2 +- console.log | 36838 +++++++++++++++--------------- jenkins/manifest.sh | 12 +- 12 files changed, 36846 insertions(+), 36842 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allmodconfig updated (26df22e3909 -> 70fe4fc073e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allmodconfig in repository toolchain/ci/gcc. from 26df22e3909 Daily bump. adds 70fe4fc073e Daily bump. No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allmodconfig updated (2b567633 -> 917c5908)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allmodconfig in repository toolchain/ci/base-artifacts. discards 2b567633 0: update: binutils-gcc-linux: all new 917c5908 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (2b567633) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 182 +- 02-prepare_abe/console.log | 350 +- 03-build_abe-binutils/console.log | 10579 ++++++------- 04-build_abe-stage1/console.log | 13587 ++++++++-------- 05-build_linux/console.log | 754 +- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 12 +- 07-check_regression/results.regressions | 2 +- 08-update_baseline/console.log | 12 +- 08-update_baseline/results.regressions | 2 +- console.log | 25478 +++++++++++++++--------------- jenkins/manifest.sh | 8 +- 12 files changed, 25484 insertions(+), 25484 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[gcc] branch master updated (673bb288e62 -> c76df72f1a9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 673bb288e62 Daily bump. new c76df72f1a9 testsuite: Split up gdc-test.exp into each subdirectory The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/testsuite/ChangeLog | 11 ++++++ .../compilable/compilable.exp} | 12 +++---- .../fail_compilation/fail_compilation.exp} | 12 +++---- .../ubsan.exp => gdc.test/runnable/runnable.exp} | 17 +++++---- .../{gdc.test/gdc-test.exp => lib/gdc-utils.exp} | 41 ++++++---------------- 5 files changed, 42 insertions(+), 51 deletions(-) copy gcc/testsuite/{gdc.dg/asan/asan.exp => gdc.test/compilable/compilable.exp} (77%) copy gcc/testsuite/{gdc.dg/asan/asan.exp => gdc.test/fail_compilation/fail_compila [...] copy gcc/testsuite/{gdc.dg/ubsan/ubsan.exp => gdc.test/runnable/runnable.exp} (73%) rename gcc/testsuite/{gdc.test/gdc-test.exp => lib/gdc-utils.exp} (94%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-O2-vs-O2_LTO updated (b8de7980c0 -> 642d5abaf1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-O2-vs-O2_LTO in repository toolchain/ci/glibc. from b8de7980c0 Extended Char Intro: Use getwc in example (Bug 25626) new 0334369949 y2038: fix: Add missing libc_hidden_def attribute for some s [...] new f09542c584 posix: Fix system error return value [BZ #25715] new 07d16a6deb Add NEWS entry for CVE-2020-1751 (bug 25423) new 5fce0e095b support/shell-container.c: Return 127 if execve fails new 5a5a3a3234 support/shell-container.c: Add builtin exit new 1c17100c43 support/shell-container.c: Add builtin kill new 4eda036f5b stdlib: Move tst-system to tests-container new 45ae17dd7e ldbl-128ibm-compat: PLT redirects for using ldbl redirects i [...] new d0d1811fb9 Fix tests which expose ldbl -> _Float128 redirects new 076d06e849 powerpc64le: Ensure correct ldouble compiler flags are used new 3618e5fece Makeconfig: sandwich gnulib-tests between libc/ld linking of tests new 39517c008f powerpc64le: add -mno-gnu-attribute to *f128 objects and difftime new 57651ee4c8 powerpc64: apply -mabi=ibmlongdouble to special files new e8a0f5831e ARC: add definitions to elf/elf.h new 4da2597af5 sysv/linux: Rename alpha functions to be alpha specific new d1876749a8 time: Add a timeval with a 32-bit tv_sec and tv_usec new 933dc0e570 time: Add a __itimerval64 struct new 642d5abaf1 Add benchtests for roundeven and roundevenf. The 18 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: Makeconfig | 12 +- NEWS | 3 + benchtests/Makefile | 6 +- benchtests/{trunc-inputs => roundeven-inputs} | 0 benchtests/{truncf-inputs => roundevenf-inputs} | 0 elf/elf.h | 70 +++++++++++- elf/tst-addr1.c | 11 ++ include/err.h | 12 +- include/libc-symbols.h | 2 + include/stdio.h | 52 ++++++--- include/sys/cdefs.h | 20 ++++ include/sys/syslog.h | 2 +- include/time.h | 52 +++++++++ include/wchar.h | 2 +- stdio-common/tst-vfprintf-user-type.c | 4 + stdlib/Makefile | 3 +- stdlib/tst-system.c | 124 ++++++++++++++++++++- support/shell-container.c | 40 ++++++- sysdeps/ieee754/ldbl-128ibm-compat/Makefile | 13 --- .../ieee754/ldbl-128ibm-compat/ieee128-asprintf.c | 5 +- .../ieee754/ldbl-128ibm-compat/ieee128-dprintf.c | 1 + sysdeps/ieee754/ldbl-128ibm-compat/ieee128-err.c | 7 ++ .../ieee754/ldbl-128ibm-compat/ieee128-fprintf.c | 1 + .../ldbl-128ibm-compat/ieee128-isoc99_sscanf.c | 1 + .../ldbl-128ibm-compat/ieee128-isoc99_vfscanf.c | 2 + .../ldbl-128ibm-compat/ieee128-isoc99_vsscanf.c | 1 + .../ieee754/ldbl-128ibm-compat/ieee128-sprintf.c | 1 + .../ieee754/ldbl-128ibm-compat/ieee128-syslog.c | 1 + .../ieee754/ldbl-128ibm-compat/ieee128-vfprintf.c | 1 + .../ieee754/ldbl-128ibm/include/bits/iscanonical.h | 2 +- sysdeps/posix/system.c | 18 +-- sysdeps/powerpc/powerpc64/Makefile | 6 + sysdeps/powerpc/powerpc64/le/Makefile | 96 ++++++++++++---- .../powerpc/powerpc64/le/fpu/multiarch/Makefile | 4 +- sysdeps/powerpc/powerpc64/power7/Makefile | 6 +- .../alpha/{tv32-compat.h => alpha-tv32-compat.h} | 16 +-- sysdeps/unix/sysv/linux/alpha/osf_adjtime.c | 10 +- sysdeps/unix/sysv/linux/alpha/osf_getitimer.c | 6 +- sysdeps/unix/sysv/linux/alpha/osf_getrusage.c | 4 +- sysdeps/unix/sysv/linux/alpha/osf_gettimeofday.c | 4 +- sysdeps/unix/sysv/linux/alpha/osf_setitimer.c | 10 +- sysdeps/unix/sysv/linux/alpha/osf_settimeofday.c | 4 +- sysdeps/unix/sysv/linux/alpha/osf_utimes.c | 6 +- sysdeps/unix/sysv/linux/alpha/osf_wait4.c | 4 +- sysdeps/unix/sysv/linux/clock_getres.c | 2 + sysdeps/unix/sysv/linux/clock_gettime.c | 2 + sysdeps/unix/sysv/linux/clock_nanosleep.c | 2 + sysdeps/unix/sysv/linux/clock_settime.c | 2 + sysdeps/unix/sysv/linux/ppoll.c | 2 + 49 files changed, 536 insertions(+), 119 deletions(-) copy benchtests/{trunc-inputs => roundeven-inputs} (100%) copy benchtests/{truncf-inputs => roundevenf-inputs} (100%) rename sysdeps/unix/sysv/linux/alpha/{tv32-compat.h => alpha-tv32-compat.h} (88%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-O2-vs-O2_LTO updated (72b3bc895f0 -> 673bb288e62)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-O2-vs-O2_LTO in repository toolchain/ci/gcc. from 72b3bc895f0 Fix verifier ICE on wrong comdat local flag [PR93347] adds 68dd57808f7 rs6000: Add command line and builtin compatibility check adds cc3afc9db07 Regenerate gcc.pot. adds 29f23ed79b6 sra: Cap number of sub-access propagations with a param (PR 93435) adds 8416602026d Daily bump. adds 15711e837b2 Fix comma at end of enumerator list seen with -std=c++98. adds 497498c878d lra: Tighten check for reloading paradoxical subregs [PR94052] adds b599bf9d6d1 c++: Reject changing active member of union during initiali [...] adds 98eb7b2ed24 d: Fix ICE in add_symbol_to_partition_1, at lto/lto-partiti [...] adds 837cece888f Darwin: Address translation comments (PR93694). adds dfb25dfe3d3 Darwin: Handle NULL DECL_SIZE_TYPE in machopic_select_secti [...] adds 9fc985118d9 libstdc++: Fix path::generic_string allocator handling (PR 94242) adds a577c0c2693 libstdc++: Fix experimental::path::generic_string (PR 93245) adds 424e39081f9 d: Fix typo in ChangeLog for last change adds 4a01f7b1e73 d: Fix missing dependencies in depfile for imported files ( [...] adds 88d7d0ce8fa testsuite: Fix lambda-vis.C for targets with user label pre [...] adds 85e10e4f0fa Darwin: Fix i686 bootstrap when the assembler supports GOTO [...] adds fbe60463bb8 d: Generate phony targets for content imported files (PR93038) adds 83aa5aa313a Daily bump. adds 6e00d8dcf32 Daily bump. adds b809f0b6580 Set proper DECL_ALIGN in offload_handle_link_vars (PR94233) adds 2fa4b1ffd6e Save ref->speculative_id before clone_reference. adds 263ee1260bc tree-optimization/94266 - aovid propagating addresses of TA [...] adds 7a2090b04e5 ipa/94245 - avoid folding when we want an ADDR_EXPR adds 26b3e568a60 [PR94044] Fix ICE with sizeof<argumentpack> adds a3586eeb884 AMDGCN offloading – use amdgcn-amdhsa adds ce6413087de lto/lto.c – used $ or . in generated linkptr name adds 4897bb0045d libgomp – fix declare target link handling (PR94251) adds b0d84ecc55f fortran: ICE in gfc_match_assignment PR93600 adds 4dcc4502f31 tree-optimization/94261 - avoid IL adjustments in SLP analysis adds 6debbff6ca3 arm: Add earlyclobber to MVE instructions that require it adds 962406639c0 testsuite, arm: Change tests to assemble adds 0cd55f9d3af libgccjit: handle long literals in playback::context::new_s [...] adds 1a5c27b1b43 [ARM][GCC][12x]: MVE ACLE intrinsics to set and get vector lane. adds 85244449104 [ARM][GCC][13x]: MVE ACLE scalar shift intrinsics. adds 88c9a831f3a [ARM][GCC][14x]: MVE ACLE whole vector left shift with carr [...] adds d326e9586b4 driver: Improve the generated help text for alias options adds 5db9e89323c c: Fix up cfun->function_end_locus on invalid function bodi [...] adds ca6c722561c c++: Handle COMPOUND_EXPRs in get_narrower and warnings_for [...] adds 1f6c1c82eb5 c++: Avoid a suspicious -Wnoexcept warning [PR93805] adds 75fb811dfaa Verify the code used for the optimized comparison is valid [...] adds c86c99e6950 Update gcc es.po, sv.po. adds 75c24a08d69 Daily bump. adds 047811579f0 cgraphunit: Avoid code generation differences based on -w/T [...] adds a5a9400a846 if-conv: Fix -fcompare-debug bugs in ifcvt_local_dce [PR94283] adds 565ab7efbdc loop-manip: Avoid -fcompare-debug issues in create_iv [PR94285] adds 596c90d3559 arm: Fix arm {,u}subvdi4 and usubvsi4 expanders [PR94286] adds 906b3eb9df6 Improve endianess detection. adds c2211a60ff0 Fix OpenMP offload handling for target-link variables for n [...] adds 04099157691 Define __BIG_ENDIAN__ adds 8001f59c82b [testsuite,arm] target-supports.exp: Add arm_fp_dp_ok effec [...] adds 2a0eaca3e9c [testsuite,arm] cmp-2.c: Move double-precision tests to cmp-3.c adds 07f8bcc6ea9 [testsuite,arm] use arm_fp_dp_ok effective-target adds 6e771c087b1 c++: Give more expressions locations. adds 5c161741843 c++: Fix template parm with dependent type in concepts. adds fddfd3ce555 c++: Improve handling of ill-formed constraints [PR94186]. adds 75b7b7fdc45 c++: Fix wrong no post-decrement operator error in template [...] adds 0c1c8d9f137 Daily bump. adds adaf4b6c66e Test for sigsetjmp support in analyzer tests requiring that [...] adds c2133167ad5 if-conv: Delete dead stmts backwards in ifcvt_local_dce [PR94283] adds f1154b4d3c5 sccvn: Fix buffer overflow in push_partial_def [PR94300] adds 158cccea0d0 middle-end: Avoid using DECL_UID in ASM_FORMAT_PRIVATE_NAME [...] adds 5f18995e23e varasm: Fix output_constructor where a RANGE_EXPR index nee [...] adds c38daa79768 fortran: ICE using undeclared symbol in array constructor PR93484 adds c8504ebef1d testsuite: Fix up FAILs in gfortran testsuite with -fcompar [...] adds 0fb0240a051 Fix handling of --with{,out}-zstd option. adds 724ec02c2c6 Make target_clones resolver fn static if possible. adds d5ad8ee04a7 i386: Fix ix86_add_reg_usage_to_vzeroupper [PR94308] adds 780f1cfd8ee testsuite: Mention cleanup-13.c test is incompatible with - [...] adds 68c4570a4de Do not error about missing zstd unless --with-zstd. adds 83dfa06cb5c coroutines: Fix missing dereference (PR94319). adds 0fca105f8ca Fix gcc.dg/pr92301.c on targets that don't support argc/argv. adds 05c13c43990 PR tree-optimization/94131 - ICE on printf with a VLA strin [...] adds c7a252ba2d0 c++: Fix invalid -Wduplicated-cond warning [PR94265] adds 713ecb3d417 rs6000: Allow FPRs to change between SDmode and DDmode [...] adds b5228b1bc8c PR middle-end/94004 - missing -Walloca on calls to alloca d [...] adds 6e4cd3cd259 arm: Fix ICE caused by arm_gen_dicompare_reg [PR94292] adds eeb0c7c0713 Fix vector-compare-1 regressions on sh4/sh4eb caused by pat [...] adds 48817fbd761 Fix vector-compare-1 regressions on sh4/sh4eb caused by [...] adds fe4b53b2e7e testsuite: adjustments for amdgcn adds bf1fc37bb4a libstdc++: Define and use chrono::is_clock for C++20 adds e3ef371982a libstdc++ Add missing tests for std::shared_timed_mutex adds 9673d11ec53 libstdc++: Fix author in previous ChangeLog entry adds e97929e20b2 [PATCH] rs6000: vec_rlnm fix to make builtin work according to ABI adds 27f8c8c4c92 Daily bump. adds d21dff5b4fe widening_mul: restrict ops to be defined in the same basic- [...] adds 9708ca2be40 var-tracking: Mark as sp based more VALUEs [PR92264] adds 5a1706f63a2 c++: Fix a -fcompare-debug issue with DEBUG_BEGIN_STMT stmt [...] adds dab932d1519 c++: Fix up user_provided_p [PR81349] adds 10ea09ee846 gimplify: Fix -fcompare-debug differences caused by gimplif [...] adds d6730f06420 Skip test for non-x86 targets. adds da920d0c46c tree: Fix -fcompare-debug issues due to protected_set_expr_ [...] adds 40cdcddf274 Fix UNRESOLVED test-case. adds e519d644999 arm: unified syntax for libgcc when built with -Os [PR94220] adds 16948c54b75 libstdc++: Add some C++20 additions to <chrono> adds 2a1f0f64160 coroutines: Implement n4849 changes to exception handling. adds 6d85947d23a coroutines: Implement n4849 recommended symmetric transfer. adds 517f5356bb0 c++: DR1710, template keyword in a typename-specifier [PR94057] adds b1c905ba83e Update gcc .po files. adds f9c38702e96 Daily bump. adds 65937db83cd coroutines, testsuite: Fix symmetric-transfer-00-basic.C on Linux. adds 54f58e9416d c++: Remove redundant calls to type_dependent_expression_p adds 71d69548a1b c++: template keyword accepted before destructor names [PR94336] adds 06d5d63d994 modulo-sched: fix bootstrap compare-debug issue adds 72809d6fe8e c++: Handle COMPOUND_EXPRs in ocp_convert [PR94339] adds 2eea00c518d c++: Avoid calls in non-evaluated contexts affect whether f [...] adds a76ff304f90 Fortran] Reject invalid association target (PR93363) adds a9cd2d786ad fixup: move ChangeLog entry for last Arm fix to correct file. adds 66e0e23c12d fixup: move ChangeLog entry for last Arm fix to correct file. adds 8d689cf43b5 Fix PR90332 by extending half size vector mode adds 62ede14d30f [Fortran] Fix ICE with deferred-rank arrays (PR93957) adds 917e21e8bcd tree-optimization/94352 - fix uninitialized use of curr_order adds 45cfaf9903d debug/94273 - avoid creating type DIEs for DINFO_LEVEL_TERSE adds 4d661bb7a2e analyzer: tweaks to superedge::dump adds 8f02357571a analyzer: improvements to diagnostic-manager.cc logging adds 42c63313252 analyzer: add new supergraph visualization adds 6969ac301f2 analyzer: fix malloc pointer NULL-ness adds 9dba60130dc c++: Fix ICE after ambiguous inline namespace reopen [PR94257] adds 04dd734b52d c++: avoid -Wredundant-tags on a first declaration in use [ [...] adds 038769535a8 amdgcn: refactor mode iterators adds ccacf77be55 PR c++/94098 - ICE on attribute access redeclaration adds c7fc15f54b3 [pr84733] Fix ICE popping local scope adds 52f24a9e989 PR c++/94346 - [9/10 Regression] ICE due to handle_copy_att [...] adds 54de5afb4a9 c++: Handle COMPOUND_EXPRs in ocp_convert [PR94339] adds 19e5389debb [RS6000] PR94145, make PLT loads volatile adds 491009b609d Update gcc de.po. adds 0302a2de7f1 libstdc++: Move definition earlier in file adds ae6076b5bc1 libstdc++: Implement C++20 changes to insert iterators adds 81a8d137c22 libstdc++: Add remaining C++20 changes to iterator adaptors adds b8a28a06eaf libstdc++: Define __cpp_lib_ranges macro for C++20 adds c2781192292 Daily bump. adds 679becf175c reassoc: Fix -fcompare-debug bug in reassociate_bb [PR94329] adds c6a562de88c c: After issuing errors about array size, for error-recover [...] adds 75defde9fb5 c++: Replay errors during diagnosis of constraint satisfact [...] adds cd68edf894d c++: Respect current_constraint_diagnosis_depth in diagnose [...] adds a7ea3d2ced7 c++: requires-expression outside of a template is misevalua [...] adds 7981c06ae92 c++: Diagnose when "requires" is used instead of "requires [...] adds 3fb7f2fbd5f [Fortran] Fix result-variable handling of MODULE PROCEDURE [...] adds 7d57570b065 Patch for PR94246 adds 946a444df34 testsuite: adjust modulo-sched compare-debug tests adds 42cda3ba45f libstdc++: Fix std::reverse_iterator relational operators adds f6b2b79040d libstdc++: Fix two tests that fail in C++20 mode adds 673bb288e62 Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 514 + gcc/DATESTAMP | 2 +- gcc/analyzer/ChangeLog | 84 + gcc/analyzer/analyzer.h | 1 + gcc/analyzer/diagnostic-manager.cc | 47 +- gcc/analyzer/diagnostic-manager.h | 32 + gcc/analyzer/engine.cc | 270 +- gcc/analyzer/exploded-graph.h | 24 +- gcc/analyzer/program-state.cc | 2 +- gcc/analyzer/region-model.cc | 61 + gcc/analyzer/region-model.h | 10 +- gcc/analyzer/state-purge.cc | 21 +- gcc/analyzer/state-purge.h | 5 +- gcc/analyzer/supergraph.cc | 56 +- gcc/analyzer/supergraph.h | 19 +- gcc/c-family/ChangeLog | 23 + gcc/c-family/c-attribs.c | 35 +- gcc/c-family/c-warn.c | 5 + gcc/c-family/c.opt | 4 + gcc/c/ChangeLog | 8 + gcc/c/c-decl.c | 3 + gcc/c/c-parser.c | 7 +- gcc/calls.c | 82 +- gcc/cgraphunit.c | 12 +- gcc/config/arm/arm-builtins.c | 20 + gcc/config/arm/arm.c | 2 +- gcc/config/arm/arm.md | 7 +- gcc/config/arm/arm_mve.h | 457 + gcc/config/arm/arm_mve_builtins.def | 18 + gcc/config/arm/iterators.md | 3 + gcc/config/arm/mve.md | 397 +- gcc/config/arm/neon.md | 21 +- gcc/config/arm/vec-common.md | 33 + gcc/config/darwin.c | 29 +- gcc/config/darwin.opt | 96 +- gcc/config/gcn/gcn-valu.md | 798 +- gcc/config/gcn/gcn.md | 2 + gcc/config/i386/darwin.h | 10 + gcc/config/i386/i386-features.c | 4 + gcc/config/i386/i386.h | 5 +- gcc/config/pa/pa.h | 1 + gcc/config/rs6000/altivec.h | 2 +- gcc/config/rs6000/rs6000.c | 39 +- gcc/config/rs6000/rs6000.md | 20 +- gcc/config/sh/sh.md | 8 +- gcc/configure | 13 +- gcc/configure.ac | 9 +- gcc/cp/ChangeLog | 230 + gcc/cp/call.c | 16 +- gcc/cp/class.c | 10 +- gcc/cp/constexpr.c | 69 +- gcc/cp/constraint.cc | 267 +- gcc/cp/coroutines.cc | 309 +- gcc/cp/cp-gimplify.c | 36 + gcc/cp/cp-tree.h | 7 +- gcc/cp/cvt.c | 11 + gcc/cp/decl.c | 3 +- gcc/cp/decl2.c | 3 +- gcc/cp/except.c | 5 +- gcc/cp/method.c | 2 +- gcc/cp/name-lookup.c | 63 +- gcc/cp/parser.c | 358 +- gcc/cp/pt.c | 13 +- gcc/cp/semantics.c | 6 +- gcc/cp/tree.c | 6 +- gcc/d/ChangeLog | 24 + gcc/d/d-lang.cc | 81 +- gcc/d/typeinfo.cc | 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gcc/testsuite/g++.dg/cpp1y/pr94066.C | 18 + gcc/testsuite/g++.dg/cpp1z/pr81349.C | 29 + gcc/testsuite/g++.dg/cpp2a/concepts-iconv1.C | 1 + gcc/testsuite/g++.dg/cpp2a/concepts-nonbool1.C | 20 + gcc/testsuite/g++.dg/cpp2a/concepts-nonbool2.C | 11 + gcc/testsuite/g++.dg/cpp2a/concepts-requires1.C | 4 +- gcc/testsuite/g++.dg/cpp2a/concepts-requires18.C | 2 +- gcc/testsuite/g++.dg/cpp2a/concepts-requires2.C | 12 +- gcc/testsuite/g++.dg/cpp2a/concepts-requires5.C | 2 +- gcc/testsuite/g++.dg/cpp2a/constexpr-union1.C | 18 + gcc/testsuite/g++.dg/debug/pr94272.C | 14 + gcc/testsuite/g++.dg/debug/pr94273.C | 4 + gcc/testsuite/g++.dg/debug/pr94281.C | 11 + gcc/testsuite/g++.dg/debug/pr94323.C | 13 + gcc/testsuite/g++.dg/ext/attr-access-2.C | 88 + gcc/testsuite/g++.dg/ext/stmtexpr15.C | 2 +- gcc/testsuite/g++.dg/lookup/pr84733.C | 21 + gcc/testsuite/g++.dg/lookup/pr94257.C | 16 + gcc/testsuite/g++.dg/opt/pr94223.C | 5 + gcc/testsuite/g++.dg/other/pr94326.C | 19 + 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| 1 - .../arm/mve/intrinsics/viwdupq_x_n_u16.c | 1 - .../arm/mve/intrinsics/viwdupq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c | 1 - .../arm/mve/intrinsics/viwdupq_x_wb_u16.c | 1 - .../arm/mve/intrinsics/viwdupq_x_wb_u32.c | 1 - .../arm/mve/intrinsics/viwdupq_x_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_s8.c | 1 - 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libstdc++-v3/testsuite/std/time/clock/file/overview.cc create mode 100644 libstdc++-v3/testsuite/std/time/syn_c++20.cc create mode 100644 libstdc++-v3/testsuite/std/time/traits/is_clock.cc -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-O2-vs-O2_LTO updated (fe26d3a34a -> 37d59eacfe)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-O2-vs-O2_LTO in repository toolchain/ci/binutils-gdb. from fe26d3a34a Make dwarf2_evaluate_property parameter const adds d9fb0d7136 Automatic date update in version.in adds e3b1fa32c2 include: Sync lto-symtab.h and plugin-api.h with GCC adds da2efc2050 Automatic date update in version.in adds d1023b5d1e s12z disassembler tidy adds 03704c7704 NS32K arg_bufs uninitialised adds beea5cc1bc ARC: Use of uninitialised value adds 57cb32b3c3 H8300 use of uninitialised value adds c15a8f173e XCOFF64 uninitialised read adds 2957d8d054 Automatic date update in version.in adds 5935fd1530 gdb/testsuite: Remove hard coded addresses from expected results adds 5e737279c6 i386msdos uninitialised read adds cf28cfef60 ECOFF archive uninitialised read adds fdde2fb60c Mention .tdata in comment in _bfd_elf_tls_setup() adds 0636b24556 Avoid trigger an assertion failure in the STABS parser by re [...] adds 1ce0847daa Automatic date update in version.in adds 5a814d6d96 readelf memory leak in process_mips_specific adds 65109548f8 Overlarge allocation in _bfd_generic_read_ar_hdr_mag adds a64fafb545 [gdb] Print user for maint info psymtabs adds 7e6e972f74 bfd: Display symbol version for nm -D adds dfb68cc358 include: Sync plugin-api.h with GCC adds cda7e5603f bfd: Change num_group to unsigned int adds ec2e748ad3 Fix assertion failure in the BFD library when linking with - [...] adds 0b8448af68 Add code to the BFD library to handle opening files with pat [...] adds e11cd7c491 Update changelog. adds 5ab2fbf185 gdb: bool-ify follow_fork adds a18cd0cab4 Uninitialised memory read in z80-dis.c adds 1081065c51 bfd: Add a bfd_boolean argument to bfd_get_symbol_version_string adds 0d4a4bc56f Automatic date update in version.in adds d16e3d2e5b PR25662, invalid sh_offset for first section in segment with phdrs adds 86fd7e2e10 h8300-linux ld testsuite adds cf2611febc arc: Use correct string when printing bfd DEBUG data adds dd8953924b gdb/riscv: Apply NaN boxing when writing return values into [...] adds 7b1eff95be [gdb] Print user/includes fields for maint commands adds b778095777 The "b" flag for COFF sections only unsets the LOAD attribut [...] adds aac88046e6 Add a new function to the BFD library to allow users access [...] adds 4c83662712 readelf looping in process_archive adds d503b685c6 Fix WOW64 process system DLL paths adds 33aa3c10f6 Fix error message in compile-object-load.c adds 46b438bb73 Automatic date update in version.in adds f75fbe8ad2 alpha-vms: Sanity check ETIR__C_CTL_DFLOC index adds 4c4addbe57 Re: ARC: Use of uninitialised value adds ff76851054 Re: i386msdos uninitialised read adds 832a580781 Re: H8300 use of uninitialised value adds aa49fc22c1 Revert earlier delta adding bfd_coff_get_internal_extra_pe_a [...] adds 9fda78b611 Introduce dwarf2/dwz.h adds 0314b3901c Add dwz.c and dwz_file::read_string adds bf80d71052 Change dwarf_decode_macro_bytes calling convention adds 9eac9650ce Split dwarf_decode_macros into two overloads adds 3d27bbdb4b Move dwarf2_section_buffer_overflow_complaint to dwarf2/section.c adds a0194fa8f2 Convert dwarf2_section_buffer_overflow_complaint to a method adds 4f44ae6c69 Add dwarf2_section_info::read_string method adds c90ec28ae4 Move code to new file dwarf2/macro.c adds 8844c11b8b Make some line_header methods const adds 5a0e026fe1 Use a const line_header in macro reader adds 4f9c1eda9f Use a const dwarf2_section_info in macro reader adds 2ef46c2fbb Trivial fix in dwarf_decode_macro_bytes adds 86c0bb4c57 Convert read_indirect_line_string to a method adds 0df7ad3a67 Move more code to line-header.c adds c2d50fd0b3 Move die_info to new header adds 2b24b6e4a6 Remove dwarf2_cu::base_known adds 052c8bb83a Change dwarf2_attr_no_follow to be a method adds 436c571c6a Remove sibling_die adds a39fdb411d Change two more functions to be methods on die_info adds eeb647814f Rewrite new die_info methods adds 2b2558bfac Move DWARF-constant stringifying code to new file adds 0826b30a9f Change two functions to be methods on struct attribute adds a879b4d5a6 Support AT_BSDFLAGS on FreeBSD. adds 89ff19d45e Automatic date update in version.in adds 80e2a3b66e Re: readelf looping in process_archive adds 1fafefd594 Add testcase for PR 25662 invalid sh_offset for section adds 8f2dae6a6a gdbsupport: Resolve shellcheck issues in create-version.sh script adds cacb9d8713 ld: Skip some x86 IFUNC tests for Solaris adds 258e884429 ld: Xfail pr20995-2 tests for Solaris adds ebea762639 Always fix system DLL paths for 32bit programs adds 8f4afc7112 Automatic date update in version.in adds 6a81c59be7 Adjust objcopy_test adds 0a6a8b596b Re: Adjust objcopy_test adds 767be9d907 ld: Set COMMONPAGESIZE for i386 Solaris adds f1749218ff Fix formatting of read_attribute_reprocess adds 4d1b9ab645 Fix comment in dwarf2/attribute.h adds 37d59eacfe Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 105 ++ bfd/archive.c | 15 +- bfd/bfd-in2.h | 5 +- bfd/bfdio.c | 36 +- bfd/coff64-rs6000.c | 4 +- bfd/ecoff.c | 35 +- bfd/elf-bfd.h | 4 +- bfd/elf.c | 46 +- bfd/elf32-arc.c | 4 +- bfd/elflink.c | 4 +- bfd/i386msdos.c | 14 +- bfd/libbfd-in.h | 2 +- bfd/libbfd.h | 2 +- bfd/syms.c | 1 + bfd/targets.c | 5 +- bfd/version.h | 2 +- bfd/vms-alpha.c | 26 +- binutils/ChangeLog | 77 ++ binutils/nm.c | 28 +- binutils/objdump.c | 3 +- binutils/readelf.c | 17 +- binutils/testsuite/binutils-all/objcopy.exp | 97 +- binutils/testsuite/binutils-all/pr25662.ld | 15 + binutils/testsuite/binutils-all/pr25662.s | 34 + binutils/wrstabs.c | 56 +- gas/ChangeLog | 9 + gas/config/obj-coff.c | 5 + gas/testsuite/gas/s12z/truncated.d | 6 +- gdb/ChangeLog | 262 ++++ gdb/Makefile.in | 3 + gdb/compile/compile-object-load.c | 2 +- gdb/dwarf2/attribute.c | 37 + gdb/dwarf2/attribute.h | 18 +- gdb/dwarf2/die.h | 103 ++ gdb/dwarf2/dwz.c | 40 + gdb/dwarf2/dwz.h | 65 + gdb/dwarf2/index-cache.c | 1 + gdb/dwarf2/index-write.c | 1 + gdb/dwarf2/line-header.c | 339 ++++- gdb/dwarf2/line-header.h | 32 +- gdb/dwarf2/macro.c | 868 ++++++++++++ gdb/dwarf2/macro.h | 33 + gdb/dwarf2/read.c | 1722 ++---------------------- gdb/dwarf2/read.h | 39 +- gdb/dwarf2/section.c | 26 + gdb/dwarf2/section.h | 9 + gdb/dwarf2/stringify.c | 114 ++ gdb/dwarf2/stringify.h | 38 + gdb/fbsd-nat.c | 6 +- gdb/fbsd-nat.h | 2 +- gdb/fbsd-tdep.c | 1 + gdb/inf-ptrace.c | 6 +- gdb/inf-ptrace.h | 2 +- gdb/infrun.c | 23 +- gdb/linux-nat.c | 6 +- gdb/linux-nat.h | 2 +- gdb/psymtab.c | 5 + gdb/remote.c | 9 +- gdb/riscv-tdep.c | 69 +- gdb/symmisc.c | 54 +- gdb/symtab.h | 7 + gdb/target-delegates.c | 24 +- gdb/target.c | 13 +- gdb/target.h | 6 +- gdb/testsuite/ChangeLog | 5 + gdb/testsuite/gdb.fortran/mixed-lang-stack.exp | 4 +- gdb/windows-nat.c | 49 +- gdbsupport/ChangeLog | 4 + gdbsupport/create-version.sh | 18 +- include/ChangeLog | 15 + include/elf/common.h | 1 + include/lto-symtab.h | 2 +- include/plugin-api.h | 67 +- ld/ChangeLog | 125 ++ ld/Makefile.am | 2 + ld/Makefile.in | 3 + ld/emulparams/elf_i386_ldso.sh | 1 + ld/po/BLD-POTFILES.in | 1 + ld/testsuite/ld-elf/compress1c.d | 1 + ld/testsuite/ld-elf/compressed1c.d | 1 + ld/testsuite/ld-elf/compressed1e.d | 2 +- ld/testsuite/ld-elf/dynamic1.d | 1 + ld/testsuite/ld-elf/dynsym1.d | 1 + ld/testsuite/ld-elf/ehdr_start-shared.d | 2 +- ld/testsuite/ld-elf/exclude3b.d | 1 + ld/testsuite/ld-elf/export-class.exp | 2 +- ld/testsuite/ld-elf/global1.d | 1 + ld/testsuite/ld-elf/hash.d | 1 + ld/testsuite/ld-elf/loadaddr1.d | 1 + ld/testsuite/ld-elf/loadaddr2.d | 1 + ld/testsuite/ld-elf/local1.d | 1 + ld/testsuite/ld-elf/mbind1b.d | 1 + ld/testsuite/ld-elf/mbind1c.d | 1 + ld/testsuite/ld-elf/now-1.d | 1 + ld/testsuite/ld-elf/now-2.d | 1 + ld/testsuite/ld-elf/now-3.d | 1 + ld/testsuite/ld-elf/now-4.d | 1 + ld/testsuite/ld-elf/pie.d | 1 + ld/testsuite/ld-elf/pr12975.d | 2 +- ld/testsuite/ld-elf/pr13177.d | 2 +- ld/testsuite/ld-elf/pr13195.d | 2 +- ld/testsuite/ld-elf/pr16322.d | 1 + ld/testsuite/ld-elf/pr16498a.d | 1 + ld/testsuite/ld-elf/pr16498b.d | 1 + ld/testsuite/ld-elf/pr17615.d | 2 +- ld/testsuite/ld-elf/pr19162.d | 2 +- ld/testsuite/ld-elf/pr19539.d | 2 +- ld/testsuite/ld-elf/pr19617a.d | 1 + ld/testsuite/ld-elf/pr19698.d | 1 + ld/testsuite/ld-elf/pr20513c.d | 1 + ld/testsuite/ld-elf/pr20513d.d | 1 + ld/testsuite/ld-elf/pr21389a.d | 1 + ld/testsuite/ld-elf/pr21389b.d | 1 + ld/testsuite/ld-elf/pr21389c.d | 1 + ld/testsuite/ld-elf/pr21562a.d | 2 +- ld/testsuite/ld-elf/pr21562b.d | 2 +- ld/testsuite/ld-elf/pr21562c.d | 2 +- ld/testsuite/ld-elf/pr21562d.d | 2 +- ld/testsuite/ld-elf/pr21562e.d | 1 + ld/testsuite/ld-elf/pr21562f.d | 1 + ld/testsuite/ld-elf/pr21562g.d | 1 + ld/testsuite/ld-elf/pr21562h.d | 1 + ld/testsuite/ld-elf/pr21562i.d | 2 +- ld/testsuite/ld-elf/pr21562j.d | 2 +- ld/testsuite/ld-elf/pr21562k.d | 2 +- ld/testsuite/ld-elf/pr21562l.d | 2 +- ld/testsuite/ld-elf/pr21562m.d | 2 +- ld/testsuite/ld-elf/pr21562n.d | 2 +- ld/testsuite/ld-elf/pr21903a.d | 1 + ld/testsuite/ld-elf/pr21903b.d | 1 + ld/testsuite/ld-elf/pr21903d.d | 1 + ld/testsuite/ld-elf/pr22269a.d | 1 + ld/testsuite/ld-elf/pr22269b.d | 1 + ld/testsuite/ld-elf/pr22393-1a.d | 1 + ld/testsuite/ld-elf/pr22393-1b.d | 1 + ld/testsuite/ld-elf/pr22393-1c.d | 1 + ld/testsuite/ld-elf/pr22393-1d.d | 1 + ld/testsuite/ld-elf/pr22393-1e.d | 1 + ld/testsuite/ld-elf/pr22393-1f.d | 1 + ld/testsuite/ld-elf/pr22423.d | 1 + ld/testsuite/ld-elf/pr22450.d | 2 +- ld/testsuite/ld-elf/pr23658-1c.d | 1 + ld/testsuite/ld-elf/pr25708.d | 11 + ld/testsuite/ld-elf/rpath-1.d | 1 + ld/testsuite/ld-elf/rpath-2.d | 1 + ld/testsuite/ld-elf/runpath-1.d | 1 + ld/testsuite/ld-elf/runpath-2.d | 1 + ld/testsuite/ld-elf/sizeofb.d | 1 + ld/testsuite/ld-elf/startofb.d | 1 + ld/testsuite/ld-elf/strtab.d | 1 + ld/testsuite/ld-elf/textaddr1.d | 1 + ld/testsuite/ld-elf/textaddr2.d | 1 + ld/testsuite/ld-elf/textaddr4.d | 1 + ld/testsuite/ld-elf/textaddr5.d | 1 + ld/testsuite/ld-elf/textaddr6.d | 1 + ld/testsuite/ld-elf/unknown2.d | 1 + ld/testsuite/ld-h8300/gcsection.d | 5 +- ld/testsuite/ld-h8300/h8300.exp | 19 +- ld/testsuite/ld-h8300/relax-2.d | 4 +- ld/testsuite/ld-h8300/relax-3.d | 4 +- ld/testsuite/ld-h8300/relax-4.d | 4 +- ld/testsuite/ld-h8300/relax-5.d | 4 +- ld/testsuite/ld-h8300/relax-6.d | 4 +- ld/testsuite/ld-h8300/relax-7.d | 4 +- ld/testsuite/ld-h8300/relax.d | 2 +- ld/testsuite/ld-ifunc/ifunc-23a-x86.d | 1 + ld/testsuite/ld-ifunc/ifunc-24a-x86.d | 1 + ld/testsuite/ld-ifunc/ifunc-25a-x86.d | 1 + ld/testsuite/ld-undefined/entry-3.d | 1 + ld/testsuite/ld-undefined/entry-4.d | 1 + opcodes/ChangeLog | 70 + opcodes/arc-dis.c | 11 +- opcodes/disassemble.c | 10 +- opcodes/disassemble.h | 6 + opcodes/h8300-dis.c | 261 ++-- opcodes/ns32k-dis.c | 19 +- opcodes/s12z-dis.c | 14 +- opcodes/s12z-opc.c | 1030 +++++++++----- opcodes/z80-dis.c | 1 + 179 files changed, 4167 insertions(+), 2359 deletions(-) create mode 100644 binutils/testsuite/binutils-all/pr25662.ld create mode 100644 binutils/testsuite/binutils-all/pr25662.s create mode 100644 gdb/dwarf2/die.h create mode 100644 gdb/dwarf2/dwz.c create mode 100644 gdb/dwarf2/dwz.h create mode 100644 gdb/dwarf2/macro.c create mode 100644 gdb/dwarf2/macro.h create mode 100644 gdb/dwarf2/stringify.c create mode 100644 gdb/dwarf2/stringify.h create mode 100644 ld/testsuite/ld-elf/pr25708.d -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-O2-vs-O2_LTO updated (26ececf8 -> e1d63d16)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-spec2k6-O2-vs-O2_LTO in repository toolchain/ci/base-artifacts. discards 26ececf8 2: update: binutils-gcc-glibc: 1 new e1d63d16 2: update: binutils-gcc-glibc: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (26ececf8) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk_tk1/gnu-master-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 181 +- 02-prepare_abe/console.log | 230 +- 03-build_abe-binutils/console.log | 10898 +- 04-build_abe-stage1/console.log | 20408 ++-- 05-build_abe-linux/console.log | 284 +- 06-build_abe-glibc/console.log | 38780 +++---- 07-build_abe-stage2/console.log | 45329 ++++---- 08-benchmark--O2_marm/benchmark-start.log | 2 +- 08-benchmark--O2_marm/benchmark.log | 13 +- 08-benchmark--O2_marm/console.log | 145 +- 09-benchmark--O2_LTO_marm/benchmark-start.log | 2 +- 09-benchmark--O2_LTO_marm/benchmark.log | 78 +- 09-benchmark--O2_LTO_marm/console.log | 242 +- 10-check_regression/console.log | 2385 +- 10-check_regression/new-results-0.csv | 58 +- 10-check_regression/new-results-1.csv | 58 +- 10-check_regression/new-results-brief.csv | 58 +- 10-check_regression/new-results-full.csv | 58 +- 10-check_regression/new-results.csv | 58 +- 10-check_regression/new-results.log | 4212 +- 10-check_regression/new-results.regressions | 4 + 10-check_regression/ref-results-0.csv | 58 +- 10-check_regression/ref-results-1.csv | 58 +- 10-check_regression/ref-results-brief.csv | 58 +- 10-check_regression/ref-results-full.csv | 58 +- 10-check_regression/ref-results.csv | 58 +- 10-check_regression/ref-results.log | 4262 +- 10-check_regression/ref-results.regressions | 9 + 11-update_baseline/console.log | 7257 +- 11-update_baseline/new-results-0.csv | 58 +- 11-update_baseline/new-results-1.csv | 58 +- 11-update_baseline/new-results-brief.csv | 58 +- 11-update_baseline/new-results-full.csv | 58 +- 11-update_baseline/new-results.csv | 58 +- 11-update_baseline/new-results.log | 4290 +- 11-update_baseline/new-results.regressions | 4 + 11-update_baseline/ref-results.log | 1874 +- 11-update_baseline/ref-results.regressions | 11 + 11-update_baseline/results.regressions | 1 + console.log | 126205 ++++++++++++----------- jenkins/manifest.sh | 20 +- regressions.txt | 2 - results | 1 - results_id-1 | 2 +- results_id-2 | 2 +- 45 files changed, 134105 insertions(+), 133898 deletions(-) create mode 100644 10-check_regression/new-results.regressions create mode 100644 10-check_regression/ref-results.regressions create mode 100644 11-update_baseline/new-results.regressions create mode 100644 11-update_baseline/ref-results.regressions create mode 100644 11-update_baseline/results.regressions delete mode 100644 regressions.txt -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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Tcwg-commits March 2020