Tcwg-commits March 2020

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[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_O3 updated (37482edc3f7 -> 9fc985118d9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_O3 in repository toolchain/ci/gcc. from 37482edc3f7 d/dmd: Merge upstream dmd d1a606599 adds 9def91e9f2a c: Fix up cfun->function_end_locus from the C FE [PR94029] adds f7dceb4e658 Fix cgraph_node::function_symbol availability compuattion [ [...] adds 3373d3e38ea Daily bump. adds 94e2418780f c++: Avoid unnecessary empty class copy [94175]. adds 4a18f168f47 [rs6000] Rewrite the declaration of a variable adds 05009698eeb gcc, Arm: Fix no_cond issue introduced by MVE adds 4119cd693d2 store-merging: Fix up -fnon-call-exceptions handling [PR94224] adds 0efe7d8796e gcc, Arm: Fix MVE move from GPR -> GPR adds 005f6fc59e5 gcc, Arm: Fix testisms for MVE testsuite adds 719c864225e gcc, Arm: Revert changes to {get,set}_fpscr adds 8fefa21fcf6 tree-optimization/94266 - fix object type extraction heuristics adds 7d4549b2cd2 Fix correct offset in ipa_get_jf_ancestor_result. adds 3eff57aacfe [ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic p [...] adds 85a94e87901 [ARM][GCC][7x]: MVE vreinterpretq and vuninitializedq intrinsics. adds 92f80065d10 [ARM][GCC][1/8x]: MVE ACLE vidup, vddup, viwdup and vdwdup [...] adds 41e1a7ffae9 [ARM][GCC][2/8x]: MVE ACLE gather load and scatter store in [...] adds 3d42842c07f fix CTOR vectorization adds 261014a1be4 [ARM][GCC][9x]: MVE ACLE predicated intrinsics with (dont-c [...] adds 828878c35c8 c++: Include the constraint parameter mapping in diagnostic [...] adds c3562f81042 [ARM][GCC][10x]: MVE ACLE intrinsics "add with carry across [...] adds 1aa22b1916a c-family: Tighten vector handling in type_for_mode [PR94072] adds b5446d0cc09 d: Fix SEGV in hash_table<odr_name_hasher, false, xcallocat [...] adds 1dfcc3b541c [ARM][GCC][11x]: MVE ACLE vector interleaving store and dei [...] adds a23eff1bd04 c++: Add testcases from PR c++/69694 adds a89349e664f adjust SLP tree dumping adds 72b3bc895f0 Fix verifier ICE on wrong comdat local flag [PR93347] adds 68dd57808f7 rs6000: Add command line and builtin compatibility check adds cc3afc9db07 Regenerate gcc.pot. adds 29f23ed79b6 sra: Cap number of sub-access propagations with a param (PR 93435) adds 8416602026d Daily bump. adds 15711e837b2 Fix comma at end of enumerator list seen with -std=c++98. adds 497498c878d lra: Tighten check for reloading paradoxical subregs [PR94052] adds b599bf9d6d1 c++: Reject changing active member of union during initiali [...] adds 98eb7b2ed24 d: Fix ICE in add_symbol_to_partition_1, at lto/lto-partiti [...] adds 837cece888f Darwin: Address translation comments (PR93694). adds dfb25dfe3d3 Darwin: Handle NULL DECL_SIZE_TYPE in machopic_select_secti [...] adds 9fc985118d9 libstdc++: Fix path::generic_string allocator handling (PR 94242) No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 1585 ++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 7 + gcc/c-family/c-common.c | 11 +- gcc/c/ChangeLog | 14 + gcc/c/c-decl.c | 4 +- gcc/c/c-parser.c | 51 +- gcc/c/c-tree.h | 2 +- gcc/cgraph.c | 90 +- gcc/cgraph.h | 17 +- gcc/config/arm/arm-builtins.c | 86 + gcc/config/arm/arm.md | 8 +- gcc/config/arm/arm_mve.h | 8413 ++++++++-- gcc/config/arm/arm_mve_builtins.def | 61 + gcc/config/arm/iterators.md | 8 + gcc/config/arm/mve.md | 1250 +- gcc/config/arm/neon.md | 32 +- gcc/config/arm/unspecs.md | 4 +- gcc/config/arm/vec-common.md | 42 +- gcc/config/arm/vfp.md | 7 +- gcc/config/darwin.c | 29 +- gcc/config/darwin.opt | 96 +- gcc/config/rs6000/rs6000-internal.h | 1 - gcc/config/rs6000/rs6000.c | 9 +- gcc/config/rs6000/rs6000.h | 1 + gcc/cp/ChangeLog | 39 + gcc/cp/call.c | 4 + gcc/cp/constexpr.c | 69 +- gcc/cp/cp-gimplify.c | 13 +- gcc/cp/cp-tree.h | 1 + gcc/cp/cxx-pretty-print.c | 18 +- gcc/cp/cxx-pretty-print.h | 1 + gcc/cp/error.c | 35 +- gcc/d/ChangeLog | 25 + gcc/d/d-tree.h | 5 + gcc/d/decl.cc | 10 +- gcc/d/typeinfo.cc | 47 +- gcc/d/types.cc | 48 + gcc/gimple-ssa-sprintf.c | 4 +- gcc/gimple-ssa-store-merging.c | 4 +- gcc/ipa-cp.c | 5 +- gcc/ipa-fnsummary.c | 4 - gcc/ipa-inline-transform.c | 9 +- gcc/ipa-split.c | 2 +- gcc/lra-constraints.c | 24 +- gcc/params.opt | 4 + gcc/po/ChangeLog | 4 + gcc/po/gcc.pot | 15239 +++++++++++-------- gcc/symtab.c | 11 + gcc/testsuite/ChangeLog | 642 + gcc/testsuite/g++.dg/abi/empty30.C | 14 + gcc/testsuite/g++.dg/concepts/diagnostic6.C | 14 + gcc/testsuite/g++.dg/cpp0x/decltype74.C | 30 + gcc/testsuite/g++.dg/cpp0x/decltype75.C | 24 + gcc/testsuite/g++.dg/cpp1y/constexpr-union2.C | 9 + gcc/testsuite/g++.dg/cpp1y/constexpr-union3.C | 9 + gcc/testsuite/g++.dg/cpp1y/constexpr-union4.C | 9 + gcc/testsuite/g++.dg/cpp1y/constexpr-union5.C | 15 + gcc/testsuite/g++.dg/cpp1y/pr94066-2.C | 19 + gcc/testsuite/g++.dg/cpp1y/pr94066-3.C | 16 + gcc/testsuite/g++.dg/cpp1y/pr94066.C | 18 + gcc/testsuite/g++.dg/cpp2a/constexpr-union1.C | 18 + gcc/testsuite/g++.dg/torture/pr93347.C | 306 + gcc/testsuite/g++.dg/torture/pr94202.C | 22 + gcc/testsuite/g++.dg/tree-ssa/pr94224.C | 34 + gcc/testsuite/g++.target/aarch64/pr94052.C | 174 + gcc/testsuite/gcc.dg/tree-ssa/pr93435.c | 159 + gcc/testsuite/gcc.misc-tests/gcov-pr94029.c | 14 + gcc/testsuite/gcc.target/aarch64/pr94072.c | 9 + .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 2 +- .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 1 + .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 1 + .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 18 + .../arm/mve/intrinsics/mve_vector_float.c | 3 +- .../arm/mve/intrinsics/mve_vector_float1.c | 3 +- .../arm/mve/intrinsics/mve_vector_float2.c | 3 +- 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c create mode 100644 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create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c create mode 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mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c create 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mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c create mode 100644 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mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c create mode 100644 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gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c 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5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_O3 updated (2bd40f1 -> 8945e6e)

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5 years, 3 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig updated (5ad0ec0b8652 -> b74b991fb8b9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig in repository toolchain/ci/linux. from 5ad0ec0b8652 Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/li [...] adds af3d0a68698c powerpc/kasan: Fix shadow memory protection with CONFIG_KA [...] adds 1d0c32ec3b86 KVM: PPC: Fix kernel crash with PR KVM adds c63c50fc2ec9 Merge tag 'powerpc-5.6-5' of git://git.kernel.org/pub/scm/ [...] adds 081c54323b27 tools/power turbostat: Support Cometlake adds d8d005ba6afa tools/power turbostat: Fix gcc build warnings adds 4bf7132a0ace tools/power turbostat: Support Tiger Lake adds 23274faf9650 tools/power turbostat: Support Ice Lake server adds d7814c3098dd tools/power turbostat: Support Jasper Lake adds f6708400707f tools/power turbostat: Support Elkhart Lake adds 1f81c5efc020 tools/power turbostat: Fix missing SYS_LPI counter on some [...] adds fcaa681c03ea tools/power turbostat: Fix 32-bit capabilities warning adds abdcbdb26526 tools/power turbostat: Print cpuidle information adds b95fffb9b4af tools/power turbostat: update version adds 6c1bae744d5a Merge branch 'turbostat' of git://git.kernel.org/pub/scm/l [...] adds f1d96a8fcbbb io_uring: NULL-deref for IOSQE_{ASYNC,DRAIN} adds 4022e7af86be io_uring: make sure openat/openat2 honor rlimit nofile adds 09952e3e7826 io_uring: make sure accept honor rlimit nofile adds 1ab7ea1f83d1 Merge tag 'io_uring-5.6-20200320' of git://git.kernel.dk/l [...] adds 9134ae2a2546 nvme-rdma: Avoid double freeing of async event data adds 98fd5c723730 nvmet-tcp: set MSG_MORE only if we actually have more to send adds 83166ac82b53 Merge branch 'nvme-5.6-rc6' of git://git.infradead.org/nvm [...] adds b74b991fb8b9 Merge tag 'block-5.6-20200320' of git://git.kernel.dk/linux-block No new revisions were added by this update. Summary of changes: arch/powerpc/kvm/book3s_pr.c | 1 + arch/powerpc/kvm/powerpc.c | 2 - arch/powerpc/mm/kasan/kasan_init_32.c | 9 +-- drivers/nvme/host/rdma.c | 8 +- drivers/nvme/target/tcp.c | 12 ++- fs/file.c | 7 +- fs/io_uring.c | 18 ++++- include/linux/file.h | 1 + include/linux/socket.h | 3 +- net/socket.c | 8 +- tools/power/x86/turbostat/Makefile | 2 +- tools/power/x86/turbostat/turbostat.c | 142 +++++++++++++++++++++++++++------- 12 files changed, 161 insertions(+), 52 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig updated (bdab45d -> 0a57b33)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-defconfig in repository toolchain/ci/base-artifacts. discards bdab45d 0: update: binutils-gcc-linux: boot new 0a57b33 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (bdab45d) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-m [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 130 +- 02-prepare_abe/console.log | 234 +- 03-build_abe-binutils/console.log | 11355 +++++++------ 04-build_abe-stage1/console.log | 18146 +++++++++++---------- 05-build_linux/console.log | 646 +- 06-boot_linux/console.log | 484 +- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 2 +- console.log | 31019 ++++++++++++++++++------------------ jenkins/manifest.sh | 8 +- regressions.txt | 2 +- 11 files changed, 31007 insertions(+), 31021 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-defconfig updated (257edc6db943 -> 585e0cc08069)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-defconfig in repository toolchain/ci/linux. from 257edc6db943 Linux 5.4.26 adds 536942bf70b5 netfilter: hashlimit: do not use indirect calls during gc adds f6fccb0a0e59 netfilter: xt_hashlimit: unregister proc file before relea [...] adds f3c478104a9a drm/amdgpu: Fix TLB invalidation request when using semaphore adds 20eed7692749 ACPI: watchdog: Allow disabling WDAT at boot adds 65b44497414b HID: apple: Add support for recent firmware on Magic Keyboards adds 87bd74b77531 ACPI: watchdog: Set default timeout in probe adds 190e929e6cba HID: i2c-hid: add Trekstor Surfbook E11B to descriptor override adds 1bc271dd397d HID: hid-bigbenff: fix general protection fault caused by [...] adds ccb747d805d3 HID: hid-bigbenff: call hid_hw_stop() in case of error adds dd0d2d6ab6a2 HID: hid-bigbenff: fix race condition for scheduled work d [...] adds c35aa36fec91 selftests/rseq: Fix out-of-tree compilation adds a6f7e69cfafd tracing: Fix number printing bug in print_synth_event() adds 079e9ad79410 cfg80211: check reg_rule for NULL in handle_channel_custom() adds 6c663120ecdb scsi: libfc: free response frame from GPN_ID adds d939f3389f9b net: usb: qmi_wwan: restore mtu min/max values after raw_i [...] adds 5d92d834aa27 net: ks8851-ml: Fix IRQ handling and locking adds a342bb7b9902 mac80211: rx: avoid RCU list traversal under mutex adds 0c050d655475 net: ll_temac: Fix race condition causing TX hang adds 6e3b69543b5e net: ll_temac: Add more error handling of dma_map_single() calls adds c2cffaea4fde net: ll_temac: Fix RX buffer descriptor handling on GFP_AT [...] adds 74886a6d9de8 net: ll_temac: Handle DMA halt condition caused by buffer [...] adds 74c77d6a4ea9 blk-mq: insert passthrough request into hctx->dispatch directly adds bbf3acbb8a77 drm/amdgpu: fix memory leak during TDR test(v2) adds fd1f29f2a824 kbuild: add dtbs_check to PHONY adds df8e98b00941 kbuild: add dt_binding_check to PHONY in a correct place adds d1984c92f072 signal: avoid double atomic counter increments for user ac [...] adds 4d6ee3123d65 slip: not call free_netdev before rtnl_unlock in slip_open adds 1c7dde0a9bfc net: phy: mscc: fix firmware paths adds 65340b196811 hinic: fix a irq affinity bug adds e6f52d5ce172 hinic: fix a bug of setting hw_ioctxt adds cfc7f5fe5c61 hinic: fix a bug of rss configuration adds 006cd2426a05 net: rmnet: fix NULL pointer dereference in rmnet_newlink() adds 8a027eee62f7 net: rmnet: fix NULL pointer dereference in rmnet_changelink() adds 002b4bd9b51d net: rmnet: fix suspicious RCU usage adds 5ce5e95d72f1 net: rmnet: remove rcu_read_lock in rmnet_force_unassociat [...] adds 835bbd892683 net: rmnet: do not allow to change mux id if mux id is duplicated adds 8eccc6d06ea1 net: rmnet: use upper/lower device infrastructure adds 34c550ebb219 net: rmnet: fix bridge mode bugs adds e2b8b042c98b net: rmnet: fix packet forwarding in rmnet bridge mode adds 99746e92fa4c sfc: fix timestamp reconstruction at 16-bit rollover points adds dbce8292217a jbd2: fix data races at struct journal_head adds 235fb892d846 blk-mq: insert flush request to the front of dispatch queue adds 881876bee657 net: qrtr: fix len of skb_put_padto in qrtr_node_enqueue adds 1a9e78628d44 ARM: 8957/1: VDSO: Match ARMv8 timer in cntvct_functional() adds 47b6d269dbbd ARM: 8958/1: rename missed uaccess .fixup section adds ae119b7e1247 mm: slub: add missing TID bump in kmem_cache_alloc_bulk() adds 5d961582ea88 HID: google: add moonball USB id adds 1dc67950e2d1 HID: add ALWAYS_POLL quirk to lenovo pixart mouse adds 81e0dac3780a ARM: 8961/2: Fix Kbuild issue caused by per-task stack pro [...] adds 20ba40d262b0 ipv4: ensure rcu_read_lock() in cipso_v4_error() adds 585e0cc08069 Linux 5.4.27 No new revisions were added by this update. Summary of changes: Documentation/admin-guide/kernel-parameters.txt | 4 + Makefile | 5 +- arch/arm/Makefile | 4 +- arch/arm/boot/compressed/Makefile | 4 +- arch/arm/kernel/vdso.c | 2 + arch/arm/lib/copy_from_user.S | 2 +- block/blk-flush.c | 2 +- block/blk-mq-sched.c | 44 ++++- block/blk-mq.c | 18 +- block/blk-mq.h | 3 +- drivers/acpi/acpi_watchdog.c | 12 +- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 5 +- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 +- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 +- drivers/hid/hid-apple.c | 3 +- drivers/hid/hid-bigbenff.c | 31 ++- drivers/hid/hid-google-hammer.c | 2 + drivers/hid/hid-ids.h | 2 + drivers/hid/hid-quirks.c | 1 + drivers/hid/i2c-hid/i2c-hid-dmi-quirks.c | 8 + drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c | 1 + drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h | 2 +- drivers/net/ethernet/huawei/hinic/hinic_hw_if.h | 1 + drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h | 1 + drivers/net/ethernet/huawei/hinic/hinic_main.c | 3 +- drivers/net/ethernet/huawei/hinic/hinic_rx.c | 5 +- drivers/net/ethernet/micrel/ks8851_mll.c | 14 +- drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c | 186 +++++++++--------- drivers/net/ethernet/qualcomm/rmnet/rmnet_config.h | 3 +- .../net/ethernet/qualcomm/rmnet/rmnet_handlers.c | 7 +- drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.c | 8 - drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.h | 1 - drivers/net/ethernet/sfc/ptp.c | 38 +++- drivers/net/ethernet/xilinx/ll_temac.h | 4 + drivers/net/ethernet/xilinx/ll_temac_main.c | 209 +++++++++++++++++---- drivers/net/phy/mscc.c | 4 +- drivers/net/slip/slip.c | 3 + drivers/net/usb/qmi_wwan.c | 3 + drivers/scsi/libfc/fc_disc.c | 2 + drivers/watchdog/wdat_wdt.c | 23 +++ fs/jbd2/transaction.c | 8 +- kernel/signal.c | 23 ++- kernel/trace/trace_events_hist.c | 32 +++- mm/slub.c | 9 + net/ipv4/cipso_ipv4.c | 7 +- net/mac80211/rx.c | 2 +- net/netfilter/xt_hashlimit.c | 36 +--- net/qrtr/qrtr.c | 2 +- net/wireless/reg.c | 2 +- tools/testing/selftests/rseq/Makefile | 2 +- 50 files changed, 560 insertions(+), 247 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-defconfig updated (6f49d55 -> be76da6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-stable-defconfig in repository toolchain/ci/base-artifacts. discards 6f49d55 0: update: binutils-gcc-linux: boot new be76da6 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (6f49d55) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 166 +- 02-prepare_abe/console.log | 408 +- 03-build_abe-binutils/console.log | 11131 +++++++------ 04-build_abe-stage1/console.log | 18018 ++++++++++----------- 05-build_linux/console.log | 750 +- 06-boot_linux/console.log | 416 +- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 2 +- console.log | 30913 ++++++++++++++++++------------------ jenkins/manifest.sh | 8 +- regressions.txt | 2 +- 11 files changed, 30911 insertions(+), 30905 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-defconfig updated (257edc6db943 -> 585e0cc08069)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-defconfig in repository toolchain/ci/linux. from 257edc6db943 Linux 5.4.26 adds 536942bf70b5 netfilter: hashlimit: do not use indirect calls during gc adds f6fccb0a0e59 netfilter: xt_hashlimit: unregister proc file before relea [...] adds f3c478104a9a drm/amdgpu: Fix TLB invalidation request when using semaphore adds 20eed7692749 ACPI: watchdog: Allow disabling WDAT at boot adds 65b44497414b HID: apple: Add support for recent firmware on Magic Keyboards adds 87bd74b77531 ACPI: watchdog: Set default timeout in probe adds 190e929e6cba HID: i2c-hid: add Trekstor Surfbook E11B to descriptor override adds 1bc271dd397d HID: hid-bigbenff: fix general protection fault caused by [...] adds ccb747d805d3 HID: hid-bigbenff: call hid_hw_stop() in case of error adds dd0d2d6ab6a2 HID: hid-bigbenff: fix race condition for scheduled work d [...] adds c35aa36fec91 selftests/rseq: Fix out-of-tree compilation adds a6f7e69cfafd tracing: Fix number printing bug in print_synth_event() adds 079e9ad79410 cfg80211: check reg_rule for NULL in handle_channel_custom() adds 6c663120ecdb scsi: libfc: free response frame from GPN_ID adds d939f3389f9b net: usb: qmi_wwan: restore mtu min/max values after raw_i [...] adds 5d92d834aa27 net: ks8851-ml: Fix IRQ handling and locking adds a342bb7b9902 mac80211: rx: avoid RCU list traversal under mutex adds 0c050d655475 net: ll_temac: Fix race condition causing TX hang adds 6e3b69543b5e net: ll_temac: Add more error handling of dma_map_single() calls adds c2cffaea4fde net: ll_temac: Fix RX buffer descriptor handling on GFP_AT [...] adds 74886a6d9de8 net: ll_temac: Handle DMA halt condition caused by buffer [...] adds 74c77d6a4ea9 blk-mq: insert passthrough request into hctx->dispatch directly adds bbf3acbb8a77 drm/amdgpu: fix memory leak during TDR test(v2) adds fd1f29f2a824 kbuild: add dtbs_check to PHONY adds df8e98b00941 kbuild: add dt_binding_check to PHONY in a correct place adds d1984c92f072 signal: avoid double atomic counter increments for user ac [...] adds 4d6ee3123d65 slip: not call free_netdev before rtnl_unlock in slip_open adds 1c7dde0a9bfc net: phy: mscc: fix firmware paths adds 65340b196811 hinic: fix a irq affinity bug adds e6f52d5ce172 hinic: fix a bug of setting hw_ioctxt adds cfc7f5fe5c61 hinic: fix a bug of rss configuration adds 006cd2426a05 net: rmnet: fix NULL pointer dereference in rmnet_newlink() adds 8a027eee62f7 net: rmnet: fix NULL pointer dereference in rmnet_changelink() adds 002b4bd9b51d net: rmnet: fix suspicious RCU usage adds 5ce5e95d72f1 net: rmnet: remove rcu_read_lock in rmnet_force_unassociat [...] adds 835bbd892683 net: rmnet: do not allow to change mux id if mux id is duplicated adds 8eccc6d06ea1 net: rmnet: use upper/lower device infrastructure adds 34c550ebb219 net: rmnet: fix bridge mode bugs adds e2b8b042c98b net: rmnet: fix packet forwarding in rmnet bridge mode adds 99746e92fa4c sfc: fix timestamp reconstruction at 16-bit rollover points adds dbce8292217a jbd2: fix data races at struct journal_head adds 235fb892d846 blk-mq: insert flush request to the front of dispatch queue adds 881876bee657 net: qrtr: fix len of skb_put_padto in qrtr_node_enqueue adds 1a9e78628d44 ARM: 8957/1: VDSO: Match ARMv8 timer in cntvct_functional() adds 47b6d269dbbd ARM: 8958/1: rename missed uaccess .fixup section adds ae119b7e1247 mm: slub: add missing TID bump in kmem_cache_alloc_bulk() adds 5d961582ea88 HID: google: add moonball USB id adds 1dc67950e2d1 HID: add ALWAYS_POLL quirk to lenovo pixart mouse adds 81e0dac3780a ARM: 8961/2: Fix Kbuild issue caused by per-task stack pro [...] adds 20ba40d262b0 ipv4: ensure rcu_read_lock() in cipso_v4_error() adds 585e0cc08069 Linux 5.4.27 No new revisions were added by this update. Summary of changes: Documentation/admin-guide/kernel-parameters.txt | 4 + Makefile | 5 +- arch/arm/Makefile | 4 +- arch/arm/boot/compressed/Makefile | 4 +- arch/arm/kernel/vdso.c | 2 + arch/arm/lib/copy_from_user.S | 2 +- block/blk-flush.c | 2 +- block/blk-mq-sched.c | 44 ++++- block/blk-mq.c | 18 +- block/blk-mq.h | 3 +- drivers/acpi/acpi_watchdog.c | 12 +- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 5 +- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 +- drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 +- drivers/hid/hid-apple.c | 3 +- drivers/hid/hid-bigbenff.c | 31 ++- drivers/hid/hid-google-hammer.c | 2 + drivers/hid/hid-ids.h | 2 + drivers/hid/hid-quirks.c | 1 + drivers/hid/i2c-hid/i2c-hid-dmi-quirks.c | 8 + drivers/net/ethernet/huawei/hinic/hinic_hw_dev.c | 1 + drivers/net/ethernet/huawei/hinic/hinic_hw_dev.h | 2 +- drivers/net/ethernet/huawei/hinic/hinic_hw_if.h | 1 + drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h | 1 + drivers/net/ethernet/huawei/hinic/hinic_main.c | 3 +- drivers/net/ethernet/huawei/hinic/hinic_rx.c | 5 +- drivers/net/ethernet/micrel/ks8851_mll.c | 14 +- drivers/net/ethernet/qualcomm/rmnet/rmnet_config.c | 186 +++++++++--------- drivers/net/ethernet/qualcomm/rmnet/rmnet_config.h | 3 +- .../net/ethernet/qualcomm/rmnet/rmnet_handlers.c | 7 +- drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.c | 8 - drivers/net/ethernet/qualcomm/rmnet/rmnet_vnd.h | 1 - drivers/net/ethernet/sfc/ptp.c | 38 +++- drivers/net/ethernet/xilinx/ll_temac.h | 4 + drivers/net/ethernet/xilinx/ll_temac_main.c | 209 +++++++++++++++++---- drivers/net/phy/mscc.c | 4 +- drivers/net/slip/slip.c | 3 + drivers/net/usb/qmi_wwan.c | 3 + drivers/scsi/libfc/fc_disc.c | 2 + drivers/watchdog/wdat_wdt.c | 23 +++ fs/jbd2/transaction.c | 8 +- kernel/signal.c | 23 ++- kernel/trace/trace_events_hist.c | 32 +++- mm/slub.c | 9 + net/ipv4/cipso_ipv4.c | 7 +- net/mac80211/rx.c | 2 +- net/netfilter/xt_hashlimit.c | 36 +--- net/qrtr/qrtr.c | 2 +- net/wireless/reg.c | 2 +- tools/testing/selftests/rseq/Makefile | 2 +- 50 files changed, 560 insertions(+), 247 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-defconfig updated (d1da9b3 -> 5445c9d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-stable-defconfig in repository toolchain/ci/base-artifacts. discards d1da9b3 0: update: llvm-linux: boot new 5445c9d 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (d1da9b3) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-build_llvm/console.log | 12576 +++++++++++++++++---------------- 03-build_linux/console.log | 894 +-- 04-boot_linux/console.log | 438 +- 05-check_regression/console.log | 12 +- 06-update_baseline/console.log | 12 +- console.log | 14176 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 14150 insertions(+), 14186 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig updated (5ad0ec0b8652 -> b74b991fb8b9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig in repository toolchain/ci/linux. from 5ad0ec0b8652 Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/li [...] adds af3d0a68698c powerpc/kasan: Fix shadow memory protection with CONFIG_KA [...] adds 1d0c32ec3b86 KVM: PPC: Fix kernel crash with PR KVM adds c63c50fc2ec9 Merge tag 'powerpc-5.6-5' of git://git.kernel.org/pub/scm/ [...] adds 081c54323b27 tools/power turbostat: Support Cometlake adds d8d005ba6afa tools/power turbostat: Fix gcc build warnings adds 4bf7132a0ace tools/power turbostat: Support Tiger Lake adds 23274faf9650 tools/power turbostat: Support Ice Lake server adds d7814c3098dd tools/power turbostat: Support Jasper Lake adds f6708400707f tools/power turbostat: Support Elkhart Lake adds 1f81c5efc020 tools/power turbostat: Fix missing SYS_LPI counter on some [...] adds fcaa681c03ea tools/power turbostat: Fix 32-bit capabilities warning adds abdcbdb26526 tools/power turbostat: Print cpuidle information adds b95fffb9b4af tools/power turbostat: update version adds 6c1bae744d5a Merge branch 'turbostat' of git://git.kernel.org/pub/scm/l [...] adds f1d96a8fcbbb io_uring: NULL-deref for IOSQE_{ASYNC,DRAIN} adds 4022e7af86be io_uring: make sure openat/openat2 honor rlimit nofile adds 09952e3e7826 io_uring: make sure accept honor rlimit nofile adds 1ab7ea1f83d1 Merge tag 'io_uring-5.6-20200320' of git://git.kernel.dk/l [...] adds 9134ae2a2546 nvme-rdma: Avoid double freeing of async event data adds 98fd5c723730 nvmet-tcp: set MSG_MORE only if we actually have more to send adds 83166ac82b53 Merge branch 'nvme-5.6-rc6' of git://git.infradead.org/nvm [...] adds b74b991fb8b9 Merge tag 'block-5.6-20200320' of git://git.kernel.dk/linux-block No new revisions were added by this update. Summary of changes: arch/powerpc/kvm/book3s_pr.c | 1 + arch/powerpc/kvm/powerpc.c | 2 - arch/powerpc/mm/kasan/kasan_init_32.c | 9 +-- drivers/nvme/host/rdma.c | 8 +- drivers/nvme/target/tcp.c | 12 ++- fs/file.c | 7 +- fs/io_uring.c | 18 ++++- include/linux/file.h | 1 + include/linux/socket.h | 3 +- net/socket.c | 8 +- tools/power/x86/turbostat/Makefile | 2 +- tools/power/x86/turbostat/turbostat.c | 142 +++++++++++++++++++++++++++------- 12 files changed, 161 insertions(+), 52 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig updated (1ae737a7c6a -> d1739f1e2f2)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-mainline-allnoconfig in repository toolchain/ci/llvm-project. from 1ae737a7c6a [libc++] Temporarily disable an availability test that is broken adds fc7233d7744 Temporarily Revert "[X86] Reland D71360 Clean up UseInitArr [...] adds be10b7e43a3 Use values cached in ConstantExprs for expression evaluatio [...] adds d35a454170d [CodeGen] Emit destructor calls to destruct non-trivial C s [...] adds 09c8845adfd [lldb]/Tablegen] Use ElementType instead of DefaultValueUnsinged adds ced7617c385 PR45267: Don't reject pure-specifiers with escaped newlines [...] adds a299178ae77 [cmake] Fix -stripped for umbrella library install targets adds a8c22ba4162 [lldb-vscode] Add missing launchCommands entry in the package.json adds 4ec6ebabfc3 [lldb-vscode] Add inheritEnvironment option adds 34c0759f846 Create basic SBEnvironment class adds c85bf7cfa8b Revert "[lldb-vscode] Add inheritEnvironment option" adds e292cdfb338 Revert "[lldb-vscode] Add missing launchCommands entry in t [...] adds 7ece7c0faae Revert "Create basic SBEnvironment class" adds 85c30f3374d [X86] Reland D71360 Clean up UseInitArray initialization fo [...] adds de6cd3e836e [WebAssembly] Add SIMD integer abs builtins adds c6d799156a0 [clangd] Skip ClangdVFSTest.TestStackOverflow when address [...] adds c5fd9e3888d [DAG] Don't permit EXTLOAD when combining FSHL/FSHR consecu [...] adds 0f4c70dd3ec [clang-tidy] Add spuriously-wake-up-functions check adds b6d9bfd180c [gn build] Port 0f4c70dd3ec adds ff3aae69084 Fix Wdocumentation warning. NFCI. adds a6787244010 Fix Wdocumentation warning. NFCI. adds 770df904512 [clang-tidy] my work: fix sphinx docs adds f00a4b531a5 [InstCombine][X86] simplifyX86immShift - remove ConstantAgg [...] adds d5d8569df14 Fix static analysis warnings about classes with virtual met [...] adds f9a8650578d Revert rGd5d8569df14e95e2c53d167bd1b37995bcbec565 "Fix stat [...] adds d260a10d98d [clang] Fix crash during template sema checking adds 49ccb32fd41 Update ConversionToLLVMDialect.md adds f424d51c3e1 Revert rGe6a7e3b5e3e7 "[X86][SSE] matchShuffleWithSHUFPD - [...] adds 73cf8abbe69 [ADT] Implement the Waymarking as an independent utility adds 9ab0c9a6440 [gn build] Port 73cf8abbe69 adds 7a62ea3889b [ValueTracking] Short-circuit computeKnownBitsAddSub(); NFCI adds 4ceade04284 [X86] Combine concat(shufps,shufps) -> shufps(concat,concat) adds be41a98ac22 tsan: fix deadlock with pthread_atfork callbacks adds 05880fc9ae7 [libc++] fix some non-modular tests adds deb51033784 [libc++] Rework buildbot configuration for the greater good. adds c0e1135fb08 [libc++] Fix URL to llvm github adds 601d25cb736 [obj2yaml] - Simplify and reduce `ELFDumper<ELFT>::dumpSect [...] adds 684ee2057f5 [clang/docs] Fix various sphinx warnings/errors in docs. adds 7a3d994880c [X86][AVX] Add HADDPD test case for PR44694 adds 25eb9056d7f [X86] getTargetShuffleAndZeroables - add insert_subvector(u [...] adds 2d712fb7558 [InstCombine] Add ctpop -> cttz combine tests (PR43513) adds 920d90f9663 The generated code does not need to check for a null Decl; NFC. adds 90c74435d36 [libc++] tolerate missing diagnostic with modules enabled adds 34fd007aaf8 Revert "[ADT] Implement the Waymarking as an independent utility" adds d779ee152ce [gn build] Port 34fd007aaf8 new d1739f1e2f2 [X86] Add test for v4i8 loop sad pattern. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../clang-tidy/bugprone/BugproneTidyModule.cpp | 3 + .../clang-tidy/bugprone/CMakeLists.txt | 1 + .../bugprone/SpuriouslyWakeUpFunctionsCheck.cpp | 108 +++++++++ .../bugprone/SpuriouslyWakeUpFunctionsCheck.h | 37 ++++ .../clang-tidy/cert/CERTTidyModule.cpp | 7 + clang-tools-extra/clangd/unittests/ClangdTests.cpp | 4 + clang-tools-extra/docs/ReleaseNotes.rst | 18 ++ .../bugprone-spuriously-wake-up-functions.rst | 29 +++ .../docs/clang-tidy/checks/cert-con36-c.rst | 10 + .../docs/clang-tidy/checks/cert-con54-cpp.rst | 10 + clang-tools-extra/docs/clang-tidy/checks/list.rst | 3 + .../bugprone-spuriously-wake-up-functions.c | 164 ++++++++++++++ .../bugprone-spuriously-wake-up-functions.cpp | 191 ++++++++++++++++ clang/CMakeLists.txt | 1 + clang/docs/InternalsManual.rst | 2 +- clang/docs/LanguageExtensions.rst | 2 +- clang/docs/OpenMPSupport.rst | 4 +- clang/docs/analyzer/checkers.rst | 4 +- clang/docs/analyzer/developer-docs/DebugChecks.rst | 2 +- clang/include/clang/AST/Expr.h | 3 + clang/include/clang/Basic/AttrDocs.td | 16 +- clang/include/clang/Basic/BuiltinsWebAssembly.def | 4 + clang/include/clang/Basic/DiagnosticGroups.td | 2 +- clang/lib/AST/Expr.cpp | 8 +- clang/lib/AST/ExprConstant.cpp | 9 +- clang/lib/CodeGen/CGBuiltin.cpp | 9 + clang/lib/CodeGen/CGCall.cpp | 5 + clang/lib/CodeGen/CGCall.h | 33 ++- clang/lib/CodeGen/CGClass.cpp | 4 +- clang/lib/CodeGen/CGExprAgg.cpp | 21 +- clang/lib/CodeGen/CGExprConstant.cpp | 4 +- clang/lib/CodeGen/CGVTables.cpp | 3 +- clang/lib/Parse/ParseDeclCXX.cpp | 2 +- clang/lib/Sema/SemaChecking.cpp | 13 +- clang/lib/Sema/SemaDecl.cpp | 3 + clang/lib/Sema/SemaDeclCXX.cpp | 1 - clang/lib/Sema/SemaExpr.cpp | 9 + clang/lib/Sema/SemaExprCXX.cpp | 3 + clang/test/CodeGen/builtins-wasm.c | 24 ++ clang/test/CodeGenObjC/arc.m | 11 +- clang/test/CodeGenObjC/strong-in-c-struct.m | 79 +++++++ clang/test/Parser/cxx-class.cpp | 4 +- ...-memcpy-inline.c => builtins-memcpy-inline.cpp} | 6 + clang/utils/TableGen/ClangAttrEmitter.cpp | 4 +- compiler-rt/lib/tsan/rtl/tsan_rtl.cpp | 9 + compiler-rt/test/tsan/pthread_atfork_deadlock2.c | 49 ++++ .../array/array.creation/to_array.fail.cpp | 2 +- .../std/containers/sequences/deque/types.pass.cpp | 2 + .../std/containers/sequences/list/types.pass.cpp | 2 + .../std/containers/sequences/vector/types.pass.cpp | 2 + libcxx/utils/docker/debian9/buildbot/Dockerfile | 40 ++++ .../docker/debian9/buildbot/buildbot-auth.json | 4 + .../docker/debian9/buildbot/docker-compose.yml | 19 ++ .../debian9/buildbot/install-gcloud-agents.sh | 11 + .../docker/debian9/buildbot/install-packages.sh | 35 +++ .../debian9/{scripts => }/buildbot/run_buildbot.sh | 41 ++-- libcxx/utils/docker/debian9/compilers.yml | 174 --------------- .../docker/debian9/compilers/clang.Dockerfile | 19 -- .../debian9/compilers/compiler-zoo.Dockerfile | 37 ---- .../utils/docker/debian9/compilers/gcc.Dockerfile | 24 -- libcxx/utils/docker/debian9/docker-compose.yml | 14 -- .../docker/debian9/llvm-buildbot-worker.Dockerfile | 23 -- .../docker/debian9/llvm-builder-base.Dockerfile | 47 ---- .../docker/debian9/scripts/build_gcc_version.sh | 108 --------- .../docker/debian9/scripts/build_llvm_version.sh | 106 --------- .../scripts/buildbot/docker_start_buildbots.sh | 8 - .../debian9/scripts/install_clang_packages.sh | 81 ------- lldb/include/lldb/Core/PropertiesBase.td | 6 + lldb/source/Target/TargetProperties.td | 6 +- lldb/utils/TableGen/LLDBPropertyDefEmitter.cpp | 15 +- llvm/CMakeLists.txt | 1 + llvm/lib/Analysis/ValueTracking.cpp | 14 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 4 +- llvm/lib/Target/AVR/MCTargetDesc/AVRFixupKinds.h | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 43 +++- .../Transforms/InstCombine/InstCombineCalls.cpp | 30 ++- llvm/test/CodeGen/X86/funnel-shift.ll | 64 ++++++ llvm/test/CodeGen/X86/haddsub-undef.ll | 28 +++ llvm/test/CodeGen/X86/masked_store_trunc.ll | 18 +- llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll | 36 ++- llvm/test/CodeGen/X86/masked_store_trunc_usat.ll | 30 ++- llvm/test/CodeGen/X86/pr40891.ll | 6 +- llvm/test/CodeGen/X86/sad.ll | 75 +++++++ llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll | 2 +- llvm/test/CodeGen/X86/var-permute-256.ll | 50 ++--- llvm/test/CodeGen/X86/vector-reduce-and-bool.ll | 6 +- llvm/test/CodeGen/X86/vector-reduce-mul.ll | 4 +- llvm/test/CodeGen/X86/vector-reduce-or-bool.ll | 6 +- llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll | 6 +- llvm/test/CodeGen/X86/vector-trunc-math.ll | 240 ++++++++------------ llvm/test/CodeGen/X86/vector-trunc-packus.ll | 40 ++-- llvm/test/CodeGen/X86/vector-trunc-ssat.ll | 34 ++- llvm/test/CodeGen/X86/vector-trunc-usat.ll | 26 +-- llvm/test/CodeGen/X86/vector-trunc.ll | 58 ++--- llvm/test/Transforms/InstCombine/ctpop-cttz.ll | 69 ++++++ llvm/tools/llc/llc.cpp | 4 +- llvm/tools/obj2yaml/elf2yaml.cpp | 246 +++++++-------------- .../clang-tools-extra/clang-tidy/bugprone/BUILD.gn | 1 + mlir/docs/ConversionToLLVMDialect.md | 14 +- 99 files changed, 1647 insertions(+), 1274 deletions(-) create mode 100644 clang-tools-extra/clang-tidy/bugprone/SpuriouslyWakeUpFunctions [...] create mode 100644 clang-tools-extra/clang-tidy/bugprone/SpuriouslyWakeUpFunctionsCheck.h create mode 100644 clang-tools-extra/docs/clang-tidy/checks/bugprone-spuriously-wa [...] create mode 100644 clang-tools-extra/docs/clang-tidy/checks/cert-con36-c.rst create mode 100644 clang-tools-extra/docs/clang-tidy/checks/cert-con54-cpp.rst create mode 100644 clang-tools-extra/test/clang-tidy/checkers/bugprone-spuriously- [...] create mode 100644 clang-tools-extra/test/clang-tidy/checkers/bugprone-spuriously- [...] rename clang/test/Sema/{builtins-memcpy-inline.c => builtins-memcpy-inline.cpp} (86%) create mode 100644 compiler-rt/test/tsan/pthread_atfork_deadlock2.c create mode 100644 libcxx/utils/docker/debian9/buildbot/Dockerfile create mode 100644 libcxx/utils/docker/debian9/buildbot/buildbot-auth.json create mode 100644 libcxx/utils/docker/debian9/buildbot/docker-compose.yml create mode 100755 libcxx/utils/docker/debian9/buildbot/install-gcloud-agents.sh create mode 100755 libcxx/utils/docker/debian9/buildbot/install-packages.sh rename libcxx/utils/docker/debian9/{scripts => }/buildbot/run_buildbot.sh (72%) delete mode 100644 libcxx/utils/docker/debian9/compilers.yml delete mode 100644 libcxx/utils/docker/debian9/compilers/clang.Dockerfile delete mode 100644 libcxx/utils/docker/debian9/compilers/compiler-zoo.Dockerfile delete mode 100644 libcxx/utils/docker/debian9/compilers/gcc.Dockerfile delete mode 100644 libcxx/utils/docker/debian9/docker-compose.yml delete mode 100644 libcxx/utils/docker/debian9/llvm-buildbot-worker.Dockerfile delete mode 100644 libcxx/utils/docker/debian9/llvm-builder-base.Dockerfile delete mode 100755 libcxx/utils/docker/debian9/scripts/build_gcc_version.sh delete mode 100755 libcxx/utils/docker/debian9/scripts/build_llvm_version.sh delete mode 100755 libcxx/utils/docker/debian9/scripts/buildbot/docker_start_buildbots.sh delete mode 100755 libcxx/utils/docker/debian9/scripts/install_clang_packages.sh create mode 100644 llvm/test/Transforms/InstCombine/ctpop-cttz.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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Tcwg-commits March 2020