Tcwg-commits March 2020

tcwg-commits@lists.linaro.org

4 participants
11017 discussions

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-next-allmodconfig updated (ecce469d89e -> 938de7cbb1c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-next-allmodconfig in repository toolchain/ci/gcc. from ecce469d89e Daily bump. adds 938de7cbb1c Daily bump. No new revisions were added by this update. Summary of changes: gcc/DATESTAMP | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-next-allmodconfig updated (9050435 -> 38a8fd5)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-next-allmodconfig in repository toolchain/ci/base-artifacts. discards 9050435 2: update: binutils-gcc-linux: 20424 new 38a8fd5 2: update: binutils-gcc-linux: 20424 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (9050435) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-n [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 130 +- 02-prepare_abe/console.log | 420 +- 03-build_abe-binutils/console.log | 10846 +++++------ 04-build_abe-stage1/console.log | 18066 +++++++++--------- 05-build_linux/console.log | 1068 +- 07-check_regression/console.log | 3 +- 07-check_regression/results.regressions | 5 + 08-update_baseline/console.log | 39 +- 08-update_baseline/results.regressions | 8 + console.log | 30576 +++++++++++++++--------------- jenkins/manifest.sh | 10 +- regressions.txt | 8 - 12 files changed, 30602 insertions(+), 30577 deletions(-) create mode 100644 07-check_regression/results.regressions create mode 100644 08-update_baseline/results.regressions delete mode 100644 regressions.txt -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-bootstrap_ubsan updated (7d4549b2cd2 -> 85e10e4f0fa)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-bootstrap_ubsan in repository toolchain/ci/gcc. from 7d4549b2cd2 Fix correct offset in ipa_get_jf_ancestor_result. adds 3eff57aacfe [ARM][GCC][6x]:MVE ACLE vaddq intrinsics using arithmetic p [...] adds 85a94e87901 [ARM][GCC][7x]: MVE vreinterpretq and vuninitializedq intrinsics. adds 92f80065d10 [ARM][GCC][1/8x]: MVE ACLE vidup, vddup, viwdup and vdwdup [...] adds 41e1a7ffae9 [ARM][GCC][2/8x]: MVE ACLE gather load and scatter store in [...] adds 3d42842c07f fix CTOR vectorization adds 261014a1be4 [ARM][GCC][9x]: MVE ACLE predicated intrinsics with (dont-c [...] adds 828878c35c8 c++: Include the constraint parameter mapping in diagnostic [...] adds c3562f81042 [ARM][GCC][10x]: MVE ACLE intrinsics "add with carry across [...] adds 1aa22b1916a c-family: Tighten vector handling in type_for_mode [PR94072] adds b5446d0cc09 d: Fix SEGV in hash_table<odr_name_hasher, false, xcallocat [...] adds 1dfcc3b541c [ARM][GCC][11x]: MVE ACLE vector interleaving store and dei [...] adds a23eff1bd04 c++: Add testcases from PR c++/69694 adds a89349e664f adjust SLP tree dumping adds 72b3bc895f0 Fix verifier ICE on wrong comdat local flag [PR93347] adds 68dd57808f7 rs6000: Add command line and builtin compatibility check adds cc3afc9db07 Regenerate gcc.pot. adds 29f23ed79b6 sra: Cap number of sub-access propagations with a param (PR 93435) adds 8416602026d Daily bump. adds 15711e837b2 Fix comma at end of enumerator list seen with -std=c++98. adds 497498c878d lra: Tighten check for reloading paradoxical subregs [PR94052] adds b599bf9d6d1 c++: Reject changing active member of union during initiali [...] adds 98eb7b2ed24 d: Fix ICE in add_symbol_to_partition_1, at lto/lto-partiti [...] adds 837cece888f Darwin: Address translation comments (PR93694). adds dfb25dfe3d3 Darwin: Handle NULL DECL_SIZE_TYPE in machopic_select_secti [...] adds 9fc985118d9 libstdc++: Fix path::generic_string allocator handling (PR 94242) adds a577c0c2693 libstdc++: Fix experimental::path::generic_string (PR 93245) adds 424e39081f9 d: Fix typo in ChangeLog for last change adds 4a01f7b1e73 d: Fix missing dependencies in depfile for imported files ( [...] adds 88d7d0ce8fa testsuite: Fix lambda-vis.C for targets with user label pre [...] adds 85e10e4f0fa Darwin: Fix i686 bootstrap when the assembler supports GOTO [...] No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 1550 ++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 7 + gcc/c-family/c-common.c | 11 +- gcc/cgraph.c | 64 +- gcc/cgraph.h | 17 +- gcc/config/arm/arm-builtins.c | 86 + gcc/config/arm/arm_mve.h | 8413 ++++++++-- gcc/config/arm/arm_mve_builtins.def | 61 + gcc/config/arm/iterators.md | 8 + gcc/config/arm/mve.md | 1246 +- gcc/config/arm/neon.md | 32 +- gcc/config/arm/unspecs.md | 2 + gcc/config/arm/vec-common.md | 42 +- gcc/config/darwin.c | 29 +- gcc/config/darwin.opt | 96 +- gcc/config/i386/darwin.h | 10 + gcc/config/i386/i386.h | 5 +- gcc/config/rs6000/rs6000.c | 8 + gcc/cp/ChangeLog | 28 + gcc/cp/constexpr.c | 69 +- gcc/cp/cxx-pretty-print.c | 18 +- gcc/cp/cxx-pretty-print.h | 1 + gcc/cp/error.c | 35 +- gcc/d/ChangeLog | 31 + gcc/d/d-lang.cc | 52 +- gcc/d/d-tree.h | 5 + gcc/d/decl.cc | 10 +- gcc/d/typeinfo.cc | 47 +- gcc/d/types.cc | 48 + gcc/ipa-fnsummary.c | 4 - gcc/ipa-inline-transform.c | 9 +- gcc/ipa-split.c | 2 +- gcc/lra-constraints.c | 24 +- gcc/params.opt | 4 + gcc/po/ChangeLog | 4 + gcc/po/gcc.pot | 15239 +++++++++++-------- gcc/symtab.c | 11 + gcc/testsuite/ChangeLog | 614 + gcc/testsuite/g++.dg/abi/lambda-vis.C | 12 +- gcc/testsuite/g++.dg/concepts/diagnostic6.C | 14 + gcc/testsuite/g++.dg/cpp0x/decltype74.C | 30 + gcc/testsuite/g++.dg/cpp0x/decltype75.C | 24 + gcc/testsuite/g++.dg/cpp1y/constexpr-union2.C | 9 + gcc/testsuite/g++.dg/cpp1y/constexpr-union3.C | 9 + gcc/testsuite/g++.dg/cpp1y/constexpr-union4.C | 9 + gcc/testsuite/g++.dg/cpp1y/constexpr-union5.C | 15 + gcc/testsuite/g++.dg/cpp1y/pr94066-2.C | 19 + gcc/testsuite/g++.dg/cpp1y/pr94066-3.C | 16 + gcc/testsuite/g++.dg/cpp1y/pr94066.C | 18 + gcc/testsuite/g++.dg/cpp2a/constexpr-union1.C | 18 + gcc/testsuite/g++.dg/torture/pr93347.C | 306 + gcc/testsuite/g++.target/aarch64/pr94052.C | 174 + gcc/testsuite/gcc.dg/tree-ssa/pr93435.c | 159 + gcc/testsuite/gcc.target/aarch64/pr94072.c | 9 + .../gcc.target/arm/mve/intrinsics/vabdq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabdq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vabsq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vadciq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vadciq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vadcq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vadcq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vadcq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vadcq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vaddq_x_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vaddq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vandq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vandq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vbicq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vcaddq_rot270_x_f16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_f32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_s16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_s32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_s8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_u16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_u32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot270_x_u8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_f16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_f32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_s16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_s32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_s8.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_u16.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_u32.c | 23 + .../arm/mve/intrinsics/vcaddq_rot90_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclsq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vclzq_x_u8.c | 23 + .../arm/mve/intrinsics/vcmulq_rot180_x_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot180_x_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot270_x_f16.c | 23 + .../arm/mve/intrinsics/vcmulq_rot270_x_f32.c | 23 + .../arm/mve/intrinsics/vcmulq_rot90_x_f16.c | 24 + .../arm/mve/intrinsics/vcmulq_rot90_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c | 23 + .../arm/mve/intrinsics/vcvtaq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtaq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtaq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtaq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtbq_x_f32_f16.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtmq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtnq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtpq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_f16_s16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_f16_u16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_f32_s32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_f32_u32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f16_s16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f16_u16.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f32_s32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_f32_u32.c | 24 + .../arm/mve/intrinsics/vcvtq_x_n_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_n_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_n_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_n_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_s16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_s32_f32.c | 15 + .../arm/mve/intrinsics/vcvtq_x_u16_f16.c | 15 + .../arm/mve/intrinsics/vcvtq_x_u32_f32.c | 15 + .../arm/mve/intrinsics/vcvttq_x_f32_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vddupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/vddupq_m_wb_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vddupq_x_wb_u16.c | 26 + .../arm/mve/intrinsics/vddupq_x_wb_u32.c | 26 + .../gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c | 26 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c | 15 + .../arm/mve/intrinsics/vdwdupq_m_n_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u32.c | 24 + .../arm/mve/intrinsics/vdwdupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c | 22 + .../arm/mve/intrinsics/vdwdupq_x_n_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_wb_u16.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_wb_u32.c | 24 + .../arm/mve/intrinsics/vdwdupq_x_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/veorq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c | 2 +- .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c | 2 +- .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s16.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s32.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot270_x_s8.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s16.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s32.c | 23 + .../arm/mve/intrinsics/vhcaddq_rot90_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/vidupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/vidupq_m_wb_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/vidupq_x_wb_u16.c | 26 + .../arm/mve/intrinsics/vidupq_x_wb_u32.c | 26 + .../gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c | 26 + .../arm/mve/intrinsics/viwdupq_m_n_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u32.c | 24 + .../arm/mve/intrinsics/viwdupq_m_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c | 22 + .../arm/mve/intrinsics/viwdupq_x_n_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c | 24 + .../arm/mve/intrinsics/viwdupq_x_wb_u16.c | 24 + .../arm/mve/intrinsics/viwdupq_x_wb_u32.c | 24 + .../arm/mve/intrinsics/viwdupq_x_wb_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vld1q_z_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vld1q_z_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vld2q_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vld2q_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vld4q_f16.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_f32.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_s16.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_s32.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_s8.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_u16.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_u32.c | 25 + .../gcc.target/arm/mve/intrinsics/vld4q_u8.c | 25 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c | 14 + .../arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c | 14 + .../mve/intrinsics/vldrdq_gather_base_wb_z_s64.c | 12 + .../mve/intrinsics/vldrdq_gather_base_wb_z_u64.c | 12 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c | 14 + .../arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c | 14 + .../mve/intrinsics/vldrwq_gather_base_wb_z_f32.c | 14 + .../mve/intrinsics/vldrwq_gather_base_wb_z_s32.c | 14 + .../mve/intrinsics/vldrwq_gather_base_wb_z_u32.c | 14 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vminq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_s16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_s32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_s8.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u16.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u32.c | 23 + .../arm/mve/intrinsics/vmullbq_int_x_u8.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_x_p16.c | 23 + .../arm/mve/intrinsics/vmullbq_poly_x_p8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_s8.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u16.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u32.c | 23 + .../arm/mve/intrinsics/vmulltq_int_x_u8.c | 23 + .../arm/mve/intrinsics/vmulltq_poly_x_p16.c | 23 + .../arm/mve/intrinsics/vmulltq_poly_x_p8.c | 23 + .../gcc.target/arm/mve/intrinsics/vmulq_x_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmulq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vnegq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vnegq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vornq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vorrq_x_u8.c | 23 + .../arm/mve/intrinsics/vreinterpretq_f16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_f32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_s64.c | 46 + .../arm/mve/intrinsics/vreinterpretq_s8.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u16.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u32.c | 45 + .../arm/mve/intrinsics/vreinterpretq_u64.c | 46 + .../arm/mve/intrinsics/vreinterpretq_u8.c | 45 + .../gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c | 23 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c | 24 + .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 24 + .../gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 22 + .../arm/mve/intrinsics/vshllbq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c | 16 + .../arm/mve/intrinsics/vshllbq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c | 16 + .../arm/mve/intrinsics/vshlltq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c | 16 + .../arm/mve/intrinsics/vshlltq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshlq_x_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vst1q_p_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vst1q_p_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vst2q_f16.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_f32.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_s16.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_s32.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_s8.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_u16.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_u32.c | 23 + .../gcc.target/arm/mve/intrinsics/vst2q_u8.c | 23 + .../mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_s64.c | 22 + .../mve/intrinsics/vstrdq_scatter_base_wb_u64.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_f32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_s32.c | 22 + .../mve/intrinsics/vstrwq_scatter_base_wb_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vsubq_x_f16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_f32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_s8.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u16.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u32.c | 16 + .../gcc.target/arm/mve/intrinsics/vsubq_x_u8.c | 16 + .../arm/mve/intrinsics/vuninitializedq_float.c | 17 + .../arm/mve/intrinsics/vuninitializedq_float1.c | 17 + .../arm/mve/intrinsics/vuninitializedq_int.c | 29 + .../arm/mve/intrinsics/vuninitializedq_int1.c | 29 + gcc/testsuite/gdc.dg/fileimports/pr93038.txt | 1 + gcc/testsuite/gdc.dg/pr93038.d | 8 + gcc/tree-sra.c | 37 +- gcc/tree-vect-slp.c | 4 +- include/ChangeLog | 6 + include/lto-symtab.h | 2 +- include/plugin-api.h | 2 +- libstdc++-v3/ChangeLog | 17 + libstdc++-v3/include/bits/fs_path.h | 11 +- libstdc++-v3/include/experimental/bits/fs_path.h | 40 +- .../filesystem/path/generic/94242.cc} | 41 +- .../filesystem/path/generic/generic_string.cc | 32 + .../filesystem/path/generic/generic_string.cc | 46 +- 593 files changed, 33345 insertions(+), 7315 deletions(-) create mode 100644 gcc/testsuite/g++.dg/concepts/diagnostic6.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/decltype74.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/decltype75.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-union2.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-union3.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-union4.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/constexpr-union5.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/pr94066-2.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/pr94066-3.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/pr94066.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/constexpr-union1.C create mode 100644 gcc/testsuite/g++.dg/torture/pr93347.C create mode 100644 gcc/testsuite/g++.target/aarch64/pr94052.C create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr93435.c create mode 100644 gcc/testsuite/gcc.target/aarch64/pr94072.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabdq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vabsq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadciq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vadcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vandq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbicq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot270_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcaddq_rot90_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclsq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vclzq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot180_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot270_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_rot90_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtaq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtbq_x_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtmq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtnq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtpq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f16_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_f32_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_n_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_s32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u16_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvtq_x_u32_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vcvttq_x_f32_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vdwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/veorq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot270_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhcaddq_rot90_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_m_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/viwdupq_x_wb_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld1q_z_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld2q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vld4q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrdq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vldrwq_gather_base_ [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmullbq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_int_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulltq_poly_x_p8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmulq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vnegq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vornq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vorrq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vreinterpretq_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbciq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsbcq_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshlq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst1q_p_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vst2q_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrdq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vstrwq_scatter_base [...] create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsubq_x_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_float1.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vuninitializedq_int1.c create mode 100644 gcc/testsuite/gdc.dg/fileimports/pr93038.txt create mode 100644 gcc/testsuite/gdc.dg/pr93038.d copy libstdc++-v3/testsuite/{experimental/filesystem/path/generic/generic_string.c [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-bootstrap_ubsan updated (2849b50 -> 38aa038)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-bootstrap_ubsan in repository toolchain/ci/base-artifacts. discards 2849b50 0: update: gcc-7d4549b2cd209eb621453ce13be7ffd84ffa720a: 1 new 38aa038 0: update: gcc-85e10e4f0fa5c6b1a9f3caf7d9cab28ef8490a83: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (2849b50) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-master-aarch64-b [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 166 +- 02-prepare_abe/console.log | 436 +- 03-build_abe-bootstrap_ubsan/console.log | 77591 ++++++++++++++-------------- 05-check_regression/console.log | 20 +- 06-update_baseline/console.log | 2 +- console.log | 78215 ++++++++++++++--------------- jenkins/manifest.sh | 8 +- regressions.txt | 20 +- 8 files changed, 77420 insertions(+), 79038 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig updated (684ee2057f5 -> 2655d1b4578)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig in repository toolchain/ci/llvm-project. from 684ee2057f5 [clang/docs] Fix various sphinx warnings/errors in docs. adds 7a3d994880c [X86][AVX] Add HADDPD test case for PR44694 adds 25eb9056d7f [X86] getTargetShuffleAndZeroables - add insert_subvector(u [...] adds 2d712fb7558 [InstCombine] Add ctpop -> cttz combine tests (PR43513) adds 920d90f9663 The generated code does not need to check for a null Decl; NFC. adds 90c74435d36 [libc++] tolerate missing diagnostic with modules enabled adds 34fd007aaf8 Revert "[ADT] Implement the Waymarking as an independent utility" adds d779ee152ce [gn build] Port 34fd007aaf8 adds d1739f1e2f2 [X86] Add test for v4i8 loop sad pattern. adds d477df59cf4 [MLIR][NFC] fix memref type doc comment on dynamic shape adds a1e02753c0e [X86] Add nonloop v64i8 test to sad.ll. adds 38a8760b99b [ORC] Move ostream operators for debugging output out of Core.h. adds b5eafda8d3e Revert "EHScopeStack::Cleanup has virtual functions so the [...] adds b4456436321 [X86] Delete unneeded X86ELFTargetObjectFile::Initialize. NFC adds 140d6245af2 Delete TargetLoweringObjectFile::Ctx adds 71f8b78d897 [AsmPrinter] Simplify AsmPrinter::emitXXStructorList after D61547 adds dbf78ae1287 [LVI] Use SmallDenseMap for getValueFromCondition(); NFC adds e9482ed1942 [mlir] Move several static cl::opts to be pass options instead. adds e74961eee26 [mlir][NFC] Remove Analysis/Passes.h adds e8f5c072f6d [mlir] Move the testing pass for GpuKernelToCubin to the te [...] adds c1bc56bf4f2 [NFC] [PowerPC] Update FMA association test adds a63eaa5449f [SLP] Avoid repeated visitation in getVectorElementSize(); NFC adds d077d678d34 [ValueTracking] Avoid blind cast from Operator to Instruction adds 0105e9cd92b [X86][SSE] Add some additional irregular AVG tests adds 996dc13dc4c [NFC] [PowerPC] Remove unsafe-fp-math in FMA test adds 763871053cc [DAGCombiner] Require nsz for aggressive fma fold adds 830cfda19f7 Utils: Mostly convert memcpy expansion to use Align adds dc81923659c [InstCombine] Remove ExpensiveCombines option adds b76bbcc60db Verifier: Check bswap is supported size new 2655d1b4578 Remove a dead function. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang/lib/CodeGen/EHScopeStack.h | 2 +- clang/utils/TableGen/ClangAttrEmitter.cpp | 4 +- .../array/array.creation/to_array.fail.cpp | 2 +- llvm/include/llvm/ADT/Waymarking.h | 325 ----------- llvm/include/llvm/ExecutionEngine/Orc/Core.h | 75 +-- llvm/include/llvm/ExecutionEngine/Orc/DebugUtils.h | 69 +++ .../include/llvm/ExecutionEngine/Orc/Speculation.h | 1 + llvm/include/llvm/MC/MCObjectFileInfo.h | 1 + .../include/llvm/Target/TargetLoweringObjectFile.h | 3 - llvm/include/llvm/TextAPI/MachO/InterfaceFile.h | 5 - .../llvm/Transforms/IPO/PassManagerBuilder.h | 1 - .../llvm/Transforms/InstCombine/InstCombine.h | 16 +- .../llvm/Transforms/Utils/LowerMemIntrinsics.h | 6 +- llvm/lib/Analysis/LazyValueInfo.cpp | 8 +- llvm/lib/Analysis/ValueTracking.cpp | 19 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 15 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 3 +- llvm/lib/ExecutionEngine/Orc/Core.cpp | 284 +--------- llvm/lib/ExecutionEngine/Orc/DebugUtils.cpp | 276 ++++++++++ llvm/lib/ExecutionEngine/Orc/Layer.cpp | 1 + llvm/lib/ExecutionEngine/Orc/MachOPlatform.cpp | 1 + llvm/lib/IR/Verifier.cpp | 6 + llvm/lib/Target/NVPTX/NVPTXLowerAggrCopies.cpp | 4 +- llvm/lib/Target/TargetLoweringObjectFile.cpp | 7 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 18 + llvm/lib/Target/X86/X86TargetObjectFile.cpp | 5 - llvm/lib/Target/X86/X86TargetObjectFile.h | 1 - llvm/lib/Transforms/IPO/PassManagerBuilder.cpp | 36 +- .../Transforms/InstCombine/InstCombineInternal.h | 7 +- .../InstCombine/InstructionCombining.cpp | 45 +- llvm/lib/Transforms/Utils/LowerMemIntrinsics.cpp | 85 +-- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 7 +- .../known-bits-from-operator-constexpr.ll | 15 + llvm/test/CodeGen/AMDGPU/fma-combine.ll | 9 +- llvm/test/CodeGen/AMDGPU/mad-combine.ll | 9 +- llvm/test/CodeGen/PowerPC/fma-assoc.ll | 594 +++++++++++++++------ llvm/test/CodeGen/X86/avg.ll | 391 ++++++++++++++ llvm/test/CodeGen/X86/haddsub-undef.ll | 28 + llvm/test/CodeGen/X86/sad.ll | 509 ++++++++++++++++++ llvm/test/CodeGen/X86/var-permute-256.ll | 50 +- llvm/test/CodeGen/X86/vector-reduce-mul.ll | 4 +- .../ExecutionEngine/OrcMCJIT/test-global-ctors.ll | 4 +- llvm/test/Transforms/InstCombine/all-bits-shift.ll | 3 +- llvm/test/Transforms/InstCombine/assume.ll | 3 +- llvm/test/Transforms/InstCombine/call-returned.ll | 3 +- llvm/test/Transforms/InstCombine/ctpop-cttz.ll | 69 +++ .../Transforms/InstCombine/expensive-combines.ll | 28 - llvm/test/Transforms/InstCombine/known-bits.ll | 3 +- .../Transforms/InstCombine/known-signbit-shift.ll | 3 +- .../InstCombine/out-of-bounds-indexes.ll | 3 +- llvm/test/Transforms/InstCombine/phi-shifts.ll | 3 +- llvm/test/Transforms/InstCombine/pr44541.ll | 2 +- llvm/test/Verifier/bswap.ll | 53 ++ llvm/unittests/ADT/CMakeLists.txt | 1 - llvm/unittests/ADT/WaymarkingTest.cpp | 150 ------ .../utils/gn/secondary/llvm/unittests/ADT/BUILD.gn | 1 - mlir/include/mlir/Analysis/Passes.h | 33 -- mlir/include/mlir/IR/StandardTypes.h | 4 +- mlir/include/mlir/InitAllPasses.h | 5 - .../GPUToCUDA/ConvertKernelFuncToCubin.cpp | 17 +- mlir/lib/Conversion/LoopsToGPU/LoopsToGPUPass.cpp | 79 ++- mlir/lib/Dialect/Linalg/Transforms/Fusion.cpp | 8 - mlir/lib/Dialect/Linalg/Transforms/Promotion.cpp | 20 +- mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp | 27 +- mlir/lib/Support/MlirOptMain.cpp | 1 - mlir/lib/Transforms/Vectorize.cpp | 62 +-- mlir/test/Conversion/LoopsToGPU/imperfect_2D.mlir | 2 +- mlir/test/Conversion/LoopsToGPU/imperfect_3D.mlir | 4 +- mlir/test/Conversion/LoopsToGPU/imperfect_4D.mlir | 4 +- .../Conversion/LoopsToGPU/imperfect_linalg.mlir | 2 +- .../LoopsToGPU/no_blocks_no_threads.mlir | 4 +- .../LoopsToGPU/perfect_1D_setlaunch.mlir | 4 +- mlir/test/Conversion/LoopsToGPU/step_one.mlir | 4 +- mlir/test/Conversion/LoopsToGPU/step_positive.mlir | 2 +- mlir/test/Dialect/Linalg/promote.mlir | 2 +- mlir/test/Dialect/Linalg/tile.mlir | 8 +- mlir/test/Dialect/Linalg/tile_conv.mlir | 2 +- mlir/test/Dialect/Linalg/tile_indexed_generic.mlir | 6 +- mlir/test/Dialect/Linalg/tile_parallel.mlir | 8 +- mlir/test/Transforms/Vectorize/vectorize_1d.mlir | 2 +- mlir/test/Transforms/Vectorize/vectorize_2d.mlir | 4 +- mlir/test/Transforms/Vectorize/vectorize_3d.mlir | 2 +- .../Vectorize/vectorize_outer_loop_2d.mlir | 2 +- .../vectorize_outer_loop_transpose_2d.mlir | 2 +- .../Vectorize/vectorize_transpose_2d.mlir | 2 +- .../test/lib/Dialect/Affine/TestAffineDataCopy.cpp | 1 - mlir/test/lib/Transforms/CMakeLists.txt | 2 + .../lib/Transforms/TestConvertGPUKernelToCubin.cpp | 34 ++ mlir/test/lib/Transforms/TestLoopFusion.cpp | 1 - mlir/test/lib/Transforms/TestMemRefBoundCheck.cpp | 5 - .../lib/Transforms/TestMemRefDependenceCheck.cpp | 6 - .../lib/Transforms/TestParallelismDetection.cpp | 1 - .../mlir-cpu-runner/linalg_integration_test.mlir | 4 +- mlir/tools/mlir-opt/mlir-opt.cpp | 13 +- mlir/tools/mlir-vulkan-runner/VulkanRuntime.h | 1 - 95 files changed, 2195 insertions(+), 1471 deletions(-) delete mode 100644 llvm/include/llvm/ADT/Waymarking.h create mode 100644 llvm/test/Analysis/ValueTracking/known-bits-from-operator-constexpr.ll create mode 100644 llvm/test/Transforms/InstCombine/ctpop-cttz.ll delete mode 100644 llvm/test/Transforms/InstCombine/expensive-combines.ll create mode 100644 llvm/test/Verifier/bswap.ll delete mode 100644 llvm/unittests/ADT/WaymarkingTest.cpp delete mode 100644 mlir/include/mlir/Analysis/Passes.h create mode 100644 mlir/test/lib/Transforms/TestConvertGPUKernelToCubin.cpp -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig updated (c8f5b20 -> a7bc310)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig in repository toolchain/ci/base-artifacts. discards c8f5b20 0: update: llvm-linux: boot new a7bc310 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (c8f5b20) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 128 +- 02-build_llvm/console.log | 12717 ++++++++++++++------------- 03-build_linux/console.log | 734 +- 04-boot_linux/console.log | 480 +- 05-check_regression/console.log | 3 +- 05-check_regression/results.regressions | 2 + 06-update_baseline/console.log | 3 +- 06-update_baseline/results.regressions | 2 + console.log | 14062 +++++++++++++++--------------- jenkins/manifest.sh | 10 +- regressions.txt | 2 - 11 files changed, 14071 insertions(+), 14072 deletions(-) create mode 100644 05-check_regression/results.regressions create mode 100644 06-update_baseline/results.regressions delete mode 100644 regressions.txt -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allmodconfig updated (c63c50fc2ec9 -> b74b991fb8b9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allmodconfig in repository toolchain/ci/linux. from c63c50fc2ec9 Merge tag 'powerpc-5.6-5' of git://git.kernel.org/pub/scm/ [...] adds 081c54323b27 tools/power turbostat: Support Cometlake adds d8d005ba6afa tools/power turbostat: Fix gcc build warnings adds 4bf7132a0ace tools/power turbostat: Support Tiger Lake adds 23274faf9650 tools/power turbostat: Support Ice Lake server adds d7814c3098dd tools/power turbostat: Support Jasper Lake adds f6708400707f tools/power turbostat: Support Elkhart Lake adds 1f81c5efc020 tools/power turbostat: Fix missing SYS_LPI counter on some [...] adds fcaa681c03ea tools/power turbostat: Fix 32-bit capabilities warning adds abdcbdb26526 tools/power turbostat: Print cpuidle information adds b95fffb9b4af tools/power turbostat: update version adds 6c1bae744d5a Merge branch 'turbostat' of git://git.kernel.org/pub/scm/l [...] adds f1d96a8fcbbb io_uring: NULL-deref for IOSQE_{ASYNC,DRAIN} adds 4022e7af86be io_uring: make sure openat/openat2 honor rlimit nofile adds 09952e3e7826 io_uring: make sure accept honor rlimit nofile adds 1ab7ea1f83d1 Merge tag 'io_uring-5.6-20200320' of git://git.kernel.dk/l [...] adds 9134ae2a2546 nvme-rdma: Avoid double freeing of async event data adds 98fd5c723730 nvmet-tcp: set MSG_MORE only if we actually have more to send adds 83166ac82b53 Merge branch 'nvme-5.6-rc6' of git://git.infradead.org/nvm [...] adds b74b991fb8b9 Merge tag 'block-5.6-20200320' of git://git.kernel.dk/linux-block No new revisions were added by this update. Summary of changes: drivers/nvme/host/rdma.c | 8 +- drivers/nvme/target/tcp.c | 12 ++- fs/file.c | 7 +- fs/io_uring.c | 18 ++++- include/linux/file.h | 1 + include/linux/socket.h | 3 +- net/socket.c | 8 +- tools/power/x86/turbostat/Makefile | 2 +- tools/power/x86/turbostat/turbostat.c | 142 +++++++++++++++++++++++++++------- 9 files changed, 158 insertions(+), 43 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allmodconfig updated (defb567 -> d48b15f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allmodconfig in repository toolchain/ci/base-artifacts. discards defb567 0: update: llvm-linux: all new d48b15f 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (defb567) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-arm- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 182 +- 02-build_llvm/console.log | 12562 +++++++++++++-------------- 03-build_linux/console.log | 764 +- 04-boot_linux/console.log | 2 +- 05-check_regression/console.log | 15 +- 05-check_regression/results.regressions | 2 + 06-update_baseline/console.log | 13 +- 06-update_baseline/results.regressions | 2 + console.log | 13538 +++++++++++++++--------------- jenkins/manifest.sh | 10 +- regressions.txt | 2 - 11 files changed, 13549 insertions(+), 13543 deletions(-) create mode 100644 05-check_regression/results.regressions create mode 100644 06-update_baseline/results.regressions delete mode 100644 regressions.txt -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-lts-allyesconfig updated (de9c501 -> 64f6eff)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-lts-allyesconfig in repository toolchain/ci/base-artifacts. discards de9c501 0: update: llvm-linux: 16 new 64f6eff 0: update: llvm-linux: 16 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (de9c501) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-arm- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 14 +- 02-build_llvm/console.log | 12620 ++++++++++++++-------------- 03-build_linux/console.log | 812 +- 05-check_regression/console.log | 3 +- 05-check_regression/results.regressions | 11 + 06-update_baseline/console.log | 39 - 06-update_baseline/results.regressions | 11 + console.log | 13449 +++++++++++++++--------------- jenkins/manifest.sh | 6 +- regressions.txt | 11 - 10 files changed, 13473 insertions(+), 13503 deletions(-) create mode 100644 05-check_regression/results.regressions create mode 100644 06-update_baseline/results.regressions delete mode 100644 regressions.txt -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allnoconfig updated (c63c50fc2ec9 -> b74b991fb8b9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allnoconfig in repository toolchain/ci/linux. from c63c50fc2ec9 Merge tag 'powerpc-5.6-5' of git://git.kernel.org/pub/scm/ [...] adds 081c54323b27 tools/power turbostat: Support Cometlake adds d8d005ba6afa tools/power turbostat: Fix gcc build warnings adds 4bf7132a0ace tools/power turbostat: Support Tiger Lake adds 23274faf9650 tools/power turbostat: Support Ice Lake server adds d7814c3098dd tools/power turbostat: Support Jasper Lake adds f6708400707f tools/power turbostat: Support Elkhart Lake adds 1f81c5efc020 tools/power turbostat: Fix missing SYS_LPI counter on some [...] adds fcaa681c03ea tools/power turbostat: Fix 32-bit capabilities warning adds abdcbdb26526 tools/power turbostat: Print cpuidle information adds b95fffb9b4af tools/power turbostat: update version adds 6c1bae744d5a Merge branch 'turbostat' of git://git.kernel.org/pub/scm/l [...] adds f1d96a8fcbbb io_uring: NULL-deref for IOSQE_{ASYNC,DRAIN} adds 4022e7af86be io_uring: make sure openat/openat2 honor rlimit nofile adds 09952e3e7826 io_uring: make sure accept honor rlimit nofile adds 1ab7ea1f83d1 Merge tag 'io_uring-5.6-20200320' of git://git.kernel.dk/l [...] adds 9134ae2a2546 nvme-rdma: Avoid double freeing of async event data adds 98fd5c723730 nvmet-tcp: set MSG_MORE only if we actually have more to send adds 83166ac82b53 Merge branch 'nvme-5.6-rc6' of git://git.infradead.org/nvm [...] adds b74b991fb8b9 Merge tag 'block-5.6-20200320' of git://git.kernel.dk/linux-block No new revisions were added by this update. Summary of changes: drivers/nvme/host/rdma.c | 8 +- drivers/nvme/target/tcp.c | 12 ++- fs/file.c | 7 +- fs/io_uring.c | 18 ++++- include/linux/file.h | 1 + include/linux/socket.h | 3 +- net/socket.c | 8 +- tools/power/x86/turbostat/Makefile | 2 +- tools/power/x86/turbostat/turbostat.c | 142 +++++++++++++++++++++++++++------- 9 files changed, 158 insertions(+), 43 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 3 months

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

Tcwg-commits March 2020