Tcwg-commits March 2020

tcwg-commits@lists.linaro.org

4 participants
11017 discussions

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-bootstrap_O3 updated (02023c5 -> 8bd2b42)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-bootstrap_O3 in repository toolchain/ci/base-artifacts. discards 02023c5 0: update: gcc-b599bf9d6d1e180d350b71e51e08a66a1bb1546a: 1 new 8bd2b42 0: update: gcc-4dcc4502f316a7320fe72b62c60af12c77e1c96c: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (02023c5) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-master-aarch64-b [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 128 +- 02-prepare_abe/console.log | 432 +- 03-build_abe-bootstrap_O3/console.log | 71288 +++++++++++++++-------------- 05-check_regression/console.log | 3 +- 05-check_regression/results.regressions | 8 + 06-update_baseline/console.log | 3 +- 06-update_baseline/results.regressions | 9 + console.log | 71854 +++++++++++++++--------------- jenkins/manifest.sh | 10 +- regressions.txt | 9 - 10 files changed, 71854 insertions(+), 71890 deletions(-) create mode 100644 05-check_regression/results.regressions create mode 100644 06-update_baseline/results.regressions delete mode 100644 regressions.txt -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[gcc] branch master updated (ca6c722561c -> 1f6c1c82eb5)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from ca6c722561c c++: Handle COMPOUND_EXPRs in get_narrower and warnings_for [...] new 1f6c1c82eb5 c++: Avoid a suspicious -Wnoexcept warning [PR93805] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/cp/ChangeLog | 6 ++++++ gcc/cp/except.c | 5 ++++- gcc/cp/method.c | 2 +- gcc/testsuite/ChangeLog | 5 +++++ gcc/testsuite/g++.dg/warn/Wnoexcept2.C | 15 +++++++++++++++ 5 files changed, 31 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/g++.dg/warn/Wnoexcept2.C -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allyesconfig updated (78957bab551 -> 2ad5fc1d915)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allyesconfig in repository toolchain/ci/llvm-project. from 78957bab551 [NFC] Refactor handling of Xarch option adds 0e1e9b9a811 [libc][NFC] Fix typo in milliseconds adds bb621cac3d4 [mlir] Change include image to be toplevel adds 0f15ace018b [mips] Rename target feature Mips3D => HasMips3D. NFC adds ecc92fd018c [mips] Add HasMips3D to the list of features unsupported by [...] adds 862f120fdb0 [mips] Remove instructions related to "wired paired single" [...] adds dca9e40c0cf [mips] Implement sle/sleu pseudo instructions adds 9bbddfbeaab [mips] Implement sne pseudo instruction adds 2dc4eb08cd9 [mips] Implement .cpadd directive adds 7cfd5de61b8 clang/release notes: s/Subversion/git/ adds f4c67dfa925 [X86] More accurately model the cost of horizontal reductions. adds ea4ec172080 update of the llvm doc: we moved to git adds 006244152d6 [SCCP] Add a few more tests for conditional propagation,XOR. adds 72fd1033ea5 Doc: Links should use https adds 986051749cb doc: use the right url to bugzilla adds e2cb1213745 [X86] Remove maximum vector length limit from combineBasicS [...] adds 5d4c1c00e6b Roll an expression into an assert to remove the need for a [...] adds 0d0b90105f9 Revert "[FIX] Do not copy an llvm::function_ref if it has t [...] adds 56e1c20bfdf [MLIR][NFC] rename ConvertStandardToLLVM, ConvertLoopToStan [...] adds b8737614964 [MLIR][NFC] Move some of the affine transforms / tests to d [...] adds 196b48a2244 [NFC] [PowerPC] Prepare test for FMA negate check adds 5792c2236d5 Add test cases that are addressed by D76010 adds 2ec59a0a40f Buildbot debugging of 0d0b90105f92f6cd9cc7004d565834f442918 [...] adds a1762f9ceb9 [libc] Don't configure test and fuzzer when -DLLVM_INCLUDE_ [...] adds 0cc124c186a [llvm-objdump][test] Improve PowerPC branch offset tests adds ccf49b9ef01 [GlobalISel] support widen unmerge if WideTy > SrcTy adds 8e45eaf1da5 [NFC][DAGCombine] Refactor post-inc logic adds 62fdb1f534b [DAGCombine] Skip PostInc combine with later users adds 7cdbf1ed4b9 Make use of APInt::countLeadingOnes. NFC. adds df5fa487397 [clang-tidy][NFC] Add missing check group docs and order entries adds 6a6a83c6e9b MergeFunctions.rst - multiply vs shift typo (PR44717) adds ea64ee0edb2 [Alignment][NFC] Deprecate ensureMaxAlignment adds b43ae21e608 Fix all-reduce int tests by host-registering memrefs. adds 6081ccf4a3b Apply function attributes through array declarators adds 72d1419bfba [InstCombine] Add CTPOP -> CTTZ simplifications (PR43513) adds b259ce998f5 [llvm-readobj] Derive dynamic symtab size from DT_HASH adds b8a2cf6b5b9 [SCCP] Extend test coverage in conditions-ranges.ll to fals [...] adds 16d2065cfc8 [InstCombine] Add ub-safe negation patterns (PR27817) adds 3ba550a05af [Alignment][NFC] Use TFL::getStackAlign() adds 32851f8d635 [Alignment][NFC] Deprecate VectorUtils::getAlignment adds 9adc7fc3cdf [SystemZ] Perform instruction shortening for fused fp ops. adds fa0320dd8d5 Add ParsedAttrInfo::handleDeclAttribute adds 5eeea337bec [VectorCombine] add more tests for extract-extract patterns; NFC adds 78e2a3c6784 [clang-format] Reflow long C# generic type constraints correctly adds 7693a9b9314 [clang-tidy] Fix RenamerClangTidy handling qualified TypeLocs adds 0eeee83d751 [VectorUtils] move x86's scaleShuffleMask to generic VectorUtils adds 33942d18b11 [SCCP] Precommit additional range propagation test. adds 24698e526f6 Implement wave32 DWARF register mapping adds 6a4905ae2d6 [lldb] Mark expressions that couldn't be parsed or executed [...] adds 60bad941a1c [Analyzer] Iterator Modeling - Model `std::advance()`, `std [...] adds 5e1a026c2d8 [clang-format] Do not indent C# array initialisers as conti [...] adds fdcb2710553 [InstCombine] Limit CTPOP -> CTTZ simplifications to one use adds f383fb40b17 Remove legacy CMake targets for libcxx and libcxxabi adds 9228a9efc6c [lldb/Target] Initialize new targets environment variables [...] adds cd7b45057ca [lldb/API] Make Launch(Simple) use args and env from target [...] adds b4a6e63ea12 [lldb/Target] Rework the way the inferior environment is created adds 04d48111bf9 Revert "Remove legacy CMake targets for libcxx and libcxxabi" adds db3f3f0240b AMDGPU/GlobalISel: Add some oversized G_IMPLICIT_DEF tests adds 0444d16a16c [GlobalISel] Add generic opcodes for saturating add/subtract adds a711a3a4603 [Syntax] Build mapping from AST to syntax tree nodes adds f3bf4b05c2a [Attributor][NFC] clang-format Attributor.{h,cpp} adds 0995001ce57 [Attributor][NFC] Predetermine the module before verification adds 54ec9b54f6b [Attributor] Unify handling of must-tail calls adds 68fed270674 [Attributor] Handle calls in AAValueConstantRange properly adds c57689bef26 [Attributor][NFC] Copy llvm::function_ref, don't use references adds ebf83c36e29 [Analysis] simplify code for scaleShuffleMask adds 5ff5ddd0adc [Win64] Insert int3 into trailing empty BBs adds 596da62d21e Add support for custom op parser/printer hooks to know abou [...] adds 278c00c4ff8 [libc++] [NFC] Test that correct value category is used in [...] adds b670ab7b6b3 recommit 1b978ddba05c [CUDA][HIP][OpenMP] Emit deferred dia [...] adds 57b8a407493 [analyzer][NFC] Tie CheckerRegistry to CheckerManager, allo [...] adds 0ca19efe7b5 Add AMDGPU MC unittests only when AMDGPU target is being built adds 7e10581e8c1 [lldb/testsuite] Skip part of TestSettings.py on windows adds 3c84aca9b35 [libc++] Bump Clang support for Clang 4 adds e10af89d991 [ARM] Extra VMOVN and VMULL tests. NFC adds c1f8595fe5b [Support] Silence warning in Path unittests when compiling [...] adds ccc0d351817 [Analyzer] IteratorRangeChecker verify `std::advance()`, `s [...] adds 0a076f2660b [ELF][test] Clean text-section-prefix.s adds ff2f5097ed4 [Attributor] Fold single-use variable into assert adds 3f51c5d9caa [OpenMPOpt][FIX] Resolve OpenMP runtime call type mismatches adds 9d38f98dc30 [OpenMPOpt] Validate declaration types against the expected types adds ae37e2285d2 [lldb/Reproducers] Mark reproducer test directory as unsupp [...] adds 552bd477f8e [gn build] Port 24698e526f619271705fe72bcaa928be9bc82484 adds ae044467ede [openmp][runtime] Fixed hang for explicit task inside a taskloop. adds 63828a35da6 [OPENMP50]Bassic support for exclusive clause. adds 04336ada175 [clang-format] No space inserted between commas in C# adds ff042de67d5 [gn build] Port 24698e526f619271705fe72bcaa928be9bc82484. F [...] adds 9607a119bd5 [gn build] Port 57b8a407493 adds 9e33c096476 [ELF] Keep orphan section names (.rodata.foo .text.foo) unc [...] adds a1fe6beb1ec [InstCombine] remove one-use check for ctpop -> cttz adds 42d8f48ccfc Fix a warning building on my machine, NFC. warning: unused [...] adds 1b9cd51d55b [CMake] Fix AMDGPUTests -DBUILD_SHARED_LIBS=on builds and t [...] new a567d6809e1 [DataFormatters] Add formatter for libc++ std::unique_ptr new 04f2b717d23 [mlir] Fix unsafe create operation in GreedyPatternRewriter new 328b72dd820 [Support] Fix clang warning in widenPath NFC new aa63eb6a461 GlobalISel: Add computeKnownBitsForTargetInstr new 58f843a5b3d GlobalISel: Prepare to allow other target unit tests new 2ad5fc1d915 AMDGPU/GlobalISel: Implement computeNumSignBitsForTargetInstr The 6 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../clang-tidy/ClangTidyForceLinker.h | 66 +- .../clang-tidy/utils/RenamerClangTidyCheck.cpp | 9 +- clang-tools-extra/docs/clang-rename.rst | 2 +- clang-tools-extra/docs/clang-tidy/index.rst | 4 +- .../bugprone-reserved-identifier-invert.cpp | 2 +- .../checkers/readability-identifier-naming.cpp | 13 + clang/docs/ClangPlugins.rst | 47 ++ clang/docs/InternalsManual.rst | 14 +- clang/docs/LibASTImporter.rst | 2 +- clang/docs/ReleaseNotes.rst | 2 +- clang/docs/analyzer/checkers.rst | 4 +- clang/include/clang/AST/OpenMPClause.h | 80 ++- clang/include/clang/AST/RecursiveASTVisitor.h | 7 + clang/include/clang/Basic/Attr.td | 56 ++ clang/include/clang/Basic/OpenMPKinds.def | 2 + clang/include/clang/Sema/ExternalSemaSource.h | 9 + .../clang/Sema/MultiplexExternalSemaSource.h | 9 + clang/include/clang/Sema/ParsedAttr.h | 14 +- clang/include/clang/Sema/Sema.h | 57 +- clang/include/clang/Serialization/ASTBitCodes.h | 5 +- clang/include/clang/Serialization/ASTReader.h | 9 + .../clang/StaticAnalyzer/Core/CheckerManager.h | 42 +- .../StaticAnalyzer/Frontend/AnalysisConsumer.h | 2 +- .../StaticAnalyzer/Frontend/AnalyzerHelpFlags.h | 30 + .../StaticAnalyzer/Frontend/CheckerRegistration.h | 38 -- .../StaticAnalyzer/Frontend/CheckerRegistry.h | 38 +- .../StaticAnalyzer/Frontend/FrontendActions.h | 17 +- clang/include/clang/Tooling/Syntax/Tree.h | 7 +- clang/lib/AST/OpenMPClause.cpp | 28 + clang/lib/AST/StmtProfile.cpp | 3 + clang/lib/Basic/OpenMPKinds.cpp | 2 + clang/lib/CodeGen/CGStmtOpenMP.cpp | 1 + clang/lib/Format/ContinuationIndenter.cpp | 19 +- clang/lib/Format/ContinuationIndenter.h | 7 +- clang/lib/Format/TokenAnnotator.cpp | 7 + clang/lib/Format/UnwrappedLineParser.cpp | 7 +- .../lib/FrontendTool/ExecuteCompilerInvocation.cpp | 20 +- clang/lib/Parse/ParseOpenMP.cpp | 8 +- clang/lib/Sema/MultiplexExternalSemaSource.cpp | 6 + clang/lib/Sema/ParsedAttr.cpp | 3 +- clang/lib/Sema/Sema.cpp | 177 ++--- clang/lib/Sema/SemaCUDA.cpp | 19 - clang/lib/Sema/SemaDecl.cpp | 27 +- clang/lib/Sema/SemaDeclAttr.cpp | 168 +---- clang/lib/Sema/SemaExpr.cpp | 7 +- clang/lib/Sema/SemaOpenMP.cpp | 195 ++---- clang/lib/Sema/SemaType.cpp | 26 + clang/lib/Sema/TreeTransform.h | 27 + clang/lib/Sema/UsedDeclVisitor.h | 12 + clang/lib/Serialization/ASTReader.cpp | 31 + clang/lib/Serialization/ASTWriter.cpp | 18 + .../StaticAnalyzer/Checkers/IteratorModeling.cpp | 301 ++++++--- .../Checkers/IteratorRangeChecker.cpp | 70 +- clang/lib/StaticAnalyzer/Core/CheckerManager.cpp | 7 +- .../StaticAnalyzer/Frontend/AnalysisConsumer.cpp | 5 +- ...eckerRegistration.cpp => AnalyzerHelpFlags.cpp} | 60 +- clang/lib/StaticAnalyzer/Frontend/CMakeLists.txt | 2 +- .../StaticAnalyzer/Frontend/CheckerRegistry.cpp | 101 ++- clang/lib/Tooling/Syntax/BuildTree.cpp | 289 +++++---- clang/lib/Tooling/Syntax/Mutations.cpp | 2 +- clang/lib/Tooling/Syntax/Tree.cpp | 23 +- .../Analysis/Inputs/system-header-simulator-cxx.h | 67 +- clang/test/Analysis/iterator-modelling.cpp | 68 ++ clang/test/Analysis/iterator-range.cpp | 417 ++++++++++++ clang/test/CodeGen/attr-noreturn.c | 10 + clang/test/OpenMP/declare_target_messages.cpp | 12 +- .../OpenMP/nvptx_target_exceptions_messages.cpp | 4 +- clang/test/OpenMP/scan_ast_print.cpp | 4 +- clang/test/OpenMP/scan_messages.cpp | 30 +- clang/test/Sema/attr-noreturn.c | 31 + clang/test/SemaCUDA/bad-calls-on-same-line.cu | 4 +- clang/test/SemaCUDA/call-device-fn-from-host.cu | 4 +- clang/test/SemaCUDA/call-host-fn-from-device.cu | 4 +- clang/test/SemaCUDA/openmp-target.cu | 4 +- clang/test/SemaCUDA/trace-through-global.cu | 2 +- clang/tools/libclang/CIndex.cpp | 3 + clang/unittests/Format/FormatTestCSharp.cpp | 22 + clang/utils/TableGen/ClangAttrEmitter.cpp | 15 + libc/CMakeLists.txt | 6 +- libc/utils/UnitTest/Test.cpp | 4 +- libcxx/docs/TestingLibcxx.rst | 2 +- libcxx/docs/UsingLibcxx.rst | 2 +- libcxx/docs/index.rst | 10 +- .../new.delete.array/new_align_val_t.pass.cpp | 3 - .../new_align_val_t_nothrow.pass.cpp | 3 - .../new_align_val_t_nothrow_replace.pass.cpp | 2 - .../new_align_val_t_replace.pass.cpp | 3 - .../new.delete.single/new_align_val_t.pass.cpp | 3 - .../new_align_val_t_nothrow.pass.cpp | 3 - .../new_align_val_t_nothrow_replace.pass.cpp | 3 - .../new_align_val_t_replace.pass.cpp | 3 - .../allocator.adaptor.members/construct.pass.cpp | 23 + libcxx/utils/libcxx/test/config.py | 4 - libcxx/www/cxx1z_status.html | 2 +- libunwind/docs/BuildingLibunwind.rst | 4 +- libunwind/docs/index.rst | 8 +- lld/ELF/Writer.cpp | 26 +- lld/docs/AtomLLD.rst | 2 +- lld/docs/NewLLD.rst | 2 +- lld/docs/design.rst | 2 +- lld/docs/development.rst | 2 +- lld/docs/getting_started.rst | 4 +- lld/docs/index.rst | 2 +- lld/test/ELF/linkerscript/data-commands-gc.s | 2 +- lld/test/ELF/linkerscript/icf-output-sections.s | 14 +- lld/test/ELF/linkerscript/linkorder.s | 4 +- lld/test/ELF/linkerscript/linkorder2.s | 2 +- lld/test/ELF/linkerscript/memory3.s | 2 +- lld/test/ELF/linkerscript/orphan-report.s | 2 +- .../linkerscript/symbol-assign-many-passes2.test | 2 +- lld/test/ELF/mips-npic-call-pic-script.s | 34 +- lld/test/ELF/shuffle-sections-init-fini.s | 4 +- lld/test/ELF/text-section-prefix.s | 54 +- lldb/include/lldb/API/SBTarget.h | 8 +- .../lldb/DataFormatters/FormattersHelpers.h | 2 + lldb/include/lldb/Target/Target.h | 5 + lldb/source/API/SBTarget.cpp | 13 +- lldb/source/Commands/CommandObjectExpression.cpp | 3 +- lldb/source/Commands/CommandObjectExpression.h | 10 + lldb/source/Commands/CommandObjectTarget.cpp | 38 ++ lldb/source/DataFormatters/FormattersHelpers.cpp | 11 + .../Language/CPlusPlus/CPlusPlusLanguage.cpp | 13 + lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp | 98 +++ lldb/source/Plugins/Language/CPlusPlus/LibCxx.h | 28 + .../Plugins/Language/CPlusPlus/LibCxxList.cpp | 13 +- lldb/source/Target/Target.cpp | 119 ++-- lldb/source/Target/TargetProperties.td | 5 +- lldb/test/API/commands/settings/TestSettings.py | 134 +++- .../API/commands/statistics/basic/TestStats.py | 14 + .../data-formatter-stl/libcxx/unique_ptr/Makefile | 6 + .../unique_ptr/TestDataFormatterLibcxxUniquePtr.py | 47 ++ .../data-formatter-stl/libcxx/unique_ptr/main.cpp | 13 + .../Functionalities/TestDataFormatter.test | 2 +- .../Functionalities/TestExpressionEvaluation.test | 2 +- .../Reproducer/Functionalities/TestImageList.test | 2 +- .../Reproducer/Functionalities/TestStepping.test | 2 +- .../Shell/Reproducer/TestCaptureEnvOverride.test | 1 - lldb/test/Shell/Reproducer/TestCrash.test | 1 - lldb/test/Shell/Reproducer/TestDiscard.test | 1 - lldb/test/Shell/Reproducer/TestDump.test | 1 - lldb/test/Shell/Reproducer/TestGDBRemoteRepro.test | 2 +- .../test/Shell/Reproducer/TestMultipleTargets.test | 2 +- lldb/test/Shell/Reproducer/TestRelativePath.test | 1 - lldb/test/Shell/Reproducer/TestReuseDirectory.test | 2 +- lldb/test/Shell/Reproducer/TestSynchronous.test | 1 - lldb/test/Shell/Reproducer/TestWorkingDir.test | 2 - lldb/test/Shell/Reproducer/lit.local.cfg | 3 + llvm/docs/AMDGPUUsage.rst | 2 +- llvm/docs/AliasAnalysis.rst | 8 +- llvm/docs/CMake.rst | 2 +- llvm/docs/CommandGuide/llvm-lipo.rst | 2 +- llvm/docs/CommandGuide/llvm-objcopy.rst | 2 +- llvm/docs/CommandGuide/llvm-objdump.rst | 2 +- llvm/docs/CommandGuide/llvm-size.rst | 2 +- llvm/docs/CommandGuide/llvm-strings.rst | 2 +- llvm/docs/CommandGuide/llvm-strip.rst | 2 +- llvm/docs/CompileCudaWithLLVM.rst | 14 +- llvm/docs/Docker.rst | 4 +- llvm/docs/FAQ.rst | 8 +- llvm/docs/Frontend/PerformanceTips.rst | 2 +- llvm/docs/GettingStarted.rst | 16 +- llvm/docs/GettingStartedVS.rst | 17 +- llvm/docs/GlobalISel/GMIR.rst | 2 +- llvm/docs/GlobalISel/GenericOpcode.rst | 9 + llvm/docs/GlobalISel/IRTranslator.rst | 2 +- llvm/docs/GlobalISel/KnownBits.rst | 2 +- .../HistoricalNotes/2007-OriginalClangReadme.txt | 2 +- llvm/docs/HowToCrossCompileLLVM.rst | 4 +- llvm/docs/HowToSetUpLLVMStyleRTTI.rst | 6 +- llvm/docs/HowToSubmitABug.rst | 2 +- llvm/docs/LLVMBuild.txt | 2 +- llvm/docs/LangRef.rst | 6 +- llvm/docs/Lexicon.rst | 2 +- llvm/docs/LibFuzzer.rst | 24 +- llvm/docs/LoopTerminology.rst | 4 +- llvm/docs/MarkdownQuickstartTemplate.md | 2 +- llvm/docs/MergeFunctions.rst | 16 +- llvm/docs/Packaging.rst | 2 +- llvm/docs/ProgrammersManual.rst | 82 +-- llvm/docs/Proposals/GitHubMove.rst | 14 +- llvm/docs/README.txt | 6 +- llvm/docs/Reference.rst | 4 +- llvm/docs/ReleaseProcess.rst | 6 +- llvm/docs/SphinxQuickstartTemplate.rst | 2 +- llvm/docs/TableGen/index.rst | 2 +- llvm/docs/TestSuiteGuide.md | 8 +- llvm/docs/TestingGuide.rst | 2 +- llvm/docs/TypeMetadata.rst | 4 +- llvm/docs/UserGuides.rst | 4 +- llvm/docs/Vectorizers.rst | 4 +- llvm/docs/WritingAnLLVMPass.rst | 38 +- llvm/docs/index.rst | 8 +- llvm/docs/tutorial/BuildingAJIT1.rst | 2 +- .../MyFirstLanguageFrontend/LangImpl02.rst | 2 +- .../MyFirstLanguageFrontend/LangImpl03.rst | 6 +- .../MyFirstLanguageFrontend/LangImpl04.rst | 2 +- .../MyFirstLanguageFrontend/LangImpl05.rst | 2 +- .../MyFirstLanguageFrontend/LangImpl08.rst | 2 +- .../MyFirstLanguageFrontend/LangImpl09.rst | 4 +- llvm/docs/tutorial/OCamlLangImpl3.rst | 4 +- llvm/docs/tutorial/OCamlLangImpl5.rst | 2 +- llvm/docs/tutorial/index.rst | 2 +- llvm/include/llvm/Analysis/VectorUtils.h | 33 +- llvm/include/llvm/CodeGen/CallingConvLower.h | 2 +- .../llvm/CodeGen/GlobalISel/GISelKnownBits.h | 3 + llvm/include/llvm/CodeGen/MachineFrameInfo.h | 5 +- llvm/include/llvm/CodeGen/TargetLowering.h | 10 + llvm/include/llvm/CodeGen/TargetRegisterInfo.h | 6 + llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 6 +- llvm/include/llvm/IR/Function.h | 7 + llvm/include/llvm/Support/TargetOpcodes.def | 12 + llvm/include/llvm/Target/GenericOpcodes.td | 36 ++ llvm/include/llvm/Transforms/IPO/Attributor.h | 32 +- llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp | 41 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 8 + llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 17 +- llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 6 +- llvm/lib/CodeGen/MIRParser/MILexer.cpp | 1 + llvm/lib/CodeGen/MIRParser/MILexer.h | 1 + llvm/lib/CodeGen/MIRParser/MIParser.cpp | 6 + llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 2 +- llvm/lib/CodeGen/MIRPrinter.cpp | 5 + llvm/lib/CodeGen/MachineFunction.cpp | 4 +- llvm/lib/CodeGen/PrologEpilogInserter.cpp | 8 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 232 +++---- .../CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 20 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 7 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 22 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 6 + llvm/lib/DebugInfo/CodeView/TypeStreamMerger.cpp | 4 +- llvm/lib/Support/Windows/Path.inc | 5 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 23 + llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 6 + llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h | 8 + llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 + .../AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp | 6 + .../AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h | 4 + llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 9 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 13 +- llvm/lib/Target/AVR/AVRFrameLowering.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 8 +- llvm/lib/Target/MSP430/MSP430FrameLowering.cpp | 4 +- llvm/lib/Target/Mips/AsmParser/MipsAsmParser.cpp | 218 +++++++ .../Mips/MCTargetDesc/MipsTargetStreamer.cpp | 18 + llvm/lib/Target/Mips/Mips64InstrInfo.td | 14 + llvm/lib/Target/Mips/MipsCallLowering.cpp | 5 +- llvm/lib/Target/Mips/MipsInstrFPU.td | 4 +- llvm/lib/Target/Mips/MipsInstrInfo.td | 44 ++ llvm/lib/Target/Mips/MipsScheduleP5600.td | 5 +- llvm/lib/Target/Mips/MipsSubtarget.h | 1 + llvm/lib/Target/Mips/MipsTargetStreamer.h | 3 + llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 10 +- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 3 +- llvm/lib/Target/SystemZ/SystemZShortenInst.cpp | 43 ++ llvm/lib/Target/X86/X86.h | 1 + llvm/lib/Target/X86/X86AvoidTrailingCall.cpp | 97 ++- llvm/lib/Target/X86/X86CallFrameOptimization.cpp | 4 +- llvm/lib/Target/X86/X86FastISel.cpp | 6 +- llvm/lib/Target/X86/X86FrameLowering.cpp | 14 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 39 +- llvm/lib/Target/X86/X86ISelLowering.h | 26 - llvm/lib/Target/X86/X86InstrInfo.cpp | 52 +- llvm/lib/Target/X86/X86InstrInfo.h | 4 +- llvm/lib/Target/X86/X86TargetMachine.cpp | 1 + llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 180 +++--- llvm/lib/Transforms/IPO/Attributor.cpp | 96 ++- llvm/lib/Transforms/IPO/OpenMPOpt.cpp | 65 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 24 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 2 +- llvm/lib/Transforms/Vectorize/VPlan.cpp | 2 +- llvm/test/Analysis/CostModel/X86/reduce-add.ll | 165 +++-- llvm/test/Analysis/CostModel/X86/reduce-and.ll | 199 ++---- llvm/test/Analysis/CostModel/X86/reduce-mul.ll | 138 ++-- llvm/test/Analysis/CostModel/X86/reduce-or.ll | 199 ++---- llvm/test/Analysis/CostModel/X86/reduce-xor.ll | 199 ++---- llvm/test/Analysis/CostModel/X86/reduction.ll | 137 ++-- .../GlobalISel/legalizer-info-validation.mir | 12 + .../CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll | 318 +++++++++ .../AMDGPU/GlobalISel/legalize-implicit-def.mir | 104 +++ .../AMDGPU/GlobalISel/legalize-unmerge-values.mir | 88 ++- llvm/test/CodeGen/PowerPC/fma-negate.ll | 314 +++++++++ llvm/test/CodeGen/SystemZ/shorten-fused-fp-ops.mir | 60 ++ llvm/test/CodeGen/Thumb/frame-access.ll | 4 +- .../cond-vector-reduce-mve-codegen.ll | 12 +- .../Thumb2/LowOverheadLoops/extending-loads.ll | 44 +- llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll | 16 +- llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll | 541 ++++++++++++++++ llvm/test/CodeGen/Thumb2/mve-vmull.ll | 99 +++ llvm/test/CodeGen/X86/sad.ll | 516 ++------------- llvm/test/CodeGen/X86/win64-eh-empty-block-2.mir | 223 +++++++ llvm/test/CodeGen/X86/win64-eh-empty-block.ll | 2 +- llvm/test/CodeGen/X86/wineh-coreclr.ll | 8 +- llvm/test/MC/Mips/cpadd-bad.s | 13 + llvm/test/MC/Mips/cpadd.s | 29 + llvm/test/MC/Mips/macro-sle.s | 31 + llvm/test/MC/Mips/macro-sle64.s | 29 + llvm/test/MC/Mips/macro-sne.s | 27 + .../Attributor/IPConstantProp/musttail-call.ll | 7 +- llvm/test/Transforms/Attributor/range.ll | 102 +++ llvm/test/Transforms/InstCombine/ctpop-cttz.ll | 72 ++- llvm/test/Transforms/InstCombine/select.ll | 23 + llvm/test/Transforms/InstSimplify/freeze.ll | 254 ++++++++ llvm/test/Transforms/OpenMP/rtf_type_checking.ll | 63 ++ llvm/test/Transforms/SCCP/apint-xor.ll | 39 ++ llvm/test/Transforms/SCCP/conditions-iter-order.ll | 79 +++ llvm/test/Transforms/SCCP/conditions-ranges.ll | 712 +++++++++++++++++++++ .../SLPVectorizer/X86/reduction_unrolled.ll | 70 +- .../Transforms/VectorCombine/X86/extract-binop.ll | 68 ++ .../Transforms/VectorCombine/X86/extract-cmp.ll | 37 ++ .../tools/llvm-objdump/ELF/PowerPC/branch-offset.s | 76 +-- llvm/test/tools/llvm-readobj/ELF/all.test | 3 +- .../ELF/dyn-symbols-size-from-hash-table.test | 314 +++++++++ llvm/tools/llvm-readobj/ELFDumper.cpp | 117 ++-- llvm/unittests/Analysis/VectorUtilsTest.cpp | 8 + llvm/unittests/CodeGen/GlobalISel/CSETest.cpp | 4 +- .../CodeGen/GlobalISel/ConstantFoldingTest.cpp | 4 +- llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp | 76 +++ llvm/unittests/CodeGen/GlobalISel/GISelMITest.h | 67 +- .../unittests/CodeGen/GlobalISel/KnownBitsTest.cpp | 61 +- .../CodeGen/GlobalISel/LegalizerHelperTest.cpp | 161 +++-- .../unittests/CodeGen/GlobalISel/LegalizerTest.cpp | 6 +- .../CodeGen/GlobalISel/MachineIRBuilderTest.cpp | 27 +- .../CodeGen/GlobalISel/PatternMatchTest.cpp | 18 +- llvm/unittests/MC/AMDGPU/CMakeLists.txt | 11 + llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp | 77 +++ llvm/unittests/MC/CMakeLists.txt | 7 + llvm/unittests/Support/Path.cpp | 4 +- llvm/unittests/Target/AMDGPU/CMakeLists.txt | 16 + llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp | 88 +++ .../clang/lib/StaticAnalyzer/Frontend/BUILD.gn | 2 +- .../utils/gn/secondary/llvm/lib/Target/targets.gni | 5 +- llvm/utils/gn/secondary/llvm/unittests/BUILD.gn | 6 + .../gn/secondary/llvm/unittests/MC/AMDGPU/BUILD.gn | 14 + .../llvm/unittests/Target/AMDGPU/BUILD.gn | 17 + mlir/docs/LangRef.md | 2 +- mlir/include/mlir/Dialect/Affine/Passes.h | 27 +- mlir/include/mlir/IR/OpImplementation.h | 19 + mlir/include/mlir/InitAllPasses.h | 2 +- mlir/include/mlir/Transforms/FoldUtils.h | 19 +- mlir/include/mlir/Transforms/Passes.h | 29 - mlir/lib/Conversion/LoopToStandard/CMakeLists.txt | 2 +- ...onvertLoopToStandard.cpp => LoopToStandard.cpp} | 2 +- mlir/lib/Conversion/StandardToLLVM/CMakeLists.txt | 2 +- ...onvertStandardToLLVM.cpp => StandardToLLVM.cpp} | 2 +- .../Transforms/AffineLoopInvariantCodeMotion.cpp | 2 +- mlir/lib/Dialect/Affine/Transforms/CMakeLists.txt | 4 + .../{ => Dialect/Affine}/Transforms/LoopTiling.cpp | 9 +- .../{ => Dialect/Affine}/Transforms/LoopUnroll.cpp | 3 +- .../Affine}/Transforms/LoopUnrollAndJam.cpp | 3 +- .../Affine/Transforms/SuperVectorize.cpp} | 8 +- mlir/lib/IR/AsmPrinter.cpp | 22 +- mlir/lib/Parser/Parser.cpp | 63 +- mlir/lib/Transforms/CMakeLists.txt | 4 - mlir/lib/Transforms/Utils/FoldUtils.cpp | 20 +- .../Affine/SuperVectorize}/compose_maps.mlir | 2 +- .../Affine/SuperVectorize}/normalize_maps.mlir | 2 +- .../Affine/SuperVectorize}/vector_utils.mlir | 4 +- .../Affine/SuperVectorize}/vectorize_1d.mlir | 2 +- .../Affine/SuperVectorize}/vectorize_2d.mlir | 4 +- .../Affine/SuperVectorize}/vectorize_3d.mlir | 2 +- .../SuperVectorize}/vectorize_outer_loop_2d.mlir | 2 +- .../vectorize_outer_loop_transpose_2d.mlir | 2 +- .../SuperVectorize}/vectorize_transpose_2d.mlir | 2 +- .../Affine}/affine-data-copy.mlir | 0 .../Affine}/affine-loop-invariant-code-motion.mlir | 0 .../Affine}/dma-generate.mlir | 0 .../Affine}/loop-tiling.mlir | 4 +- .../Affine}/parallelism-detection.mlir | 0 .../Affine}/simplify-affine-structures.mlir | 0 .../Affine}/slicing-utils.mlir | 6 +- .../{Transforms => Dialect/Affine}/unroll-jam.mlir | 0 .../{Transforms => Dialect/Affine}/unroll.mlir | 0 mlir/test/IR/parser.mlir | 40 ++ mlir/test/lib/Dialect/Affine/CMakeLists.txt | 2 + .../Affine}/TestParallelismDetection.cpp | 1 - .../Affine}/TestVectorizationUtils.cpp | 5 +- mlir/test/lib/TestDialect/TestDialect.cpp | 81 +++ mlir/test/lib/TestDialect/TestOps.td | 12 + mlir/test/lib/Transforms/CMakeLists.txt | 2 - .../lib/Transforms/TestConvertGPUKernelToCubin.cpp | 5 +- mlir/test/mlir-cuda-runner/all-reduce-and.mlir | 21 +- mlir/test/mlir-cuda-runner/all-reduce-max.mlir | 9 +- mlir/test/mlir-cuda-runner/all-reduce-min.mlir | 9 +- mlir/test/mlir-cuda-runner/all-reduce-or.mlir | 9 +- mlir/test/mlir-cuda-runner/all-reduce-xor.mlir | 9 +- .../test/mlir-cuda-runner/multiple-all-reduce.mlir | 9 + .../mlir-cuda-runner/cuda-runtime-wrappers.cpp | 80 ++- openmp/README.rst | 2 +- openmp/runtime/src/kmp_tasking.cpp | 9 +- .../runtime/test/tasking/omp_task_red_taskloop.c | 57 ++ polly/docs/TipsAndTricks.rst | 2 +- 391 files changed, 9230 insertions(+), 3473 deletions(-) create mode 100644 clang/include/clang/StaticAnalyzer/Frontend/AnalyzerHelpFlags.h delete mode 100644 clang/include/clang/StaticAnalyzer/Frontend/CheckerRegistration.h rename clang/lib/StaticAnalyzer/Frontend/{CheckerRegistration.cpp => AnalyzerHelpF [...] create mode 100644 clang/test/CodeGen/attr-noreturn.c create mode 100644 lldb/test/API/functionalities/data-formatter/data-formatter-stl [...] create mode 100644 lldb/test/API/functionalities/data-formatter/data-formatter-stl [...] create mode 100644 lldb/test/API/functionalities/data-formatter/data-formatter-stl [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll create mode 100644 llvm/test/CodeGen/PowerPC/fma-negate.ll create mode 100644 llvm/test/CodeGen/SystemZ/shorten-fused-fp-ops.mir create mode 100644 llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll create mode 100644 llvm/test/CodeGen/X86/win64-eh-empty-block-2.mir create mode 100644 llvm/test/MC/Mips/cpadd-bad.s create mode 100644 llvm/test/MC/Mips/cpadd.s create mode 100644 llvm/test/MC/Mips/macro-sle.s create mode 100644 llvm/test/MC/Mips/macro-sle64.s create mode 100644 llvm/test/MC/Mips/macro-sne.s create mode 100644 llvm/test/Transforms/OpenMP/rtf_type_checking.ll create mode 100644 llvm/test/Transforms/SCCP/apint-xor.ll create mode 100644 llvm/test/Transforms/SCCP/conditions-iter-order.ll create mode 100644 llvm/test/Transforms/SCCP/conditions-ranges.ll create mode 100644 llvm/test/tools/llvm-readobj/ELF/dyn-symbols-size-from-hash-table.test create mode 100644 llvm/unittests/MC/AMDGPU/CMakeLists.txt create mode 100644 llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp create mode 100644 llvm/unittests/Target/AMDGPU/CMakeLists.txt create mode 100644 llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp create mode 100644 llvm/utils/gn/secondary/llvm/unittests/MC/AMDGPU/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU/BUILD.gn rename mlir/lib/Conversion/LoopToStandard/{ConvertLoopToStandard.cpp => LoopToStan [...] rename mlir/lib/Conversion/StandardToLLVM/{ConvertStandardToLLVM.cpp => StandardTo [...] rename mlir/lib/{ => Dialect/Affine}/Transforms/LoopTiling.cpp (98%) rename mlir/lib/{ => Dialect/Affine}/Transforms/LoopUnroll.cpp (99%) rename mlir/lib/{ => Dialect/Affine}/Transforms/LoopUnrollAndJam.cpp (99%) rename mlir/lib/{Transforms/Vectorize.cpp => Dialect/Affine/Transforms/SuperVector [...] rename mlir/test/{Transforms/Vectorize => Dialect/Affine/SuperVectorize}/compose_m [...] rename mlir/test/{Transforms/Vectorize => Dialect/Affine/SuperVectorize}/normalize [...] rename mlir/test/{Transforms/Vectorize => Dialect/Affine/SuperVectorize}/vector_ut [...] rename mlir/test/{Transforms/Vectorize => Dialect/Affine/SuperVectorize}/vectorize [...] rename mlir/test/{Transforms/Vectorize => Dialect/Affine/SuperVectorize}/vectorize [...] rename mlir/test/{Transforms/Vectorize => Dialect/Affine/SuperVectorize}/vectorize [...] rename mlir/test/{Transforms/Vectorize => Dialect/Affine/SuperVectorize}/vectorize [...] rename mlir/test/{Transforms/Vectorize => Dialect/Affine/SuperVectorize}/vectorize [...] rename mlir/test/{Transforms/Vectorize => Dialect/Affine/SuperVectorize}/vectorize [...] rename mlir/test/{Transforms => Dialect/Affine}/affine-data-copy.mlir (100%) rename mlir/test/{Transforms => Dialect/Affine}/affine-loop-invariant-code-motion. [...] rename mlir/test/{Transforms => Dialect/Affine}/dma-generate.mlir (100%) rename mlir/test/{Transforms => Dialect/Affine}/loop-tiling.mlir (97%) rename mlir/test/{Transforms => Dialect/Affine}/parallelism-detection.mlir (100%) rename mlir/test/{Transforms => Dialect/Affine}/simplify-affine-structures.mlir (100%) rename mlir/test/{Transforms => Dialect/Affine}/slicing-utils.mlir (97%) rename mlir/test/{Transforms => Dialect/Affine}/unroll-jam.mlir (100%) rename mlir/test/{Transforms => Dialect/Affine}/unroll.mlir (100%) rename mlir/test/lib/{Transforms => Dialect/Affine}/TestParallelismDetection.cpp (99%) rename mlir/test/lib/{Transforms => Dialect/Affine}/TestVectorizationUtils.cpp (98%) create mode 100644 openmp/runtime/test/tasking/omp_task_red_taskloop.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allyesconfig updated (2eb8f17 -> eb10e29)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allyesconfig in repository toolchain/ci/base-artifacts. discards 2eb8f17 11: update: llvm-linux: 16048 new eb10e29 11: update: llvm-linux: 16048 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (2eb8f17) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 182 +- 02-build_llvm/console.log | 12782 +++++++++---------- 03-build_linux/console.log | 7428 ++++++----- 05-check_regression/console.log | 12 +- 05-check_regression/results.regressions | 20 +- 06-update_baseline/console.log | 32 +- 06-update_baseline/results.regressions | 20 +- console.log | 20436 +++++++++++++++--------------- jenkins/manifest.sh | 8 +- 9 files changed, 20460 insertions(+), 20460 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[newlib] branch topic/serial_io updated (a1f058545 -> 2a4b1de77)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch topic/serial_io in repository newlib. from a1f058545 Cygwin: serial: select: call ClearCommError prior to calling [...] new 2a4b1de77 Cygwin: serial: use per call OVERLAPPED structs The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: winsup/cygwin/fhandler.h | 8 ----- winsup/cygwin/fhandler_serial.cc | 70 +++++++++------------------------------- winsup/cygwin/select.cc | 38 ++++++++++++---------- winsup/cygwin/select.h | 21 +++++++++++- 4 files changed, 56 insertions(+), 81 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig updated (83aa5aa313a -> 5db9e89323c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig in repository toolchain/ci/gcc. from 83aa5aa313a Daily bump. adds 6e00d8dcf32 Daily bump. adds b809f0b6580 Set proper DECL_ALIGN in offload_handle_link_vars (PR94233) adds 2fa4b1ffd6e Save ref->speculative_id before clone_reference. adds 263ee1260bc tree-optimization/94266 - aovid propagating addresses of TA [...] adds 7a2090b04e5 ipa/94245 - avoid folding when we want an ADDR_EXPR adds 26b3e568a60 [PR94044] Fix ICE with sizeof<argumentpack> adds a3586eeb884 AMDGCN offloading – use amdgcn-amdhsa adds ce6413087de lto/lto.c – used $ or . in generated linkptr name adds 4897bb0045d libgomp – fix declare target link handling (PR94251) adds b0d84ecc55f fortran: ICE in gfc_match_assignment PR93600 adds 4dcc4502f31 tree-optimization/94261 - avoid IL adjustments in SLP analysis adds 6debbff6ca3 arm: Add earlyclobber to MVE instructions that require it new 962406639c0 testsuite, arm: Change tests to assemble new 0cd55f9d3af libgccjit: handle long literals in playback::context::new_s [...] new 1a5c27b1b43 [ARM][GCC][12x]: MVE ACLE intrinsics to set and get vector lane. new 85244449104 [ARM][GCC][13x]: MVE ACLE scalar shift intrinsics. new 88c9a831f3a [ARM][GCC][14x]: MVE ACLE whole vector left shift with carr [...] new d326e9586b4 driver: Improve the generated help text for alias options new 5db9e89323c c: Fix up cfun->function_end_locus on invalid function bodi [...] The 7 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 192 ++ gcc/DATESTAMP | 2 +- gcc/c/ChangeLog | 8 + gcc/c/c-parser.c | 7 +- gcc/config/arm/arm-builtins.c | 20 + gcc/config/arm/arm_mve.h | 457 ++++ gcc/config/arm/arm_mve_builtins.def | 18 + gcc/config/arm/iterators.md | 3 + gcc/config/arm/mve.md | 397 +++- gcc/config/arm/neon.md | 21 +- gcc/config/arm/vec-common.md | 33 + gcc/cp/ChangeLog | 6 + gcc/cp/tree.c | 6 +- gcc/doc/install.texi | 16 +- gcc/fortran/ChangeLog | 17 + gcc/fortran/expr.c | 34 +- gcc/fortran/match.c | 8 + gcc/fortran/resolve.c | 2 +- gcc/ipa-prop.c | 2 +- gcc/jit/ChangeLog | 11 + gcc/jit/jit-playback.c | 16 +- gcc/jit/jit-playback.h | 1 - gcc/lto/ChangeLog | 11 + gcc/lto/lto.c | 12 +- gcc/opts.c | 29 +- gcc/symtab.c | 9 +- gcc/testsuite/ChangeLog | 2446 ++++++++++++++++++++ .../arm/mve/intrinsics/{vbicq_n_s16.c => asrl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => lsll.c} | 9 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 3 +- .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 3 +- .../arm/mve/intrinsics/mve_vector_float.c | 3 +- .../arm/mve/intrinsics/mve_vector_float1.c | 3 +- .../arm/mve/intrinsics/mve_vector_float2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 3 +- .../arm/mve/intrinsics/mve_vector_int1.c | 3 +- .../arm/mve/intrinsics/mve_vector_int2.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint1.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint2.c | 3 +- .../arm/mve/intrinsics/{vbicq_n_u16.c => sqrshr.c} | 9 +- .../gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c | 13 + .../gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c | 13 + .../arm/mve/intrinsics/{vdupq_n_s8.c => sqshl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => sqshll.c} | 9 +- .../arm/mve/intrinsics/{vdupq_n_s8.c => srshr.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => srshrl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_u32.c => uqrshl.c} | 9 +- .../gcc.target/arm/mve/intrinsics/uqrshll_sat48.c | 13 + .../gcc.target/arm/mve/intrinsics/uqrshll_sat64.c | 13 + .../arm/mve/intrinsics/{vdupq_n_s8.c => uqshl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => uqshll.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => urshr.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => urshrl.c} | 9 +- .../gcc.target/arm/mve/intrinsics/vabavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadcq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadcq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmlaq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmlaq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot180_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot180_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot180_m_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot180_m_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot270_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot270_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot270_m_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot270_m_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot90_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot90_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot90_m_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot90_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpcsq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vcmpcsq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_f16.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_f32.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpgeq_m_n_f16.c | 1 - .../arm/mve/intrinsics/vcmpgeq_m_n_f32.c | 1 - .../arm/mve/intrinsics/vcmpgeq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vcmpgeq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpgtq_m_n_f16.c | 1 - .../arm/mve/intrinsics/vcmpgtq_m_n_f32.c | 1 - .../arm/mve/intrinsics/vcmpgtq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vcmpgtq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c | 1 - .../arm/mve/intrinsics/vcmphiq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vcmphiq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpleq_m_n_f16.c | 1 - .../arm/mve/intrinsics/vcmpleq_m_n_f32.c | 1 - .../arm/mve/intrinsics/vcmpleq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vcmpleq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpltq_m_n_f16.c | 1 - .../arm/mve/intrinsics/vcmpltq_m_n_f32.c | 1 - .../arm/mve/intrinsics/vcmpltq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vcmpltq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpneq_m_n_f16.c | 1 - .../arm/mve/intrinsics/vcmpneq_m_n_f32.c | 1 - .../arm/mve/intrinsics/vcmpneq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vcmpneq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vcmpneq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vcmpneq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmulq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmulq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot180_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot180_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot180_m_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot180_m_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot180_x_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot180_x_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot270_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot270_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot270_m_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot270_m_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot270_x_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot270_x_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot90_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot90_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot90_m_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot90_m_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot90_x_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot90_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_s64.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_u64.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp16q.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp16q_m.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp32q.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp32q_m.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp64q.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp64q_m.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp8q.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp8q_m.c | 1 - .../arm/mve/intrinsics/vcvtaq_m_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtaq_m_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtaq_m_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtaq_m_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtaq_x_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtaq_x_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtaq_x_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtaq_x_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c | 1 - .../arm/mve/intrinsics/vcvtbq_m_f16_f32.c | 1 - .../arm/mve/intrinsics/vcvtbq_m_f32_f16.c | 1 - .../arm/mve/intrinsics/vcvtbq_x_f32_f16.c | 1 - .../arm/mve/intrinsics/vcvtmq_m_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtmq_m_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtmq_m_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtmq_m_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtmq_x_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtmq_x_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtmq_x_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtmq_x_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtnq_m_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtnq_m_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtnq_m_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtnq_m_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtnq_x_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtnq_x_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtnq_x_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtnq_x_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtpq_m_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtpq_m_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtpq_m_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtpq_m_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtpq_x_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtpq_x_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtpq_x_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtpq_x_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_f16_s16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_f16_u16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_f32_s32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_f16_s16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_f16_u16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_f32_s32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_n_f16_s16.c | 1 - .../arm/mve/intrinsics/vcvtq_n_f16_u16.c | 1 - .../arm/mve/intrinsics/vcvtq_n_f32_s32.c | 1 - .../arm/mve/intrinsics/vcvtq_n_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_n_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_n_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_n_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_n_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_f16_s16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_f16_u16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_f32_s32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_f16_s16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_f16_u16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_f32_s32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c | 1 - .../arm/mve/intrinsics/vcvttq_m_f16_f32.c | 1 - .../arm/mve/intrinsics/vcvttq_m_f32_f16.c | 1 - .../arm/mve/intrinsics/vcvttq_x_f32_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c | 1 - .../arm/mve/intrinsics/vddupq_m_wb_u16.c | 1 - .../arm/mve/intrinsics/vddupq_m_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vddupq_x_wb_u16.c | 1 - .../arm/mve/intrinsics/vddupq_x_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vdwdupq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vdwdupq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c | 1 - .../arm/mve/intrinsics/vdwdupq_m_wb_u16.c | 1 - .../arm/mve/intrinsics/vdwdupq_m_wb_u32.c | 1 - .../arm/mve/intrinsics/vdwdupq_m_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c | 1 - .../arm/mve/intrinsics/vdwdupq_x_n_u16.c | 1 - .../arm/mve/intrinsics/vdwdupq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vdwdupq_x_wb_u16.c | 1 - .../arm/mve/intrinsics/vdwdupq_x_wb_u32.c | 1 - .../arm/mve/intrinsics/vdwdupq_x_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmsq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmsq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_m_s16.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_m_s32.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_m_s8.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_s16.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_s32.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_s8.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_x_s16.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_x_s32.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_x_s8.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_m_s16.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_m_s32.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_m_s8.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_s16.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_s32.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_s8.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_x_s16.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_x_s32.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c | 1 - .../arm/mve/intrinsics/vidupq_m_wb_u16.c | 1 - .../arm/mve/intrinsics/vidupq_m_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vidupq_x_wb_u16.c | 1 - .../arm/mve/intrinsics/vidupq_x_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c | 1 - .../arm/mve/intrinsics/viwdupq_m_n_u16.c | 1 - .../arm/mve/intrinsics/viwdupq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c | 1 - .../arm/mve/intrinsics/viwdupq_m_wb_u16.c | 1 - .../arm/mve/intrinsics/viwdupq_m_wb_u32.c | 1 - .../arm/mve/intrinsics/viwdupq_m_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c | 1 - .../arm/mve/intrinsics/viwdupq_x_n_u16.c | 1 - .../arm/mve/intrinsics/viwdupq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c | 1 - .../arm/mve/intrinsics/viwdupq_x_wb_u16.c | 1 - .../arm/mve/intrinsics/viwdupq_x_wb_u32.c | 1 - .../arm/mve/intrinsics/viwdupq_x_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_u8.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_s16.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_s32.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_s8.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_u16.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_u32.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_u8.c | 1 - .../mve/intrinsics/vldrbq_gather_offset_z_s16.c | 1 - .../mve/intrinsics/vldrbq_gather_offset_z_s32.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c | 1 - .../mve/intrinsics/vldrbq_gather_offset_z_u16.c | 1 - .../mve/intrinsics/vldrbq_gather_offset_z_u32.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_base_s64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_base_u64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c | 1 - .../mve/intrinsics/vldrdq_gather_base_wb_z_s64.c | 1 - .../mve/intrinsics/vldrdq_gather_base_wb_z_u64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_base_z_s64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_base_z_u64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_offset_s64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_offset_u64.c | 1 - .../mve/intrinsics/vldrdq_gather_offset_z_s64.c | 1 - .../mve/intrinsics/vldrdq_gather_offset_z_u64.c | 1 - .../intrinsics/vldrdq_gather_shifted_offset_s64.c | 1 - .../intrinsics/vldrdq_gather_shifted_offset_u64.c | 1 - .../vldrdq_gather_shifted_offset_z_s64.c | 1 - .../vldrdq_gather_shifted_offset_z_u64.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_f16.c | 1 - .../arm/mve/intrinsics/vldrhq_gather_offset_f16.c | 1 - .../arm/mve/intrinsics/vldrhq_gather_offset_s16.c | 1 - .../arm/mve/intrinsics/vldrhq_gather_offset_s32.c | 1 - .../arm/mve/intrinsics/vldrhq_gather_offset_u16.c | 1 - .../arm/mve/intrinsics/vldrhq_gather_offset_u32.c | 1 - .../mve/intrinsics/vldrhq_gather_offset_z_f16.c | 1 - .../mve/intrinsics/vldrhq_gather_offset_z_s16.c | 1 - .../mve/intrinsics/vldrhq_gather_offset_z_s32.c | 1 - .../mve/intrinsics/vldrhq_gather_offset_z_u16.c | 1 - .../mve/intrinsics/vldrhq_gather_offset_z_u32.c | 1 - .../intrinsics/vldrhq_gather_shifted_offset_f16.c | 1 - .../intrinsics/vldrhq_gather_shifted_offset_s16.c | 1 - .../intrinsics/vldrhq_gather_shifted_offset_s32.c | 1 - .../intrinsics/vldrhq_gather_shifted_offset_u16.c | 1 - .../intrinsics/vldrhq_gather_shifted_offset_u32.c | 1 - .../vldrhq_gather_shifted_offset_z_f16.c | 1 - .../vldrhq_gather_shifted_offset_z_s16.c | 1 - .../vldrhq_gather_shifted_offset_z_s32.c | 1 - .../vldrhq_gather_shifted_offset_z_u16.c | 1 - .../vldrhq_gather_shifted_offset_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrwq_f32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_f32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_s32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_u32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c | 1 - .../mve/intrinsics/vldrwq_gather_base_wb_z_f32.c | 1 - .../mve/intrinsics/vldrwq_gather_base_wb_z_s32.c | 1 - .../mve/intrinsics/vldrwq_gather_base_wb_z_u32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_z_f32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_z_s32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_z_u32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_offset_f32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_offset_s32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_offset_u32.c | 1 - .../mve/intrinsics/vldrwq_gather_offset_z_f32.c | 1 - .../mve/intrinsics/vldrwq_gather_offset_z_s32.c | 1 - .../mve/intrinsics/vldrwq_gather_offset_z_u32.c | 1 - .../intrinsics/vldrwq_gather_shifted_offset_f32.c | 1 - .../intrinsics/vldrwq_gather_shifted_offset_s32.c | 1 - .../intrinsics/vldrwq_gather_shifted_offset_u32.c | 1 - .../vldrwq_gather_shifted_offset_z_f32.c | 1 - .../vldrwq_gather_shifted_offset_z_s32.c | 1 - .../vldrwq_gather_shifted_offset_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrwq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrwq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxaq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxavq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c | 1 - .../arm/mve/intrinsics/vmaxnmavq_p_f16.c | 1 - .../arm/mve/intrinsics/vmaxnmavq_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminaq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminaq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminaq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminaq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminavq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmaq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmaq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmavq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmavq_f32.c | 1 - .../arm/mve/intrinsics/vminnmavq_p_f16.c | 1 - .../arm/mve/intrinsics/vminnmavq_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmvq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmvq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_u8.c | 1 - .../arm/mve/intrinsics/vmladavaq_p_s16.c | 1 - .../arm/mve/intrinsics/vmladavaq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c | 1 - .../arm/mve/intrinsics/vmladavaq_p_u16.c | 1 - .../arm/mve/intrinsics/vmladavaq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_u8.c | 1 - .../arm/mve/intrinsics/vmladavaxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmladavaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vmladavaxq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_u8.c | 1 - .../arm/mve/intrinsics/vmladavxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmladavxq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavxq_s8.c | 1 - .../arm/mve/intrinsics/vmlaldavaq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlaldavaq_p_s32.c | 1 - .../arm/mve/intrinsics/vmlaldavaq_p_u16.c | 1 - .../arm/mve/intrinsics/vmlaldavaq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c | 1 - .../arm/mve/intrinsics/vmlaldavaxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlaldavaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vmlaldavaxq_p_u16.c | 1 - .../arm/mve/intrinsics/vmlaldavaxq_p_u32.c | 1 - .../arm/mve/intrinsics/vmlaldavaxq_s16.c | 1 - .../arm/mve/intrinsics/vmlaldavaxq_s32.c | 1 - .../arm/mve/intrinsics/vmlaldavq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlaldavq_p_s32.c | 1 - .../arm/mve/intrinsics/vmlaldavq_p_u16.c | 1 - .../arm/mve/intrinsics/vmlaldavq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c | 1 - .../arm/mve/intrinsics/vmlaldavxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlaldavxq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c | 1 - .../arm/mve/intrinsics/vmlsdavaq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsdavaq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c | 1 - .../arm/mve/intrinsics/vmlsdavaxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsdavaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vmlsdavaxq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c | 1 - .../arm/mve/intrinsics/vmlsdavxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsdavxq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c | 1 - .../arm/mve/intrinsics/vmlsldavaq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsldavaq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c | 1 - .../arm/mve/intrinsics/vmlsldavaxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsldavaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vmlsldavaxq_s16.c | 1 - .../arm/mve/intrinsics/vmlsldavaxq_s32.c | 1 - .../arm/mve/intrinsics/vmlsldavq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsldavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c | 1 - .../arm/mve/intrinsics/vmlsldavxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsldavxq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c | 1 - .../arm/mve/intrinsics/vmullbq_int_m_s16.c | 1 - .../arm/mve/intrinsics/vmullbq_int_m_s32.c | 1 - .../arm/mve/intrinsics/vmullbq_int_m_s8.c | 1 - .../arm/mve/intrinsics/vmullbq_int_m_u16.c | 1 - .../arm/mve/intrinsics/vmullbq_int_m_u32.c | 1 - .../arm/mve/intrinsics/vmullbq_int_m_u8.c | 1 - .../arm/mve/intrinsics/vmullbq_int_s16.c | 1 - .../arm/mve/intrinsics/vmullbq_int_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c | 1 - .../arm/mve/intrinsics/vmullbq_int_u16.c | 1 - .../arm/mve/intrinsics/vmullbq_int_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c | 1 - .../arm/mve/intrinsics/vmullbq_int_x_s16.c | 1 - .../arm/mve/intrinsics/vmullbq_int_x_s32.c | 1 - .../arm/mve/intrinsics/vmullbq_int_x_s8.c | 1 - .../arm/mve/intrinsics/vmullbq_int_x_u16.c | 1 - .../arm/mve/intrinsics/vmullbq_int_x_u32.c | 1 - .../arm/mve/intrinsics/vmullbq_int_x_u8.c | 1 - .../arm/mve/intrinsics/vmullbq_poly_m_p16.c | 1 - .../arm/mve/intrinsics/vmullbq_poly_m_p8.c | 1 - .../arm/mve/intrinsics/vmullbq_poly_p16.c | 1 - .../arm/mve/intrinsics/vmullbq_poly_p8.c | 1 - .../arm/mve/intrinsics/vmullbq_poly_x_p16.c | 1 - .../arm/mve/intrinsics/vmullbq_poly_x_p8.c | 1 - .../arm/mve/intrinsics/vmulltq_int_m_s16.c | 1 - .../arm/mve/intrinsics/vmulltq_int_m_s32.c | 1 - .../arm/mve/intrinsics/vmulltq_int_m_s8.c | 1 - .../arm/mve/intrinsics/vmulltq_int_m_u16.c | 1 - .../arm/mve/intrinsics/vmulltq_int_m_u32.c | 1 - .../arm/mve/intrinsics/vmulltq_int_m_u8.c | 1 - .../arm/mve/intrinsics/vmulltq_int_s16.c | 1 - .../arm/mve/intrinsics/vmulltq_int_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c | 1 - .../arm/mve/intrinsics/vmulltq_int_u16.c | 1 - .../arm/mve/intrinsics/vmulltq_int_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c | 1 - .../arm/mve/intrinsics/vmulltq_int_x_s16.c | 1 - .../arm/mve/intrinsics/vmulltq_int_x_s32.c | 1 - .../arm/mve/intrinsics/vmulltq_int_x_s8.c | 1 - .../arm/mve/intrinsics/vmulltq_int_x_u16.c | 1 - .../arm/mve/intrinsics/vmulltq_int_x_u32.c | 1 - .../arm/mve/intrinsics/vmulltq_int_x_u8.c | 1 - .../arm/mve/intrinsics/vmulltq_poly_m_p16.c | 1 - .../arm/mve/intrinsics/vmulltq_poly_m_p8.c | 1 - .../arm/mve/intrinsics/vmulltq_poly_p16.c | 1 - .../arm/mve/intrinsics/vmulltq_poly_p8.c | 1 - .../arm/mve/intrinsics/vmulltq_poly_x_p16.c | 1 - .../arm/mve/intrinsics/vmulltq_poly_x_p8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vpnot.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_s64.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_u64.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqabsq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqabsq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqabsq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_u8.c | 1 - .../arm/mve/intrinsics/vqdmladhq_m_s16.c | 1 - .../arm/mve/intrinsics/vqdmladhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c | 1 - .../arm/mve/intrinsics/vqdmladhxq_m_s16.c | 1 - .../arm/mve/intrinsics/vqdmladhxq_m_s32.c | 1 - .../arm/mve/intrinsics/vqdmladhxq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c | 1 - .../arm/mve/intrinsics/vqdmlahq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqdmlahq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqdmlahq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c | 1 - .../arm/mve/intrinsics/vqdmlsdhq_m_s16.c | 1 - .../arm/mve/intrinsics/vqdmlsdhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c | 1 - .../arm/mve/intrinsics/vqdmlsdhxq_m_s16.c | 1 - .../arm/mve/intrinsics/vqdmlsdhxq_m_s32.c | 1 - .../arm/mve/intrinsics/vqdmlsdhxq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c | 1 - .../arm/mve/intrinsics/vqdmulhq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqdmulhq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqdmulhq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c | 1 - .../arm/mve/intrinsics/vqdmullbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqdmullbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqdmullbq_m_s16.c | 1 - .../arm/mve/intrinsics/vqdmullbq_m_s32.c | 1 - .../arm/mve/intrinsics/vqdmullbq_n_s16.c | 1 - .../arm/mve/intrinsics/vqdmullbq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c | 1 - .../arm/mve/intrinsics/vqdmulltq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqdmulltq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqdmulltq_m_s16.c | 1 - .../arm/mve/intrinsics/vqdmulltq_m_s32.c | 1 - .../arm/mve/intrinsics/vqdmulltq_n_s16.c | 1 - .../arm/mve/intrinsics/vqdmulltq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_u32.c | 1 - .../arm/mve/intrinsics/vqmovunbq_m_s16.c | 1 - .../arm/mve/intrinsics/vqmovunbq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c | 1 - .../arm/mve/intrinsics/vqmovuntq_m_s16.c | 1 - .../arm/mve/intrinsics/vqmovuntq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqnegq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqnegq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqnegq_s8.c | 1 - .../arm/mve/intrinsics/vqrdmladhq_m_s16.c | 1 - .../arm/mve/intrinsics/vqrdmladhq_m_s32.c | 1 - .../arm/mve/intrinsics/vqrdmladhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c | 1 - .../arm/mve/intrinsics/vqrdmladhxq_m_s16.c | 1 - .../arm/mve/intrinsics/vqrdmladhxq_m_s32.c | 1 - .../arm/mve/intrinsics/vqrdmladhxq_m_s8.c | 1 - .../arm/mve/intrinsics/vqrdmladhxq_s16.c | 1 - .../arm/mve/intrinsics/vqrdmladhxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_n_u16.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_n_s32.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_n_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_n_u16.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_n_u32.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_n_u8.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhq_m_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhq_m_s32.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhxq_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_m_s16.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c | 1 - .../arm/mve/intrinsics/vqrshlq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vqrshlq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vqrshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_u8.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_m_n_u32.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_n_u16.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_n_u32.c | 1 - .../arm/mve/intrinsics/vqrshrntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshrntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshrntq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vqrshrntq_m_n_u32.c | 1 - .../arm/mve/intrinsics/vqrshrntq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshrntq_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshrntq_n_u16.c | 1 - .../arm/mve/intrinsics/vqrshrntq_n_u32.c | 1 - .../arm/mve/intrinsics/vqrshrunbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshrunbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshrunbq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshrunbq_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshruntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshruntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshruntq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshruntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_u8.c | 1 - .../arm/mve/intrinsics/vqshluq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqshluq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c | 1 - .../arm/mve/intrinsics/vqshrnbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqshrnbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqshrnbq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vqshrnbq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c | 1 - .../arm/mve/intrinsics/vqshrntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqshrntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqshrntq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vqshrntq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c | 1 - .../arm/mve/intrinsics/vqshrunbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqshrunbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqshrunbq_n_s16.c | 1 - .../arm/mve/intrinsics/vqshrunbq_n_s32.c | 1 - .../arm/mve/intrinsics/vqshruntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqshruntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqshruntq_n_s16.c | 1 - .../arm/mve/intrinsics/vqshruntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_u8.c | 1 - .../arm/mve/intrinsics/vreinterpretq_f16.c | 1 - .../arm/mve/intrinsics/vreinterpretq_f32.c | 1 - .../arm/mve/intrinsics/vreinterpretq_s16.c | 1 - .../arm/mve/intrinsics/vreinterpretq_s32.c | 1 - .../arm/mve/intrinsics/vreinterpretq_s64.c | 1 - .../arm/mve/intrinsics/vreinterpretq_s8.c | 1 - .../arm/mve/intrinsics/vreinterpretq_u16.c | 1 - .../arm/mve/intrinsics/vreinterpretq_u32.c | 1 - .../arm/mve/intrinsics/vreinterpretq_u64.c | 1 - .../arm/mve/intrinsics/vreinterpretq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev16q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev16q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c | 1 - .../arm/mve/intrinsics/vrmlaldavhaq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhaq_p_u32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhaq_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhaq_u32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhaxq_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhq_p_u32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhq_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhq_u32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhxq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhxq_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhaq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhaq_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhaxq_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhq_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhxq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c | 15 + .../intrinsics/{vabsq_m_s16.c => vshlcq_m_s16.c} | 12 +- .../intrinsics/{vabdq_x_s32.c => vshlcq_m_s32.c} | 12 +- .../mve/intrinsics/{vabsq_m_s8.c => vshlcq_m_s8.c} | 12 +- .../intrinsics/{vbicq_x_u16.c => vshlcq_m_u16.c} | 12 +- .../{vdwdupq_x_n_u16.c => vshlcq_m_u32.c} | 17 +- .../mve/intrinsics/{vabdq_x_u8.c => vshlcq_m_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vshlcq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u8.c | 1 - .../arm/mve/intrinsics/vshllbq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vshllbq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c | 1 - .../arm/mve/intrinsics/vshllbq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c | 1 - .../arm/mve/intrinsics/vshllbq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vshlltq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vshlltq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c | 1 - .../arm/mve/intrinsics/vshlltq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c | 1 - .../arm/mve/intrinsics/vshlltq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_u8.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_s8.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s16.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s32.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s8.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u16.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u32.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u8.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s16.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s32.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s8.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u16.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u32.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u8.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_u64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_s64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_u64.c | 1 - .../mve/intrinsics/vstrdq_scatter_offset_p_s64.c | 1 - .../mve/intrinsics/vstrdq_scatter_offset_p_u64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_offset_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_offset_u64.c | 1 - .../vstrdq_scatter_shifted_offset_p_s64.c | 1 - .../vstrdq_scatter_shifted_offset_p_u64.c | 1 - .../intrinsics/vstrdq_scatter_shifted_offset_s64.c | 1 - .../intrinsics/vstrdq_scatter_shifted_offset_u64.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_s32.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_f16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_f16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_s16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_s32.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_u16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_u32.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_s16.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_s32.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_u16.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_u32.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_f16.c | 1 - .../vstrhq_scatter_shifted_offset_p_f16.c | 1 - .../vstrhq_scatter_shifted_offset_p_s16.c | 1 - .../vstrhq_scatter_shifted_offset_p_s32.c | 1 - .../vstrhq_scatter_shifted_offset_p_u16.c | 1 - .../vstrhq_scatter_shifted_offset_p_u32.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_s16.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_s32.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_u16.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_f32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_u32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_s32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_u32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_offset_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_offset_p_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_offset_p_s32.c | 1 - .../mve/intrinsics/vstrwq_scatter_offset_p_u32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_offset_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_offset_u32.c | 1 - .../intrinsics/vstrwq_scatter_shifted_offset_f32.c | 1 - .../vstrwq_scatter_shifted_offset_p_f32.c | 1 - .../vstrwq_scatter_shifted_offset_p_s32.c | 1 - .../vstrwq_scatter_shifted_offset_p_u32.c | 1 - .../intrinsics/vstrwq_scatter_shifted_offset_s32.c | 1 - .../intrinsics/vstrwq_scatter_shifted_offset_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u8.c | 1 - .../arm/mve/intrinsics/vuninitializedq_float.c | 1 - .../arm/mve/intrinsics/vuninitializedq_float1.c | 1 - .../arm/mve/intrinsics/vuninitializedq_int.c | 1 - .../arm/mve/intrinsics/vuninitializedq_int1.c | 1 - gcc/testsuite/gcc.target/arm/mve/mve.exp | 2 + gcc/testsuite/gfortran.dg/pr93365.f90 | 15 + gcc/testsuite/gfortran.dg/pr93600_1.f90 | 9 + gcc/testsuite/gfortran.dg/pr93600_2.f90 | 10 + gcc/testsuite/jit.dg/all-non-failing-tests.h | 10 + gcc/testsuite/jit.dg/test-long-string-literal.c | 54 + gcc/testsuite/lib/target-supports.exp | 12 +- gcc/tree-ssa-forwprop.c | 1 + gcc/tree-vect-slp.c | 54 +- libgomp/ChangeLog | 6 + libgomp/target.c | 5 +- 2443 files changed, 4334 insertions(+), 2632 deletions(-) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => asrl.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => lsll.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u16.c => sqrshr.c} (51%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => sqshl.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => sqshll.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => srshr.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => srshrl.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u32.c => uqrshl.c} (51%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat64.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => uqshl.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => uqshll.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => urshr.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => urshrl.c} (53%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s16.c => vshlcq_m_s16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_x_s32.c => vshlcq_m_s32.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s8.c => vshlcq_m_s8.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_x_u16.c => vshlcq_m_u16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdwdupq_x_n_u16.c => vshlcq_m_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_x_u8.c => vshlcq_m_u8.c} (51%) create mode 100644 gcc/testsuite/gfortran.dg/pr93365.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_2.f90 create mode 100644 gcc/testsuite/jit.dg/test-long-string-literal.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig updated (c15a8f173e -> 0636b24556)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig in repository toolchain/ci/binutils-gdb. from c15a8f173e XCOFF64 uninitialised read adds 2957d8d054 Automatic date update in version.in adds 5935fd1530 gdb/testsuite: Remove hard coded addresses from expected results adds 5e737279c6 i386msdos uninitialised read adds cf28cfef60 ECOFF archive uninitialised read adds fdde2fb60c Mention .tdata in comment in _bfd_elf_tls_setup() adds 0636b24556 Avoid trigger an assertion failure in the STABS parser by re [...] No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 16 ++++++++ bfd/ecoff.c | 35 +++++++++++----- bfd/elflink.c | 4 +- bfd/i386msdos.c | 14 ++++--- bfd/version.h | 2 +- binutils/ChangeLog | 21 ++++++++++ binutils/wrstabs.c | 56 +++++++++++++++++--------- gdb/testsuite/ChangeLog | 5 +++ gdb/testsuite/gdb.fortran/mixed-lang-stack.exp | 4 +- ld/ChangeLog | 7 ++++ ld/Makefile.am | 2 + ld/Makefile.in | 3 ++ ld/po/BLD-POTFILES.in | 1 + 13 files changed, 131 insertions(+), 39 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig updated (727ff09 -> 56c08af)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards 727ff09 0: update: binutils-gcc-linux: all new 56c08af 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (727ff09) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-st [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 50 +- 02-prepare_abe/console.log | 436 +- 03-build_abe-binutils/console.log | 11702 ++++----- 04-build_abe-stage1/console.log | 20251 +++++++-------- 05-build_linux/console.log | 6692 ++--- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 18 +- 07-check_regression/results.regressions | 2 +- 08-update_baseline/console.log | 8 +- 08-update_baseline/results.regressions | 2 +- console.log | 39159 +++++++++++++++--------------- jenkins/manifest.sh | 12 +- 12 files changed, 39204 insertions(+), 39130 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-defconfig updated (938de7cbb1c -> 46de8b3eb1a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-defconfig in repository toolchain/ci/gcc. from 938de7cbb1c Daily bump. adds a5ef37f868b Daily bump. adds 46de8b3eb1a Darwin: Fix i686 bootstrap when the assembler supports GOTO [...] No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 10 ++++++++++ gcc/DATESTAMP | 2 +- gcc/config/i386/darwin.h | 10 ++++++++++ gcc/config/i386/i386.h | 5 ++--- 4 files changed, 23 insertions(+), 4 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-defconfig updated (e42cff6 -> 667f9cf)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-defconfig in repository toolchain/ci/base-artifacts. discards e42cff6 0: update: binutils-gcc-linux: boot new 667f9cf 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (e42cff6) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 182 +- 02-prepare_abe/console.log | 170 +- 03-build_abe-binutils/console.log | 11146 +++++------ 04-build_abe-stage1/console.log | 18061 ++++++++--------- 05-build_linux/console.log | 714 +- 06-boot_linux/console.log | 472 +- 07-check_regression/console.log | 12 +- 07-check_regression/results.regressions | 3 +- 08-update_baseline/console.log | 18 +- 08-update_baseline/results.regressions | 2 +- console.log | 30847 +++++++++++++++--------------- jenkins/manifest.sh | 8 +- 12 files changed, 30850 insertions(+), 30785 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

Tcwg-commits March 2020