Tcwg-commits March 2020

tcwg-commits@lists.linaro.org

4 participants
11017 discussions

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allnoconfig updated (602e4b2 -> d031b15)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allnoconfig in repository toolchain/ci/base-artifacts. discards 602e4b2 0: update: binutils-gcc-linux: all new d031b15 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (602e4b2) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-ma [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 182 +- 02-prepare_abe/console.log | 420 +- 03-build_abe-binutils/console.log | 11616 +++++------ 04-build_abe-stage1/console.log | 20254 +++++++++--------- 05-build_linux/console.log | 660 +- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 12 +- 07-check_regression/results.regressions | 2 +- 08-update_baseline/console.log | 12 +- 08-update_baseline/results.regressions | 2 +- console.log | 33158 +++++++++++++++--------------- jenkins/manifest.sh | 16 +- 12 files changed, 33204 insertions(+), 33132 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allnoconfig updated (938de7cbb1c -> c7bc3b65623)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allnoconfig in repository toolchain/ci/gcc. from 938de7cbb1c Daily bump. adds a5ef37f868b Daily bump. adds 46de8b3eb1a Darwin: Fix i686 bootstrap when the assembler supports GOTO [...] adds 5c7bd28d1cb backport PR90763: PowerPC vec_xl_len should take const argument. adds c7bc3b65623 Remove wrongly committed file. No new revisions were added by this update. Summary of changes: a | 81 --------------------------- gcc/ChangeLog | 19 +++++++ gcc/DATESTAMP | 2 +- gcc/config/i386/darwin.h | 10 ++++ gcc/config/i386/i386.h | 5 +- gcc/config/rs6000/rs6000-c.c | 13 +++++ gcc/testsuite/ChangeLog | 8 +++ gcc/testsuite/gcc.target/powerpc/pr90763.c | 88 ++++++++++++++++++++++++++++++ 8 files changed, 141 insertions(+), 85 deletions(-) delete mode 100644 a create mode 100644 gcc/testsuite/gcc.target/powerpc/pr90763.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allnoconfig updated (b2e5ce7 -> 80b9a6d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allnoconfig in repository toolchain/ci/base-artifacts. discards b2e5ce7 0: update: binutils-gcc-linux: all new 80b9a6d 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (b2e5ce7) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 216 +- 02-prepare_abe/console.log | 420 +- 03-build_abe-binutils/console.log | 11322 ++++++------ 04-build_abe-stage1/console.log | 17014 +++++++++-------- 05-build_linux/console.log | 626 +- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 12 +- 07-check_regression/results.regressions | 2 +- 08-update_baseline/console.log | 18 +- 08-update_baseline/results.regressions | 2 +- console.log | 29808 +++++++++++++++--------------- jenkins/manifest.sh | 8 +- 12 files changed, 29719 insertions(+), 29731 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allmodconfig updated (85e10e4f0fa -> ca6c722561c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allmodconfig in repository toolchain/ci/gcc. from 85e10e4f0fa Darwin: Fix i686 bootstrap when the assembler supports GOTO [...] adds fbe60463bb8 d: Generate phony targets for content imported files (PR93038) adds 83aa5aa313a Daily bump. adds 6e00d8dcf32 Daily bump. adds b809f0b6580 Set proper DECL_ALIGN in offload_handle_link_vars (PR94233) adds 2fa4b1ffd6e Save ref->speculative_id before clone_reference. adds 263ee1260bc tree-optimization/94266 - aovid propagating addresses of TA [...] adds 7a2090b04e5 ipa/94245 - avoid folding when we want an ADDR_EXPR adds 26b3e568a60 [PR94044] Fix ICE with sizeof<argumentpack> adds a3586eeb884 AMDGCN offloading – use amdgcn-amdhsa adds ce6413087de lto/lto.c – used $ or . in generated linkptr name adds 4897bb0045d libgomp – fix declare target link handling (PR94251) adds b0d84ecc55f fortran: ICE in gfc_match_assignment PR93600 adds 4dcc4502f31 tree-optimization/94261 - avoid IL adjustments in SLP analysis adds 6debbff6ca3 arm: Add earlyclobber to MVE instructions that require it adds 962406639c0 testsuite, arm: Change tests to assemble adds 0cd55f9d3af libgccjit: handle long literals in playback::context::new_s [...] adds 1a5c27b1b43 [ARM][GCC][12x]: MVE ACLE intrinsics to set and get vector lane. adds 85244449104 [ARM][GCC][13x]: MVE ACLE scalar shift intrinsics. adds 88c9a831f3a [ARM][GCC][14x]: MVE ACLE whole vector left shift with carr [...] adds d326e9586b4 driver: Improve the generated help text for alias options adds 5db9e89323c c: Fix up cfun->function_end_locus on invalid function bodi [...] new ca6c722561c c++: Handle COMPOUND_EXPRs in get_narrower and warnings_for [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 199 ++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 6 + gcc/c-family/c-warn.c | 5 + gcc/c/ChangeLog | 8 + gcc/c/c-parser.c | 7 +- gcc/config/arm/arm-builtins.c | 20 + gcc/config/arm/arm_mve.h | 457 ++++ gcc/config/arm/arm_mve_builtins.def | 18 + gcc/config/arm/iterators.md | 3 + gcc/config/arm/mve.md | 397 +++- gcc/config/arm/neon.md | 21 +- gcc/config/arm/vec-common.md | 33 + gcc/cp/ChangeLog | 6 + gcc/cp/tree.c | 6 +- gcc/d/ChangeLog | 6 + gcc/d/d-lang.cc | 39 +- gcc/doc/install.texi | 16 +- gcc/fortran/ChangeLog | 17 + gcc/fortran/expr.c | 34 +- gcc/fortran/match.c | 8 + gcc/fortran/resolve.c | 2 +- gcc/ipa-prop.c | 2 +- gcc/jit/ChangeLog | 11 + gcc/jit/jit-playback.c | 16 +- gcc/jit/jit-playback.h | 1 - gcc/lto/ChangeLog | 11 + gcc/lto/lto.c | 12 +- gcc/opts.c | 29 +- gcc/symtab.c | 9 +- gcc/testsuite/ChangeLog | 2461 ++++++++++++++++++++ .../c-c++-common/ubsan/float-cast-overflow-1.c | 2 +- .../c-c++-common/ubsan/float-cast-overflow-2.c | 2 +- .../c-c++-common/ubsan/float-cast-overflow-4.c | 2 +- gcc/testsuite/g++.dg/ubsan/pr91993.C | 17 + gcc/testsuite/g++.dg/warn/Wconversion-pr91993.C | 17 + .../arm/mve/intrinsics/{vbicq_n_s16.c => asrl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => lsll.c} | 9 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 3 +- .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 3 +- .../arm/mve/intrinsics/mve_vector_float.c | 3 +- .../arm/mve/intrinsics/mve_vector_float1.c | 3 +- .../arm/mve/intrinsics/mve_vector_float2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 3 +- .../arm/mve/intrinsics/mve_vector_int1.c | 3 +- .../arm/mve/intrinsics/mve_vector_int2.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint1.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint2.c | 3 +- .../arm/mve/intrinsics/{vbicq_n_u16.c => sqrshr.c} | 9 +- .../gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c | 13 + .../gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c | 13 + .../arm/mve/intrinsics/{vdupq_n_s8.c => sqshl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => sqshll.c} | 9 +- .../arm/mve/intrinsics/{vdupq_n_s8.c => srshr.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => srshrl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_u32.c => uqrshl.c} | 9 +- .../gcc.target/arm/mve/intrinsics/uqrshll_sat48.c | 13 + .../gcc.target/arm/mve/intrinsics/uqrshll_sat64.c | 13 + .../arm/mve/intrinsics/{vdupq_n_s8.c => uqshl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => uqshll.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => urshr.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => urshrl.c} | 9 +- .../gcc.target/arm/mve/intrinsics/vabavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadcq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadcq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmlaq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmlaq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot180_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot180_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot180_m_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot180_m_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot270_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot270_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot270_m_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot270_m_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot90_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot90_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot90_m_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot90_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpcsq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vcmpcsq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_f16.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_f32.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpgeq_m_n_f16.c | 1 - .../arm/mve/intrinsics/vcmpgeq_m_n_f32.c | 1 - .../arm/mve/intrinsics/vcmpgeq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vcmpgeq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpgtq_m_n_f16.c | 1 - .../arm/mve/intrinsics/vcmpgtq_m_n_f32.c | 1 - .../arm/mve/intrinsics/vcmpgtq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vcmpgtq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c | 1 - .../arm/mve/intrinsics/vcmphiq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vcmphiq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpleq_m_n_f16.c | 1 - .../arm/mve/intrinsics/vcmpleq_m_n_f32.c | 1 - .../arm/mve/intrinsics/vcmpleq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vcmpleq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpltq_m_n_f16.c | 1 - .../arm/mve/intrinsics/vcmpltq_m_n_f32.c | 1 - .../arm/mve/intrinsics/vcmpltq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vcmpltq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpneq_m_n_f16.c | 1 - .../arm/mve/intrinsics/vcmpneq_m_n_f32.c | 1 - .../arm/mve/intrinsics/vcmpneq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vcmpneq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vcmpneq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vcmpneq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmulq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmulq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot180_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot180_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot180_m_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot180_m_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot180_x_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot180_x_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot270_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot270_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot270_m_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot270_m_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot270_x_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot270_x_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot90_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot90_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot90_m_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot90_m_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot90_x_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot90_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_s64.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_u64.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp16q.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp16q_m.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp32q.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp32q_m.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp64q.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp64q_m.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp8q.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp8q_m.c | 1 - .../arm/mve/intrinsics/vcvtaq_m_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtaq_m_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtaq_m_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtaq_m_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtaq_x_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtaq_x_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtaq_x_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtaq_x_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c | 1 - .../arm/mve/intrinsics/vcvtbq_m_f16_f32.c | 1 - .../arm/mve/intrinsics/vcvtbq_m_f32_f16.c | 1 - .../arm/mve/intrinsics/vcvtbq_x_f32_f16.c | 1 - .../arm/mve/intrinsics/vcvtmq_m_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtmq_m_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtmq_m_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtmq_m_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtmq_x_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtmq_x_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtmq_x_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtmq_x_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtnq_m_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtnq_m_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtnq_m_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtnq_m_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtnq_x_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtnq_x_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtnq_x_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtnq_x_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtpq_m_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtpq_m_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtpq_m_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtpq_m_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtpq_x_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtpq_x_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtpq_x_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtpq_x_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_f16_s16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_f16_u16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_f32_s32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_f16_s16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_f16_u16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_f32_s32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_n_f16_s16.c | 1 - .../arm/mve/intrinsics/vcvtq_n_f16_u16.c | 1 - .../arm/mve/intrinsics/vcvtq_n_f32_s32.c | 1 - .../arm/mve/intrinsics/vcvtq_n_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_n_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_n_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_n_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_n_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_f16_s16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_f16_u16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_f32_s32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_f16_s16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_f16_u16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_f32_s32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c | 1 - .../arm/mve/intrinsics/vcvttq_m_f16_f32.c | 1 - .../arm/mve/intrinsics/vcvttq_m_f32_f16.c | 1 - .../arm/mve/intrinsics/vcvttq_x_f32_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c | 1 - .../arm/mve/intrinsics/vddupq_m_wb_u16.c | 1 - .../arm/mve/intrinsics/vddupq_m_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vddupq_x_wb_u16.c | 1 - .../arm/mve/intrinsics/vddupq_x_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vdwdupq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vdwdupq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c | 1 - .../arm/mve/intrinsics/vdwdupq_m_wb_u16.c | 1 - .../arm/mve/intrinsics/vdwdupq_m_wb_u32.c | 1 - .../arm/mve/intrinsics/vdwdupq_m_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c | 1 - .../arm/mve/intrinsics/vdwdupq_x_n_u16.c | 1 - .../arm/mve/intrinsics/vdwdupq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vdwdupq_x_wb_u16.c | 1 - .../arm/mve/intrinsics/vdwdupq_x_wb_u32.c | 1 - .../arm/mve/intrinsics/vdwdupq_x_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmsq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmsq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_m_s16.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_m_s32.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_m_s8.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_s16.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_s32.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_s8.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_x_s16.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_x_s32.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_x_s8.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_m_s16.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_m_s32.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_m_s8.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_s16.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_s32.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_s8.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_x_s16.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_x_s32.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c | 1 - .../arm/mve/intrinsics/vidupq_m_wb_u16.c | 1 - .../arm/mve/intrinsics/vidupq_m_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vidupq_x_wb_u16.c | 1 - .../arm/mve/intrinsics/vidupq_x_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c | 1 - .../arm/mve/intrinsics/viwdupq_m_n_u16.c | 1 - .../arm/mve/intrinsics/viwdupq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c | 1 - .../arm/mve/intrinsics/viwdupq_m_wb_u16.c | 1 - .../arm/mve/intrinsics/viwdupq_m_wb_u32.c | 1 - .../arm/mve/intrinsics/viwdupq_m_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c | 1 - .../arm/mve/intrinsics/viwdupq_x_n_u16.c | 1 - .../arm/mve/intrinsics/viwdupq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c | 1 - .../arm/mve/intrinsics/viwdupq_x_wb_u16.c | 1 - .../arm/mve/intrinsics/viwdupq_x_wb_u32.c | 1 - .../arm/mve/intrinsics/viwdupq_x_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_u8.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_s16.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_s32.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_s8.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_u16.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_u32.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_u8.c | 1 - .../mve/intrinsics/vldrbq_gather_offset_z_s16.c | 1 - .../mve/intrinsics/vldrbq_gather_offset_z_s32.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c | 1 - .../mve/intrinsics/vldrbq_gather_offset_z_u16.c | 1 - .../mve/intrinsics/vldrbq_gather_offset_z_u32.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_base_s64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_base_u64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c | 1 - .../mve/intrinsics/vldrdq_gather_base_wb_z_s64.c | 1 - .../mve/intrinsics/vldrdq_gather_base_wb_z_u64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_base_z_s64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_base_z_u64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_offset_s64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_offset_u64.c | 1 - .../mve/intrinsics/vldrdq_gather_offset_z_s64.c | 1 - .../mve/intrinsics/vldrdq_gather_offset_z_u64.c | 1 - .../intrinsics/vldrdq_gather_shifted_offset_s64.c | 1 - .../intrinsics/vldrdq_gather_shifted_offset_u64.c | 1 - .../vldrdq_gather_shifted_offset_z_s64.c | 1 - .../vldrdq_gather_shifted_offset_z_u64.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_f16.c | 1 - .../arm/mve/intrinsics/vldrhq_gather_offset_f16.c | 1 - .../arm/mve/intrinsics/vldrhq_gather_offset_s16.c | 1 - .../arm/mve/intrinsics/vldrhq_gather_offset_s32.c | 1 - .../arm/mve/intrinsics/vldrhq_gather_offset_u16.c | 1 - .../arm/mve/intrinsics/vldrhq_gather_offset_u32.c | 1 - .../mve/intrinsics/vldrhq_gather_offset_z_f16.c | 1 - .../mve/intrinsics/vldrhq_gather_offset_z_s16.c | 1 - .../mve/intrinsics/vldrhq_gather_offset_z_s32.c | 1 - .../mve/intrinsics/vldrhq_gather_offset_z_u16.c | 1 - .../mve/intrinsics/vldrhq_gather_offset_z_u32.c | 1 - .../intrinsics/vldrhq_gather_shifted_offset_f16.c | 1 - .../intrinsics/vldrhq_gather_shifted_offset_s16.c | 1 - .../intrinsics/vldrhq_gather_shifted_offset_s32.c | 1 - .../intrinsics/vldrhq_gather_shifted_offset_u16.c | 1 - .../intrinsics/vldrhq_gather_shifted_offset_u32.c | 1 - .../vldrhq_gather_shifted_offset_z_f16.c | 1 - .../vldrhq_gather_shifted_offset_z_s16.c | 1 - .../vldrhq_gather_shifted_offset_z_s32.c | 1 - .../vldrhq_gather_shifted_offset_z_u16.c | 1 - .../vldrhq_gather_shifted_offset_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrwq_f32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_f32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_s32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_u32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c | 1 - .../mve/intrinsics/vldrwq_gather_base_wb_z_f32.c | 1 - .../mve/intrinsics/vldrwq_gather_base_wb_z_s32.c | 1 - .../mve/intrinsics/vldrwq_gather_base_wb_z_u32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_z_f32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_z_s32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_z_u32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_offset_f32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_offset_s32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_offset_u32.c | 1 - .../mve/intrinsics/vldrwq_gather_offset_z_f32.c | 1 - .../mve/intrinsics/vldrwq_gather_offset_z_s32.c | 1 - .../mve/intrinsics/vldrwq_gather_offset_z_u32.c | 1 - .../intrinsics/vldrwq_gather_shifted_offset_f32.c | 1 - .../intrinsics/vldrwq_gather_shifted_offset_s32.c | 1 - .../intrinsics/vldrwq_gather_shifted_offset_u32.c | 1 - .../vldrwq_gather_shifted_offset_z_f32.c | 1 - .../vldrwq_gather_shifted_offset_z_s32.c | 1 - .../vldrwq_gather_shifted_offset_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrwq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrwq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxaq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxavq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c | 1 - .../arm/mve/intrinsics/vmaxnmavq_p_f16.c | 1 - .../arm/mve/intrinsics/vmaxnmavq_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminaq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminaq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminaq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminaq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminavq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmaq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmaq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmavq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmavq_f32.c | 1 - .../arm/mve/intrinsics/vminnmavq_p_f16.c | 1 - .../arm/mve/intrinsics/vminnmavq_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmvq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmvq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_u8.c | 1 - .../arm/mve/intrinsics/vmladavaq_p_s16.c | 1 - .../arm/mve/intrinsics/vmladavaq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c | 1 - .../arm/mve/intrinsics/vmladavaq_p_u16.c | 1 - .../arm/mve/intrinsics/vmladavaq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_u8.c | 1 - .../arm/mve/intrinsics/vmladavaxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmladavaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vmladavaxq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_u8.c | 1 - .../arm/mve/intrinsics/vmladavxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmladavxq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavxq_s8.c | 1 - .../arm/mve/intrinsics/vmlaldavaq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlaldavaq_p_s32.c | 1 - .../arm/mve/intrinsics/vmlaldavaq_p_u16.c | 1 - .../arm/mve/intrinsics/vmlaldavaq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c | 1 - .../arm/mve/intrinsics/vmlaldavaxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlaldavaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vmlaldavaxq_p_u16.c | 1 - .../arm/mve/intrinsics/vmlaldavaxq_p_u32.c | 1 - .../arm/mve/intrinsics/vmlaldavaxq_s16.c | 1 - .../arm/mve/intrinsics/vmlaldavaxq_s32.c | 1 - .../arm/mve/intrinsics/vmlaldavq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlaldavq_p_s32.c | 1 - .../arm/mve/intrinsics/vmlaldavq_p_u16.c | 1 - .../arm/mve/intrinsics/vmlaldavq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c | 1 - .../arm/mve/intrinsics/vmlaldavxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlaldavxq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c | 1 - .../arm/mve/intrinsics/vmlsdavaq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsdavaq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c | 1 - .../arm/mve/intrinsics/vmlsdavaxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsdavaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vmlsdavaxq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c | 1 - .../arm/mve/intrinsics/vmlsdavxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsdavxq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c | 1 - .../arm/mve/intrinsics/vmlsldavaq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsldavaq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c | 1 - .../arm/mve/intrinsics/vmlsldavaxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsldavaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vmlsldavaxq_s16.c | 1 - .../arm/mve/intrinsics/vmlsldavaxq_s32.c | 1 - .../arm/mve/intrinsics/vmlsldavq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsldavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c | 1 - .../arm/mve/intrinsics/vmlsldavxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsldavxq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c | 1 - .../arm/mve/intrinsics/vmullbq_int_m_s16.c | 1 - .../arm/mve/intrinsics/vmullbq_int_m_s32.c | 1 - .../arm/mve/intrinsics/vmullbq_int_m_s8.c | 1 - .../arm/mve/intrinsics/vmullbq_int_m_u16.c | 1 - .../arm/mve/intrinsics/vmullbq_int_m_u32.c | 1 - .../arm/mve/intrinsics/vmullbq_int_m_u8.c | 1 - .../arm/mve/intrinsics/vmullbq_int_s16.c | 1 - .../arm/mve/intrinsics/vmullbq_int_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c | 1 - .../arm/mve/intrinsics/vmullbq_int_u16.c | 1 - .../arm/mve/intrinsics/vmullbq_int_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c | 1 - .../arm/mve/intrinsics/vmullbq_int_x_s16.c | 1 - .../arm/mve/intrinsics/vmullbq_int_x_s32.c | 1 - .../arm/mve/intrinsics/vmullbq_int_x_s8.c | 1 - .../arm/mve/intrinsics/vmullbq_int_x_u16.c | 1 - .../arm/mve/intrinsics/vmullbq_int_x_u32.c | 1 - .../arm/mve/intrinsics/vmullbq_int_x_u8.c | 1 - .../arm/mve/intrinsics/vmullbq_poly_m_p16.c | 1 - .../arm/mve/intrinsics/vmullbq_poly_m_p8.c | 1 - .../arm/mve/intrinsics/vmullbq_poly_p16.c | 1 - .../arm/mve/intrinsics/vmullbq_poly_p8.c | 1 - .../arm/mve/intrinsics/vmullbq_poly_x_p16.c | 1 - .../arm/mve/intrinsics/vmullbq_poly_x_p8.c | 1 - .../arm/mve/intrinsics/vmulltq_int_m_s16.c | 1 - .../arm/mve/intrinsics/vmulltq_int_m_s32.c | 1 - .../arm/mve/intrinsics/vmulltq_int_m_s8.c | 1 - .../arm/mve/intrinsics/vmulltq_int_m_u16.c | 1 - .../arm/mve/intrinsics/vmulltq_int_m_u32.c | 1 - .../arm/mve/intrinsics/vmulltq_int_m_u8.c | 1 - .../arm/mve/intrinsics/vmulltq_int_s16.c | 1 - .../arm/mve/intrinsics/vmulltq_int_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c | 1 - .../arm/mve/intrinsics/vmulltq_int_u16.c | 1 - .../arm/mve/intrinsics/vmulltq_int_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c | 1 - .../arm/mve/intrinsics/vmulltq_int_x_s16.c | 1 - .../arm/mve/intrinsics/vmulltq_int_x_s32.c | 1 - .../arm/mve/intrinsics/vmulltq_int_x_s8.c | 1 - .../arm/mve/intrinsics/vmulltq_int_x_u16.c | 1 - .../arm/mve/intrinsics/vmulltq_int_x_u32.c | 1 - .../arm/mve/intrinsics/vmulltq_int_x_u8.c | 1 - .../arm/mve/intrinsics/vmulltq_poly_m_p16.c | 1 - .../arm/mve/intrinsics/vmulltq_poly_m_p8.c | 1 - .../arm/mve/intrinsics/vmulltq_poly_p16.c | 1 - .../arm/mve/intrinsics/vmulltq_poly_p8.c | 1 - .../arm/mve/intrinsics/vmulltq_poly_x_p16.c | 1 - .../arm/mve/intrinsics/vmulltq_poly_x_p8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vpnot.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_s64.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_u64.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqabsq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqabsq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqabsq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_u8.c | 1 - .../arm/mve/intrinsics/vqdmladhq_m_s16.c | 1 - .../arm/mve/intrinsics/vqdmladhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c | 1 - .../arm/mve/intrinsics/vqdmladhxq_m_s16.c | 1 - .../arm/mve/intrinsics/vqdmladhxq_m_s32.c | 1 - .../arm/mve/intrinsics/vqdmladhxq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c | 1 - .../arm/mve/intrinsics/vqdmlahq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqdmlahq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqdmlahq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c | 1 - .../arm/mve/intrinsics/vqdmlsdhq_m_s16.c | 1 - .../arm/mve/intrinsics/vqdmlsdhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c | 1 - .../arm/mve/intrinsics/vqdmlsdhxq_m_s16.c | 1 - .../arm/mve/intrinsics/vqdmlsdhxq_m_s32.c | 1 - .../arm/mve/intrinsics/vqdmlsdhxq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c | 1 - .../arm/mve/intrinsics/vqdmulhq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqdmulhq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqdmulhq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c | 1 - .../arm/mve/intrinsics/vqdmullbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqdmullbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqdmullbq_m_s16.c | 1 - .../arm/mve/intrinsics/vqdmullbq_m_s32.c | 1 - .../arm/mve/intrinsics/vqdmullbq_n_s16.c | 1 - .../arm/mve/intrinsics/vqdmullbq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c | 1 - .../arm/mve/intrinsics/vqdmulltq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqdmulltq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqdmulltq_m_s16.c | 1 - .../arm/mve/intrinsics/vqdmulltq_m_s32.c | 1 - .../arm/mve/intrinsics/vqdmulltq_n_s16.c | 1 - .../arm/mve/intrinsics/vqdmulltq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_u32.c | 1 - .../arm/mve/intrinsics/vqmovunbq_m_s16.c | 1 - .../arm/mve/intrinsics/vqmovunbq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c | 1 - .../arm/mve/intrinsics/vqmovuntq_m_s16.c | 1 - .../arm/mve/intrinsics/vqmovuntq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqnegq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqnegq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqnegq_s8.c | 1 - .../arm/mve/intrinsics/vqrdmladhq_m_s16.c | 1 - .../arm/mve/intrinsics/vqrdmladhq_m_s32.c | 1 - .../arm/mve/intrinsics/vqrdmladhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c | 1 - .../arm/mve/intrinsics/vqrdmladhxq_m_s16.c | 1 - .../arm/mve/intrinsics/vqrdmladhxq_m_s32.c | 1 - .../arm/mve/intrinsics/vqrdmladhxq_m_s8.c | 1 - .../arm/mve/intrinsics/vqrdmladhxq_s16.c | 1 - .../arm/mve/intrinsics/vqrdmladhxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_n_u16.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_n_s32.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_n_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_n_u16.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_n_u32.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_n_u8.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhq_m_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhq_m_s32.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhxq_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_m_s16.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c | 1 - .../arm/mve/intrinsics/vqrshlq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vqrshlq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vqrshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_u8.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_m_n_u32.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_n_u16.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_n_u32.c | 1 - .../arm/mve/intrinsics/vqrshrntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshrntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshrntq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vqrshrntq_m_n_u32.c | 1 - .../arm/mve/intrinsics/vqrshrntq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshrntq_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshrntq_n_u16.c | 1 - .../arm/mve/intrinsics/vqrshrntq_n_u32.c | 1 - .../arm/mve/intrinsics/vqrshrunbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshrunbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshrunbq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshrunbq_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshruntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshruntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshruntq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshruntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_u8.c | 1 - .../arm/mve/intrinsics/vqshluq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqshluq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c | 1 - .../arm/mve/intrinsics/vqshrnbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqshrnbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqshrnbq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vqshrnbq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c | 1 - .../arm/mve/intrinsics/vqshrntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqshrntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqshrntq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vqshrntq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c | 1 - .../arm/mve/intrinsics/vqshrunbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqshrunbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqshrunbq_n_s16.c | 1 - .../arm/mve/intrinsics/vqshrunbq_n_s32.c | 1 - .../arm/mve/intrinsics/vqshruntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqshruntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqshruntq_n_s16.c | 1 - .../arm/mve/intrinsics/vqshruntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_u8.c | 1 - .../arm/mve/intrinsics/vreinterpretq_f16.c | 1 - .../arm/mve/intrinsics/vreinterpretq_f32.c | 1 - .../arm/mve/intrinsics/vreinterpretq_s16.c | 1 - .../arm/mve/intrinsics/vreinterpretq_s32.c | 1 - .../arm/mve/intrinsics/vreinterpretq_s64.c | 1 - .../arm/mve/intrinsics/vreinterpretq_s8.c | 1 - .../arm/mve/intrinsics/vreinterpretq_u16.c | 1 - .../arm/mve/intrinsics/vreinterpretq_u32.c | 1 - .../arm/mve/intrinsics/vreinterpretq_u64.c | 1 - .../arm/mve/intrinsics/vreinterpretq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev16q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev16q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c | 1 - .../arm/mve/intrinsics/vrmlaldavhaq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhaq_p_u32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhaq_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhaq_u32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhaxq_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhq_p_u32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhq_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhq_u32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhxq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhxq_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhaq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhaq_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhaxq_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhq_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhxq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c | 15 + .../intrinsics/{vabsq_m_s16.c => vshlcq_m_s16.c} | 12 +- .../intrinsics/{vabdq_x_s32.c => vshlcq_m_s32.c} | 12 +- .../mve/intrinsics/{vabsq_m_s8.c => vshlcq_m_s8.c} | 12 +- .../intrinsics/{vbicq_x_u16.c => vshlcq_m_u16.c} | 12 +- .../{vdwdupq_x_n_u16.c => vshlcq_m_u32.c} | 17 +- .../mve/intrinsics/{vabdq_x_u8.c => vshlcq_m_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vshlcq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u8.c | 1 - .../arm/mve/intrinsics/vshllbq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vshllbq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c | 1 - .../arm/mve/intrinsics/vshllbq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c | 1 - .../arm/mve/intrinsics/vshllbq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vshlltq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vshlltq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c | 1 - .../arm/mve/intrinsics/vshlltq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c | 1 - .../arm/mve/intrinsics/vshlltq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_u8.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_s8.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s16.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s32.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s8.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u16.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u32.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u8.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s16.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s32.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s8.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u16.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u32.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u8.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_u64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_s64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_u64.c | 1 - .../mve/intrinsics/vstrdq_scatter_offset_p_s64.c | 1 - .../mve/intrinsics/vstrdq_scatter_offset_p_u64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_offset_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_offset_u64.c | 1 - .../vstrdq_scatter_shifted_offset_p_s64.c | 1 - .../vstrdq_scatter_shifted_offset_p_u64.c | 1 - .../intrinsics/vstrdq_scatter_shifted_offset_s64.c | 1 - .../intrinsics/vstrdq_scatter_shifted_offset_u64.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_s32.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_f16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_f16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_s16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_s32.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_u16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_u32.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_s16.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_s32.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_u16.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_u32.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_f16.c | 1 - .../vstrhq_scatter_shifted_offset_p_f16.c | 1 - .../vstrhq_scatter_shifted_offset_p_s16.c | 1 - .../vstrhq_scatter_shifted_offset_p_s32.c | 1 - .../vstrhq_scatter_shifted_offset_p_u16.c | 1 - .../vstrhq_scatter_shifted_offset_p_u32.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_s16.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_s32.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_u16.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_f32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_u32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_s32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_u32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_offset_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_offset_p_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_offset_p_s32.c | 1 - .../mve/intrinsics/vstrwq_scatter_offset_p_u32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_offset_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_offset_u32.c | 1 - .../intrinsics/vstrwq_scatter_shifted_offset_f32.c | 1 - .../vstrwq_scatter_shifted_offset_p_f32.c | 1 - .../vstrwq_scatter_shifted_offset_p_s32.c | 1 - .../vstrwq_scatter_shifted_offset_p_u32.c | 1 - .../intrinsics/vstrwq_scatter_shifted_offset_s32.c | 1 - .../intrinsics/vstrwq_scatter_shifted_offset_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u8.c | 1 - .../arm/mve/intrinsics/vuninitializedq_float.c | 1 - .../arm/mve/intrinsics/vuninitializedq_float1.c | 1 - .../arm/mve/intrinsics/vuninitializedq_int.c | 1 - .../arm/mve/intrinsics/vuninitializedq_int1.c | 1 - gcc/testsuite/gcc.target/arm/mve/mve.exp | 2 + gcc/testsuite/gdc.dg/pr93038b.d | 8 + gcc/testsuite/gfortran.dg/pr93365.f90 | 15 + gcc/testsuite/gfortran.dg/pr93600_1.f90 | 9 + gcc/testsuite/gfortran.dg/pr93600_2.f90 | 10 + gcc/testsuite/jit.dg/all-non-failing-tests.h | 10 + gcc/testsuite/jit.dg/test-long-string-literal.c | 54 + gcc/testsuite/lib/target-supports.exp | 12 +- gcc/tree-ssa-forwprop.c | 1 + gcc/tree-vect-slp.c | 54 +- gcc/tree.c | 15 + libgomp/ChangeLog | 6 + libgomp/target.c | 5 +- 2454 files changed, 4451 insertions(+), 2656 deletions(-) create mode 100644 gcc/testsuite/g++.dg/ubsan/pr91993.C create mode 100644 gcc/testsuite/g++.dg/warn/Wconversion-pr91993.C copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => asrl.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => lsll.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u16.c => sqrshr.c} (51%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => sqshl.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => sqshll.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => srshr.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => srshrl.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u32.c => uqrshl.c} (51%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat64.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => uqshl.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => uqshll.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => urshr.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => urshrl.c} (53%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s16.c => vshlcq_m_s16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_x_s32.c => vshlcq_m_s32.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s8.c => vshlcq_m_s8.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_x_u16.c => vshlcq_m_u16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdwdupq_x_n_u16.c => vshlcq_m_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_x_u8.c => vshlcq_m_u8.c} (51%) create mode 100644 gcc/testsuite/gdc.dg/pr93038b.d create mode 100644 gcc/testsuite/gfortran.dg/pr93365.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_2.f90 create mode 100644 gcc/testsuite/jit.dg/test-long-string-literal.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allmodconfig updated (2957d8d054 -> 0636b24556)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allmodconfig in repository toolchain/ci/binutils-gdb. from 2957d8d054 Automatic date update in version.in adds 5935fd1530 gdb/testsuite: Remove hard coded addresses from expected results adds 5e737279c6 i386msdos uninitialised read adds cf28cfef60 ECOFF archive uninitialised read adds fdde2fb60c Mention .tdata in comment in _bfd_elf_tls_setup() adds 0636b24556 Avoid trigger an assertion failure in the STABS parser by re [...] No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 16 ++++++++ bfd/ecoff.c | 35 +++++++++++----- bfd/elflink.c | 4 +- bfd/i386msdos.c | 14 ++++--- binutils/ChangeLog | 21 ++++++++++ binutils/wrstabs.c | 56 +++++++++++++++++--------- gdb/testsuite/ChangeLog | 5 +++ gdb/testsuite/gdb.fortran/mixed-lang-stack.exp | 4 +- ld/ChangeLog | 7 ++++ ld/Makefile.am | 2 + ld/Makefile.in | 3 ++ ld/po/BLD-POTFILES.in | 1 + 12 files changed, 130 insertions(+), 38 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allmodconfig updated (11fa905 -> db71106)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allmodconfig in repository toolchain/ci/base-artifacts. discards 11fa905 0: update: binutils-2957d8d05405c53b0d377e578fe1b770af732254: boot new db71106 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (11fa905) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 70 +- 02-prepare_abe/console.log | 338 +- 03-build_abe-binutils/console.log | 11645 +++++----- 04-build_abe-stage1/console.log | 15588 ++++++------- 05-build_linux/console.log | 8062 +++---- 06-boot_linux/console.log | 4 +- 07-check_regression/console.log | 18 +- 07-check_regression/results.regressions | 3 +- 08-update_baseline/console.log | 12 +- 08-update_baseline/results.regressions | 3 +- console.log | 35737 +++++++++++++++--------------- jenkins/manifest.sh | 14 +- 12 files changed, 36078 insertions(+), 35416 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allyesconfig updated (938de7cbb1c -> c7bc3b65623)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allyesconfig in repository toolchain/ci/gcc. from 938de7cbb1c Daily bump. adds a5ef37f868b Daily bump. adds 46de8b3eb1a Darwin: Fix i686 bootstrap when the assembler supports GOTO [...] new 5c7bd28d1cb backport PR90763: PowerPC vec_xl_len should take const argument. new c7bc3b65623 Remove wrongly committed file. The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: a | 81 --------------------------- gcc/ChangeLog | 19 +++++++ gcc/DATESTAMP | 2 +- gcc/config/i386/darwin.h | 10 ++++ gcc/config/i386/i386.h | 5 +- gcc/config/rs6000/rs6000-c.c | 13 +++++ gcc/testsuite/ChangeLog | 8 +++ gcc/testsuite/gcc.target/powerpc/pr90763.c | 88 ++++++++++++++++++++++++++++++ 8 files changed, 141 insertions(+), 85 deletions(-) delete mode 100644 a create mode 100644 gcc/testsuite/gcc.target/powerpc/pr90763.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allyesconfig updated (d4e63ef -> b1524e6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards d4e63ef 0: update: binutils-gcc-linux: all new b1524e6 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (d4e63ef) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 160 +- 02-prepare_abe/console.log | 408 +- 03-build_abe-binutils/console.log | 11644 ++++++------- 04-build_abe-stage1/console.log | 13720 ++++++++-------- 05-build_linux/console.log | 822 +- 06-boot_linux/console.log | 8 +- 07-check_regression/console.log | 2 +- 07-check_regression/results.regressions | 2 +- 08-update_baseline/console.log | 2 +- 08-update_baseline/results.regressions | 3 +- console.log | 26114 +++++++++++++++--------------- jenkins/manifest.sh | 8 +- 12 files changed, 26442 insertions(+), 26451 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[glibc] branch master updated (b8de7980c0 -> 0334369949)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository glibc. from b8de7980c0 Extended Char Intro: Use getwc in example (Bug 25626) new 0334369949 y2038: fix: Add missing libc_hidden_def attribute for some s [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: sysdeps/unix/sysv/linux/clock_getres.c | 2 ++ sysdeps/unix/sysv/linux/clock_gettime.c | 2 ++ sysdeps/unix/sysv/linux/clock_nanosleep.c | 2 ++ sysdeps/unix/sysv/linux/clock_settime.c | 2 ++ sysdeps/unix/sysv/linux/ppoll.c | 2 ++ 5 files changed, 10 insertions(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-bootstrap_O3 updated (b599bf9d6d1 -> 4dcc4502f31)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-bootstrap_O3 in repository toolchain/ci/gcc. from b599bf9d6d1 c++: Reject changing active member of union during initiali [...] adds 98eb7b2ed24 d: Fix ICE in add_symbol_to_partition_1, at lto/lto-partiti [...] adds 837cece888f Darwin: Address translation comments (PR93694). adds dfb25dfe3d3 Darwin: Handle NULL DECL_SIZE_TYPE in machopic_select_secti [...] adds 9fc985118d9 libstdc++: Fix path::generic_string allocator handling (PR 94242) adds a577c0c2693 libstdc++: Fix experimental::path::generic_string (PR 93245) adds 424e39081f9 d: Fix typo in ChangeLog for last change adds 4a01f7b1e73 d: Fix missing dependencies in depfile for imported files ( [...] adds 88d7d0ce8fa testsuite: Fix lambda-vis.C for targets with user label pre [...] adds 85e10e4f0fa Darwin: Fix i686 bootstrap when the assembler supports GOTO [...] adds fbe60463bb8 d: Generate phony targets for content imported files (PR93038) adds 83aa5aa313a Daily bump. adds 6e00d8dcf32 Daily bump. adds b809f0b6580 Set proper DECL_ALIGN in offload_handle_link_vars (PR94233) adds 2fa4b1ffd6e Save ref->speculative_id before clone_reference. adds 263ee1260bc tree-optimization/94266 - aovid propagating addresses of TA [...] adds 7a2090b04e5 ipa/94245 - avoid folding when we want an ADDR_EXPR adds 26b3e568a60 [PR94044] Fix ICE with sizeof<argumentpack> adds a3586eeb884 AMDGCN offloading – use amdgcn-amdhsa adds ce6413087de lto/lto.c – used $ or . in generated linkptr name adds 4897bb0045d libgomp – fix declare target link handling (PR94251) adds b0d84ecc55f fortran: ICE in gfc_match_assignment PR93600 adds 4dcc4502f31 tree-optimization/94261 - avoid IL adjustments in SLP analysis No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 55 +++++++++++++ gcc/DATESTAMP | 2 +- gcc/config/darwin.c | 29 ++++--- gcc/config/darwin.opt | 96 +++++++++++----------- gcc/config/i386/darwin.h | 10 +++ gcc/config/i386/i386.h | 5 +- gcc/cp/ChangeLog | 6 ++ gcc/cp/tree.c | 6 +- gcc/d/ChangeLog | 24 ++++++ gcc/d/d-lang.cc | 81 ++++++++++-------- gcc/d/typeinfo.cc | 47 ++++++----- gcc/doc/install.texi | 16 ++-- gcc/fortran/ChangeLog | 17 ++++ gcc/fortran/expr.c | 34 ++++++-- gcc/fortran/match.c | 8 ++ gcc/fortran/resolve.c | 2 +- gcc/ipa-prop.c | 2 +- gcc/lto/ChangeLog | 11 +++ gcc/lto/lto.c | 12 +-- gcc/symtab.c | 9 +- gcc/testsuite/ChangeLog | 29 +++++++ gcc/testsuite/g++.dg/abi/lambda-vis.C | 12 +-- gcc/testsuite/gdc.dg/fileimports/pr93038.txt | 1 + gcc/testsuite/gdc.dg/pr93038.d | 8 ++ gcc/testsuite/gdc.dg/pr93038b.d | 8 ++ gcc/testsuite/gfortran.dg/pr93365.f90 | 15 ++++ gcc/testsuite/gfortran.dg/pr93600_1.f90 | 9 ++ gcc/testsuite/gfortran.dg/pr93600_2.f90 | 10 +++ gcc/testsuite/lib/target-supports.exp | 2 +- gcc/tree-ssa-forwprop.c | 1 + gcc/tree-vect-slp.c | 54 ++---------- libgomp/ChangeLog | 6 ++ libgomp/target.c | 5 +- libstdc++-v3/ChangeLog | 17 ++++ libstdc++-v3/include/bits/fs_path.h | 11 ++- libstdc++-v3/include/experimental/bits/fs_path.h | 40 +++++++-- .../filesystem/path/generic/94242.cc} | 41 ++++----- .../filesystem/path/generic/generic_string.cc | 32 ++++++++ .../filesystem/path/generic/generic_string.cc | 46 +++++++++-- 39 files changed, 575 insertions(+), 244 deletions(-) create mode 100644 gcc/testsuite/gdc.dg/fileimports/pr93038.txt create mode 100644 gcc/testsuite/gdc.dg/pr93038.d create mode 100644 gcc/testsuite/gdc.dg/pr93038b.d create mode 100644 gcc/testsuite/gfortran.dg/pr93365.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_2.f90 copy libstdc++-v3/testsuite/{experimental/filesystem/path/generic/generic_string.c [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

Tcwg-commits March 2020