Tcwg-commits March 2020

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[gcc] branch devel/c++-coroutines updated (455e55b4858 -> d77b7b294d6)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch devel/c++-coroutines in repository gcc. from 455e55b4858 Merge master r10-7316. adds 9fc985118d9 libstdc++: Fix path::generic_string allocator handling (PR 94242) adds a577c0c2693 libstdc++: Fix experimental::path::generic_string (PR 93245) adds 424e39081f9 d: Fix typo in ChangeLog for last change adds 4a01f7b1e73 d: Fix missing dependencies in depfile for imported files ( [...] adds 88d7d0ce8fa testsuite: Fix lambda-vis.C for targets with user label pre [...] adds 85e10e4f0fa Darwin: Fix i686 bootstrap when the assembler supports GOTO [...] adds fbe60463bb8 d: Generate phony targets for content imported files (PR93038) adds 83aa5aa313a Daily bump. adds 6e00d8dcf32 Daily bump. adds b809f0b6580 Set proper DECL_ALIGN in offload_handle_link_vars (PR94233) adds 2fa4b1ffd6e Save ref->speculative_id before clone_reference. adds 263ee1260bc tree-optimization/94266 - aovid propagating addresses of TA [...] adds 7a2090b04e5 ipa/94245 - avoid folding when we want an ADDR_EXPR adds 26b3e568a60 [PR94044] Fix ICE with sizeof<argumentpack> adds a3586eeb884 AMDGCN offloading – use amdgcn-amdhsa adds ce6413087de lto/lto.c – used $ or . in generated linkptr name adds 4897bb0045d libgomp – fix declare target link handling (PR94251) adds b0d84ecc55f fortran: ICE in gfc_match_assignment PR93600 adds 4dcc4502f31 tree-optimization/94261 - avoid IL adjustments in SLP analysis adds 6debbff6ca3 arm: Add earlyclobber to MVE instructions that require it adds 962406639c0 testsuite, arm: Change tests to assemble adds 0cd55f9d3af libgccjit: handle long literals in playback::context::new_s [...] adds 1a5c27b1b43 [ARM][GCC][12x]: MVE ACLE intrinsics to set and get vector lane. adds 85244449104 [ARM][GCC][13x]: MVE ACLE scalar shift intrinsics. adds 88c9a831f3a [ARM][GCC][14x]: MVE ACLE whole vector left shift with carr [...] adds d326e9586b4 driver: Improve the generated help text for alias options adds 5db9e89323c c: Fix up cfun->function_end_locus on invalid function bodi [...] adds ca6c722561c c++: Handle COMPOUND_EXPRs in get_narrower and warnings_for [...] new d77b7b294d6 Merge master r10-7344. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 206 ++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 6 + gcc/c-family/c-warn.c | 5 + gcc/c/ChangeLog | 8 + gcc/c/c-parser.c | 7 +- gcc/config/arm/arm-builtins.c | 20 + gcc/config/arm/arm_mve.h | 457 ++++ gcc/config/arm/arm_mve_builtins.def | 18 + gcc/config/arm/iterators.md | 3 + gcc/config/arm/mve.md | 397 +++- gcc/config/arm/neon.md | 21 +- gcc/config/arm/vec-common.md | 33 + gcc/config/i386/darwin.h | 10 + gcc/config/i386/i386.h | 5 +- gcc/cp/ChangeLog | 6 + gcc/cp/tree.c | 6 +- gcc/d/ChangeLog | 14 +- gcc/d/d-lang.cc | 81 +- gcc/doc/install.texi | 16 +- gcc/fortran/ChangeLog | 17 + gcc/fortran/expr.c | 34 +- gcc/fortran/match.c | 8 + gcc/fortran/resolve.c | 2 +- gcc/ipa-prop.c | 2 +- gcc/jit/ChangeLog | 11 + gcc/jit/jit-playback.c | 16 +- gcc/jit/jit-playback.h | 1 - gcc/lto/ChangeLog | 11 + gcc/lto/lto.c | 12 +- gcc/opts.c | 29 +- gcc/symtab.c | 9 +- gcc/testsuite/ChangeLog | 2472 ++++++++++++++++++++ .../c-c++-common/ubsan/float-cast-overflow-1.c | 2 +- .../c-c++-common/ubsan/float-cast-overflow-2.c | 2 +- .../c-c++-common/ubsan/float-cast-overflow-4.c | 2 +- gcc/testsuite/g++.dg/abi/lambda-vis.C | 12 +- gcc/testsuite/g++.dg/ubsan/pr91993.C | 17 + gcc/testsuite/g++.dg/warn/Wconversion-pr91993.C | 17 + .../arm/mve/intrinsics/{vbicq_n_s16.c => asrl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => lsll.c} | 9 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 3 +- .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 3 +- .../arm/mve/intrinsics/mve_vector_float.c | 3 +- .../arm/mve/intrinsics/mve_vector_float1.c | 3 +- .../arm/mve/intrinsics/mve_vector_float2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 3 +- .../arm/mve/intrinsics/mve_vector_int1.c | 3 +- .../arm/mve/intrinsics/mve_vector_int2.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint1.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint2.c | 3 +- .../arm/mve/intrinsics/{vbicq_n_u16.c => sqrshr.c} | 9 +- .../gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c | 13 + .../gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c | 13 + .../arm/mve/intrinsics/{vdupq_n_s8.c => sqshl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => sqshll.c} | 9 +- .../arm/mve/intrinsics/{vdupq_n_s8.c => srshr.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => srshrl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_u32.c => uqrshl.c} | 9 +- .../gcc.target/arm/mve/intrinsics/uqrshll_sat48.c | 13 + .../gcc.target/arm/mve/intrinsics/uqrshll_sat64.c | 13 + .../arm/mve/intrinsics/{vdupq_n_s8.c => uqshl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => uqshll.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => urshr.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => urshrl.c} | 9 +- .../gcc.target/arm/mve/intrinsics/vabavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_f32.c | 1 - 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| 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_u16.c | 1 - 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| 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 1 - 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| 1 - .../arm/mve/intrinsics/vcmpneq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_s32.c | 1 - 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.../arm/mve/intrinsics/vrmlsldavhaq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhaq_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhaxq_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhq_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhxq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c | 15 + .../intrinsics/{vabsq_m_s16.c => vshlcq_m_s16.c} | 12 +- .../intrinsics/{vabdq_x_s32.c => vshlcq_m_s32.c} | 12 +- .../mve/intrinsics/{vabsq_m_s8.c => vshlcq_m_s8.c} | 12 +- .../intrinsics/{vbicq_x_u16.c => vshlcq_m_u16.c} | 12 +- .../{vdwdupq_x_n_u16.c => vshlcq_m_u32.c} | 17 +- .../mve/intrinsics/{vabdq_x_u8.c => vshlcq_m_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vshlcq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u8.c | 1 - .../arm/mve/intrinsics/vshllbq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vshllbq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c | 1 - .../arm/mve/intrinsics/vshllbq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c | 1 - .../arm/mve/intrinsics/vshllbq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vshlltq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vshlltq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c | 1 - .../arm/mve/intrinsics/vshlltq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c | 1 - .../arm/mve/intrinsics/vshlltq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s16.c | 1 - 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| 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s32.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s8.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u16.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u32.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u8.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s16.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s32.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s8.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u16.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u32.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u8.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_u64.c | 1 - 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.../gcc.target/arm/mve/intrinsics/vsubq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u8.c | 1 - .../arm/mve/intrinsics/vuninitializedq_float.c | 1 - .../arm/mve/intrinsics/vuninitializedq_float1.c | 1 - .../arm/mve/intrinsics/vuninitializedq_int.c | 1 - .../arm/mve/intrinsics/vuninitializedq_int1.c | 1 - gcc/testsuite/gcc.target/arm/mve/mve.exp | 2 + gcc/testsuite/gdc.dg/fileimports/pr93038.txt | 1 + gcc/testsuite/gdc.dg/pr93038.d | 8 + gcc/testsuite/gdc.dg/pr93038b.d | 8 + gcc/testsuite/gfortran.dg/pr93365.f90 | 15 + gcc/testsuite/gfortran.dg/pr93600_1.f90 | 9 + gcc/testsuite/gfortran.dg/pr93600_2.f90 | 10 + gcc/testsuite/jit.dg/all-non-failing-tests.h | 10 + gcc/testsuite/jit.dg/test-long-string-literal.c | 54 + gcc/testsuite/lib/target-supports.exp | 12 +- gcc/tree-ssa-forwprop.c | 1 + gcc/tree-vect-slp.c | 54 +- gcc/tree.c | 15 + libgomp/ChangeLog | 6 + libgomp/target.c | 5 +- libstdc++-v3/ChangeLog | 17 + libstdc++-v3/include/bits/fs_path.h | 11 +- libstdc++-v3/include/experimental/bits/fs_path.h | 40 +- .../replace_filename.cc => generic/94242.cc} | 26 +- .../filesystem/path/generic/generic_string.cc | 32 + .../filesystem/path/generic/generic_string.cc | 46 +- 2465 files changed, 4666 insertions(+), 2717 deletions(-) create mode 100644 gcc/testsuite/g++.dg/ubsan/pr91993.C create mode 100644 gcc/testsuite/g++.dg/warn/Wconversion-pr91993.C copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => asrl.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => lsll.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u16.c => sqrshr.c} (51%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => sqshl.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => sqshll.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => srshr.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => srshrl.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u32.c => uqrshl.c} (51%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat64.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => uqshl.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => uqshll.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => urshr.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => urshrl.c} (53%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s16.c => vshlcq_m_s16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_x_s32.c => vshlcq_m_s32.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s8.c => vshlcq_m_s8.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_x_u16.c => vshlcq_m_u16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdwdupq_x_n_u16.c => vshlcq_m_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_x_u8.c => vshlcq_m_u8.c} (51%) create mode 100644 gcc/testsuite/gdc.dg/fileimports/pr93038.txt create mode 100644 gcc/testsuite/gdc.dg/pr93038.d create mode 100644 gcc/testsuite/gdc.dg/pr93038b.d create mode 100644 gcc/testsuite/gfortran.dg/pr93365.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_2.f90 create mode 100644 gcc/testsuite/jit.dg/test-long-string-literal.c copy libstdc++-v3/testsuite/27_io/filesystem/path/{modifiers/replace_filename.cc = [...] -- To stop receiving notification emails like this one, please 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5 years, 2 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allmodconfig updated (67d584e33e54 -> 16fbf79b0f83)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allmodconfig in repository toolchain/ci/linux. from 67d584e33e54 Merge tag 'for-5.6-rc6-tag' of git://git.kernel.org/pub/sc [...] adds 16fbf79b0f83 Linux 5.6-rc7 No new revisions were added by this update. Summary of changes: Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allmodconfig updated (938de7cbb1c -> c7bc3b65623)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allmodconfig in repository toolchain/ci/gcc. from 938de7cbb1c Daily bump. adds a5ef37f868b Daily bump. adds 46de8b3eb1a Darwin: Fix i686 bootstrap when the assembler supports GOTO [...] adds 5c7bd28d1cb backport PR90763: PowerPC vec_xl_len should take const argument. adds c7bc3b65623 Remove wrongly committed file. No new revisions were added by this update. Summary of changes: a | 81 --------------------------- gcc/ChangeLog | 19 +++++++ gcc/DATESTAMP | 2 +- gcc/config/i386/darwin.h | 10 ++++ gcc/config/i386/i386.h | 5 +- gcc/config/rs6000/rs6000-c.c | 13 +++++ gcc/testsuite/ChangeLog | 8 +++ gcc/testsuite/gcc.target/powerpc/pr90763.c | 88 ++++++++++++++++++++++++++++++ 8 files changed, 141 insertions(+), 85 deletions(-) delete mode 100644 a create mode 100644 gcc/testsuite/gcc.target/powerpc/pr90763.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allmodconfig updated (39ef90b -> 41bd7aa)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-mainline-allmodconfig in repository toolchain/ci/base-artifacts. discards 39ef90b 0: update: binutils-gcc-linux: boot new 41bd7aa 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (39ef90b) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 130 +- 02-prepare_abe/console.log | 374 +- 03-build_abe-binutils/console.log | 11694 ++++++------- 04-build_abe-stage1/console.log | 13639 ++++++++-------- 05-build_linux/console.log | 600 +- 06-boot_linux/console.log | 4 +- 07-check_regression/console.log | 2 +- 07-check_regression/results.regressions | 2 +- 08-update_baseline/console.log | 4 +- 08-update_baseline/results.regressions | 2 +- console.log | 26359 +++++++++++++++--------------- jenkins/manifest.sh | 12 +- 12 files changed, 26420 insertions(+), 26402 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allmodconfig updated (67d584e33e54 -> 16fbf79b0f83)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allmodconfig in repository toolchain/ci/linux. from 67d584e33e54 Merge tag 'for-5.6-rc6-tag' of git://git.kernel.org/pub/sc [...] adds 16fbf79b0f83 Linux 5.6-rc7 No new revisions were added by this update. Summary of changes: Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allnoconfig updated (67d584e33e54 -> 16fbf79b0f83)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allnoconfig in repository toolchain/ci/linux. from 67d584e33e54 Merge tag 'for-5.6-rc6-tag' of git://git.kernel.org/pub/sc [...] adds 16fbf79b0f83 Linux 5.6-rc7 No new revisions were added by this update. Summary of changes: Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allnoconfig updated (83aa5aa313a -> 1f6c1c82eb5)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allnoconfig in repository toolchain/ci/gcc. from 83aa5aa313a Daily bump. adds 6e00d8dcf32 Daily bump. adds b809f0b6580 Set proper DECL_ALIGN in offload_handle_link_vars (PR94233) adds 2fa4b1ffd6e Save ref->speculative_id before clone_reference. adds 263ee1260bc tree-optimization/94266 - aovid propagating addresses of TA [...] adds 7a2090b04e5 ipa/94245 - avoid folding when we want an ADDR_EXPR adds 26b3e568a60 [PR94044] Fix ICE with sizeof<argumentpack> adds a3586eeb884 AMDGCN offloading – use amdgcn-amdhsa adds ce6413087de lto/lto.c – used $ or . in generated linkptr name adds 4897bb0045d libgomp – fix declare target link handling (PR94251) adds b0d84ecc55f fortran: ICE in gfc_match_assignment PR93600 adds 4dcc4502f31 tree-optimization/94261 - avoid IL adjustments in SLP analysis adds 6debbff6ca3 arm: Add earlyclobber to MVE instructions that require it adds 962406639c0 testsuite, arm: Change tests to assemble adds 0cd55f9d3af libgccjit: handle long literals in playback::context::new_s [...] adds 1a5c27b1b43 [ARM][GCC][12x]: MVE ACLE intrinsics to set and get vector lane. adds 85244449104 [ARM][GCC][13x]: MVE ACLE scalar shift intrinsics. adds 88c9a831f3a [ARM][GCC][14x]: MVE ACLE whole vector left shift with carr [...] adds d326e9586b4 driver: Improve the generated help text for alias options adds 5db9e89323c c: Fix up cfun->function_end_locus on invalid function bodi [...] adds ca6c722561c c++: Handle COMPOUND_EXPRs in get_narrower and warnings_for [...] new 1f6c1c82eb5 c++: Avoid a suspicious -Wnoexcept warning [PR93805] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 199 ++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 6 + gcc/c-family/c-warn.c | 5 + gcc/c/ChangeLog | 8 + gcc/c/c-parser.c | 7 +- gcc/config/arm/arm-builtins.c | 20 + gcc/config/arm/arm_mve.h | 457 ++++ gcc/config/arm/arm_mve_builtins.def | 18 + gcc/config/arm/iterators.md | 3 + gcc/config/arm/mve.md | 397 +++- gcc/config/arm/neon.md | 21 +- gcc/config/arm/vec-common.md | 33 + gcc/cp/ChangeLog | 12 + gcc/cp/except.c | 5 +- gcc/cp/method.c | 2 +- gcc/cp/tree.c | 6 +- gcc/doc/install.texi | 16 +- gcc/fortran/ChangeLog | 17 + gcc/fortran/expr.c | 34 +- gcc/fortran/match.c | 8 + gcc/fortran/resolve.c | 2 +- gcc/ipa-prop.c | 2 +- gcc/jit/ChangeLog | 11 + gcc/jit/jit-playback.c | 16 +- gcc/jit/jit-playback.h | 1 - gcc/lto/ChangeLog | 11 + gcc/lto/lto.c | 12 +- gcc/opts.c | 29 +- gcc/symtab.c | 9 +- gcc/testsuite/ChangeLog | 2461 ++++++++++++++++++++ .../c-c++-common/ubsan/float-cast-overflow-1.c | 2 +- .../c-c++-common/ubsan/float-cast-overflow-2.c | 2 +- .../c-c++-common/ubsan/float-cast-overflow-4.c | 2 +- gcc/testsuite/g++.dg/ubsan/pr91993.C | 17 + gcc/testsuite/g++.dg/warn/Wconversion-pr91993.C | 17 + gcc/testsuite/g++.dg/warn/Wnoexcept2.C | 15 + .../arm/mve/intrinsics/{vbicq_n_s16.c => asrl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => lsll.c} | 9 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 3 +- .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 3 +- .../arm/mve/intrinsics/mve_vector_float.c | 3 +- .../arm/mve/intrinsics/mve_vector_float1.c | 3 +- .../arm/mve/intrinsics/mve_vector_float2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 3 +- .../arm/mve/intrinsics/mve_vector_int1.c | 3 +- .../arm/mve/intrinsics/mve_vector_int2.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint1.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint2.c | 3 +- .../arm/mve/intrinsics/{vbicq_n_u16.c => sqrshr.c} | 9 +- .../gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c | 13 + .../gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c | 13 + .../arm/mve/intrinsics/{vdupq_n_s8.c => sqshl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => sqshll.c} | 9 +- .../arm/mve/intrinsics/{vdupq_n_s8.c => srshr.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => srshrl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_u32.c => uqrshl.c} | 9 +- .../gcc.target/arm/mve/intrinsics/uqrshll_sat48.c | 13 + .../gcc.target/arm/mve/intrinsics/uqrshll_sat64.c | 13 + .../arm/mve/intrinsics/{vdupq_n_s8.c => uqshl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => uqshll.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => urshr.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => urshrl.c} | 9 +- .../gcc.target/arm/mve/intrinsics/vabavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_u32.c | 1 - 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| 1 - .../gcc.target/arm/mve/intrinsics/vcmlaq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot180_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot180_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot180_m_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot180_m_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot270_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot270_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot270_m_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot270_m_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot90_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot90_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot90_m_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot90_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpcsq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vcmpcsq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c | 1 - 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.../gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c | 15 + .../intrinsics/{vabsq_m_s16.c => vshlcq_m_s16.c} | 12 +- .../intrinsics/{vabdq_x_s32.c => vshlcq_m_s32.c} | 12 +- .../mve/intrinsics/{vabsq_m_s8.c => vshlcq_m_s8.c} | 12 +- .../intrinsics/{vbicq_x_u16.c => vshlcq_m_u16.c} | 12 +- .../{vdwdupq_x_n_u16.c => vshlcq_m_u32.c} | 17 +- .../mve/intrinsics/{vabdq_x_u8.c => vshlcq_m_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vshlcq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u8.c | 1 - .../arm/mve/intrinsics/vshllbq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vshllbq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c | 1 - .../arm/mve/intrinsics/vshllbq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c | 1 - .../arm/mve/intrinsics/vshllbq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vshlltq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vshlltq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c | 1 - .../arm/mve/intrinsics/vshlltq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c | 1 - .../arm/mve/intrinsics/vshlltq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_u8.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_s8.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s16.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s32.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s8.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u16.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u32.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u8.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s16.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s32.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s8.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u16.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u32.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u8.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_u64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_s64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_u64.c | 1 - .../mve/intrinsics/vstrdq_scatter_offset_p_s64.c | 1 - .../mve/intrinsics/vstrdq_scatter_offset_p_u64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_offset_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_offset_u64.c | 1 - .../vstrdq_scatter_shifted_offset_p_s64.c | 1 - .../vstrdq_scatter_shifted_offset_p_u64.c | 1 - .../intrinsics/vstrdq_scatter_shifted_offset_s64.c | 1 - .../intrinsics/vstrdq_scatter_shifted_offset_u64.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_s32.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_f16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_f16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_s16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_s32.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_u16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_u32.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_s16.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_s32.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_u16.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_u32.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_f16.c | 1 - .../vstrhq_scatter_shifted_offset_p_f16.c | 1 - .../vstrhq_scatter_shifted_offset_p_s16.c | 1 - .../vstrhq_scatter_shifted_offset_p_s32.c | 1 - .../vstrhq_scatter_shifted_offset_p_u16.c | 1 - .../vstrhq_scatter_shifted_offset_p_u32.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_s16.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_s32.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_u16.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_f32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_u32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_s32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_u32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_offset_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_offset_p_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_offset_p_s32.c | 1 - .../mve/intrinsics/vstrwq_scatter_offset_p_u32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_offset_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_offset_u32.c | 1 - .../intrinsics/vstrwq_scatter_shifted_offset_f32.c | 1 - .../vstrwq_scatter_shifted_offset_p_f32.c | 1 - .../vstrwq_scatter_shifted_offset_p_s32.c | 1 - .../vstrwq_scatter_shifted_offset_p_u32.c | 1 - .../intrinsics/vstrwq_scatter_shifted_offset_s32.c | 1 - .../intrinsics/vstrwq_scatter_shifted_offset_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u8.c | 1 - .../arm/mve/intrinsics/vuninitializedq_float.c | 1 - .../arm/mve/intrinsics/vuninitializedq_float1.c | 1 - .../arm/mve/intrinsics/vuninitializedq_int.c | 1 - .../arm/mve/intrinsics/vuninitializedq_int1.c | 1 - gcc/testsuite/gcc.target/arm/mve/mve.exp | 2 + gcc/testsuite/gfortran.dg/pr93365.f90 | 15 + gcc/testsuite/gfortran.dg/pr93600_1.f90 | 9 + gcc/testsuite/gfortran.dg/pr93600_2.f90 | 10 + gcc/testsuite/jit.dg/all-non-failing-tests.h | 10 + gcc/testsuite/jit.dg/test-long-string-literal.c | 54 + gcc/testsuite/lib/target-supports.exp | 12 +- gcc/tree-ssa-forwprop.c | 1 + gcc/tree-vect-slp.c | 54 +- gcc/tree.c | 15 + libgomp/ChangeLog | 6 + libgomp/target.c | 5 +- 2454 files changed, 4445 insertions(+), 2637 deletions(-) create mode 100644 gcc/testsuite/g++.dg/ubsan/pr91993.C create mode 100644 gcc/testsuite/g++.dg/warn/Wconversion-pr91993.C create mode 100644 gcc/testsuite/g++.dg/warn/Wnoexcept2.C copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => asrl.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => lsll.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u16.c => sqrshr.c} (51%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => sqshl.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => sqshll.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => srshr.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => srshrl.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u32.c => uqrshl.c} (51%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat64.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => uqshl.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => uqshll.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => urshr.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => urshrl.c} (53%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s16.c => vshlcq_m_s16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_x_s32.c => vshlcq_m_s32.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s8.c => vshlcq_m_s8.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_x_u16.c => vshlcq_m_u16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdwdupq_x_n_u16.c => vshlcq_m_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_x_u8.c => vshlcq_m_u8.c} (51%) create mode 100644 gcc/testsuite/gfortran.dg/pr93365.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_2.f90 create mode 100644 gcc/testsuite/jit.dg/test-long-string-literal.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allmodconfig updated (938de7cbb1c -> c7bc3b65623)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allmodconfig in repository toolchain/ci/gcc. from 938de7cbb1c Daily bump. adds a5ef37f868b Daily bump. adds 46de8b3eb1a Darwin: Fix i686 bootstrap when the assembler supports GOTO [...] adds 5c7bd28d1cb backport PR90763: PowerPC vec_xl_len should take const argument. adds c7bc3b65623 Remove wrongly committed file. No new revisions were added by this update. Summary of changes: a | 81 --------------------------- gcc/ChangeLog | 19 +++++++ gcc/DATESTAMP | 2 +- gcc/config/i386/darwin.h | 10 ++++ gcc/config/i386/i386.h | 5 +- gcc/config/rs6000/rs6000-c.c | 13 +++++ gcc/testsuite/ChangeLog | 8 +++ gcc/testsuite/gcc.target/powerpc/pr90763.c | 88 ++++++++++++++++++++++++++++++ 8 files changed, 141 insertions(+), 85 deletions(-) delete mode 100644 a create mode 100644 gcc/testsuite/gcc.target/powerpc/pr90763.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allnoconfig updated (c15a8f173e -> 0636b24556)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allnoconfig in repository toolchain/ci/binutils-gdb. from c15a8f173e XCOFF64 uninitialised read adds 2957d8d054 Automatic date update in version.in adds 5935fd1530 gdb/testsuite: Remove hard coded addresses from expected results adds 5e737279c6 i386msdos uninitialised read adds cf28cfef60 ECOFF archive uninitialised read adds fdde2fb60c Mention .tdata in comment in _bfd_elf_tls_setup() adds 0636b24556 Avoid trigger an assertion failure in the STABS parser by re [...] No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 16 ++++++++ bfd/ecoff.c | 35 +++++++++++----- bfd/elflink.c | 4 +- bfd/i386msdos.c | 14 ++++--- bfd/version.h | 2 +- binutils/ChangeLog | 21 ++++++++++ binutils/wrstabs.c | 56 +++++++++++++++++--------- gdb/testsuite/ChangeLog | 5 +++ gdb/testsuite/gdb.fortran/mixed-lang-stack.exp | 4 +- ld/ChangeLog | 7 ++++ ld/Makefile.am | 2 + ld/Makefile.in | 3 ++ ld/po/BLD-POTFILES.in | 1 + 13 files changed, 131 insertions(+), 39 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allmodconfig updated (a844839 -> 4e01204)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allmodconfig in repository toolchain/ci/base-artifacts. discards a844839 0: update: binutils-gcc-linux: all new 4e01204 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (a844839) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-m [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 68 +- 02-prepare_abe/console.log | 430 +- 03-build_abe-binutils/console.log | 10922 +++++------ 04-build_abe-stage1/console.log | 17684 +++++++++--------- 05-build_linux/console.log | 846 +- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 12 +- 07-check_regression/results.regressions | 2 +- 08-update_baseline/console.log | 12 +- 08-update_baseline/results.regressions | 2 +- console.log | 29980 +++++++++++++++--------------- jenkins/manifest.sh | 12 +- 12 files changed, 29984 insertions(+), 29988 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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Tcwg-commits March 2020