Tcwg-commits March 2020

tcwg-commits@lists.linaro.org

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11017 discussions

[linux] branch master updated (16fbf79b0f83 -> 979e52ca0469)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository linux. from 16fbf79b0f83 Linux 5.6-rc7 new c8cfcb78c658 crypto: arm64/chacha - correctly walk through blocks new 979e52ca0469 Merge branch 'linus' of git://git.kernel.org/pub/scm/linux [...] The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: arch/arm64/crypto/chacha-neon-glue.c | 8 ++++---- lib/crypto/chacha20poly1305-selftest.c | 11 ++++++++--- 2 files changed, 12 insertions(+), 7 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig updated (e2cb1213745 -> c5c4109071c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig in repository toolchain/ci/llvm-project. from e2cb1213745 [X86] Remove maximum vector length limit from combineBasicS [...] adds 5d4c1c00e6b Roll an expression into an assert to remove the need for a [...] adds 0d0b90105f9 Revert "[FIX] Do not copy an llvm::function_ref if it has t [...] adds 56e1c20bfdf [MLIR][NFC] rename ConvertStandardToLLVM, ConvertLoopToStan [...] adds b8737614964 [MLIR][NFC] Move some of the affine transforms / tests to d [...] adds 196b48a2244 [NFC] [PowerPC] Prepare test for FMA negate check adds 5792c2236d5 Add test cases that are addressed by D76010 adds 2ec59a0a40f Buildbot debugging of 0d0b90105f92f6cd9cc7004d565834f442918 [...] adds a1762f9ceb9 [libc] Don't configure test and fuzzer when -DLLVM_INCLUDE_ [...] adds 0cc124c186a [llvm-objdump][test] Improve PowerPC branch offset tests adds ccf49b9ef01 [GlobalISel] support widen unmerge if WideTy > SrcTy adds 8e45eaf1da5 [NFC][DAGCombine] Refactor post-inc logic adds 62fdb1f534b [DAGCombine] Skip PostInc combine with later users adds 7cdbf1ed4b9 Make use of APInt::countLeadingOnes. NFC. adds df5fa487397 [clang-tidy][NFC] Add missing check group docs and order entries adds 6a6a83c6e9b MergeFunctions.rst - multiply vs shift typo (PR44717) adds ea64ee0edb2 [Alignment][NFC] Deprecate ensureMaxAlignment adds b43ae21e608 Fix all-reduce int tests by host-registering memrefs. adds 6081ccf4a3b Apply function attributes through array declarators adds 72d1419bfba [InstCombine] Add CTPOP -> CTTZ simplifications (PR43513) adds b259ce998f5 [llvm-readobj] Derive dynamic symtab size from DT_HASH adds b8a2cf6b5b9 [SCCP] Extend test coverage in conditions-ranges.ll to fals [...] adds 16d2065cfc8 [InstCombine] Add ub-safe negation patterns (PR27817) adds 3ba550a05af [Alignment][NFC] Use TFL::getStackAlign() adds 32851f8d635 [Alignment][NFC] Deprecate VectorUtils::getAlignment adds 9adc7fc3cdf [SystemZ] Perform instruction shortening for fused fp ops. adds fa0320dd8d5 Add ParsedAttrInfo::handleDeclAttribute adds 5eeea337bec [VectorCombine] add more tests for extract-extract patterns; NFC adds 78e2a3c6784 [clang-format] Reflow long C# generic type constraints correctly adds 7693a9b9314 [clang-tidy] Fix RenamerClangTidy handling qualified TypeLocs adds 0eeee83d751 [VectorUtils] move x86's scaleShuffleMask to generic VectorUtils adds 33942d18b11 [SCCP] Precommit additional range propagation test. adds 24698e526f6 Implement wave32 DWARF register mapping adds 6a4905ae2d6 [lldb] Mark expressions that couldn't be parsed or executed [...] adds 60bad941a1c [Analyzer] Iterator Modeling - Model `std::advance()`, `std [...] adds 5e1a026c2d8 [clang-format] Do not indent C# array initialisers as conti [...] adds fdcb2710553 [InstCombine] Limit CTPOP -> CTTZ simplifications to one use adds f383fb40b17 Remove legacy CMake targets for libcxx and libcxxabi adds 9228a9efc6c [lldb/Target] Initialize new targets environment variables [...] adds cd7b45057ca [lldb/API] Make Launch(Simple) use args and env from target [...] adds b4a6e63ea12 [lldb/Target] Rework the way the inferior environment is created adds 04d48111bf9 Revert "Remove legacy CMake targets for libcxx and libcxxabi" adds db3f3f0240b AMDGPU/GlobalISel: Add some oversized G_IMPLICIT_DEF tests adds 0444d16a16c [GlobalISel] Add generic opcodes for saturating add/subtract adds a711a3a4603 [Syntax] Build mapping from AST to syntax tree nodes adds f3bf4b05c2a [Attributor][NFC] clang-format Attributor.{h,cpp} adds 0995001ce57 [Attributor][NFC] Predetermine the module before verification adds 54ec9b54f6b [Attributor] Unify handling of must-tail calls adds 68fed270674 [Attributor] Handle calls in AAValueConstantRange properly adds c57689bef26 [Attributor][NFC] Copy llvm::function_ref, don't use references adds ebf83c36e29 [Analysis] simplify code for scaleShuffleMask adds 5ff5ddd0adc [Win64] Insert int3 into trailing empty BBs adds 596da62d21e Add support for custom op parser/printer hooks to know abou [...] adds 278c00c4ff8 [libc++] [NFC] Test that correct value category is used in [...] adds b670ab7b6b3 recommit 1b978ddba05c [CUDA][HIP][OpenMP] Emit deferred dia [...] adds 57b8a407493 [analyzer][NFC] Tie CheckerRegistry to CheckerManager, allo [...] adds 0ca19efe7b5 Add AMDGPU MC unittests only when AMDGPU target is being built adds 7e10581e8c1 [lldb/testsuite] Skip part of TestSettings.py on windows adds 3c84aca9b35 [libc++] Bump Clang support for Clang 4 adds e10af89d991 [ARM] Extra VMOVN and VMULL tests. NFC adds c1f8595fe5b [Support] Silence warning in Path unittests when compiling [...] adds ccc0d351817 [Analyzer] IteratorRangeChecker verify `std::advance()`, `s [...] adds 0a076f2660b [ELF][test] Clean text-section-prefix.s adds ff2f5097ed4 [Attributor] Fold single-use variable into assert adds 3f51c5d9caa [OpenMPOpt][FIX] Resolve OpenMP runtime call type mismatches adds 9d38f98dc30 [OpenMPOpt] Validate declaration types against the expected types adds ae37e2285d2 [lldb/Reproducers] Mark reproducer test directory as unsupp [...] adds 552bd477f8e [gn build] Port 24698e526f619271705fe72bcaa928be9bc82484 adds ae044467ede [openmp][runtime] Fixed hang for explicit task inside a taskloop. adds 63828a35da6 [OPENMP50]Bassic support for exclusive clause. adds 04336ada175 [clang-format] No space inserted between commas in C# adds ff042de67d5 [gn build] Port 24698e526f619271705fe72bcaa928be9bc82484. F [...] adds 9607a119bd5 [gn build] Port 57b8a407493 adds 9e33c096476 [ELF] Keep orphan section names (.rodata.foo .text.foo) unc [...] adds a1fe6beb1ec [InstCombine] remove one-use check for ctpop -> cttz adds 42d8f48ccfc Fix a warning building on my machine, NFC. warning: unused [...] adds 1b9cd51d55b [CMake] Fix AMDGPUTests -DBUILD_SHARED_LIBS=on builds and t [...] adds a567d6809e1 [DataFormatters] Add formatter for libc++ std::unique_ptr adds 04f2b717d23 [mlir] Fix unsafe create operation in GreedyPatternRewriter adds 328b72dd820 [Support] Fix clang warning in widenPath NFC adds aa63eb6a461 GlobalISel: Add computeKnownBitsForTargetInstr adds 58f843a5b3d GlobalISel: Prepare to allow other target unit tests adds 2ad5fc1d915 AMDGPU/GlobalISel: Implement computeNumSignBitsForTargetInstr adds 56abcfad70e Revert "[analyzer][NFC] Tie CheckerRegistry to CheckerManag [...] adds 75add0b2ef1 [gn build] Port 56abcfad70e adds 896335bfb8e Don't export symbols from clang/opt/llc if plugins are disabled. adds 6b57d7f57d2 [OpenMP][NFC] Reduce instantiation time with different data [...] adds 55eca2853e4 [OpenMP][NFC] Minimize memory usage and copying of `OMPTraitInfo`s adds 43d98a0ecfe Allow replacing intrinsic operands with variables adds cfaa84e1a67 Fix "previously declared as a struct" warning adds 5f5fb56c68e [compiler-rt] Intercept the uname() function adds 67d67ebe8f2 Internal expressions shouldn't increment the result variabl [...] adds a650d555fc2 [Attributor][NFC] Refactorings and typos in doc adds f2f96eb605b [llvm-objcopy] Improve tool selection logic to recognize ll [...] adds 7bf871c39f7 [analyzer][NFC] Move the text output type to its own file, [...] adds b20a1d840f0 GVNSink: Allow handling addrspacecast adds 3f533006ba8 AMDGPU: Emit llvm.fshr for __builtin_amdgcn_alignbit adds 5896e2df45d [Clang] Fix HIP tests when running on Windows with the LLVM [...] adds 66073953a5c AMDGPU: Allow vectorization of round intrinsic adds 1a4421a5e86 [analyzer] ConstraintManager - use EXPENSIVE_CHECKS instead [...] new defd96f1e36 [gn build] Port 7bf871c39f7 new f3018068517 [lld] Enabling loading LLVM pass plugins new b6ae8937e03 [lldb/PlatformDarwin] Always delete destination file first [...] new a20862307ff Improve module.pcm lock file performance on machines with h [...] new 502915c619a PR45142: 'template ~X<T>' is ill-formed; reject it rather t [...] new f0990e104b0 [PowerPC]: e500 target can't use lwsync, use msync instead new 1236eb6c31f [OPENMP50]Add 'default' modifier in reduction clauses. new 564ece93b83 [MLIR] Insert loop.yield to IfOp regions only if it's void. new de0758e5bd9 [MLIR] Fixes for BUILD_SHARED_LIBS=on new c5c4109071c [examples] Fixes for BUILD_SHARED_LIBS=on The 10 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../clang-tidy/ClangTidyForceLinker.h | 66 +-- .../clang-tidy/utils/RenamerClangTidyCheck.cpp | 9 +- clang-tools-extra/docs/clang-tidy/index.rst | 4 +- .../bugprone-reserved-identifier-invert.cpp | 2 +- .../checkers/readability-identifier-naming.cpp | 13 + clang/docs/ClangPlugins.rst | 47 ++ clang/docs/InternalsManual.rst | 14 +- clang/include/clang/AST/ASTContext.h | 9 + clang/include/clang/AST/OpenMPClause.h | 128 ++++- clang/include/clang/AST/RecursiveASTVisitor.h | 7 + clang/include/clang/Basic/Attr.td | 58 ++- clang/include/clang/Basic/DiagnosticParseKinds.td | 2 + clang/include/clang/Basic/OpenMPKinds.def | 9 + clang/include/clang/Basic/OpenMPKinds.h | 7 + clang/include/clang/Parse/Parser.h | 2 +- clang/include/clang/Sema/ExternalSemaSource.h | 9 + .../clang/Sema/MultiplexExternalSemaSource.h | 9 + clang/include/clang/Sema/ParsedAttr.h | 14 +- clang/include/clang/Sema/Sema.h | 66 ++- clang/include/clang/Serialization/ASTBitCodes.h | 5 +- clang/include/clang/Serialization/ASTReader.h | 9 + .../include/clang/Serialization/ASTRecordReader.h | 4 +- .../include/clang/Serialization/ASTRecordWriter.h | 2 +- .../include/clang/StaticAnalyzer/Core/Analyses.def | 70 ++- .../Core/PathSensitive/ConstraintManager.h | 6 +- clang/include/clang/Tooling/Syntax/Tree.h | 7 +- clang/lib/AST/ASTContext.cpp | 8 + clang/lib/AST/AttrImpl.cpp | 2 +- clang/lib/AST/OpenMPClause.cpp | 43 +- clang/lib/AST/StmtProfile.cpp | 3 + clang/lib/Basic/OpenMPKinds.cpp | 19 +- clang/lib/CodeGen/CGBuiltin.cpp | 7 + clang/lib/CodeGen/CGOpenMPRuntime.cpp | 2 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 1 + clang/lib/Format/ContinuationIndenter.cpp | 19 +- clang/lib/Format/ContinuationIndenter.h | 7 +- clang/lib/Format/TokenAnnotator.cpp | 7 + clang/lib/Format/UnwrappedLineParser.cpp | 7 +- clang/lib/Parse/ParseExprCXX.cpp | 18 +- clang/lib/Parse/ParseOpenMP.cpp | 43 +- clang/lib/Sema/MultiplexExternalSemaSource.cpp | 6 + clang/lib/Sema/ParsedAttr.cpp | 3 +- clang/lib/Sema/Sema.cpp | 177 ++++--- clang/lib/Sema/SemaCUDA.cpp | 19 - clang/lib/Sema/SemaDecl.cpp | 27 +- clang/lib/Sema/SemaDeclAttr.cpp | 168 +------ clang/lib/Sema/SemaExpr.cpp | 7 +- clang/lib/Sema/SemaOpenMP.cpp | 233 ++++----- clang/lib/Sema/SemaTemplateInstantiateDecl.cpp | 3 +- clang/lib/Sema/SemaType.cpp | 26 + clang/lib/Sema/TreeTransform.h | 52 +- clang/lib/Sema/UsedDeclVisitor.h | 12 + clang/lib/Serialization/ASTReader.cpp | 39 +- clang/lib/Serialization/ASTReaderDecl.cpp | 2 +- clang/lib/Serialization/ASTWriter.cpp | 26 +- .../StaticAnalyzer/Checkers/IteratorModeling.cpp | 301 ++++++++---- .../Checkers/IteratorRangeChecker.cpp | 70 ++- clang/lib/StaticAnalyzer/Core/CMakeLists.txt | 2 + clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp | 47 +- clang/lib/StaticAnalyzer/Core/PlistDiagnostics.cpp | 25 +- clang/lib/StaticAnalyzer/Core/SarifDiagnostics.cpp | 8 +- clang/lib/StaticAnalyzer/Core/TextDiagnostics.cpp | 148 ++++++ .../StaticAnalyzer/Frontend/AnalysisConsumer.cpp | 166 +------ clang/lib/StaticAnalyzer/Frontend/CMakeLists.txt | 2 - clang/lib/Tooling/Syntax/BuildTree.cpp | 289 ++++++----- clang/lib/Tooling/Syntax/Mutations.cpp | 2 +- clang/lib/Tooling/Syntax/Tree.cpp | 23 +- .../Analysis/Inputs/system-header-simulator-cxx.h | 67 ++- clang/test/Analysis/iterator-modelling.cpp | 68 +++ clang/test/Analysis/iterator-range.cpp | 417 ++++++++++++++++ clang/test/CXX/drs/dr4xx.cpp | 8 +- clang/test/CodeGen/attr-noreturn.c | 10 + clang/test/CodeGenOpenCL/builtins-amdgcn.cl | 2 +- clang/test/Driver/hip-device-compile.hip | 4 +- clang/test/Driver/hip-toolchain-no-rdc.hip | 8 +- clang/test/Driver/hip-toolchain-rdc.hip | 2 +- clang/test/OpenMP/declare_target_messages.cpp | 12 +- .../OpenMP/nvptx_target_exceptions_messages.cpp | 4 +- clang/test/OpenMP/parallel_ast_print.cpp | 24 +- clang/test/OpenMP/parallel_reduction_codegen.cpp | 26 +- clang/test/OpenMP/parallel_reduction_messages.c | 13 +- clang/test/OpenMP/scan_ast_print.cpp | 4 +- clang/test/OpenMP/scan_messages.cpp | 30 +- clang/test/Sema/attr-noreturn.c | 31 ++ clang/test/SemaCUDA/bad-calls-on-same-line.cu | 4 +- clang/test/SemaCUDA/call-device-fn-from-host.cu | 4 +- clang/test/SemaCUDA/call-host-fn-from-device.cu | 4 +- clang/test/SemaCUDA/openmp-target.cu | 4 +- clang/test/SemaCUDA/trace-through-global.cu | 2 +- clang/test/SemaCXX/pseudo-destructors.cpp | 5 +- clang/tools/driver/CMakeLists.txt | 2 +- clang/tools/libclang/CIndex.cpp | 3 + clang/unittests/Format/FormatTestCSharp.cpp | 22 + clang/utils/TableGen/ClangAttrEmitter.cpp | 23 +- compiler-rt/lib/msan/msan_interceptors.cpp | 25 - .../sanitizer_common_interceptors.inc | 36 ++ .../lib/sanitizer_common/sanitizer_linux_s390.cpp | 13 +- .../sanitizer_platform_interceptors.h | 2 + .../test/sanitizer_common/TestCases/Posix/uname.c | 13 + libc/CMakeLists.txt | 6 +- libcxx/docs/index.rst | 2 +- .../new.delete.array/new_align_val_t.pass.cpp | 3 - .../new_align_val_t_nothrow.pass.cpp | 3 - .../new_align_val_t_nothrow_replace.pass.cpp | 2 - .../new_align_val_t_replace.pass.cpp | 3 - .../new.delete.single/new_align_val_t.pass.cpp | 3 - .../new_align_val_t_nothrow.pass.cpp | 3 - .../new_align_val_t_nothrow_replace.pass.cpp | 3 - .../new_align_val_t_replace.pass.cpp | 3 - .../allocator.adaptor.members/construct.pass.cpp | 23 + libcxx/utils/libcxx/test/config.py | 4 - libcxx/www/cxx1z_status.html | 2 +- lld/ELF/Writer.cpp | 26 +- lld/test/ELF/linkerscript/data-commands-gc.s | 2 +- lld/test/ELF/linkerscript/icf-output-sections.s | 14 +- lld/test/ELF/linkerscript/linkorder.s | 4 +- lld/test/ELF/linkerscript/linkorder2.s | 2 +- lld/test/ELF/linkerscript/memory3.s | 2 +- lld/test/ELF/linkerscript/orphan-report.s | 2 +- .../linkerscript/symbol-assign-many-passes2.test | 2 +- lld/test/ELF/mips-npic-call-pic-script.s | 34 +- lld/test/ELF/shuffle-sections-init-fini.s | 4 +- lld/test/ELF/text-section-prefix.s | 54 +- lld/tools/lld/CMakeLists.txt | 4 + lld/tools/lld/lld.cpp | 1 + lldb/include/lldb/API/SBTarget.h | 8 +- .../lldb/DataFormatters/FormattersHelpers.h | 2 + lldb/include/lldb/Expression/ExpressionVariable.h | 10 +- lldb/include/lldb/Target/Target.h | 10 +- lldb/source/API/SBTarget.cpp | 13 +- lldb/source/Commands/CommandObjectExpression.cpp | 3 +- lldb/source/Commands/CommandObjectExpression.h | 10 + lldb/source/Commands/CommandObjectTarget.cpp | 38 ++ lldb/source/Core/ValueObject.cpp | 4 +- lldb/source/DataFormatters/FormattersHelpers.cpp | 11 + lldb/source/Expression/ExpressionVariable.cpp | 10 - lldb/source/Expression/Materializer.cpp | 8 +- .../Clang/ClangPersistentVariables.cpp | 11 + .../Clang/ClangPersistentVariables.h | 10 +- .../ExpressionParser/Clang/ClangUserExpression.cpp | 4 +- .../Language/CPlusPlus/CPlusPlusLanguage.cpp | 13 + lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp | 98 ++++ lldb/source/Plugins/Language/CPlusPlus/LibCxx.h | 28 ++ .../Plugins/Language/CPlusPlus/LibCxxList.cpp | 13 +- .../Plugins/Platform/MacOSX/PlatformDarwin.cpp | 11 + .../Plugins/Platform/MacOSX/PlatformDarwin.h | 5 + lldb/source/Target/ABI.cpp | 4 +- lldb/source/Target/Target.cpp | 119 ++--- lldb/source/Target/TargetProperties.td | 5 +- .../{dont_allow_jit => result_numbering}/Makefile | 0 .../result_numbering/TestResultNumbering.py | 48 ++ .../commands/expression/result_numbering/main.c | 18 + lldb/test/API/commands/settings/TestSettings.py | 134 ++++- .../API/commands/statistics/basic/TestStats.py | 14 + .../data-formatter-stl/libcxx/unique_ptr/Makefile | 6 + .../unique_ptr/TestDataFormatterLibcxxUniquePtr.py | 47 ++ .../data-formatter-stl/libcxx/unique_ptr/main.cpp | 13 + .../Functionalities/TestDataFormatter.test | 2 +- .../Functionalities/TestExpressionEvaluation.test | 2 +- .../Reproducer/Functionalities/TestImageList.test | 2 +- .../Reproducer/Functionalities/TestStepping.test | 2 +- .../Shell/Reproducer/TestCaptureEnvOverride.test | 1 - lldb/test/Shell/Reproducer/TestCrash.test | 1 - lldb/test/Shell/Reproducer/TestDiscard.test | 1 - lldb/test/Shell/Reproducer/TestDump.test | 1 - lldb/test/Shell/Reproducer/TestGDBRemoteRepro.test | 2 +- .../test/Shell/Reproducer/TestMultipleTargets.test | 2 +- lldb/test/Shell/Reproducer/TestRelativePath.test | 1 - lldb/test/Shell/Reproducer/TestReuseDirectory.test | 2 +- lldb/test/Shell/Reproducer/TestSynchronous.test | 1 - lldb/test/Shell/Reproducer/TestWorkingDir.test | 2 - lldb/test/Shell/Reproducer/lit.local.cfg | 3 + llvm/cmake/modules/AddLLVM.cmake | 7 + llvm/docs/GlobalISel/GenericOpcode.rst | 9 + llvm/docs/MergeFunctions.rst | 4 +- .../CMakeLists.txt | 1 + llvm/include/llvm/Analysis/VectorUtils.h | 33 +- llvm/include/llvm/CodeGen/CallingConvLower.h | 2 +- .../llvm/CodeGen/GlobalISel/GISelKnownBits.h | 3 + llvm/include/llvm/CodeGen/MachineFrameInfo.h | 5 +- llvm/include/llvm/CodeGen/TargetLowering.h | 10 + llvm/include/llvm/CodeGen/TargetRegisterInfo.h | 6 + llvm/include/llvm/Frontend/OpenMP/OMPContext.h | 10 +- llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 13 +- llvm/include/llvm/IR/CallSite.h | 7 + llvm/include/llvm/IR/Function.h | 7 + llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 4 +- llvm/include/llvm/Support/LockFileManager.h | 4 +- llvm/include/llvm/Support/TargetOpcodes.def | 12 + llvm/include/llvm/Target/GenericOpcodes.td | 36 ++ llvm/include/llvm/Transforms/IPO/Attributor.h | 59 +-- llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp | 41 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 8 + llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 17 +- llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 6 +- llvm/lib/CodeGen/MIRParser/MILexer.cpp | 1 + llvm/lib/CodeGen/MIRParser/MILexer.h | 1 + llvm/lib/CodeGen/MIRParser/MIParser.cpp | 6 + llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 2 +- llvm/lib/CodeGen/MIRPrinter.cpp | 5 + llvm/lib/CodeGen/MachineFunction.cpp | 4 +- llvm/lib/CodeGen/PrologEpilogInserter.cpp | 8 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 232 ++++----- .../CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 20 +- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 7 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 22 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 6 + llvm/lib/DebugInfo/CodeView/TypeStreamMerger.cpp | 4 +- llvm/lib/Frontend/OpenMP/OMPContext.cpp | 39 +- llvm/lib/Support/LockFileManager.cpp | 64 +-- llvm/lib/Support/Windows/Path.inc | 5 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 23 + llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 6 + llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h | 8 + llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 + .../Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 25 +- .../AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp | 6 + .../AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h | 4 + llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 9 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 13 +- llvm/lib/Target/AVR/AVRFrameLowering.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 8 +- llvm/lib/Target/MSP430/MSP430FrameLowering.cpp | 4 +- llvm/lib/Target/Mips/MipsCallLowering.cpp | 5 +- llvm/lib/Target/PowerPC/PPC.td | 2 +- llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 10 +- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 3 +- llvm/lib/Target/SystemZ/SystemZShortenInst.cpp | 43 ++ llvm/lib/Target/X86/X86.h | 1 + llvm/lib/Target/X86/X86AvoidTrailingCall.cpp | 97 ++-- llvm/lib/Target/X86/X86CallFrameOptimization.cpp | 4 +- llvm/lib/Target/X86/X86FastISel.cpp | 6 +- llvm/lib/Target/X86/X86FrameLowering.cpp | 14 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 4 +- llvm/lib/Target/X86/X86ISelLowering.h | 26 - llvm/lib/Target/X86/X86InstrInfo.cpp | 52 +- llvm/lib/Target/X86/X86InstrInfo.h | 4 +- llvm/lib/Target/X86/X86TargetMachine.cpp | 1 + llvm/lib/Transforms/IPO/Attributor.cpp | 135 +++-- llvm/lib/Transforms/IPO/OpenMPOpt.cpp | 65 ++- .../Transforms/InstCombine/InstCombineCalls.cpp | 24 +- llvm/lib/Transforms/Scalar/ConstantHoisting.cpp | 2 +- llvm/lib/Transforms/Scalar/GVNSink.cpp | 1 + llvm/lib/Transforms/Utils/Local.cpp | 36 +- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 13 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 2 +- llvm/lib/Transforms/Vectorize/VPlan.cpp | 2 +- .../GlobalISel/legalizer-info-validation.mir | 12 + .../CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll | 318 ++++++++++++ .../AMDGPU/GlobalISel/legalize-implicit-def.mir | 104 ++++ .../AMDGPU/GlobalISel/legalize-unmerge-values.mir | 88 +++- llvm/test/CodeGen/PowerPC/atomics-fences.ll | 1 + llvm/test/CodeGen/PowerPC/fma-negate.ll | 314 ++++++++++++ llvm/test/CodeGen/SystemZ/shorten-fused-fp-ops.mir | 60 +++ llvm/test/CodeGen/Thumb/frame-access.ll | 4 +- .../cond-vector-reduce-mve-codegen.ll | 12 +- .../Thumb2/LowOverheadLoops/extending-loads.ll | 44 +- llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll | 16 +- llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll | 541 +++++++++++++++++++++ llvm/test/CodeGen/Thumb2/mve-vmull.ll | 99 ++++ llvm/test/CodeGen/X86/win64-eh-empty-block-2.mir | 223 +++++++++ llvm/test/CodeGen/X86/win64-eh-empty-block.ll | 2 +- llvm/test/CodeGen/X86/wineh-coreclr.ll | 8 +- .../Attributor/IPConstantProp/musttail-call.ll | 7 +- llvm/test/Transforms/Attributor/range.ll | 102 ++++ llvm/test/Transforms/GVNSink/indirect-call.ll | 24 + llvm/test/Transforms/GVNSink/sink-common-code.ll | 67 +++ llvm/test/Transforms/InstCombine/ctpop-cttz.ll | 72 ++- llvm/test/Transforms/InstCombine/select.ll | 23 + llvm/test/Transforms/InstSimplify/freeze.ll | 254 ++++++++++ llvm/test/Transforms/OpenMP/rtf_type_checking.ll | 63 +++ llvm/test/Transforms/SCCP/conditions-ranges.ll | 489 +++++++++++++++++-- llvm/test/Transforms/SLPVectorizer/AMDGPU/round.ll | 38 ++ .../Transforms/SimplifyCFG/sink-common-code.ll | 123 ++++- .../Transforms/VectorCombine/X86/extract-binop.ll | 68 +++ .../Transforms/VectorCombine/X86/extract-cmp.ll | 37 ++ llvm/test/tools/llvm-objcopy/tool-name.test | 33 ++ .../tools/llvm-objdump/ELF/PowerPC/branch-offset.s | 76 ++- llvm/test/tools/llvm-readobj/ELF/all.test | 3 +- .../ELF/dyn-symbols-size-from-hash-table.test | 314 ++++++++++++ llvm/tools/bugpoint/CMakeLists.txt | 2 +- llvm/tools/llc/CMakeLists.txt | 2 +- llvm/tools/llvm-objcopy/llvm-objcopy.cpp | 24 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 117 +++-- llvm/tools/llvm-stress/CMakeLists.txt | 1 - llvm/tools/opt/CMakeLists.txt | 2 +- llvm/unittests/Analysis/VectorUtilsTest.cpp | 8 + llvm/unittests/CodeGen/GlobalISel/CSETest.cpp | 4 +- .../CodeGen/GlobalISel/ConstantFoldingTest.cpp | 4 +- llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp | 76 +++ llvm/unittests/CodeGen/GlobalISel/GISelMITest.h | 67 ++- .../unittests/CodeGen/GlobalISel/KnownBitsTest.cpp | 61 ++- .../CodeGen/GlobalISel/LegalizerHelperTest.cpp | 161 +++--- .../unittests/CodeGen/GlobalISel/LegalizerTest.cpp | 6 +- .../CodeGen/GlobalISel/MachineIRBuilderTest.cpp | 27 +- .../CodeGen/GlobalISel/PatternMatchTest.cpp | 18 +- llvm/unittests/MC/AMDGPU/CMakeLists.txt | 11 + llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp | 77 +++ llvm/unittests/MC/CMakeLists.txt | 7 + llvm/unittests/Passes/CMakeLists.txt | 2 +- llvm/unittests/Support/Path.cpp | 4 +- llvm/unittests/Target/AMDGPU/CMakeLists.txt | 16 + llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp | 88 ++++ llvm/unittests/Transforms/Utils/LocalTest.cpp | 60 +++ .../clang/lib/StaticAnalyzer/Core/BUILD.gn | 1 + .../utils/gn/secondary/llvm/lib/Target/targets.gni | 5 +- llvm/utils/gn/secondary/llvm/unittests/BUILD.gn | 6 + .../gn/secondary/llvm/unittests/MC/AMDGPU/BUILD.gn | 14 + .../llvm/unittests/Target/AMDGPU/BUILD.gn | 17 + mlir/include/mlir/Dialect/Affine/Passes.h | 27 +- mlir/include/mlir/Dialect/LoopOps/LoopOps.td | 9 +- mlir/include/mlir/IR/OpImplementation.h | 19 + mlir/include/mlir/InitAllPasses.h | 2 +- mlir/include/mlir/Transforms/FoldUtils.h | 19 +- mlir/include/mlir/Transforms/Passes.h | 29 -- mlir/lib/Conversion/LoopToStandard/CMakeLists.txt | 2 +- ...onvertLoopToStandard.cpp => LoopToStandard.cpp} | 2 +- mlir/lib/Conversion/StandardToLLVM/CMakeLists.txt | 2 +- ...onvertStandardToLLVM.cpp => StandardToLLVM.cpp} | 2 +- mlir/lib/Dialect/AVX512/CMakeLists.txt | 1 + .../Transforms/AffineLoopInvariantCodeMotion.cpp | 2 +- mlir/lib/Dialect/Affine/Transforms/CMakeLists.txt | 8 + .../{ => Dialect/Affine}/Transforms/LoopTiling.cpp | 9 +- .../{ => Dialect/Affine}/Transforms/LoopUnroll.cpp | 3 +- .../Affine}/Transforms/LoopUnrollAndJam.cpp | 3 +- .../Affine/Transforms/SuperVectorize.cpp} | 8 +- mlir/lib/Dialect/LoopOps/LoopOps.cpp | 15 +- mlir/lib/IR/AsmPrinter.cpp | 22 +- mlir/lib/Parser/Parser.cpp | 63 ++- mlir/lib/Transforms/CMakeLists.txt | 4 - mlir/lib/Transforms/Utils/FoldUtils.cpp | 20 +- .../Affine/SuperVectorize}/compose_maps.mlir | 2 +- .../Affine/SuperVectorize}/normalize_maps.mlir | 2 +- .../Affine/SuperVectorize}/vector_utils.mlir | 4 +- .../Affine/SuperVectorize}/vectorize_1d.mlir | 2 +- .../Affine/SuperVectorize}/vectorize_2d.mlir | 4 +- .../Affine/SuperVectorize}/vectorize_3d.mlir | 2 +- .../SuperVectorize}/vectorize_outer_loop_2d.mlir | 2 +- .../vectorize_outer_loop_transpose_2d.mlir | 2 +- .../SuperVectorize}/vectorize_transpose_2d.mlir | 2 +- .../Affine}/affine-data-copy.mlir | 0 .../Affine}/affine-loop-invariant-code-motion.mlir | 0 .../Affine}/dma-generate.mlir | 0 .../Affine}/loop-tiling.mlir | 4 +- .../Affine}/parallelism-detection.mlir | 0 .../Affine}/simplify-affine-structures.mlir | 0 .../Affine}/slicing-utils.mlir | 6 +- .../{Transforms => Dialect/Affine}/unroll-jam.mlir | 0 .../{Transforms => Dialect/Affine}/unroll.mlir | 0 mlir/test/IR/parser.mlir | 40 ++ mlir/test/lib/Dialect/Affine/CMakeLists.txt | 2 + .../Affine}/TestParallelismDetection.cpp | 1 - .../Affine}/TestVectorizationUtils.cpp | 5 +- mlir/test/lib/TestDialect/CMakeLists.txt | 1 + mlir/test/lib/TestDialect/TestDialect.cpp | 81 +++ mlir/test/lib/TestDialect/TestOps.td | 12 + mlir/test/lib/Transforms/CMakeLists.txt | 2 - .../lib/Transforms/TestConvertGPUKernelToCubin.cpp | 5 +- mlir/test/mlir-cuda-runner/all-reduce-and.mlir | 21 +- mlir/test/mlir-cuda-runner/all-reduce-max.mlir | 9 +- mlir/test/mlir-cuda-runner/all-reduce-min.mlir | 9 +- mlir/test/mlir-cuda-runner/all-reduce-or.mlir | 9 +- mlir/test/mlir-cuda-runner/all-reduce-xor.mlir | 9 +- .../test/mlir-cuda-runner/multiple-all-reduce.mlir | 9 + .../mlir-cuda-runner/cuda-runtime-wrappers.cpp | 80 ++- openmp/runtime/src/kmp_tasking.cpp | 9 +- .../runtime/test/tasking/omp_task_red_taskloop.c | 57 +++ 367 files changed, 8713 insertions(+), 2378 deletions(-) create mode 100644 clang/lib/StaticAnalyzer/Core/TextDiagnostics.cpp create mode 100644 clang/test/CodeGen/attr-noreturn.c create mode 100644 compiler-rt/test/sanitizer_common/TestCases/Posix/uname.c copy lldb/test/API/commands/expression/{dont_allow_jit => result_numbering}/Makefi [...] create mode 100644 lldb/test/API/commands/expression/result_numbering/TestResultNu [...] create mode 100644 lldb/test/API/commands/expression/result_numbering/main.c create mode 100644 lldb/test/API/functionalities/data-formatter/data-formatter-stl [...] create mode 100644 lldb/test/API/functionalities/data-formatter/data-formatter-stl [...] create mode 100644 lldb/test/API/functionalities/data-formatter/data-formatter-stl [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll create mode 100644 llvm/test/CodeGen/PowerPC/fma-negate.ll create mode 100644 llvm/test/CodeGen/SystemZ/shorten-fused-fp-ops.mir create mode 100644 llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll create mode 100644 llvm/test/CodeGen/X86/win64-eh-empty-block-2.mir create mode 100644 llvm/test/Transforms/OpenMP/rtf_type_checking.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/AMDGPU/round.ll create mode 100644 llvm/test/tools/llvm-objcopy/tool-name.test create mode 100644 llvm/test/tools/llvm-readobj/ELF/dyn-symbols-size-from-hash-table.test create mode 100644 llvm/unittests/MC/AMDGPU/CMakeLists.txt create mode 100644 llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp create mode 100644 llvm/unittests/Target/AMDGPU/CMakeLists.txt create mode 100644 llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp create mode 100644 llvm/utils/gn/secondary/llvm/unittests/MC/AMDGPU/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU/BUILD.gn rename mlir/lib/Conversion/LoopToStandard/{ConvertLoopToStandard.cpp => LoopToStan [...] rename mlir/lib/Conversion/StandardToLLVM/{ConvertStandardToLLVM.cpp => StandardTo [...] rename mlir/lib/{ => Dialect/Affine}/Transforms/LoopTiling.cpp (98%) rename mlir/lib/{ => Dialect/Affine}/Transforms/LoopUnroll.cpp (99%) rename mlir/lib/{ => Dialect/Affine}/Transforms/LoopUnrollAndJam.cpp (99%) rename mlir/lib/{Transforms/Vectorize.cpp => Dialect/Affine/Transforms/SuperVector [...] rename mlir/test/{Transforms/Vectorize => Dialect/Affine/SuperVectorize}/compose_m [...] rename mlir/test/{Transforms/Vectorize => Dialect/Affine/SuperVectorize}/normalize [...] rename mlir/test/{Transforms/Vectorize => Dialect/Affine/SuperVectorize}/vector_ut [...] rename mlir/test/{Transforms/Vectorize => Dialect/Affine/SuperVectorize}/vectorize [...] rename mlir/test/{Transforms/Vectorize => Dialect/Affine/SuperVectorize}/vectorize [...] rename mlir/test/{Transforms/Vectorize => Dialect/Affine/SuperVectorize}/vectorize [...] rename mlir/test/{Transforms/Vectorize => Dialect/Affine/SuperVectorize}/vectorize [...] rename mlir/test/{Transforms/Vectorize => Dialect/Affine/SuperVectorize}/vectorize [...] rename mlir/test/{Transforms/Vectorize => Dialect/Affine/SuperVectorize}/vectorize [...] rename mlir/test/{Transforms => Dialect/Affine}/affine-data-copy.mlir (100%) rename mlir/test/{Transforms => Dialect/Affine}/affine-loop-invariant-code-motion. [...] rename mlir/test/{Transforms => Dialect/Affine}/dma-generate.mlir (100%) rename mlir/test/{Transforms => Dialect/Affine}/loop-tiling.mlir (97%) rename mlir/test/{Transforms => Dialect/Affine}/parallelism-detection.mlir (100%) rename mlir/test/{Transforms => Dialect/Affine}/simplify-affine-structures.mlir (100%) rename mlir/test/{Transforms => Dialect/Affine}/slicing-utils.mlir (97%) rename mlir/test/{Transforms => Dialect/Affine}/unroll-jam.mlir (100%) rename mlir/test/{Transforms => Dialect/Affine}/unroll.mlir (100%) rename mlir/test/lib/{Transforms => Dialect/Affine}/TestParallelismDetection.cpp (99%) rename mlir/test/lib/{Transforms => Dialect/Affine}/TestVectorizationUtils.cpp (98%) create mode 100644 openmp/runtime/test/tasking/omp_task_red_taskloop.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig updated (2aa5db7 -> a8e4f63)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig in repository toolchain/ci/base-artifacts. discards 2aa5db7 0: update: llvm-linux: boot new a8e4f63 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (2aa5db7) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 128 +- 02-build_llvm/console.log | 12773 ++++++++++++++++---------------- 03-build_linux/console.log | 1774 ++--- 04-boot_linux/console.log | 466 +- 05-check_regression/console.log | 2 +- 06-update_baseline/console.log | 2 +- console.log | 15145 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 15154 insertions(+), 15144 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-release-aarch64-bootstrap_O1 updated (ecce469d89e -> c7bc3b65623)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-release-aarch64-bootstrap_O1 in repository toolchain/ci/gcc. from ecce469d89e Daily bump. adds 938de7cbb1c Daily bump. adds a5ef37f868b Daily bump. adds 46de8b3eb1a Darwin: Fix i686 bootstrap when the assembler supports GOTO [...] adds 5c7bd28d1cb backport PR90763: PowerPC vec_xl_len should take const argument. adds c7bc3b65623 Remove wrongly committed file. No new revisions were added by this update. Summary of changes: a | 81 --------------------------- gcc/ChangeLog | 19 +++++++ gcc/DATESTAMP | 2 +- gcc/config/i386/darwin.h | 10 ++++ gcc/config/i386/i386.h | 5 +- gcc/config/rs6000/rs6000-c.c | 13 +++++ gcc/testsuite/ChangeLog | 8 +++ gcc/testsuite/gcc.target/powerpc/pr90763.c | 88 ++++++++++++++++++++++++++++++ 8 files changed, 141 insertions(+), 85 deletions(-) delete mode 100644 a create mode 100644 gcc/testsuite/gcc.target/powerpc/pr90763.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-release-aarch64-bootstrap_O1 updated (b5313c5 -> c81028f)

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5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_O3 updated (9fc985118d9 -> ca6c722561c)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_O3 in repository toolchain/ci/gcc. from 9fc985118d9 libstdc++: Fix path::generic_string allocator handling (PR 94242) adds a577c0c2693 libstdc++: Fix experimental::path::generic_string (PR 93245) adds 424e39081f9 d: Fix typo in ChangeLog for last change adds 4a01f7b1e73 d: Fix missing dependencies in depfile for imported files ( [...] adds 88d7d0ce8fa testsuite: Fix lambda-vis.C for targets with user label pre [...] adds 85e10e4f0fa Darwin: Fix i686 bootstrap when the assembler supports GOTO [...] adds fbe60463bb8 d: Generate phony targets for content imported files (PR93038) adds 83aa5aa313a Daily bump. adds 6e00d8dcf32 Daily bump. adds b809f0b6580 Set proper DECL_ALIGN in offload_handle_link_vars (PR94233) adds 2fa4b1ffd6e Save ref->speculative_id before clone_reference. adds 263ee1260bc tree-optimization/94266 - aovid propagating addresses of TA [...] adds 7a2090b04e5 ipa/94245 - avoid folding when we want an ADDR_EXPR adds 26b3e568a60 [PR94044] Fix ICE with sizeof<argumentpack> adds a3586eeb884 AMDGCN offloading – use amdgcn-amdhsa adds ce6413087de lto/lto.c – used $ or . in generated linkptr name adds 4897bb0045d libgomp – fix declare target link handling (PR94251) adds b0d84ecc55f fortran: ICE in gfc_match_assignment PR93600 adds 4dcc4502f31 tree-optimization/94261 - avoid IL adjustments in SLP analysis adds 6debbff6ca3 arm: Add earlyclobber to MVE instructions that require it adds 962406639c0 testsuite, arm: Change tests to assemble adds 0cd55f9d3af libgccjit: handle long literals in playback::context::new_s [...] adds 1a5c27b1b43 [ARM][GCC][12x]: MVE ACLE intrinsics to set and get vector lane. adds 85244449104 [ARM][GCC][13x]: MVE ACLE scalar shift intrinsics. adds 88c9a831f3a [ARM][GCC][14x]: MVE ACLE whole vector left shift with carr [...] adds d326e9586b4 driver: Improve the generated help text for alias options adds 5db9e89323c c: Fix up cfun->function_end_locus on invalid function bodi [...] adds ca6c722561c c++: Handle COMPOUND_EXPRs in get_narrower and warnings_for [...] No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 206 ++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 6 + gcc/c-family/c-warn.c | 5 + gcc/c/ChangeLog | 8 + gcc/c/c-parser.c | 7 +- gcc/config/arm/arm-builtins.c | 20 + gcc/config/arm/arm_mve.h | 457 ++++ gcc/config/arm/arm_mve_builtins.def | 18 + gcc/config/arm/iterators.md | 3 + gcc/config/arm/mve.md | 397 +++- gcc/config/arm/neon.md | 21 +- gcc/config/arm/vec-common.md | 33 + gcc/config/i386/darwin.h | 10 + gcc/config/i386/i386.h | 5 +- gcc/cp/ChangeLog | 6 + gcc/cp/tree.c | 6 +- gcc/d/ChangeLog | 14 +- gcc/d/d-lang.cc | 81 +- gcc/doc/install.texi | 16 +- gcc/fortran/ChangeLog | 17 + gcc/fortran/expr.c | 34 +- gcc/fortran/match.c | 8 + gcc/fortran/resolve.c | 2 +- gcc/ipa-prop.c | 2 +- gcc/jit/ChangeLog | 11 + gcc/jit/jit-playback.c | 16 +- gcc/jit/jit-playback.h | 1 - gcc/lto/ChangeLog | 11 + gcc/lto/lto.c | 12 +- gcc/opts.c | 29 +- gcc/symtab.c | 9 +- gcc/testsuite/ChangeLog | 2472 ++++++++++++++++++++ .../c-c++-common/ubsan/float-cast-overflow-1.c | 2 +- .../c-c++-common/ubsan/float-cast-overflow-2.c | 2 +- .../c-c++-common/ubsan/float-cast-overflow-4.c | 2 +- gcc/testsuite/g++.dg/abi/lambda-vis.C | 12 +- gcc/testsuite/g++.dg/ubsan/pr91993.C | 17 + gcc/testsuite/g++.dg/warn/Wconversion-pr91993.C | 17 + .../arm/mve/intrinsics/{vbicq_n_s16.c => asrl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => lsll.c} | 9 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 3 +- .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 3 +- .../arm/mve/intrinsics/mve_vector_float.c | 3 +- .../arm/mve/intrinsics/mve_vector_float1.c | 3 +- .../arm/mve/intrinsics/mve_vector_float2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 3 +- .../arm/mve/intrinsics/mve_vector_int1.c | 3 +- .../arm/mve/intrinsics/mve_vector_int2.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint1.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint2.c | 3 +- .../arm/mve/intrinsics/{vbicq_n_u16.c => sqrshr.c} | 9 +- .../gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c | 13 + .../gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c | 13 + .../arm/mve/intrinsics/{vdupq_n_s8.c => sqshl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => sqshll.c} | 9 +- .../arm/mve/intrinsics/{vdupq_n_s8.c => srshr.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => srshrl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_u32.c => uqrshl.c} | 9 +- .../gcc.target/arm/mve/intrinsics/uqrshll_sat48.c | 13 + .../gcc.target/arm/mve/intrinsics/uqrshll_sat64.c | 13 + .../arm/mve/intrinsics/{vdupq_n_s8.c => uqshl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => uqshll.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => urshr.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => urshrl.c} | 9 +- .../gcc.target/arm/mve/intrinsics/vabavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_f32.c | 1 - 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| 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_u16.c | 1 - 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| 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 1 - 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| 1 - .../arm/mve/intrinsics/vcmpneq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_s32.c | 1 - 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.../arm/mve/intrinsics/vrmlsldavhaq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhaq_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhaxq_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhq_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhxq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c | 15 + .../intrinsics/{vabsq_m_s16.c => vshlcq_m_s16.c} | 12 +- .../intrinsics/{vabdq_x_s32.c => vshlcq_m_s32.c} | 12 +- .../mve/intrinsics/{vabsq_m_s8.c => vshlcq_m_s8.c} | 12 +- .../intrinsics/{vbicq_x_u16.c => vshlcq_m_u16.c} | 12 +- .../{vdwdupq_x_n_u16.c => vshlcq_m_u32.c} | 17 +- .../mve/intrinsics/{vabdq_x_u8.c => vshlcq_m_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vshlcq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u8.c | 1 - .../arm/mve/intrinsics/vshllbq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vshllbq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c | 1 - .../arm/mve/intrinsics/vshllbq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c | 1 - .../arm/mve/intrinsics/vshllbq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vshlltq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vshlltq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c | 1 - .../arm/mve/intrinsics/vshlltq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c | 1 - .../arm/mve/intrinsics/vshlltq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s16.c | 1 - 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.../gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u8.c | 1 - .../arm/mve/intrinsics/vuninitializedq_float.c | 1 - .../arm/mve/intrinsics/vuninitializedq_float1.c | 1 - .../arm/mve/intrinsics/vuninitializedq_int.c | 1 - .../arm/mve/intrinsics/vuninitializedq_int1.c | 1 - gcc/testsuite/gcc.target/arm/mve/mve.exp | 2 + gcc/testsuite/gdc.dg/fileimports/pr93038.txt | 1 + gcc/testsuite/gdc.dg/pr93038.d | 8 + gcc/testsuite/gdc.dg/pr93038b.d | 8 + gcc/testsuite/gfortran.dg/pr93365.f90 | 15 + gcc/testsuite/gfortran.dg/pr93600_1.f90 | 9 + gcc/testsuite/gfortran.dg/pr93600_2.f90 | 10 + gcc/testsuite/jit.dg/all-non-failing-tests.h | 10 + gcc/testsuite/jit.dg/test-long-string-literal.c | 54 + gcc/testsuite/lib/target-supports.exp | 12 +- gcc/tree-ssa-forwprop.c | 1 + gcc/tree-vect-slp.c | 54 +- gcc/tree.c | 15 + libgomp/ChangeLog | 6 + libgomp/target.c | 5 +- libstdc++-v3/ChangeLog | 5 + libstdc++-v3/include/experimental/bits/fs_path.h | 40 +- .../filesystem/path/generic/generic_string.cc | 46 +- 2462 files changed, 4603 insertions(+), 2699 deletions(-) create mode 100644 gcc/testsuite/g++.dg/ubsan/pr91993.C create mode 100644 gcc/testsuite/g++.dg/warn/Wconversion-pr91993.C copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => asrl.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => lsll.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u16.c => sqrshr.c} (51%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => sqshl.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => sqshll.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => srshr.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => srshrl.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u32.c => uqrshl.c} (51%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat64.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => uqshl.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => uqshll.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => urshr.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => urshrl.c} (53%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s16.c => vshlcq_m_s16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_x_s32.c => vshlcq_m_s32.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s8.c => vshlcq_m_s8.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_x_u16.c => vshlcq_m_u16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdwdupq_x_n_u16.c => vshlcq_m_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_x_u8.c => vshlcq_m_u8.c} (51%) create mode 100644 gcc/testsuite/gdc.dg/fileimports/pr93038.txt create mode 100644 gcc/testsuite/gdc.dg/pr93038.d create mode 100644 gcc/testsuite/gdc.dg/pr93038b.d create mode 100644 gcc/testsuite/gfortran.dg/pr93365.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_2.f90 create mode 100644 gcc/testsuite/jit.dg/test-long-string-literal.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_O3 updated (8945e6e -> 4a367d2)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_O3 in repository toolchain/ci/base-artifacts. discards 8945e6e 0: update: gcc-9fc985118d9f5014afc1caf32a411ee5803fba61: 1 new 4a367d2 0: update: gcc-ca6c722561ce9b9dc7b59cfd9d29c9b466732721: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (8945e6e) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-master-arm-boots [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 131 +- 02-prepare_abe/console.log | 286 +- 03-build_abe-bootstrap_O3/console.log | 93378 ++++++++++++++--------------- 05-check_regression/console.log | 5 +- 05-check_regression/results.regressions | 5 + 06-update_baseline/console.log | 11 +- 06-update_baseline/results.regressions | 6 + console.log | 93811 +++++++++++++++--------------- jenkins/manifest.sh | 10 +- regressions.txt | 6 - 10 files changed, 93854 insertions(+), 93795 deletions(-) create mode 100644 05-check_regression/results.regressions create mode 100644 06-update_baseline/results.regressions delete mode 100644 regressions.txt -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig updated (83aa5aa313a -> 1f6c1c82eb5)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig in repository toolchain/ci/gcc. from 83aa5aa313a Daily bump. adds 6e00d8dcf32 Daily bump. adds b809f0b6580 Set proper DECL_ALIGN in offload_handle_link_vars (PR94233) adds 2fa4b1ffd6e Save ref->speculative_id before clone_reference. adds 263ee1260bc tree-optimization/94266 - aovid propagating addresses of TA [...] adds 7a2090b04e5 ipa/94245 - avoid folding when we want an ADDR_EXPR adds 26b3e568a60 [PR94044] Fix ICE with sizeof<argumentpack> adds a3586eeb884 AMDGCN offloading – use amdgcn-amdhsa adds ce6413087de lto/lto.c – used $ or . in generated linkptr name adds 4897bb0045d libgomp – fix declare target link handling (PR94251) adds b0d84ecc55f fortran: ICE in gfc_match_assignment PR93600 adds 4dcc4502f31 tree-optimization/94261 - avoid IL adjustments in SLP analysis adds 6debbff6ca3 arm: Add earlyclobber to MVE instructions that require it adds 962406639c0 testsuite, arm: Change tests to assemble adds 0cd55f9d3af libgccjit: handle long literals in playback::context::new_s [...] adds 1a5c27b1b43 [ARM][GCC][12x]: MVE ACLE intrinsics to set and get vector lane. adds 85244449104 [ARM][GCC][13x]: MVE ACLE scalar shift intrinsics. adds 88c9a831f3a [ARM][GCC][14x]: MVE ACLE whole vector left shift with carr [...] adds d326e9586b4 driver: Improve the generated help text for alias options adds 5db9e89323c c: Fix up cfun->function_end_locus on invalid function bodi [...] adds ca6c722561c c++: Handle COMPOUND_EXPRs in get_narrower and warnings_for [...] adds 1f6c1c82eb5 c++: Avoid a suspicious -Wnoexcept warning [PR93805] No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 199 ++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 6 + gcc/c-family/c-warn.c | 5 + gcc/c/ChangeLog | 8 + gcc/c/c-parser.c | 7 +- gcc/config/arm/arm-builtins.c | 20 + gcc/config/arm/arm_mve.h | 457 ++++ gcc/config/arm/arm_mve_builtins.def | 18 + gcc/config/arm/iterators.md | 3 + gcc/config/arm/mve.md | 397 +++- gcc/config/arm/neon.md | 21 +- gcc/config/arm/vec-common.md | 33 + gcc/cp/ChangeLog | 12 + gcc/cp/except.c | 5 +- gcc/cp/method.c | 2 +- gcc/cp/tree.c | 6 +- gcc/doc/install.texi | 16 +- gcc/fortran/ChangeLog | 17 + gcc/fortran/expr.c | 34 +- gcc/fortran/match.c | 8 + gcc/fortran/resolve.c | 2 +- gcc/ipa-prop.c | 2 +- gcc/jit/ChangeLog | 11 + gcc/jit/jit-playback.c | 16 +- gcc/jit/jit-playback.h | 1 - gcc/lto/ChangeLog | 11 + gcc/lto/lto.c | 12 +- gcc/opts.c | 29 +- gcc/symtab.c | 9 +- gcc/testsuite/ChangeLog | 2461 ++++++++++++++++++++ .../c-c++-common/ubsan/float-cast-overflow-1.c | 2 +- .../c-c++-common/ubsan/float-cast-overflow-2.c | 2 +- .../c-c++-common/ubsan/float-cast-overflow-4.c | 2 +- gcc/testsuite/g++.dg/ubsan/pr91993.C | 17 + gcc/testsuite/g++.dg/warn/Wconversion-pr91993.C | 17 + gcc/testsuite/g++.dg/warn/Wnoexcept2.C | 15 + .../arm/mve/intrinsics/{vbicq_n_s16.c => asrl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => lsll.c} | 9 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 3 +- .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 3 +- .../arm/mve/intrinsics/mve_vector_float.c | 3 +- .../arm/mve/intrinsics/mve_vector_float1.c | 3 +- .../arm/mve/intrinsics/mve_vector_float2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 3 +- .../arm/mve/intrinsics/mve_vector_int1.c | 3 +- .../arm/mve/intrinsics/mve_vector_int2.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint1.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint2.c | 3 +- .../arm/mve/intrinsics/{vbicq_n_u16.c => sqrshr.c} | 9 +- .../gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c | 13 + .../gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c | 13 + .../arm/mve/intrinsics/{vdupq_n_s8.c => sqshl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => sqshll.c} | 9 +- .../arm/mve/intrinsics/{vdupq_n_s8.c => srshr.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => srshrl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_u32.c => uqrshl.c} | 9 +- .../gcc.target/arm/mve/intrinsics/uqrshll_sat48.c | 13 + .../gcc.target/arm/mve/intrinsics/uqrshll_sat64.c | 13 + .../arm/mve/intrinsics/{vdupq_n_s8.c => uqshl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => uqshll.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => urshr.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => urshrl.c} | 9 +- .../gcc.target/arm/mve/intrinsics/vabavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_u32.c | 1 - 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| 1 - .../gcc.target/arm/mve/intrinsics/vbicq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_s16.c | 1 - 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.../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c | 15 + .../intrinsics/{vabsq_m_s16.c => vshlcq_m_s16.c} | 12 +- .../intrinsics/{vabdq_x_s32.c => vshlcq_m_s32.c} | 12 +- .../mve/intrinsics/{vabsq_m_s8.c => vshlcq_m_s8.c} | 12 +- .../intrinsics/{vbicq_x_u16.c => vshlcq_m_u16.c} | 12 +- .../{vdwdupq_x_n_u16.c => vshlcq_m_u32.c} | 17 +- .../mve/intrinsics/{vabdq_x_u8.c => vshlcq_m_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vshlcq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u8.c | 1 - .../arm/mve/intrinsics/vshllbq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vshllbq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c | 1 - .../arm/mve/intrinsics/vshllbq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c | 1 - .../arm/mve/intrinsics/vshllbq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vshlltq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vshlltq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c | 1 - .../arm/mve/intrinsics/vshlltq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c | 1 - .../arm/mve/intrinsics/vshlltq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_u8.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_s8.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s16.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s32.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s8.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u16.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u32.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u8.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s16.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s32.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s8.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u16.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u32.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u8.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_u64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_s64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_u64.c | 1 - .../mve/intrinsics/vstrdq_scatter_offset_p_s64.c | 1 - .../mve/intrinsics/vstrdq_scatter_offset_p_u64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_offset_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_offset_u64.c | 1 - .../vstrdq_scatter_shifted_offset_p_s64.c | 1 - .../vstrdq_scatter_shifted_offset_p_u64.c | 1 - .../intrinsics/vstrdq_scatter_shifted_offset_s64.c | 1 - .../intrinsics/vstrdq_scatter_shifted_offset_u64.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_s32.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_f16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_f16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_s16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_s32.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_u16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_u32.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_s16.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_s32.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_u16.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_u32.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_f16.c | 1 - .../vstrhq_scatter_shifted_offset_p_f16.c | 1 - .../vstrhq_scatter_shifted_offset_p_s16.c | 1 - .../vstrhq_scatter_shifted_offset_p_s32.c | 1 - .../vstrhq_scatter_shifted_offset_p_u16.c | 1 - .../vstrhq_scatter_shifted_offset_p_u32.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_s16.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_s32.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_u16.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_f32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_u32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_f32.c | 1 - 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.../gcc.target/arm/mve/intrinsics/vsubq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u8.c | 1 - .../arm/mve/intrinsics/vuninitializedq_float.c | 1 - .../arm/mve/intrinsics/vuninitializedq_float1.c | 1 - .../arm/mve/intrinsics/vuninitializedq_int.c | 1 - .../arm/mve/intrinsics/vuninitializedq_int1.c | 1 - gcc/testsuite/gcc.target/arm/mve/mve.exp | 2 + gcc/testsuite/gfortran.dg/pr93365.f90 | 15 + gcc/testsuite/gfortran.dg/pr93600_1.f90 | 9 + gcc/testsuite/gfortran.dg/pr93600_2.f90 | 10 + gcc/testsuite/jit.dg/all-non-failing-tests.h | 10 + gcc/testsuite/jit.dg/test-long-string-literal.c | 54 + gcc/testsuite/lib/target-supports.exp | 12 +- gcc/tree-ssa-forwprop.c | 1 + gcc/tree-vect-slp.c | 54 +- gcc/tree.c | 15 + libgomp/ChangeLog | 6 + libgomp/target.c | 5 +- 2454 files changed, 4445 insertions(+), 2637 deletions(-) create mode 100644 gcc/testsuite/g++.dg/ubsan/pr91993.C create mode 100644 gcc/testsuite/g++.dg/warn/Wconversion-pr91993.C create mode 100644 gcc/testsuite/g++.dg/warn/Wnoexcept2.C copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => asrl.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => lsll.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u16.c => sqrshr.c} (51%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => sqshl.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => sqshll.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => srshr.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => srshrl.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u32.c => uqrshl.c} (51%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat64.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => uqshl.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => uqshll.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => urshr.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => urshrl.c} (53%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s16.c => vshlcq_m_s16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_x_s32.c => vshlcq_m_s32.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s8.c => vshlcq_m_s8.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_x_u16.c => vshlcq_m_u16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdwdupq_x_n_u16.c => vshlcq_m_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_x_u8.c => vshlcq_m_u8.c} (51%) create mode 100644 gcc/testsuite/gfortran.dg/pr93365.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_2.f90 create mode 100644 gcc/testsuite/jit.dg/test-long-string-literal.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig updated (c15a8f173e -> 0636b24556)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig in repository toolchain/ci/binutils-gdb. from c15a8f173e XCOFF64 uninitialised read adds 2957d8d054 Automatic date update in version.in adds 5935fd1530 gdb/testsuite: Remove hard coded addresses from expected results adds 5e737279c6 i386msdos uninitialised read adds cf28cfef60 ECOFF archive uninitialised read adds fdde2fb60c Mention .tdata in comment in _bfd_elf_tls_setup() adds 0636b24556 Avoid trigger an assertion failure in the STABS parser by re [...] No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 16 ++++++++ bfd/ecoff.c | 35 +++++++++++----- bfd/elflink.c | 4 +- bfd/i386msdos.c | 14 ++++--- bfd/version.h | 2 +- binutils/ChangeLog | 21 ++++++++++ binutils/wrstabs.c | 56 +++++++++++++++++--------- gdb/testsuite/ChangeLog | 5 +++ gdb/testsuite/gdb.fortran/mixed-lang-stack.exp | 4 +- ld/ChangeLog | 7 ++++ ld/Makefile.am | 2 + ld/Makefile.in | 3 ++ ld/po/BLD-POTFILES.in | 1 + 13 files changed, 131 insertions(+), 39 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig updated (4b9e21b -> 25aaa30)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig in repository toolchain/ci/base-artifacts. discards 4b9e21b 0: update: binutils-gcc-linux: boot new 25aaa30 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (4b9e21b) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-lt [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 110 +- 02-prepare_abe/console.log | 234 +- 03-build_abe-binutils/console.log | 11374 +++++----- 04-build_abe-stage1/console.log | 19410 ++++++++--------- 05-build_linux/console.log | 3126 +-- 06-boot_linux/console.log | 470 +- 07-check_regression/console.log | 8 +- 07-check_regression/results.regressions | 2 +- 08-update_baseline/console.log | 2 +- 08-update_baseline/results.regressions | 2 +- console.log | 34734 +++++++++++++++--------------- jenkins/manifest.sh | 12 +- 12 files changed, 34780 insertions(+), 34704 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

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