Tcwg-commits March 2020

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11017 discussions

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-defconfig updated (2957d8d054 -> 1ce0847daa)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-defconfig in repository toolchain/ci/binutils-gdb. from 2957d8d054 Automatic date update in version.in adds 5935fd1530 gdb/testsuite: Remove hard coded addresses from expected results adds 5e737279c6 i386msdos uninitialised read adds cf28cfef60 ECOFF archive uninitialised read adds fdde2fb60c Mention .tdata in comment in _bfd_elf_tls_setup() adds 0636b24556 Avoid trigger an assertion failure in the STABS parser by re [...] adds 1ce0847daa Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 16 ++++++++ bfd/ecoff.c | 35 +++++++++++----- bfd/elflink.c | 4 +- bfd/i386msdos.c | 14 ++++--- bfd/version.h | 2 +- binutils/ChangeLog | 21 ++++++++++ binutils/wrstabs.c | 56 +++++++++++++++++--------- gdb/testsuite/ChangeLog | 5 +++ gdb/testsuite/gdb.fortran/mixed-lang-stack.exp | 4 +- ld/ChangeLog | 7 ++++ ld/Makefile.am | 2 + ld/Makefile.in | 3 ++ ld/po/BLD-POTFILES.in | 1 + 13 files changed, 131 insertions(+), 39 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-defconfig updated (dc8b8a4 -> 744fdce)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-defconfig in repository toolchain/ci/base-artifacts. discards dc8b8a4 0: update: binutils-gcc-linux: boot new 744fdce 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (dc8b8a4) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 176 +- 02-prepare_abe/console.log | 430 +- 03-build_abe-binutils/console.log | 11550 +++++------ 04-build_abe-stage1/console.log | 15132 +++++++-------- 05-build_linux/console.log | 2740 ++- 06-boot_linux/console.log | 470 +- 07-check_regression/console.log | 30 +- 07-check_regression/results.regressions | 4 +- 08-update_baseline/console.log | 12 +- 08-update_baseline/results.regressions | 4 +- console.log | 30554 +++++++++++++++--------------- jenkins/manifest.sh | 16 +- results | 2 +- 13 files changed, 30550 insertions(+), 30570 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/glibc] branch linaro-local/ci/tcwg_bmk_tk1/gnu-release-arm-spec2k6-Os-vs-Os_LTO updated (d53f5cac50 -> 6b11f60c70)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-release-arm-spec2k6-Os-vs-Os_LTO in repository toolchain/ci/glibc. from d53f5cac50 malloc/tst-mallocfork2: Kill lingering process for unexpecte [...] adds 75fa5fd7c3 Improve IFUNC check [BZ #25506] adds 57700813eb Avoid ldbl-96 stack corruption from range reduction of pseud [...] adds 949fbe7826 math/test-sinl-pseudo: Use stack protector only if available adds dd34bce38c Add NEWS entry for CVE-2020-10029 (bug 25487) adds da97c6b88e Fix use-after-free in glob when expanding ~user (bug 25414) adds fb266e65cc Fix array overflow in backtrace on PowerPC (bug 25423) adds 6b11f60c70 Add NEWS entry for CVE-2020-1752 (bug 25414) No new revisions were added by this update. Summary of changes: NEWS | 8 +++++++ configure | 2 +- configure.ac | 2 +- debug/tst-backtrace5.c | 12 +++++++++++ posix/glob.c | 25 +++++++++++----------- sysdeps/ieee754/ldbl-96/Makefile | 5 ++++- sysdeps/ieee754/ldbl-96/e_rem_pio2l.c | 12 +++++++++++ .../ieee754/ldbl-96/test-sinl-pseudo.c | 22 ++++++++++++++----- sysdeps/powerpc/powerpc32/backtrace.c | 2 ++ sysdeps/powerpc/powerpc64/backtrace.c | 2 ++ 10 files changed, 72 insertions(+), 20 deletions(-) copy libio/tst-bz24228.c => sysdeps/ieee754/ldbl-96/test-sinl-pseudo.c (58%) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_tk1/gnu-release-arm-spec2k6-Os-vs-Os_LTO updated (6bf890660d9 -> c7bc3b65623)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-release-arm-spec2k6-Os-vs-Os_LTO in repository toolchain/ci/gcc. from 6bf890660d9 Readd ChangeLog entries for adds cb54729240b lto: Also copy .note.gnu.property section adds 166c024a196 c++: Fix attributes with lambda and trailing return type. adds 1ccbda907d1 PR c++/90732 - ICE with VLA capture and generic lambda. adds e83a2d943a1 c++: Fix return deduction of lambda in discarded stmt. adds 9d5df8e3221 checking: avoid verify_type_variant crash on incomplete type. adds f137a7c6b12 c++: Fix cast to pointer to VLA. adds b4e53e9b3c9 c++: Allow parm of empty class type in constexpr. adds 054aeaef276 c++: Fix ({ ... }) array mem-initializer. adds 010204594d9 Daily bump. adds e913d4f4771 explow: Fix ICE caused by plus_constant [PR94002] adds 224ca3bfe8c Darwin, libsanitizer: Update minimum supported system version. adds 7b20c8645a5 Daily bump. adds f33d2797d4f maintainer-scripts: Speed up git clone in gcc_release adds bde2e6e5982 Remove unnecessary XFAILs from existing testcase 20050603-3.c. adds 831d4a69005 c++: avoid ICE with __builtin_memset (PR90997). adds 9af9e004831 c++: Fix [[no_unique_address]] and default mem-init [PR90432] adds 581825efc30 c++: Fix mismatch in template argument deduction [PR90505] adds b38d6242be6 c++: Fix value-init crash in template [PR93676] adds d8b65123ea2 sanopt: Avoid crash on anonymous parameter [PR93436] adds 2b5d109ba3a c++: Fix ICE in tsubst_copy with parenthesized expression [ [...] adds 29bb27b7ef2 Daily bump. adds 1665d97d375 PR c++/90938 - Initializing array with {1} works, but not {0} adds e19f06538c5 c++: Fix constexpr ICE from const mismatch [PR91607] adds 7beafc829c5 Fix ICE in trans_associate_var adds c47f6f69745 c++: Fix SFINAE for invalid non-type tparm types. adds 9ca4280a921 Backport fix for PR c++/93753 from trunk. adds 8f34b644549 testsuite: Compile asan_test.C with -Wno-alloc-size-larger-than adds d37244b40d2 arm: Fix incorrect modes with 'borrow' operations [PR90311] adds 08ed34284f4 libstdc++: Avoid using sizeof with function types (PR 93470) adds 65d75048c44 libstdc++: make negative count safe with std::for_each_n adds 494166791ea Add 'noexcept' to std::lerp adds 9d0ad2d40ee PR libstdc++/91910 fix data race in Debug Mode destructors adds 128418afd7e libstdc++: Fix some warnings in filesystem tests adds 07d52e63d99 i386: Fix some -O0 avx2intrin.h and xopintrin.h intrinsic m [...] adds e50627ff8cd c++: Avoid ICE on infinite recursion with concepts. adds c5edde44f5b Daily bump. adds 39bdebf3725 libstdc++: Fix call to __glibcxx_rwlock_init (PR 94069) adds 3786be02885 Daily bump. adds 7341a557418 Daily bump. adds 5b1a849ee47 Daily bump. adds 85c08558c66 Backport to gcc-9: PR92398: Fix testcase failure of pr72804.c adds 3b0babc396b Daily bump. adds c9858be2e71 Fix internal error on locally-defined subpools adds f7589b1c8b7 Daily bump. adds 4212a6a3e44 Update ChangeLog and version files for release adds 9f26e5863a7 Bump BASE-VER to 9.3.1. adds 716cc43745f Backport 314b91220a07bd63f13c58e37f1b5b9430a3702b adds 08f00a213f8 arm: correct constraints on movsi_compare0 [PR91913] adds 362c8772e77 libstdc++: Ensure root-dir converted to forward slash (PR93244) adds 2fa3247fef7 libstdc++: Fix FS-dependent filesystem tests adds 55925fe3a97 libstdc++: Fix test failure due to -Wnonnull warnings adds 95a82afc8a7 libstdc++: Fix name of macro in #undef directive adds 7ef07b622d8 libstdc++: Handle type-changing path concatenations (PR 94063) adds de8e3b71c8b rs6000: Fix -mpower9-vector -mno-altivec ICE (PR87560) adds 0816fafce9b Daily bump. adds 593e47a6134 Fix incorrect filling of delay slots in branchy code at -O2 adds db358455287 tree-optimization/94163 constrain alignment set by PRE adds ab768006bc5 Fix wrong year in ChangeLog. adds 0f66f1d8039 Daily bump. adds 6c7e43f4702 Daily bump. adds cb05d702a17 c++: Fix CTAD with multiple-arg ctor template [93248]. adds 2fa5f9e380b c++: Fix ICE-after-error on partial spec [92068] adds c3747bca384 c++: Find parameter pack in typedef in lambda [92909]. adds a81912b0740 Daily bump. adds 31b204ace29 libstdc++: Add default constructor to net::service_already_ [...] adds 9a532a94e35 Daily bump. adds 62960ccdefe [testsuite] Fix PR94023 to guard case under vect_hw_misalign adds 05409a1edd8 [testsuite] Fix PR94019 to check vector char when vect_hw_misalign adds 5de0dc84c75 tailcall: Fix up process_assignment [PR94001] adds d2a810ee83e inliner: Copy DECL_BY_REFERENCE in copy_decl_to_var [PR93888] adds e0d6777cda9 print-rtl: Fix printing of CONST_STRING in DEBUG_INSNs [PR93399] adds 2fd27691f21 ldist: Further fixes for -ftrapv [PR94114] adds 343c467ccdc dfp: Fix decimal_to_binary [PR94111] adds a644079a702 aarch64: Fix ICE in aarch64_add_offset_1 [PR94121] adds f1125cf88ac pdp11: Fix handling of common (local and global) vars [PR94134] adds a545ffafa38 tree-dse: Fix mem* head trimming if call has lhs [PR94130] adds 9a8af207d7d doc: Fix up ASM_OUTPUT_ALIGNED_DECL_LOCAL description adds 3739894d0cf maintainer-scripts: Fix up gcc_release without -l, where mk [...] adds c2f836c413b aarch64: Fix another bug in aarch64_add_offset_1 [PR94121] adds a8fc40fd551 tree-nested: Fix handling of *reduction clauses with C arra [...] adds 378e830538a tree-inline: Fix a -fcompare-debug issue in the inliner [PR94167] adds 65de83595fa expand: Don't depend on warning flags in code generation of [...] adds c78b41b23b3 Daily bump. adds 883465f79e7 Daily bump. adds d01cb80e0fb rs6000: Check -+0 and NaN for smax/smin generation adds 337111a2349 doc: Note that some warnings depend on optimizations (PR 92757) adds bf061b9a5f7 Daily bump. adds ecce469d89e Daily bump. adds 938de7cbb1c Daily bump. adds a5ef37f868b Daily bump. adds 46de8b3eb1a Darwin: Fix i686 bootstrap when the assembler supports GOTO [...] adds 5c7bd28d1cb backport PR90763: PowerPC vec_xl_len should take const argument. adds c7bc3b65623 Remove wrongly committed file. No new revisions were added by this update. Summary of changes: ChangeLog | 4 + config/ChangeLog | 4 + contrib/ChangeLog | 4 + contrib/header-tools/ChangeLog | 4 + contrib/reghunt/ChangeLog | 4 + contrib/regression/ChangeLog | 4 + fixincludes/ChangeLog | 4 + gcc/BASE-VER | 2 +- gcc/ChangeLog | 231 +++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 9 + gcc/ada/gcc-interface/decl.c | 13 +- gcc/brig/ChangeLog | 4 + gcc/builtins.c | 22 +- gcc/c-family/ChangeLog | 4 + gcc/c/ChangeLog | 4 + gcc/config/aarch64/aarch64.c | 5 +- gcc/config/arm/arm.md | 110 +++++----- gcc/config/arm/predicates.md | 21 ++ gcc/config/i386/avx2intrin.h | 8 +- gcc/config/i386/darwin.h | 10 + gcc/config/i386/i386.h | 5 +- gcc/config/i386/xopintrin.h | 8 +- gcc/config/pdp11/pdp11.c | 3 +- gcc/config/rs6000/rs6000-c.c | 13 ++ gcc/config/rs6000/rs6000-cpus.def | 4 + gcc/config/rs6000/rs6000.c | 12 +- gcc/cp/ChangeLog | 131 ++++++++++++ gcc/cp/class.c | 2 + gcc/cp/constexpr.c | 29 ++- gcc/cp/constraint.cc | 4 + gcc/cp/cp-gimplify.c | 31 +++ gcc/cp/init.c | 13 +- gcc/cp/parser.c | 23 +- gcc/cp/pt.c | 95 +++++++-- gcc/cp/semantics.c | 1 - gcc/cp/tree.c | 10 +- gcc/d/ChangeLog | 4 + gcc/dfp.c | 10 +- gcc/doc/invoke.texi | 5 + gcc/doc/tm.texi | 6 +- gcc/doc/tm.texi.in | 6 +- gcc/explow.c | 3 + gcc/fortran/ChangeLog | 12 ++ gcc/fortran/match.c | 26 ++- gcc/go/ChangeLog | 4 + gcc/jit/ChangeLog | 4 + gcc/lto/ChangeLog | 4 + gcc/objc/ChangeLog | 4 + gcc/objcp/ChangeLog | 4 + gcc/po/ChangeLog | 4 + gcc/print-rtl.c | 4 +- gcc/reorg.c | 26 ++- gcc/resource.c | 21 +- gcc/resource.h | 1 + gcc/sanopt.c | 9 +- gcc/testsuite/ChangeLog | 160 ++++++++++++++ .../compile => c-c++-common}/pr84305.c | 2 + gcc/testsuite/g++.dg/asan/asan_test.C | 2 +- gcc/testsuite/g++.dg/concepts/concepts-pr88395.C | 23 ++ gcc/testsuite/g++.dg/cpp0x/constexpr-array23.C | 24 +++ gcc/testsuite/g++.dg/cpp0x/constexpr-empty14.C | 10 + .../g++.dg/cpp0x/lambda/lambda-variadic10.C | 12 ++ gcc/testsuite/g++.dg/cpp0x/nsdmi-template19.C | 13 ++ gcc/testsuite/g++.dg/cpp0x/variadic178.C | 6 + gcc/testsuite/g++.dg/cpp1y/lambda-vla1.C | 16 ++ gcc/testsuite/g++.dg/cpp1y/paren5.C | 12 ++ gcc/testsuite/g++.dg/cpp1z/class-deduction71.C | 6 + gcc/testsuite/g++.dg/cpp1z/constexpr-if-lambda1.C | 16 ++ gcc/testsuite/g++.dg/cpp1z/constexpr-if12.C | 3 +- gcc/testsuite/g++.dg/cpp2a/no_unique_address3.C | 16 ++ gcc/testsuite/g++.dg/cpp2a/nontype-class33.C | 36 ++++ gcc/testsuite/g++.dg/debug/verify1.C | 64 ++++++ gcc/testsuite/g++.dg/ext/attr-trailing1.C | 14 ++ gcc/testsuite/g++.dg/ext/builtin14.C | 4 + gcc/testsuite/g++.dg/ext/flexary36.C | 123 +++++++++++ gcc/testsuite/g++.dg/guality/pr93888.C | 24 +++ gcc/testsuite/g++.dg/init/array55.C | 27 +++ gcc/testsuite/g++.dg/init/array56.C | 107 ++++++++++ gcc/testsuite/g++.dg/template/deduce4.C | 17 ++ gcc/testsuite/g++.dg/template/deduce5.C | 17 ++ gcc/testsuite/g++.dg/template/deduce6.C | 17 ++ gcc/testsuite/g++.dg/template/deduce7.C | 10 + gcc/testsuite/g++.target/i386/pr94046-1.C | 55 +++++ gcc/testsuite/g++.target/i386/pr94046-2.C | 5 + gcc/testsuite/gcc.c-torture/execute/pr90311.c | 16 ++ gcc/testsuite/gcc.c-torture/execute/pr94130.c | 16 ++ gcc/testsuite/gcc.c-torture/execute/pr94134.c | 14 ++ gcc/testsuite/gcc.dg/dfp/pr94111.c | 12 ++ gcc/testsuite/gcc.dg/pr93399.c | 17 ++ gcc/testsuite/gcc.dg/pr94001.c | 11 + gcc/testsuite/gcc.dg/pr94002.c | 13 ++ gcc/testsuite/gcc.dg/pr94114.c | 13 ++ gcc/testsuite/gcc.dg/pr94121.c | 16 ++ gcc/testsuite/gcc.dg/pr94167.c | 33 +++ gcc/testsuite/gcc.dg/pr94189.c | 11 + gcc/testsuite/gcc.dg/vect/slp-perm-12.c | 2 +- gcc/testsuite/gcc.dg/vect/vect-over-widen-17.c | 5 +- gcc/testsuite/gcc.target/powerpc/20050603-3.c | 5 +- gcc/testsuite/gcc.target/powerpc/p9-minmax-3.c | 17 ++ gcc/testsuite/gcc.target/powerpc/pr72804.c | 16 +- gcc/testsuite/gcc.target/powerpc/pr90763.c | 88 ++++++++ gcc/testsuite/gcc.target/powerpc/pr92398.h | 17 ++ gcc/testsuite/gcc.target/powerpc/pr92398.p9+.c | 12 ++ gcc/testsuite/gcc.target/powerpc/pr92398.p9-.c | 10 + gcc/testsuite/gcc.target/powerpc/pr93800.c | 14 ++ gcc/testsuite/gfortran.dg/pr91913.f90 | 5 + gcc/testsuite/gfortran.dg/select_type_48.f90 | 31 +++ gcc/testsuite/gnat.dg/subpools1.adb | 82 ++++++++ gcc/testsuite/lib/target-supports.exp | 20 ++ gcc/tree-inline.c | 5 +- gcc/tree-loop-distribution.c | 6 +- gcc/tree-nested.c | 37 +++- gcc/tree-pretty-print.c | 5 +- gcc/tree-pretty-print.h | 1 + gcc/tree-ssa-dse.c | 22 +- gcc/tree-ssa-pre.c | 3 +- gcc/tree-tailcall.c | 3 +- gcc/tree.c | 2 +- gnattools/ChangeLog | 4 + gotools/ChangeLog | 4 + include/ChangeLog | 4 + intl/ChangeLog | 4 + libada/ChangeLog | 4 + libatomic/ChangeLog | 4 + libbacktrace/ChangeLog | 4 + libcc1/ChangeLog | 4 + libcpp/ChangeLog | 4 + libcpp/po/ChangeLog | 4 + libdecnumber/ChangeLog | 4 + libffi/ChangeLog | 4 + libgcc/ChangeLog | 4 + libgcc/config/libbid/ChangeLog | 4 + libgfortran/ChangeLog | 4 + libgomp/ChangeLog | 12 ++ libgomp/testsuite/libgomp.c/pr93566.c | 113 ++++++++++ libhsail-rt/ChangeLog | 4 + libiberty/ChangeLog | 13 ++ libiberty/simple-object.c | 3 + libitm/ChangeLog | 4 + libobjc/ChangeLog | 4 + liboffloadmic/ChangeLog | 4 + libphobos/ChangeLog | 4 + libquadmath/ChangeLog | 4 + libsanitizer/ChangeLog | 10 + libsanitizer/configure.tgt | 2 +- libssp/ChangeLog | 4 + libstdc++-v3/ChangeLog | 114 ++++++++++ libstdc++-v3/include/bits/fs_path.h | 7 + libstdc++-v3/include/bits/refwrap.h | 3 +- libstdc++-v3/include/bits/stl_algo.h | 2 + libstdc++-v3/include/c_global/cmath | 8 +- libstdc++-v3/include/experimental/executor | 9 +- libstdc++-v3/include/std/functional | 2 +- libstdc++-v3/include/std/shared_mutex | 2 +- libstdc++-v3/src/c++11/debug.cc | 21 +- libstdc++-v3/src/c++17/fs_path.cc | 40 ++++ .../for_each/for_each_n_debug.cc} | 43 +--- .../testsuite/27_io/filesystem/operations/all.cc | 2 +- .../testsuite/27_io/filesystem/operations/copy.cc | 2 +- .../27_io/filesystem/operations/file_size.cc | 12 +- .../27_io/filesystem/operations/last_write_time.cc | 77 +++++-- .../27_io/filesystem/path/concat/94063.cc | 111 ++++++++++ .../filesystem/path/generic/generic_string.cc | 14 +- .../testsuite/27_io/filesystem/path/generic/utf.cc | 65 ++++++ .../27_io/filesystem/path/generic/wchar_t.cc | 65 ++++++ .../30_threads/shared_timed_mutex/94069.cc | 28 +++ .../experimental/filesystem/operations/copy.cc | 2 +- .../filesystem/operations/file_size.cc | 12 +- .../filesystem/operations/last_write_time.cc | 58 ++++-- .../net/execution_context/make_service.cc | 36 ++++ .../tr1/8_c_compatibility/cstdlib/functions.cc | 2 +- libvtv/ChangeLog | 4 + lto-plugin/ChangeLog | 4 + maintainer-scripts/ChangeLog | 16 ++ maintainer-scripts/gcc_release | 21 +- zlib/ChangeLog | 4 + 177 files changed, 3161 insertions(+), 301 deletions(-) rename gcc/testsuite/{gcc.c-torture/compile => c-c++-common}/pr84305.c (78%) create mode 100644 gcc/testsuite/g++.dg/concepts/concepts-pr88395.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/constexpr-array23.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/constexpr-empty14.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/lambda/lambda-variadic10.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/nsdmi-template19.C create mode 100644 gcc/testsuite/g++.dg/cpp0x/variadic178.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/lambda-vla1.C create mode 100644 gcc/testsuite/g++.dg/cpp1y/paren5.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/class-deduction71.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/constexpr-if-lambda1.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/no_unique_address3.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/nontype-class33.C create mode 100644 gcc/testsuite/g++.dg/debug/verify1.C create mode 100644 gcc/testsuite/g++.dg/ext/attr-trailing1.C create mode 100644 gcc/testsuite/g++.dg/ext/builtin14.C create mode 100644 gcc/testsuite/g++.dg/ext/flexary36.C create mode 100644 gcc/testsuite/g++.dg/guality/pr93888.C create mode 100644 gcc/testsuite/g++.dg/init/array55.C create mode 100644 gcc/testsuite/g++.dg/init/array56.C create mode 100644 gcc/testsuite/g++.dg/template/deduce4.C create mode 100644 gcc/testsuite/g++.dg/template/deduce5.C create mode 100644 gcc/testsuite/g++.dg/template/deduce6.C create mode 100644 gcc/testsuite/g++.dg/template/deduce7.C create mode 100644 gcc/testsuite/g++.target/i386/pr94046-1.C create mode 100644 gcc/testsuite/g++.target/i386/pr94046-2.C create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr90311.c create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr94130.c create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr94134.c create mode 100644 gcc/testsuite/gcc.dg/dfp/pr94111.c create mode 100644 gcc/testsuite/gcc.dg/pr93399.c create mode 100644 gcc/testsuite/gcc.dg/pr94001.c create mode 100644 gcc/testsuite/gcc.dg/pr94002.c create mode 100644 gcc/testsuite/gcc.dg/pr94114.c create mode 100644 gcc/testsuite/gcc.dg/pr94121.c create mode 100644 gcc/testsuite/gcc.dg/pr94167.c create mode 100644 gcc/testsuite/gcc.dg/pr94189.c create mode 100644 gcc/testsuite/gcc.target/powerpc/p9-minmax-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr90763.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr92398.h create mode 100644 gcc/testsuite/gcc.target/powerpc/pr92398.p9+.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr92398.p9-.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr93800.c create mode 100644 gcc/testsuite/gfortran.dg/pr91913.f90 create mode 100644 gcc/testsuite/gfortran.dg/select_type_48.f90 create mode 100644 gcc/testsuite/gnat.dg/subpools1.adb create mode 100644 libgomp/testsuite/libgomp.c/pr93566.c copy libstdc++-v3/testsuite/{27_io/filesystem/operations/file_size.cc => 25_algori [...] create mode 100644 libstdc++-v3/testsuite/27_io/filesystem/path/concat/94063.cc create mode 100644 libstdc++-v3/testsuite/27_io/filesystem/path/generic/utf.cc create mode 100644 libstdc++-v3/testsuite/27_io/filesystem/path/generic/wchar_t.cc create mode 100644 libstdc++-v3/testsuite/30_threads/shared_timed_mutex/94069.cc create mode 100644 libstdc++-v3/testsuite/experimental/net/execution_context/make_ [...] -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_bmk_tk1/gnu-release-arm-spec2k6-Os-vs-Os_LTO updated (4dd834659f -> b9414a8064)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-release-arm-spec2k6-Os-vs-Os_LTO in repository toolchain/ci/binutils-gdb. from 4dd834659f arm: PR gas/25472 Enable DSP instructions with +mve adds 5251ab5f60 powerpc64-ld infinite loop adds a9ca89e3dd gas, arm: PR25660L Fix vadd/vsub with lt and le condition co [...] adds b9414a8064 gas, arm: Fix bad backport No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 4 ++++ bfd/elf64-ppc.c | 2 +- gas/ChangeLog | 17 +++++++++++++++++ gas/config/tc-arm.c | 20 +++++++++++++++++--- gas/testsuite/gas/arm/mve-vaddsub-it-bad.d | 6 ++++++ gas/testsuite/gas/arm/mve-vaddsub-it-bad.l | 7 +++++++ gas/testsuite/gas/arm/mve-vaddsub-it-bad.s | 11 +++++++++++ gas/testsuite/gas/arm/mve-vaddsub-it.d | 23 +++++++++++++++++++++++ gas/testsuite/gas/arm/mve-vaddsub-it.s | 17 +++++++++++++++++ gas/testsuite/gas/arm/nomve-vaddsub-it.d | 24 ++++++++++++++++++++++++ 10 files changed, 127 insertions(+), 4 deletions(-) create mode 100644 gas/testsuite/gas/arm/mve-vaddsub-it-bad.d create mode 100644 gas/testsuite/gas/arm/mve-vaddsub-it-bad.l create mode 100644 gas/testsuite/gas/arm/mve-vaddsub-it-bad.s create mode 100644 gas/testsuite/gas/arm/mve-vaddsub-it.d create mode 100644 gas/testsuite/gas/arm/mve-vaddsub-it.s create mode 100644 gas/testsuite/gas/arm/nomve-vaddsub-it.d -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_tk1/gnu-release-arm-spec2k6-Os-vs-Os_LTO updated (63e49c8 -> 9ef4bd7)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-release-arm-spec2k6-Os-vs-Os_LTO in repository toolchain/ci/base-artifacts. discards 63e49c8 0: update: binutils-gcc-glibc: 1 new 9ef4bd7 0: update: binutils-gcc-glibc: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (63e49c8) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk_tk1/gnu-release-arm- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 128 +- 02-prepare_abe/console.log | 435 +- 03-build_abe-binutils/console.log | 11353 +- 04-build_abe-stage1/console.log | 17561 ++-- 05-build_abe-linux/console.log | 264 +- 06-build_abe-glibc/console.log | 38202 ++++--- 07-build_abe-stage2/console.log | 44281 ++++---- 08-benchmark--Os_mthumb/benchmark-start.log | 2 +- 08-benchmark--Os_mthumb/benchmark.log | 20 +- 08-benchmark--Os_mthumb/console.log | 232 +- 09-benchmark--Os_LTO_mthumb/benchmark-start.log | 2 +- 09-benchmark--Os_LTO_mthumb/benchmark.log | 21 +- 09-benchmark--Os_LTO_mthumb/console.log | 179 +- 10-check_regression/console.log | 2352 +- 10-check_regression/new-results-0.csv | 56 +- 10-check_regression/new-results-1.csv | 58 +- 10-check_regression/new-results-brief.csv | 58 +- 10-check_regression/new-results-compare.csv | 2 +- 10-check_regression/new-results-full.csv | 58 +- 10-check_regression/new-results.csv | 58 +- 10-check_regression/new-results.log | 4950 +- 10-check_regression/ref-results-0.csv | 56 +- 10-check_regression/ref-results-1.csv | 58 +- 10-check_regression/ref-results-brief.csv | 58 +- 10-check_regression/ref-results-compare.csv | 2 +- 10-check_regression/ref-results-full.csv | 58 +- 10-check_regression/ref-results.csv | 58 +- 10-check_regression/ref-results.log | 4818 +- 10-check_regression/ref-results.regressions | 5 + 10-check_regression/results-compare.csv | 2 +- 11-update_baseline/console.log | 1153 +- 11-update_baseline/new-results-0.csv | 56 +- 11-update_baseline/new-results-1.csv | 58 +- 11-update_baseline/new-results-brief.csv | 58 +- 11-update_baseline/new-results-compare.csv | 2 +- 11-update_baseline/new-results-full.csv | 58 +- 11-update_baseline/new-results.csv | 58 +- 11-update_baseline/new-results.log | 4970 +- 11-update_baseline/ref-results-0.csv | 56 +- 11-update_baseline/ref-results-1.csv | 58 +- 11-update_baseline/ref-results-brief.csv | 58 +- 11-update_baseline/ref-results-compare.csv | 2 +- 11-update_baseline/ref-results-full.csv | 58 +- 11-update_baseline/ref-results.csv | 58 +- 11-update_baseline/ref-results.log | 4840 +- 11-update_baseline/ref-results.regressions | 6 + 11-update_baseline/results-compare.csv | 2 +- console.log | 116218 ++++++++++----------- jenkins/manifest.sh | 24 +- regressions.txt | 1 - results | 16 +- results_id-1 | 2 +- results_id-2 | 2 +- 53 files changed, 126735 insertions(+), 126466 deletions(-) create mode 100644 10-check_regression/ref-results.regressions create mode 100644 11-update_baseline/ref-results.regressions delete mode 100644 regressions.txt -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_O3 updated (ecce469d89e -> c7bc3b65623)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_O3 in repository toolchain/ci/gcc. from ecce469d89e Daily bump. adds 938de7cbb1c Daily bump. adds a5ef37f868b Daily bump. adds 46de8b3eb1a Darwin: Fix i686 bootstrap when the assembler supports GOTO [...] adds 5c7bd28d1cb backport PR90763: PowerPC vec_xl_len should take const argument. adds c7bc3b65623 Remove wrongly committed file. No new revisions were added by this update. Summary of changes: a | 81 --------------------------- gcc/ChangeLog | 19 +++++++ gcc/DATESTAMP | 2 +- gcc/config/i386/darwin.h | 10 ++++ gcc/config/i386/i386.h | 5 +- gcc/config/rs6000/rs6000-c.c | 13 +++++ gcc/testsuite/ChangeLog | 8 +++ gcc/testsuite/gcc.target/powerpc/pr90763.c | 88 ++++++++++++++++++++++++++++++ 8 files changed, 141 insertions(+), 85 deletions(-) delete mode 100644 a create mode 100644 gcc/testsuite/gcc.target/powerpc/pr90763.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_O3 updated (16bd5fc -> 101224c)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-release-arm-bootstrap_O3 in repository toolchain/ci/base-artifacts. discards 16bd5fc 0: update: gcc-ecce469d89e8943a021f128eca4e423d72e30c78: 1 new 101224c 0: update: gcc-c7bc3b656235604eae212515b8695c6cfdaa3675: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (16bd5fc) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-release-arm-boot [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 142 +- 02-prepare_abe/console.log | 376 +- 03-build_abe-bootstrap_O3/console.log | 88331 ++++++++++++++--------------- 05-check_regression/console.log | 3 +- 05-check_regression/results.regressions | 5 + 06-update_baseline/console.log | 5 +- 06-update_baseline/results.regressions | 6 + console.log | 88857 +++++++++++++++--------------- jenkins/manifest.sh | 10 +- regressions.txt | 6 - 10 files changed, 88888 insertions(+), 88853 deletions(-) create mode 100644 05-check_regression/results.regressions create mode 100644 06-update_baseline/results.regressions delete mode 100644 regressions.txt -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allyesconfig updated (67d584e33e54 -> 979e52ca0469)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allyesconfig in repository toolchain/ci/linux. from 67d584e33e54 Merge tag 'for-5.6-rc6-tag' of git://git.kernel.org/pub/sc [...] adds 16fbf79b0f83 Linux 5.6-rc7 adds c8cfcb78c658 crypto: arm64/chacha - correctly walk through blocks adds 979e52ca0469 Merge branch 'linus' of git://git.kernel.org/pub/scm/linux [...] No new revisions were added by this update. Summary of changes: Makefile | 2 +- arch/arm64/crypto/chacha-neon-glue.c | 8 ++++---- lib/crypto/chacha20poly1305-selftest.c | 11 ++++++++--- 3 files changed, 13 insertions(+), 8 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allyesconfig updated (6e00d8dcf32 -> 75c24a08d69)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allyesconfig in repository toolchain/ci/gcc. from 6e00d8dcf32 Daily bump. adds b809f0b6580 Set proper DECL_ALIGN in offload_handle_link_vars (PR94233) adds 2fa4b1ffd6e Save ref->speculative_id before clone_reference. adds 263ee1260bc tree-optimization/94266 - aovid propagating addresses of TA [...] adds 7a2090b04e5 ipa/94245 - avoid folding when we want an ADDR_EXPR adds 26b3e568a60 [PR94044] Fix ICE with sizeof<argumentpack> adds a3586eeb884 AMDGCN offloading – use amdgcn-amdhsa adds ce6413087de lto/lto.c – used $ or . in generated linkptr name adds 4897bb0045d libgomp – fix declare target link handling (PR94251) adds b0d84ecc55f fortran: ICE in gfc_match_assignment PR93600 adds 4dcc4502f31 tree-optimization/94261 - avoid IL adjustments in SLP analysis adds 6debbff6ca3 arm: Add earlyclobber to MVE instructions that require it adds 962406639c0 testsuite, arm: Change tests to assemble adds 0cd55f9d3af libgccjit: handle long literals in playback::context::new_s [...] adds 1a5c27b1b43 [ARM][GCC][12x]: MVE ACLE intrinsics to set and get vector lane. adds 85244449104 [ARM][GCC][13x]: MVE ACLE scalar shift intrinsics. adds 88c9a831f3a [ARM][GCC][14x]: MVE ACLE whole vector left shift with carr [...] adds d326e9586b4 driver: Improve the generated help text for alias options adds 5db9e89323c c: Fix up cfun->function_end_locus on invalid function bodi [...] adds ca6c722561c c++: Handle COMPOUND_EXPRs in get_narrower and warnings_for [...] adds 1f6c1c82eb5 c++: Avoid a suspicious -Wnoexcept warning [PR93805] new 75fb811dfaa Verify the code used for the optimized comparison is valid [...] new c86c99e6950 Update gcc es.po, sv.po. new 75c24a08d69 Daily bump. The 3 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 207 ++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 6 + gcc/c-family/c-warn.c | 5 + gcc/c/ChangeLog | 8 + gcc/c/c-parser.c | 7 +- gcc/config/arm/arm-builtins.c | 20 + gcc/config/arm/arm_mve.h | 457 ++++ gcc/config/arm/arm_mve_builtins.def | 18 + gcc/config/arm/iterators.md | 3 + gcc/config/arm/mve.md | 397 +++- gcc/config/arm/neon.md | 21 +- gcc/config/arm/vec-common.md | 33 + gcc/cp/ChangeLog | 12 + gcc/cp/except.c | 5 +- gcc/cp/method.c | 2 +- gcc/cp/tree.c | 6 +- gcc/doc/install.texi | 16 +- gcc/fortran/ChangeLog | 17 + gcc/fortran/expr.c | 34 +- gcc/fortran/match.c | 8 + gcc/fortran/resolve.c | 2 +- gcc/ipa-prop.c | 2 +- gcc/jit/ChangeLog | 11 + gcc/jit/jit-playback.c | 16 +- gcc/jit/jit-playback.h | 1 - gcc/lto/ChangeLog | 11 + gcc/lto/lto.c | 12 +- gcc/opts.c | 29 +- gcc/po/ChangeLog | 4 + gcc/po/es.po | 66 +- gcc/po/sv.po | 221 +- gcc/simplify-rtx.c | 51 + gcc/symtab.c | 9 +- gcc/testsuite/ChangeLog | 2468 ++++++++++++++++++++ .../c-c++-common/ubsan/float-cast-overflow-1.c | 2 +- .../c-c++-common/ubsan/float-cast-overflow-2.c | 2 +- .../c-c++-common/ubsan/float-cast-overflow-4.c | 2 +- gcc/testsuite/g++.dg/ubsan/pr91993.C | 17 + gcc/testsuite/g++.dg/warn/Wconversion-pr91993.C | 17 + gcc/testsuite/g++.dg/warn/Wnoexcept2.C | 15 + gcc/testsuite/gcc.c-torture/compile/pr94144.c | 18 + gcc/testsuite/gcc.c-torture/compile/pr94238.c | 22 + .../arm/mve/intrinsics/{vbicq_n_s16.c => asrl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => lsll.c} | 9 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 3 +- .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 3 +- .../arm/mve/intrinsics/mve_vector_float.c | 3 +- .../arm/mve/intrinsics/mve_vector_float1.c | 3 +- .../arm/mve/intrinsics/mve_vector_float2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 3 +- .../arm/mve/intrinsics/mve_vector_int1.c | 3 +- .../arm/mve/intrinsics/mve_vector_int2.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint1.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint2.c | 3 +- .../arm/mve/intrinsics/{vbicq_n_u16.c => sqrshr.c} | 9 +- .../gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c | 13 + .../gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c | 13 + .../arm/mve/intrinsics/{vdupq_n_s8.c => sqshl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => sqshll.c} | 9 +- .../arm/mve/intrinsics/{vdupq_n_s8.c => srshr.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => srshrl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_u32.c => uqrshl.c} | 9 +- .../gcc.target/arm/mve/intrinsics/uqrshll_sat48.c | 13 + .../gcc.target/arm/mve/intrinsics/uqrshll_sat64.c | 13 + .../arm/mve/intrinsics/{vdupq_n_s8.c => uqshl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => uqshll.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => urshr.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => urshrl.c} | 9 +- .../gcc.target/arm/mve/intrinsics/vabavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_s32.c | 1 - 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| 1 - .../mve/intrinsics/vldrbq_gather_offset_z_s16.c | 1 - .../mve/intrinsics/vldrbq_gather_offset_z_s32.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c | 1 - .../mve/intrinsics/vldrbq_gather_offset_z_u16.c | 1 - .../mve/intrinsics/vldrbq_gather_offset_z_u32.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c | 1 - 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.../gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c | 15 + .../intrinsics/{vabsq_m_s16.c => vshlcq_m_s16.c} | 12 +- .../intrinsics/{vabdq_x_s32.c => vshlcq_m_s32.c} | 12 +- .../mve/intrinsics/{vabsq_m_s8.c => vshlcq_m_s8.c} | 12 +- .../intrinsics/{vbicq_x_u16.c => vshlcq_m_u16.c} | 12 +- .../{vdwdupq_x_n_u16.c => vshlcq_m_u32.c} | 17 +- .../mve/intrinsics/{vabdq_x_u8.c => vshlcq_m_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vshlcq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u8.c | 1 - .../arm/mve/intrinsics/vshllbq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vshllbq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c | 1 - .../arm/mve/intrinsics/vshllbq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c | 1 - .../arm/mve/intrinsics/vshllbq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vshlltq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vshlltq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c | 1 - .../arm/mve/intrinsics/vshlltq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c | 1 - .../arm/mve/intrinsics/vshlltq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_u8.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_s8.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s16.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s32.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s8.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u16.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u32.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u8.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s16.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s32.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s8.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u16.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u32.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u8.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_u64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_s64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_u64.c | 1 - .../mve/intrinsics/vstrdq_scatter_offset_p_s64.c | 1 - .../mve/intrinsics/vstrdq_scatter_offset_p_u64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_offset_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_offset_u64.c | 1 - .../vstrdq_scatter_shifted_offset_p_s64.c | 1 - .../vstrdq_scatter_shifted_offset_p_u64.c | 1 - .../intrinsics/vstrdq_scatter_shifted_offset_s64.c | 1 - .../intrinsics/vstrdq_scatter_shifted_offset_u64.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_s32.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_f16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_f16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_s16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_s32.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_u16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_u32.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_s16.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_s32.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_u16.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_u32.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_f16.c | 1 - .../vstrhq_scatter_shifted_offset_p_f16.c | 1 - .../vstrhq_scatter_shifted_offset_p_s16.c | 1 - .../vstrhq_scatter_shifted_offset_p_s32.c | 1 - .../vstrhq_scatter_shifted_offset_p_u16.c | 1 - .../vstrhq_scatter_shifted_offset_p_u32.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_s16.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_s32.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_u16.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_f32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_u32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_s32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_u32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_offset_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_offset_p_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_offset_p_s32.c | 1 - .../mve/intrinsics/vstrwq_scatter_offset_p_u32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_offset_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_offset_u32.c | 1 - .../intrinsics/vstrwq_scatter_shifted_offset_f32.c | 1 - .../vstrwq_scatter_shifted_offset_p_f32.c | 1 - .../vstrwq_scatter_shifted_offset_p_s32.c | 1 - .../vstrwq_scatter_shifted_offset_p_u32.c | 1 - .../intrinsics/vstrwq_scatter_shifted_offset_s32.c | 1 - .../intrinsics/vstrwq_scatter_shifted_offset_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u8.c | 1 - .../arm/mve/intrinsics/vuninitializedq_float.c | 1 - .../arm/mve/intrinsics/vuninitializedq_float1.c | 1 - .../arm/mve/intrinsics/vuninitializedq_int.c | 1 - .../arm/mve/intrinsics/vuninitializedq_int1.c | 1 - gcc/testsuite/gcc.target/arm/mve/mve.exp | 2 + gcc/testsuite/gfortran.dg/pr93365.f90 | 15 + gcc/testsuite/gfortran.dg/pr93600_1.f90 | 9 + gcc/testsuite/gfortran.dg/pr93600_2.f90 | 10 + gcc/testsuite/jit.dg/all-non-failing-tests.h | 10 + gcc/testsuite/jit.dg/test-long-string-literal.c | 54 + gcc/testsuite/lib/target-supports.exp | 12 +- gcc/tree-ssa-forwprop.c | 1 + gcc/tree-vect-slp.c | 54 +- gcc/tree.c | 15 + libgomp/ChangeLog | 6 + libgomp/target.c | 5 +- 2460 files changed, 4694 insertions(+), 2785 deletions(-) create mode 100644 gcc/testsuite/g++.dg/ubsan/pr91993.C create mode 100644 gcc/testsuite/g++.dg/warn/Wconversion-pr91993.C create mode 100644 gcc/testsuite/g++.dg/warn/Wnoexcept2.C create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr94144.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr94238.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => asrl.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => lsll.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u16.c => sqrshr.c} (51%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => sqshl.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => sqshll.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => srshr.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => srshrl.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u32.c => uqrshl.c} (51%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat64.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => uqshl.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => uqshll.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => urshr.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => urshrl.c} (53%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s16.c => vshlcq_m_s16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_x_s32.c => vshlcq_m_s32.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s8.c => vshlcq_m_s8.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_x_u16.c => vshlcq_m_u16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdwdupq_x_n_u16.c => vshlcq_m_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_x_u8.c => vshlcq_m_u8.c} (51%) create mode 100644 gcc/testsuite/gfortran.dg/pr93365.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_2.f90 create mode 100644 gcc/testsuite/jit.dg/test-long-string-literal.c -- To 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Tcwg-commits March 2020