Tcwg-commits March 2020

tcwg-commits@lists.linaro.org

4 participants
11017 discussions

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_debug updated (c7b681d3 -> 8449d379)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-arm-bootstrap_debug in repository toolchain/ci/base-artifacts. discards c7b681d3 0: update: gcc-83aa5aa313af9463c6962c72f7c238f914677824: 1 new 8449d379 0: update: gcc-565ab7efbdc68cca5a2a81d872015f33359048b4: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (c7b681d3) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-master-arm-boots [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 334 +- 02-prepare_abe/console.log | 436 +- 03-build_abe-bootstrap_debug/console.log | 95233 ++++++++++++++-------------- 05-check_regression/console.log | 10 +- 05-check_regression/results.regressions | 6 +- 06-update_baseline/console.log | 93 +- 06-update_baseline/results.regressions | 8 +- console.log | 96106 ++++++++++++++--------------- jenkins/manifest.sh | 8 +- 9 files changed, 96064 insertions(+), 96170 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig updated (16fbf79b0f83 -> 979e52ca0469)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig in repository toolchain/ci/linux. from 16fbf79b0f83 Linux 5.6-rc7 adds c8cfcb78c658 crypto: arm64/chacha - correctly walk through blocks adds 979e52ca0469 Merge branch 'linus' of git://git.kernel.org/pub/scm/linux [...] No new revisions were added by this update. Summary of changes: arch/arm64/crypto/chacha-neon-glue.c | 8 ++++---- lib/crypto/chacha20poly1305-selftest.c | 11 ++++++++--- 2 files changed, 12 insertions(+), 7 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig updated (263ee1260bc -> 906b3eb9df6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig in repository toolchain/ci/gcc. from 263ee1260bc tree-optimization/94266 - aovid propagating addresses of TA [...] adds 7a2090b04e5 ipa/94245 - avoid folding when we want an ADDR_EXPR adds 26b3e568a60 [PR94044] Fix ICE with sizeof<argumentpack> adds a3586eeb884 AMDGCN offloading – use amdgcn-amdhsa adds ce6413087de lto/lto.c – used $ or . in generated linkptr name adds 4897bb0045d libgomp – fix declare target link handling (PR94251) adds b0d84ecc55f fortran: ICE in gfc_match_assignment PR93600 adds 4dcc4502f31 tree-optimization/94261 - avoid IL adjustments in SLP analysis adds 6debbff6ca3 arm: Add earlyclobber to MVE instructions that require it adds 962406639c0 testsuite, arm: Change tests to assemble adds 0cd55f9d3af libgccjit: handle long literals in playback::context::new_s [...] adds 1a5c27b1b43 [ARM][GCC][12x]: MVE ACLE intrinsics to set and get vector lane. adds 85244449104 [ARM][GCC][13x]: MVE ACLE scalar shift intrinsics. adds 88c9a831f3a [ARM][GCC][14x]: MVE ACLE whole vector left shift with carr [...] adds d326e9586b4 driver: Improve the generated help text for alias options adds 5db9e89323c c: Fix up cfun->function_end_locus on invalid function bodi [...] adds ca6c722561c c++: Handle COMPOUND_EXPRs in get_narrower and warnings_for [...] adds 1f6c1c82eb5 c++: Avoid a suspicious -Wnoexcept warning [PR93805] adds 75fb811dfaa Verify the code used for the optimized comparison is valid [...] adds c86c99e6950 Update gcc es.po, sv.po. adds 75c24a08d69 Daily bump. adds 047811579f0 cgraphunit: Avoid code generation differences based on -w/T [...] adds a5a9400a846 if-conv: Fix -fcompare-debug bugs in ifcvt_local_dce [PR94283] adds 565ab7efbdc loop-manip: Avoid -fcompare-debug issues in create_iv [PR94285] new 596c90d3559 arm: Fix arm {,u}subvdi4 and usubvsi4 expanders [PR94286] new 906b3eb9df6 Improve endianess detection. The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 217 ++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 6 + gcc/c-family/c-warn.c | 5 + gcc/c/ChangeLog | 8 + gcc/c/c-parser.c | 7 +- gcc/cgraphunit.c | 12 +- gcc/config/arm/arm-builtins.c | 20 + gcc/config/arm/arm.md | 7 +- gcc/config/arm/arm_mve.h | 457 ++++ gcc/config/arm/arm_mve_builtins.def | 18 + gcc/config/arm/iterators.md | 3 + gcc/config/arm/mve.md | 397 +++- gcc/config/arm/neon.md | 21 +- gcc/config/arm/vec-common.md | 33 + gcc/cp/ChangeLog | 12 + gcc/cp/except.c | 5 +- gcc/cp/method.c | 2 +- gcc/cp/tree.c | 6 +- gcc/doc/install.texi | 16 +- gcc/fortran/ChangeLog | 17 + gcc/fortran/expr.c | 34 +- gcc/fortran/match.c | 8 + gcc/fortran/resolve.c | 2 +- gcc/ipa-prop.c | 2 +- gcc/jit/ChangeLog | 11 + gcc/jit/jit-playback.c | 16 +- gcc/jit/jit-playback.h | 1 - gcc/lto/ChangeLog | 5 + gcc/lto/lto.c | 6 +- gcc/opts.c | 29 +- gcc/po/ChangeLog | 4 + gcc/po/es.po | 66 +- gcc/po/sv.po | 221 +- gcc/simplify-rtx.c | 51 + gcc/testsuite/ChangeLog | 2482 ++++++++++++++++++++ .../c-c++-common/ubsan/float-cast-overflow-1.c | 2 +- .../c-c++-common/ubsan/float-cast-overflow-2.c | 2 +- .../c-c++-common/ubsan/float-cast-overflow-4.c | 2 +- gcc/testsuite/g++.dg/ubsan/pr91993.C | 17 + gcc/testsuite/g++.dg/warn/Wconversion-pr91993.C | 17 + gcc/testsuite/g++.dg/warn/Wnoexcept2.C | 15 + gcc/testsuite/gcc.c-torture/compile/pr94144.c | 18 + gcc/testsuite/gcc.c-torture/compile/pr94238.c | 22 + gcc/testsuite/gcc.dg/pr94277.c | 11 + gcc/testsuite/gcc.dg/pr94286.c | 11 + .../arm/mve/intrinsics/{vbicq_n_s16.c => asrl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => lsll.c} | 9 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fp_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_fpu3.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall1.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_libcall2.c | 3 +- .../arm/mve/intrinsics/mve_move_gpr_to_gpr.c | 3 +- .../arm/mve/intrinsics/mve_vector_float.c | 3 +- .../arm/mve/intrinsics/mve_vector_float1.c | 3 +- .../arm/mve/intrinsics/mve_vector_float2.c | 3 +- .../gcc.target/arm/mve/intrinsics/mve_vector_int.c | 3 +- .../arm/mve/intrinsics/mve_vector_int1.c | 3 +- .../arm/mve/intrinsics/mve_vector_int2.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint1.c | 3 +- .../arm/mve/intrinsics/mve_vector_uint2.c | 3 +- .../arm/mve/intrinsics/{vbicq_n_u16.c => sqrshr.c} | 9 +- .../gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c | 13 + .../gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c | 13 + .../arm/mve/intrinsics/{vdupq_n_s8.c => sqshl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => sqshll.c} | 9 +- .../arm/mve/intrinsics/{vdupq_n_s8.c => srshr.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s16.c => srshrl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_u32.c => uqrshl.c} | 9 +- .../gcc.target/arm/mve/intrinsics/uqrshll_sat48.c | 13 + .../gcc.target/arm/mve/intrinsics/uqrshll_sat64.c | 13 + .../arm/mve/intrinsics/{vdupq_n_s8.c => uqshl.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => uqshll.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => urshr.c} | 9 +- .../arm/mve/intrinsics/{vbicq_n_s32.c => urshrl.c} | 9 +- .../gcc.target/arm/mve/intrinsics/vabavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabavq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabdq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vabsq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadciq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadcq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadcq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vadcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvaq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvaq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddlvq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvaq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vaddvq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vandq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbicq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vbrsrq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_m_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot270_x_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_m_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_u8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_f16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_f32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_s16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_s32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_s8.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_u16.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_u32.c | 1 - .../arm/mve/intrinsics/vcaddq_rot90_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclsq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vclzq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmlaq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmlaq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmlaq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot180_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot180_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot180_m_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot180_m_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot270_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot270_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot270_m_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot270_m_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot90_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot90_f32.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot90_m_f16.c | 1 - .../arm/mve/intrinsics/vcmlaq_rot90_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpcsq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vcmpcsq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpcsq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_f16.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_f32.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vcmpeqq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpeqq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpgeq_m_n_f16.c | 1 - .../arm/mve/intrinsics/vcmpgeq_m_n_f32.c | 1 - .../arm/mve/intrinsics/vcmpgeq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vcmpgeq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgeq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpgtq_m_n_f16.c | 1 - .../arm/mve/intrinsics/vcmpgtq_m_n_f32.c | 1 - .../arm/mve/intrinsics/vcmpgtq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vcmpgtq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpgtq_s8.c | 1 - .../arm/mve/intrinsics/vcmphiq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vcmphiq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmphiq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpleq_m_n_f16.c | 1 - .../arm/mve/intrinsics/vcmpleq_m_n_f32.c | 1 - .../arm/mve/intrinsics/vcmpleq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vcmpleq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpleq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpltq_m_n_f16.c | 1 - .../arm/mve/intrinsics/vcmpltq_m_n_f32.c | 1 - .../arm/mve/intrinsics/vcmpltq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vcmpltq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpltq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmpneq_m_n_f16.c | 1 - .../arm/mve/intrinsics/vcmpneq_m_n_f32.c | 1 - .../arm/mve/intrinsics/vcmpneq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vcmpneq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vcmpneq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vcmpneq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmpneq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmulq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmulq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmulq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmulq_m_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot180_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot180_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot180_m_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot180_m_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot180_x_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot180_x_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot270_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot270_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot270_m_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot270_m_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot270_x_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot270_x_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot90_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot90_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot90_m_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot90_m_f32.c | 1 - .../arm/mve/intrinsics/vcmulq_rot90_x_f16.c | 1 - .../arm/mve/intrinsics/vcmulq_rot90_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmulq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcmulq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_s64.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_u64.c | 1 - .../gcc.target/arm/mve/intrinsics/vcreateq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp16q.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp16q_m.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp32q.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp32q_m.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp64q.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp64q_m.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp8q.c | 1 - .../gcc.target/arm/mve/intrinsics/vctp8q_m.c | 1 - .../arm/mve/intrinsics/vcvtaq_m_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtaq_m_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtaq_m_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtaq_m_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtaq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtaq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtaq_u16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtaq_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtaq_x_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtaq_x_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtaq_x_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtaq_x_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtbq_f16_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtbq_f32_f16.c | 1 - .../arm/mve/intrinsics/vcvtbq_m_f16_f32.c | 1 - .../arm/mve/intrinsics/vcvtbq_m_f32_f16.c | 1 - .../arm/mve/intrinsics/vcvtbq_x_f32_f16.c | 1 - .../arm/mve/intrinsics/vcvtmq_m_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtmq_m_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtmq_m_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtmq_m_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtmq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtmq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtmq_u16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtmq_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtmq_x_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtmq_x_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtmq_x_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtmq_x_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtnq_m_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtnq_m_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtnq_m_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtnq_m_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtnq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtnq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtnq_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtnq_x_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtnq_x_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtnq_x_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtnq_x_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtpq_m_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtpq_m_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtpq_m_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtpq_m_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtpq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtpq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtpq_u16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtpq_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtpq_x_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtpq_x_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtpq_x_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtpq_x_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_f16_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_f16_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_f32_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_f16_s16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_f16_u16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_f32_s32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_f16_s16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_f16_u16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_f32_s32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_n_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_m_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_m_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_n_f16_s16.c | 1 - .../arm/mve/intrinsics/vcvtq_n_f16_u16.c | 1 - .../arm/mve/intrinsics/vcvtq_n_f32_s32.c | 1 - .../arm/mve/intrinsics/vcvtq_n_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_n_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_n_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_n_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_n_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_s16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_s32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_u16_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvtq_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_f16_s16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_f16_u16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_f32_s32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_f16_s16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_f16_u16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_f32_s32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_f32_u32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_n_u32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_s16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_s32_f32.c | 1 - .../arm/mve/intrinsics/vcvtq_x_u16_f16.c | 1 - .../arm/mve/intrinsics/vcvtq_x_u32_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvttq_f16_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vcvttq_f32_f16.c | 1 - .../arm/mve/intrinsics/vcvttq_m_f16_f32.c | 1 - .../arm/mve/intrinsics/vcvttq_m_f32_f16.c | 1 - .../arm/mve/intrinsics/vcvttq_x_f32_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_m_n_u8.c | 1 - .../arm/mve/intrinsics/vddupq_m_wb_u16.c | 1 - .../arm/mve/intrinsics/vddupq_m_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_m_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_wb_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vddupq_x_wb_u16.c | 1 - .../arm/mve/intrinsics/vddupq_x_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vddupq_x_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdupq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vdwdupq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vdwdupq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_m_n_u8.c | 1 - .../arm/mve/intrinsics/vdwdupq_m_wb_u16.c | 1 - .../arm/mve/intrinsics/vdwdupq_m_wb_u32.c | 1 - .../arm/mve/intrinsics/vdwdupq_m_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_wb_u8.c | 1 - .../arm/mve/intrinsics/vdwdupq_x_n_u16.c | 1 - .../arm/mve/intrinsics/vdwdupq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vdwdupq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vdwdupq_x_wb_u16.c | 1 - .../arm/mve/intrinsics/vdwdupq_x_wb_u32.c | 1 - .../arm/mve/intrinsics/vdwdupq_x_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/veorq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmaq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmasq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmasq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmasq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmsq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmsq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmsq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vfmsq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c | 22 + .../gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c | 22 + .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhaddq_x_u8.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_m_s16.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_m_s32.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_m_s8.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_s16.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_s32.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_s8.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_x_s16.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_x_s32.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot270_x_s8.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_m_s16.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_m_s32.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_m_s8.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_s16.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_s32.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_s8.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_x_s16.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_x_s32.c | 1 - .../arm/mve/intrinsics/vhcaddq_rot90_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vhsubq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_m_n_u8.c | 1 - .../arm/mve/intrinsics/vidupq_m_wb_u16.c | 1 - .../arm/mve/intrinsics/vidupq_m_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_m_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_wb_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vidupq_x_wb_u16.c | 1 - .../arm/mve/intrinsics/vidupq_x_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vidupq_x_wb_u8.c | 1 - .../arm/mve/intrinsics/viwdupq_m_n_u16.c | 1 - .../arm/mve/intrinsics/viwdupq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_m_n_u8.c | 1 - .../arm/mve/intrinsics/viwdupq_m_wb_u16.c | 1 - .../arm/mve/intrinsics/viwdupq_m_wb_u32.c | 1 - .../arm/mve/intrinsics/viwdupq_m_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_wb_u8.c | 1 - .../arm/mve/intrinsics/viwdupq_x_n_u16.c | 1 - .../arm/mve/intrinsics/viwdupq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/viwdupq_x_n_u8.c | 1 - .../arm/mve/intrinsics/viwdupq_x_wb_u16.c | 1 - .../arm/mve/intrinsics/viwdupq_x_wb_u32.c | 1 - .../arm/mve/intrinsics/viwdupq_x_wb_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld1q_z_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld2q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vld4q_u8.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_s16.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_s32.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_s8.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_u16.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_u32.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_u8.c | 1 - .../mve/intrinsics/vldrbq_gather_offset_z_s16.c | 1 - .../mve/intrinsics/vldrbq_gather_offset_z_s32.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_z_s8.c | 1 - .../mve/intrinsics/vldrbq_gather_offset_z_u16.c | 1 - .../mve/intrinsics/vldrbq_gather_offset_z_u32.c | 1 - .../arm/mve/intrinsics/vldrbq_gather_offset_z_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrbq_z_u8.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_base_s64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_base_u64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_base_wb_s64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_base_wb_u64.c | 1 - .../mve/intrinsics/vldrdq_gather_base_wb_z_s64.c | 1 - .../mve/intrinsics/vldrdq_gather_base_wb_z_u64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_base_z_s64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_base_z_u64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_offset_s64.c | 1 - .../arm/mve/intrinsics/vldrdq_gather_offset_u64.c | 1 - .../mve/intrinsics/vldrdq_gather_offset_z_s64.c | 1 - .../mve/intrinsics/vldrdq_gather_offset_z_u64.c | 1 - .../intrinsics/vldrdq_gather_shifted_offset_s64.c | 1 - .../intrinsics/vldrdq_gather_shifted_offset_u64.c | 1 - .../vldrdq_gather_shifted_offset_z_s64.c | 1 - .../vldrdq_gather_shifted_offset_z_u64.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_f16.c | 1 - .../arm/mve/intrinsics/vldrhq_gather_offset_f16.c | 1 - .../arm/mve/intrinsics/vldrhq_gather_offset_s16.c | 1 - .../arm/mve/intrinsics/vldrhq_gather_offset_s32.c | 1 - .../arm/mve/intrinsics/vldrhq_gather_offset_u16.c | 1 - .../arm/mve/intrinsics/vldrhq_gather_offset_u32.c | 1 - .../mve/intrinsics/vldrhq_gather_offset_z_f16.c | 1 - .../mve/intrinsics/vldrhq_gather_offset_z_s16.c | 1 - .../mve/intrinsics/vldrhq_gather_offset_z_s32.c | 1 - .../mve/intrinsics/vldrhq_gather_offset_z_u16.c | 1 - .../mve/intrinsics/vldrhq_gather_offset_z_u32.c | 1 - .../intrinsics/vldrhq_gather_shifted_offset_f16.c | 1 - .../intrinsics/vldrhq_gather_shifted_offset_s16.c | 1 - .../intrinsics/vldrhq_gather_shifted_offset_s32.c | 1 - .../intrinsics/vldrhq_gather_shifted_offset_u16.c | 1 - .../intrinsics/vldrhq_gather_shifted_offset_u32.c | 1 - .../vldrhq_gather_shifted_offset_z_f16.c | 1 - .../vldrhq_gather_shifted_offset_z_s16.c | 1 - .../vldrhq_gather_shifted_offset_z_s32.c | 1 - .../vldrhq_gather_shifted_offset_z_u16.c | 1 - .../vldrhq_gather_shifted_offset_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_z_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_z_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_z_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_z_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrhq_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrwq_f32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_f32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_s32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_u32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_wb_f32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_wb_s32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_wb_u32.c | 1 - .../mve/intrinsics/vldrwq_gather_base_wb_z_f32.c | 1 - .../mve/intrinsics/vldrwq_gather_base_wb_z_s32.c | 1 - .../mve/intrinsics/vldrwq_gather_base_wb_z_u32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_z_f32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_z_s32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_base_z_u32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_offset_f32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_offset_s32.c | 1 - .../arm/mve/intrinsics/vldrwq_gather_offset_u32.c | 1 - .../mve/intrinsics/vldrwq_gather_offset_z_f32.c | 1 - .../mve/intrinsics/vldrwq_gather_offset_z_s32.c | 1 - .../mve/intrinsics/vldrwq_gather_offset_z_u32.c | 1 - .../intrinsics/vldrwq_gather_shifted_offset_f32.c | 1 - .../intrinsics/vldrwq_gather_shifted_offset_s32.c | 1 - .../intrinsics/vldrwq_gather_shifted_offset_u32.c | 1 - .../vldrwq_gather_shifted_offset_z_f32.c | 1 - .../vldrwq_gather_shifted_offset_z_s32.c | 1 - .../vldrwq_gather_shifted_offset_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrwq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrwq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrwq_z_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrwq_z_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vldrwq_z_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxaq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxaq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxavq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmaq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmaq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmavq_f32.c | 1 - .../arm/mve/intrinsics/vmaxnmavq_p_f16.c | 1 - .../arm/mve/intrinsics/vmaxnmavq_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmvq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxnmvq_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmaxvq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminaq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminaq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminaq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminaq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminavq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmaq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmaq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmavq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmavq_f32.c | 1 - .../arm/mve/intrinsics/vminnmavq_p_f16.c | 1 - .../arm/mve/intrinsics/vminnmavq_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmvq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmvq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vminvq_u8.c | 1 - .../arm/mve/intrinsics/vmladavaq_p_s16.c | 1 - .../arm/mve/intrinsics/vmladavaq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_p_s8.c | 1 - .../arm/mve/intrinsics/vmladavaq_p_u16.c | 1 - .../arm/mve/intrinsics/vmladavaq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaq_u8.c | 1 - .../arm/mve/intrinsics/vmladavaxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmladavaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vmladavaxq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavaxq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavq_u8.c | 1 - .../arm/mve/intrinsics/vmladavxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmladavxq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavxq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmladavxq_s8.c | 1 - .../arm/mve/intrinsics/vmlaldavaq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlaldavaq_p_s32.c | 1 - .../arm/mve/intrinsics/vmlaldavaq_p_u16.c | 1 - .../arm/mve/intrinsics/vmlaldavaq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavaq_u32.c | 1 - .../arm/mve/intrinsics/vmlaldavaxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlaldavaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vmlaldavaxq_p_u16.c | 1 - .../arm/mve/intrinsics/vmlaldavaxq_p_u32.c | 1 - .../arm/mve/intrinsics/vmlaldavaxq_s16.c | 1 - .../arm/mve/intrinsics/vmlaldavaxq_s32.c | 1 - .../arm/mve/intrinsics/vmlaldavq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlaldavq_p_s32.c | 1 - .../arm/mve/intrinsics/vmlaldavq_p_u16.c | 1 - .../arm/mve/intrinsics/vmlaldavq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavq_u32.c | 1 - .../arm/mve/intrinsics/vmlaldavxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlaldavxq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaldavxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlaq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlasq_n_u8.c | 1 - .../arm/mve/intrinsics/vmlsdavaq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsdavaq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaq_s8.c | 1 - .../arm/mve/intrinsics/vmlsdavaxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsdavaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vmlsdavaxq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavaxq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavq_s8.c | 1 - .../arm/mve/intrinsics/vmlsdavxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsdavxq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavxq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsdavxq_s8.c | 1 - .../arm/mve/intrinsics/vmlsldavaq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsldavaq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsldavaq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsldavaq_s32.c | 1 - .../arm/mve/intrinsics/vmlsldavaxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsldavaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vmlsldavaxq_s16.c | 1 - .../arm/mve/intrinsics/vmlsldavaxq_s32.c | 1 - .../arm/mve/intrinsics/vmlsldavq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsldavq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsldavq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsldavq_s32.c | 1 - .../arm/mve/intrinsics/vmlsldavxq_p_s16.c | 1 - .../arm/mve/intrinsics/vmlsldavxq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsldavxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmlsldavxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovlbq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovltq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovnbq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmovntq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulhq_x_u8.c | 1 - .../arm/mve/intrinsics/vmullbq_int_m_s16.c | 1 - .../arm/mve/intrinsics/vmullbq_int_m_s32.c | 1 - .../arm/mve/intrinsics/vmullbq_int_m_s8.c | 1 - .../arm/mve/intrinsics/vmullbq_int_m_u16.c | 1 - .../arm/mve/intrinsics/vmullbq_int_m_u32.c | 1 - .../arm/mve/intrinsics/vmullbq_int_m_u8.c | 1 - .../arm/mve/intrinsics/vmullbq_int_s16.c | 1 - .../arm/mve/intrinsics/vmullbq_int_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmullbq_int_s8.c | 1 - .../arm/mve/intrinsics/vmullbq_int_u16.c | 1 - .../arm/mve/intrinsics/vmullbq_int_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmullbq_int_u8.c | 1 - .../arm/mve/intrinsics/vmullbq_int_x_s16.c | 1 - .../arm/mve/intrinsics/vmullbq_int_x_s32.c | 1 - .../arm/mve/intrinsics/vmullbq_int_x_s8.c | 1 - .../arm/mve/intrinsics/vmullbq_int_x_u16.c | 1 - .../arm/mve/intrinsics/vmullbq_int_x_u32.c | 1 - .../arm/mve/intrinsics/vmullbq_int_x_u8.c | 1 - .../arm/mve/intrinsics/vmullbq_poly_m_p16.c | 1 - .../arm/mve/intrinsics/vmullbq_poly_m_p8.c | 1 - .../arm/mve/intrinsics/vmullbq_poly_p16.c | 1 - .../arm/mve/intrinsics/vmullbq_poly_p8.c | 1 - .../arm/mve/intrinsics/vmullbq_poly_x_p16.c | 1 - .../arm/mve/intrinsics/vmullbq_poly_x_p8.c | 1 - .../arm/mve/intrinsics/vmulltq_int_m_s16.c | 1 - .../arm/mve/intrinsics/vmulltq_int_m_s32.c | 1 - .../arm/mve/intrinsics/vmulltq_int_m_s8.c | 1 - .../arm/mve/intrinsics/vmulltq_int_m_u16.c | 1 - .../arm/mve/intrinsics/vmulltq_int_m_u32.c | 1 - .../arm/mve/intrinsics/vmulltq_int_m_u8.c | 1 - .../arm/mve/intrinsics/vmulltq_int_s16.c | 1 - .../arm/mve/intrinsics/vmulltq_int_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulltq_int_s8.c | 1 - .../arm/mve/intrinsics/vmulltq_int_u16.c | 1 - .../arm/mve/intrinsics/vmulltq_int_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulltq_int_u8.c | 1 - .../arm/mve/intrinsics/vmulltq_int_x_s16.c | 1 - .../arm/mve/intrinsics/vmulltq_int_x_s32.c | 1 - .../arm/mve/intrinsics/vmulltq_int_x_s8.c | 1 - .../arm/mve/intrinsics/vmulltq_int_x_u16.c | 1 - .../arm/mve/intrinsics/vmulltq_int_x_u32.c | 1 - .../arm/mve/intrinsics/vmulltq_int_x_u8.c | 1 - .../arm/mve/intrinsics/vmulltq_poly_m_p16.c | 1 - .../arm/mve/intrinsics/vmulltq_poly_m_p8.c | 1 - .../arm/mve/intrinsics/vmulltq_poly_p16.c | 1 - .../arm/mve/intrinsics/vmulltq_poly_p8.c | 1 - .../arm/mve/intrinsics/vmulltq_poly_x_p16.c | 1 - .../arm/mve/intrinsics/vmulltq_poly_x_p8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmulq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vmvnq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vnegq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vornq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vorrq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vpnot.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_s64.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_u64.c | 1 - .../gcc.target/arm/mve/intrinsics/vpselq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqabsq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqabsq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqabsq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqabsq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqabsq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqabsq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqaddq_u8.c | 1 - .../arm/mve/intrinsics/vqdmladhq_m_s16.c | 1 - .../arm/mve/intrinsics/vqdmladhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhq_s8.c | 1 - .../arm/mve/intrinsics/vqdmladhxq_m_s16.c | 1 - .../arm/mve/intrinsics/vqdmladhxq_m_s32.c | 1 - .../arm/mve/intrinsics/vqdmladhxq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmladhxq_s8.c | 1 - .../arm/mve/intrinsics/vqdmlahq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqdmlahq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqdmlahq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlahq_n_u8.c | 1 - .../arm/mve/intrinsics/vqdmlsdhq_m_s16.c | 1 - .../arm/mve/intrinsics/vqdmlsdhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhq_s8.c | 1 - .../arm/mve/intrinsics/vqdmlsdhxq_m_s16.c | 1 - .../arm/mve/intrinsics/vqdmlsdhxq_m_s32.c | 1 - .../arm/mve/intrinsics/vqdmlsdhxq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmlsdhxq_s8.c | 1 - .../arm/mve/intrinsics/vqdmulhq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqdmulhq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqdmulhq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulhq_s8.c | 1 - .../arm/mve/intrinsics/vqdmullbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqdmullbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqdmullbq_m_s16.c | 1 - .../arm/mve/intrinsics/vqdmullbq_m_s32.c | 1 - .../arm/mve/intrinsics/vqdmullbq_n_s16.c | 1 - .../arm/mve/intrinsics/vqdmullbq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmullbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmullbq_s32.c | 1 - .../arm/mve/intrinsics/vqdmulltq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqdmulltq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqdmulltq_m_s16.c | 1 - .../arm/mve/intrinsics/vqdmulltq_m_s32.c | 1 - .../arm/mve/intrinsics/vqdmulltq_n_s16.c | 1 - .../arm/mve/intrinsics/vqdmulltq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulltq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqdmulltq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovnbq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovntq_u32.c | 1 - .../arm/mve/intrinsics/vqmovunbq_m_s16.c | 1 - .../arm/mve/intrinsics/vqmovunbq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovunbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovunbq_s32.c | 1 - .../arm/mve/intrinsics/vqmovuntq_m_s16.c | 1 - .../arm/mve/intrinsics/vqmovuntq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovuntq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqmovuntq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqnegq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqnegq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqnegq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqnegq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqnegq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqnegq_s8.c | 1 - .../arm/mve/intrinsics/vqrdmladhq_m_s16.c | 1 - .../arm/mve/intrinsics/vqrdmladhq_m_s32.c | 1 - .../arm/mve/intrinsics/vqrdmladhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmladhq_s8.c | 1 - .../arm/mve/intrinsics/vqrdmladhxq_m_s16.c | 1 - .../arm/mve/intrinsics/vqrdmladhxq_m_s32.c | 1 - .../arm/mve/intrinsics/vqrdmladhxq_m_s8.c | 1 - .../arm/mve/intrinsics/vqrdmladhxq_s16.c | 1 - .../arm/mve/intrinsics/vqrdmladhxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmladhxq_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmlahq_n_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_n_u16.c | 1 - .../arm/mve/intrinsics/vqrdmlahq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmlahq_n_u8.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_n_s32.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_n_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_n_u16.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_n_u32.c | 1 - .../arm/mve/intrinsics/vqrdmlashq_n_u8.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhq_m_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhq_m_s32.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmlsdhq_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhxq_m_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhxq_m_s32.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhxq_m_s8.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhxq_s16.c | 1 - .../arm/mve/intrinsics/vqrdmlsdhxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmlsdhxq_s8.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_m_s16.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmulhq_m_s8.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrdmulhq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmulhq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrdmulhq_s8.c | 1 - .../arm/mve/intrinsics/vqrshlq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vqrshlq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vqrshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqrshlq_u8.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_m_n_u32.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_n_u16.c | 1 - .../arm/mve/intrinsics/vqrshrnbq_n_u32.c | 1 - .../arm/mve/intrinsics/vqrshrntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshrntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshrntq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vqrshrntq_m_n_u32.c | 1 - .../arm/mve/intrinsics/vqrshrntq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshrntq_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshrntq_n_u16.c | 1 - .../arm/mve/intrinsics/vqrshrntq_n_u32.c | 1 - .../arm/mve/intrinsics/vqrshrunbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshrunbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshrunbq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshrunbq_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshruntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshruntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqrshruntq_n_s16.c | 1 - .../arm/mve/intrinsics/vqrshruntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshlq_u8.c | 1 - .../arm/mve/intrinsics/vqshluq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqshluq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshluq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshluq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshluq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshluq_n_s8.c | 1 - .../arm/mve/intrinsics/vqshrnbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqshrnbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqshrnbq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vqshrnbq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrnbq_n_u32.c | 1 - .../arm/mve/intrinsics/vqshrntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqshrntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqshrntq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vqshrntq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrntq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrntq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqshrntq_n_u32.c | 1 - .../arm/mve/intrinsics/vqshrunbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqshrunbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqshrunbq_n_s16.c | 1 - .../arm/mve/intrinsics/vqshrunbq_n_s32.c | 1 - .../arm/mve/intrinsics/vqshruntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vqshruntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vqshruntq_n_s16.c | 1 - .../arm/mve/intrinsics/vqshruntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vqsubq_u8.c | 1 - .../arm/mve/intrinsics/vreinterpretq_f16.c | 1 - .../arm/mve/intrinsics/vreinterpretq_f32.c | 1 - .../arm/mve/intrinsics/vreinterpretq_s16.c | 1 - .../arm/mve/intrinsics/vreinterpretq_s32.c | 1 - .../arm/mve/intrinsics/vreinterpretq_s64.c | 1 - .../arm/mve/intrinsics/vreinterpretq_s8.c | 1 - .../arm/mve/intrinsics/vreinterpretq_u16.c | 1 - .../arm/mve/intrinsics/vreinterpretq_u32.c | 1 - .../arm/mve/intrinsics/vreinterpretq_u64.c | 1 - .../arm/mve/intrinsics/vreinterpretq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev16q_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev16q_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev16q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev16q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev16q_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev16q_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev32q_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrev64q_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrhaddq_x_u8.c | 1 - .../arm/mve/intrinsics/vrmlaldavhaq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhaq_p_u32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhaq_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhaq_u32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhaxq_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhq_p_u32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhq_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhq_u32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhxq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlaldavhxq_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhaq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhaq_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhaxq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhaxq_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhq_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhxq_p_s32.c | 1 - .../arm/mve/intrinsics/vrmlsldavhxq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrmulhq_x_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndaq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndmq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndnq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndpq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrndxq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshlq_x_u8.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vrshrnbq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrnbq_n_u32.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vrshrntq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrntq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vrshrq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbciq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsbcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c | 15 + .../gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c | 15 + .../intrinsics/{vabsq_m_s16.c => vshlcq_m_s16.c} | 12 +- .../intrinsics/{vabdq_x_s32.c => vshlcq_m_s32.c} | 12 +- .../mve/intrinsics/{vabsq_m_s8.c => vshlcq_m_s8.c} | 12 +- .../intrinsics/{vbicq_x_u16.c => vshlcq_m_u16.c} | 12 +- .../{vdwdupq_x_n_u16.c => vshlcq_m_u32.c} | 17 +- .../mve/intrinsics/{vabdq_x_u8.c => vshlcq_m_u8.c} | 12 +- .../gcc.target/arm/mve/intrinsics/vshlcq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlcq_u8.c | 1 - .../arm/mve/intrinsics/vshllbq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vshllbq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_n_u8.c | 1 - .../arm/mve/intrinsics/vshllbq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_s8.c | 1 - .../arm/mve/intrinsics/vshllbq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshllbq_x_n_u8.c | 1 - .../arm/mve/intrinsics/vshlltq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_s8.c | 1 - .../arm/mve/intrinsics/vshlltq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_n_u8.c | 1 - .../arm/mve/intrinsics/vshlltq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_s8.c | 1 - .../arm/mve/intrinsics/vshlltq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlltq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_r_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshlq_x_u8.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vshrnbq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrnbq_n_u32.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_s16.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_s32.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_u16.c | 1 - .../arm/mve/intrinsics/vshrntq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrntq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vshrq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsliq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsriq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst1q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst2q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vst4q_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_p_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_s8.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s16.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s32.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_s8.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u16.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u32.c | 1 - .../mve/intrinsics/vstrbq_scatter_offset_p_u8.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s16.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s32.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_s8.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u16.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u32.c | 1 - .../arm/mve/intrinsics/vstrbq_scatter_offset_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrbq_u8.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_p_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_p_u64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_base_u64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_p_s64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_p_u64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_s64.c | 1 - .../mve/intrinsics/vstrdq_scatter_base_wb_u64.c | 1 - .../mve/intrinsics/vstrdq_scatter_offset_p_s64.c | 1 - .../mve/intrinsics/vstrdq_scatter_offset_p_u64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_offset_s64.c | 1 - .../arm/mve/intrinsics/vstrdq_scatter_offset_u64.c | 1 - .../vstrdq_scatter_shifted_offset_p_s64.c | 1 - .../vstrdq_scatter_shifted_offset_p_u64.c | 1 - .../intrinsics/vstrdq_scatter_shifted_offset_s64.c | 1 - .../intrinsics/vstrdq_scatter_shifted_offset_u64.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_s32.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_f16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_f16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_s16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_s32.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_u16.c | 1 - .../mve/intrinsics/vstrhq_scatter_offset_p_u32.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_s16.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_s32.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_u16.c | 1 - .../arm/mve/intrinsics/vstrhq_scatter_offset_u32.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_f16.c | 1 - .../vstrhq_scatter_shifted_offset_p_f16.c | 1 - .../vstrhq_scatter_shifted_offset_p_s16.c | 1 - .../vstrhq_scatter_shifted_offset_p_s32.c | 1 - .../vstrhq_scatter_shifted_offset_p_u16.c | 1 - .../vstrhq_scatter_shifted_offset_p_u32.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_s16.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_s32.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_u16.c | 1 - .../intrinsics/vstrhq_scatter_shifted_offset_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrhq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_p_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_p_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_p_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_f32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_p_f32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_p_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_p_u32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_base_u32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_p_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_p_s32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_p_u32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_s32.c | 1 - .../mve/intrinsics/vstrwq_scatter_base_wb_u32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_offset_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_offset_p_f32.c | 1 - .../mve/intrinsics/vstrwq_scatter_offset_p_s32.c | 1 - .../mve/intrinsics/vstrwq_scatter_offset_p_u32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_offset_s32.c | 1 - .../arm/mve/intrinsics/vstrwq_scatter_offset_u32.c | 1 - .../intrinsics/vstrwq_scatter_shifted_offset_f32.c | 1 - .../vstrwq_scatter_shifted_offset_p_f32.c | 1 - .../vstrwq_scatter_shifted_offset_p_s32.c | 1 - .../vstrwq_scatter_shifted_offset_p_u32.c | 1 - .../intrinsics/vstrwq_scatter_shifted_offset_s32.c | 1 - .../intrinsics/vstrwq_scatter_shifted_offset_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vstrwq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_m_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_f32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_n_u8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_s8.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u16.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u32.c | 1 - .../gcc.target/arm/mve/intrinsics/vsubq_x_u8.c | 1 - .../arm/mve/intrinsics/vuninitializedq_float.c | 1 - .../arm/mve/intrinsics/vuninitializedq_float1.c | 1 - .../arm/mve/intrinsics/vuninitializedq_int.c | 1 - .../arm/mve/intrinsics/vuninitializedq_int1.c | 1 - gcc/testsuite/gcc.target/arm/mve/mve.exp | 2 + gcc/testsuite/gcc.target/i386/pr94283.c | 5 + gcc/testsuite/gfortran.dg/pr93365.f90 | 15 + gcc/testsuite/gfortran.dg/pr93600_1.f90 | 9 + gcc/testsuite/gfortran.dg/pr93600_2.f90 | 10 + gcc/testsuite/gfortran.dg/pr94285.f90 | 5 + gcc/testsuite/jit.dg/all-non-failing-tests.h | 10 + gcc/testsuite/jit.dg/test-long-string-literal.c | 54 + gcc/testsuite/lib/target-supports.exp | 12 +- gcc/tree-if-conv.c | 14 +- gcc/tree-ssa-loop-manip.c | 12 +- gcc/tree-vect-slp.c | 54 +- gcc/tree.c | 15 + include/ChangeLog | 5 + include/plugin-api.h | 65 +- libgomp/ChangeLog | 6 + libgomp/target.c | 5 +- 2468 files changed, 4831 insertions(+), 2797 deletions(-) create mode 100644 gcc/testsuite/g++.dg/ubsan/pr91993.C create mode 100644 gcc/testsuite/g++.dg/warn/Wconversion-pr91993.C create mode 100644 gcc/testsuite/g++.dg/warn/Wnoexcept2.C create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr94144.c create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr94238.c create mode 100644 gcc/testsuite/gcc.dg/pr94277.c create mode 100644 gcc/testsuite/gcc.dg/pr94286.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => asrl.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => lsll.c} (50%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u16.c => sqrshr.c} (51%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/sqrshrl_sat64.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => sqshl.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => sqshll.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => srshr.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s16.c => srshrl.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_u32.c => uqrshl.c} (51%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat48.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/uqrshll_sat64.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdupq_n_s8.c => uqshl.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => uqshll.c} (53%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => urshr.c} (54%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_n_s32.c => urshrl.c} (53%) create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vgetq_lane_u8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_f32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_s8.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u16.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u32.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u64.c create mode 100644 gcc/testsuite/gcc.target/arm/mve/intrinsics/vsetq_lane_u8.c copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s16.c => vshlcq_m_s16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_x_s32.c => vshlcq_m_s32.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabsq_m_s8.c => vshlcq_m_s8.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vbicq_x_u16.c => vshlcq_m_u16.c} (51%) copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vdwdupq_x_n_u16.c => vshlcq_m_u3 [...] copy gcc/testsuite/gcc.target/arm/mve/intrinsics/{vabdq_x_u8.c => vshlcq_m_u8.c} (51%) create mode 100644 gcc/testsuite/gcc.target/i386/pr94283.c create mode 100644 gcc/testsuite/gfortran.dg/pr93365.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93600_2.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr94285.f90 create mode 100644 gcc/testsuite/jit.dg/test-long-string-literal.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig updated (2957d8d054 -> a64fafb545)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig in repository toolchain/ci/binutils-gdb. from 2957d8d054 Automatic date update in version.in adds 5935fd1530 gdb/testsuite: Remove hard coded addresses from expected results adds 5e737279c6 i386msdos uninitialised read adds cf28cfef60 ECOFF archive uninitialised read adds fdde2fb60c Mention .tdata in comment in _bfd_elf_tls_setup() adds 0636b24556 Avoid trigger an assertion failure in the STABS parser by re [...] adds 1ce0847daa Automatic date update in version.in adds 5a814d6d96 readelf memory leak in process_mips_specific adds 65109548f8 Overlarge allocation in _bfd_generic_read_ar_hdr_mag adds a64fafb545 [gdb] Print user for maint info psymtabs No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 22 ++++++++++ bfd/archive.c | 15 +++++-- bfd/ecoff.c | 35 +++++++++++----- bfd/elflink.c | 4 +- bfd/i386msdos.c | 14 ++++--- bfd/version.h | 2 +- binutils/ChangeLog | 25 ++++++++++++ binutils/readelf.c | 10 ++++- binutils/wrstabs.c | 56 +++++++++++++++++--------- gdb/ChangeLog | 4 ++ gdb/psymtab.c | 5 +++ gdb/testsuite/ChangeLog | 5 +++ gdb/testsuite/gdb.fortran/mixed-lang-stack.exp | 4 +- ld/ChangeLog | 7 ++++ ld/Makefile.am | 2 + ld/Makefile.in | 3 ++ ld/po/BLD-POTFILES.in | 1 + 17 files changed, 170 insertions(+), 44 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig updated (252674a9 -> 6fdf98e4)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-defconfig in repository toolchain/ci/base-artifacts. discards 252674a9 0: update: binutils-gcc-linux: boot new 6fdf98e4 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (252674a9) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-ma [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 162 +- 02-prepare_abe/console.log | 408 +- 03-build_abe-binutils/console.log | 11627 +++++----- 04-build_abe-stage1/console.log | 19859 +++++++++-------- 05-build_linux/console.log | 3296 +-- 06-boot_linux/console.log | 478 +- 07-check_regression/console.log | 2 +- 07-check_regression/results.regressions | 2 +- 08-update_baseline/console.log | 2 +- 08-update_baseline/results.regressions | 2 +- console.log | 35834 +++++++++++++++--------------- jenkins/manifest.sh | 16 +- 12 files changed, 35872 insertions(+), 35816 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allnoconfig updated (b43ae21e608 -> 180d211770a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allnoconfig in repository toolchain/ci/llvm-project. from b43ae21e608 Fix all-reduce int tests by host-registering memrefs. adds 6081ccf4a3b Apply function attributes through array declarators adds 72d1419bfba [InstCombine] Add CTPOP -> CTTZ simplifications (PR43513) adds b259ce998f5 [llvm-readobj] Derive dynamic symtab size from DT_HASH adds b8a2cf6b5b9 [SCCP] Extend test coverage in conditions-ranges.ll to fals [...] adds 16d2065cfc8 [InstCombine] Add ub-safe negation patterns (PR27817) adds 3ba550a05af [Alignment][NFC] Use TFL::getStackAlign() adds 32851f8d635 [Alignment][NFC] Deprecate VectorUtils::getAlignment adds 9adc7fc3cdf [SystemZ] Perform instruction shortening for fused fp ops. adds fa0320dd8d5 Add ParsedAttrInfo::handleDeclAttribute adds 5eeea337bec [VectorCombine] add more tests for extract-extract patterns; NFC adds 78e2a3c6784 [clang-format] Reflow long C# generic type constraints correctly adds 7693a9b9314 [clang-tidy] Fix RenamerClangTidy handling qualified TypeLocs adds 0eeee83d751 [VectorUtils] move x86's scaleShuffleMask to generic VectorUtils adds 33942d18b11 [SCCP] Precommit additional range propagation test. adds 24698e526f6 Implement wave32 DWARF register mapping adds 6a4905ae2d6 [lldb] Mark expressions that couldn't be parsed or executed [...] adds 60bad941a1c [Analyzer] Iterator Modeling - Model `std::advance()`, `std [...] adds 5e1a026c2d8 [clang-format] Do not indent C# array initialisers as conti [...] adds fdcb2710553 [InstCombine] Limit CTPOP -> CTTZ simplifications to one use adds f383fb40b17 Remove legacy CMake targets for libcxx and libcxxabi adds 9228a9efc6c [lldb/Target] Initialize new targets environment variables [...] adds cd7b45057ca [lldb/API] Make Launch(Simple) use args and env from target [...] adds b4a6e63ea12 [lldb/Target] Rework the way the inferior environment is created adds 04d48111bf9 Revert "Remove legacy CMake targets for libcxx and libcxxabi" adds db3f3f0240b AMDGPU/GlobalISel: Add some oversized G_IMPLICIT_DEF tests adds 0444d16a16c [GlobalISel] Add generic opcodes for saturating add/subtract adds a711a3a4603 [Syntax] Build mapping from AST to syntax tree nodes adds f3bf4b05c2a [Attributor][NFC] clang-format Attributor.{h,cpp} adds 0995001ce57 [Attributor][NFC] Predetermine the module before verification adds 54ec9b54f6b [Attributor] Unify handling of must-tail calls adds 68fed270674 [Attributor] Handle calls in AAValueConstantRange properly adds c57689bef26 [Attributor][NFC] Copy llvm::function_ref, don't use references adds ebf83c36e29 [Analysis] simplify code for scaleShuffleMask adds 5ff5ddd0adc [Win64] Insert int3 into trailing empty BBs adds 596da62d21e Add support for custom op parser/printer hooks to know abou [...] adds 278c00c4ff8 [libc++] [NFC] Test that correct value category is used in [...] adds b670ab7b6b3 recommit 1b978ddba05c [CUDA][HIP][OpenMP] Emit deferred dia [...] adds 57b8a407493 [analyzer][NFC] Tie CheckerRegistry to CheckerManager, allo [...] adds 0ca19efe7b5 Add AMDGPU MC unittests only when AMDGPU target is being built adds 7e10581e8c1 [lldb/testsuite] Skip part of TestSettings.py on windows adds 3c84aca9b35 [libc++] Bump Clang support for Clang 4 adds e10af89d991 [ARM] Extra VMOVN and VMULL tests. NFC adds c1f8595fe5b [Support] Silence warning in Path unittests when compiling [...] adds ccc0d351817 [Analyzer] IteratorRangeChecker verify `std::advance()`, `s [...] adds 0a076f2660b [ELF][test] Clean text-section-prefix.s adds ff2f5097ed4 [Attributor] Fold single-use variable into assert adds 3f51c5d9caa [OpenMPOpt][FIX] Resolve OpenMP runtime call type mismatches adds 9d38f98dc30 [OpenMPOpt] Validate declaration types against the expected types adds ae37e2285d2 [lldb/Reproducers] Mark reproducer test directory as unsupp [...] adds 552bd477f8e [gn build] Port 24698e526f619271705fe72bcaa928be9bc82484 adds ae044467ede [openmp][runtime] Fixed hang for explicit task inside a taskloop. adds 63828a35da6 [OPENMP50]Bassic support for exclusive clause. adds 04336ada175 [clang-format] No space inserted between commas in C# adds ff042de67d5 [gn build] Port 24698e526f619271705fe72bcaa928be9bc82484. F [...] adds 9607a119bd5 [gn build] Port 57b8a407493 adds 9e33c096476 [ELF] Keep orphan section names (.rodata.foo .text.foo) unc [...] adds a1fe6beb1ec [InstCombine] remove one-use check for ctpop -> cttz adds 42d8f48ccfc Fix a warning building on my machine, NFC. warning: unused [...] adds 1b9cd51d55b [CMake] Fix AMDGPUTests -DBUILD_SHARED_LIBS=on builds and t [...] adds a567d6809e1 [DataFormatters] Add formatter for libc++ std::unique_ptr adds 04f2b717d23 [mlir] Fix unsafe create operation in GreedyPatternRewriter adds 328b72dd820 [Support] Fix clang warning in widenPath NFC adds aa63eb6a461 GlobalISel: Add computeKnownBitsForTargetInstr adds 58f843a5b3d GlobalISel: Prepare to allow other target unit tests adds 2ad5fc1d915 AMDGPU/GlobalISel: Implement computeNumSignBitsForTargetInstr adds 56abcfad70e Revert "[analyzer][NFC] Tie CheckerRegistry to CheckerManag [...] adds 75add0b2ef1 [gn build] Port 56abcfad70e adds 896335bfb8e Don't export symbols from clang/opt/llc if plugins are disabled. adds 6b57d7f57d2 [OpenMP][NFC] Reduce instantiation time with different data [...] adds 55eca2853e4 [OpenMP][NFC] Minimize memory usage and copying of `OMPTraitInfo`s adds 43d98a0ecfe Allow replacing intrinsic operands with variables adds cfaa84e1a67 Fix "previously declared as a struct" warning adds 5f5fb56c68e [compiler-rt] Intercept the uname() function adds 67d67ebe8f2 Internal expressions shouldn't increment the result variabl [...] adds a650d555fc2 [Attributor][NFC] Refactorings and typos in doc adds f2f96eb605b [llvm-objcopy] Improve tool selection logic to recognize ll [...] adds 7bf871c39f7 [analyzer][NFC] Move the text output type to its own file, [...] adds b20a1d840f0 GVNSink: Allow handling addrspacecast adds 3f533006ba8 AMDGPU: Emit llvm.fshr for __builtin_amdgcn_alignbit adds 5896e2df45d [Clang] Fix HIP tests when running on Windows with the LLVM [...] adds 66073953a5c AMDGPU: Allow vectorization of round intrinsic adds 1a4421a5e86 [analyzer] ConstraintManager - use EXPENSIVE_CHECKS instead [...] adds defd96f1e36 [gn build] Port 7bf871c39f7 adds f3018068517 [lld] Enabling loading LLVM pass plugins adds b6ae8937e03 [lldb/PlatformDarwin] Always delete destination file first [...] adds a20862307ff Improve module.pcm lock file performance on machines with h [...] adds 502915c619a PR45142: 'template ~X<T>' is ill-formed; reject it rather t [...] adds f0990e104b0 [PowerPC]: e500 target can't use lwsync, use msync instead adds 1236eb6c31f [OPENMP50]Add 'default' modifier in reduction clauses. adds 564ece93b83 [MLIR] Insert loop.yield to IfOp regions only if it's void. adds de0758e5bd9 [MLIR] Fixes for BUILD_SHARED_LIBS=on adds c5c4109071c [examples] Fixes for BUILD_SHARED_LIBS=on adds bfa9ce1cb27 [PowerPC] Improve handling of some BUILD_VECTOR nodes adds 2b4027f2b8d [analyzer] Delete unneeded headers and using after D76509 f [...] adds 987f153929e [msan] Fix sigaltstack false positive. adds 5bd06118c2a Update documentation for __builtin_operator_new and __built [...] adds 2136d17d8de [compiler-rt] Add ConsumeRandomLengthString() version witho [...] adds edf6a19adf7 [clangd] Rename theia-derived semantic highlighting protocol. NFC adds 02187ed45a4 [GlobalISel] Combine G_SELECTs of the form (cond ? x : x) into x adds f09f4b26762 [OpenMPOpt] Initialize value to avoid use of uninitialized memory adds 4a219bf7ff6 Fix a bug in the .mlir lexer, where a \0 character in a fil [...] adds fd868f517d2 Create basic SBEnvironment class adds 318a0caf9ac Revert "Create basic SBEnvironment class" adds 8140f6bcde4 scudo: Create a public include directory. NFCI. adds 42df3e29856 [VirtualFileSystem] Add unit test for vfs::YAMLVFSWriter adds 8d46bfa8084 [mlir] [VectorOps] A "reference" lowering of vector.transpo [...] adds 78e61496bc4 [MLIR][NFC] loop tiling - improve comments / naming adds ca69be218c0 Create basic SBEnvironment class adds 98fa6150028 [MLIR] move loopUnrollJamBy*Factor to loop transforms utils adds 49e5a97ec36 Add an algorithm for performing "optimal" layout of a struct. adds 816ad48c820 [NFC][RUIP] Small debug output refine adds dab219eedd2 [libc] Enable llvmlibc clang-tidy checks adds 20d704a75ed [objc_direct] also go through implementations when looking [...] adds e79b1ab65b8 Make test more flexible for when the variable is renamed in [...] adds bec785ab704 [MLIR][NFC] flat affine constraints - refactor to share, renames adds b7cd291c154 [GlobalOpt] Treat null-check of loaded value as use of glob [...] adds d0f4af8f308 [Coroutines] Insert lifetime intrinsics even O0 is used adds a44de12ab21 [Coroutines] Also check lifetime intrinsic for local variab [...] adds 18e1a59eed5 Fix another instance where a variable was renamed in the ge [...] adds 9d07d91fb6c [PowerPC] fix a typo in commit 3f85134d710c adds e0279d720a6 [lldb-vscode] Add missing launchCommands entry in the package.json adds 733edf9750a [AST] Add RecoveryExpr to retain expressions on semantic errors adds 6f86e6bf404 [ARM][MVE] Add target flag for narrowing insts adds 94cacebccad [ARM][LowOverheadLoops] Add checks for narrowing adds 1232cfa385c [ARM] Don't split trunc stores that can be better handled as VMOVN new 080d046c91d [ARM][CMSE] Implement CMSE attributes new 180d211770a tsan: Adding releaseAcquire() to ThreadClock The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../clang-tidy/utils/RenamerClangTidyCheck.cpp | 9 +- clang-tools-extra/clangd/ClangdLSPServer.cpp | 16 +- clang-tools-extra/clangd/ClangdLSPServer.h | 3 +- clang-tools-extra/clangd/ClangdServer.cpp | 16 +- clang-tools-extra/clangd/ClangdServer.h | 2 +- clang-tools-extra/clangd/Protocol.cpp | 11 +- clang-tools-extra/clangd/Protocol.h | 21 +- clang-tools-extra/clangd/SemanticHighlighting.cpp | 7 +- clang-tools-extra/clangd/SemanticHighlighting.h | 5 +- .../clangd/unittests/SemanticHighlightingTests.cpp | 8 +- .../bugprone-reserved-identifier-invert.cpp | 2 +- .../checkers/readability-identifier-naming.cpp | 13 + clang/docs/ClangPlugins.rst | 47 ++ clang/docs/InternalsManual.rst | 14 +- clang/docs/LanguageExtensions.rst | 27 +- clang/include/clang/AST/ASTContext.h | 9 + clang/include/clang/AST/ComputeDependence.h | 2 + clang/include/clang/AST/Expr.h | 63 ++ clang/include/clang/AST/OpenMPClause.h | 122 ++- clang/include/clang/AST/RecursiveASTVisitor.h | 8 + clang/include/clang/AST/Type.h | 48 +- clang/include/clang/AST/TypeProperties.td | 9 +- clang/include/clang/Basic/Attr.td | 71 +- clang/include/clang/Basic/AttrDocs.td | 25 + clang/include/clang/Basic/DiagnosticDriverKinds.td | 3 + clang/include/clang/Basic/DiagnosticParseKinds.td | 2 + clang/include/clang/Basic/DiagnosticSemaKinds.td | 7 + clang/include/clang/Basic/LangOptions.def | 2 + clang/include/clang/Basic/OpenMPKinds.def | 9 + clang/include/clang/Basic/OpenMPKinds.h | 7 + clang/include/clang/Basic/StmtNodes.td | 1 + clang/include/clang/CodeGen/CGFunctionInfo.h | 10 +- clang/include/clang/Driver/CC1Options.td | 5 + clang/include/clang/Parse/Parser.h | 2 +- clang/include/clang/Sema/ExternalSemaSource.h | 9 + .../clang/Sema/MultiplexExternalSemaSource.h | 9 + clang/include/clang/Sema/ParsedAttr.h | 14 +- clang/include/clang/Sema/Sema.h | 70 +- clang/include/clang/Serialization/ASTBitCodes.h | 8 +- clang/include/clang/Serialization/ASTReader.h | 9 + .../include/clang/Serialization/ASTRecordReader.h | 4 +- .../include/clang/Serialization/ASTRecordWriter.h | 2 +- .../include/clang/StaticAnalyzer/Core/Analyses.def | 70 +- .../Core/PathSensitive/ConstraintManager.h | 6 +- clang/include/clang/Tooling/Syntax/Tree.h | 7 +- clang/lib/AST/ASTContext.cpp | 8 + clang/lib/AST/AttrImpl.cpp | 2 +- clang/lib/AST/ComputeDependence.cpp | 9 + clang/lib/AST/Expr.cpp | 29 + clang/lib/AST/ExprClassification.cpp | 1 + clang/lib/AST/ExprConstant.cpp | 1 + clang/lib/AST/ItaniumMangle.cpp | 3 +- clang/lib/AST/OpenMPClause.cpp | 43 +- clang/lib/AST/StmtPrinter.cpp | 11 + clang/lib/AST/StmtProfile.cpp | 5 + clang/lib/AST/TypePrinter.cpp | 3 + clang/lib/Basic/OpenMPKinds.cpp | 19 +- clang/lib/CodeGen/BackendUtil.cpp | 10 +- clang/lib/CodeGen/CGBuiltin.cpp | 7 + clang/lib/CodeGen/CGCall.cpp | 7 + clang/lib/CodeGen/CGOpenMPRuntime.cpp | 2 +- clang/lib/CodeGen/CGStmtOpenMP.cpp | 1 + clang/lib/Driver/ToolChains/Clang.cpp | 18 +- clang/lib/Format/ContinuationIndenter.cpp | 19 +- clang/lib/Format/ContinuationIndenter.h | 7 +- clang/lib/Format/TokenAnnotator.cpp | 7 + clang/lib/Format/UnwrappedLineParser.cpp | 7 +- clang/lib/Frontend/CompilerInvocation.cpp | 2 + clang/lib/Parse/ParseExpr.cpp | 78 +- clang/lib/Parse/ParseExprCXX.cpp | 18 +- clang/lib/Parse/ParseOpenMP.cpp | 43 +- clang/lib/Sema/MultiplexExternalSemaSource.cpp | 6 + clang/lib/Sema/ParsedAttr.cpp | 3 +- clang/lib/Sema/Sema.cpp | 177 +++-- clang/lib/Sema/SemaCUDA.cpp | 19 - clang/lib/Sema/SemaDecl.cpp | 34 +- clang/lib/Sema/SemaDeclAttr.cpp | 183 +---- clang/lib/Sema/SemaDeclObjC.cpp | 95 ++- clang/lib/Sema/SemaExceptionSpec.cpp | 1 + clang/lib/Sema/SemaExpr.cpp | 41 +- clang/lib/Sema/SemaOpenMP.cpp | 233 +++--- clang/lib/Sema/SemaTemplateInstantiateDecl.cpp | 3 +- clang/lib/Sema/SemaType.cpp | 46 ++ clang/lib/Sema/TreeTransform.h | 75 +- clang/lib/Sema/UsedDeclVisitor.h | 12 + clang/lib/Serialization/ASTReader.cpp | 39 +- clang/lib/Serialization/ASTReaderDecl.cpp | 2 +- clang/lib/Serialization/ASTReaderStmt.cpp | 18 + clang/lib/Serialization/ASTWriter.cpp | 27 +- clang/lib/Serialization/ASTWriterDecl.cpp | 8 +- clang/lib/Serialization/ASTWriterStmt.cpp | 10 + .../StaticAnalyzer/Checkers/IteratorModeling.cpp | 301 +++++--- .../Checkers/IteratorRangeChecker.cpp | 70 +- clang/lib/StaticAnalyzer/Core/CMakeLists.txt | 2 + clang/lib/StaticAnalyzer/Core/ExprEngine.cpp | 1 + clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp | 47 +- clang/lib/StaticAnalyzer/Core/PlistDiagnostics.cpp | 25 +- clang/lib/StaticAnalyzer/Core/SarifDiagnostics.cpp | 8 +- clang/lib/StaticAnalyzer/Core/TextDiagnostics.cpp | 148 ++++ .../StaticAnalyzer/Frontend/AnalysisConsumer.cpp | 169 +---- clang/lib/StaticAnalyzer/Frontend/CMakeLists.txt | 2 - clang/lib/Tooling/Syntax/BuildTree.cpp | 289 +++++--- clang/lib/Tooling/Syntax/Mutations.cpp | 2 +- clang/lib/Tooling/Syntax/Tree.cpp | 23 +- clang/test/AST/ast-dump-arm-attr.c | 4 + clang/test/AST/ast-dump-expr-errors.cpp | 46 ++ clang/test/AST/ast-dump-recovery.cpp | 85 +++ .../Analysis/Inputs/system-header-simulator-cxx.h | 67 +- clang/test/Analysis/iterator-modelling.cpp | 68 ++ clang/test/Analysis/iterator-range.cpp | 417 +++++++++++ clang/test/CXX/drs/dr4xx.cpp | 8 +- clang/test/CodeGen/arm-cmse-attr.c | 43 ++ clang/test/CodeGen/arm-cmse-call.c | 77 ++ clang/test/CodeGen/attr-noreturn.c | 10 + .../test/CodeGenCoroutines/coro-always-inline.cpp | 54 ++ clang/test/CodeGenOpenCL/builtins-amdgcn.cl | 2 +- clang/test/Driver/hip-device-compile.hip | 4 +- clang/test/Driver/hip-toolchain-no-rdc.hip | 8 +- clang/test/Driver/hip-toolchain-rdc.hip | 2 +- clang/test/Driver/ropi-rwpi.c | 13 + clang/test/Driver/save-temps.c | 8 + clang/test/Index/getcursor-recovery.cpp | 16 + ...pragma-attribute-supported-attributes-list.test | 1 + clang/test/OpenMP/declare_target_messages.cpp | 12 +- .../OpenMP/nvptx_target_exceptions_messages.cpp | 4 +- clang/test/OpenMP/parallel_ast_print.cpp | 24 +- clang/test/OpenMP/parallel_reduction_codegen.cpp | 26 +- clang/test/OpenMP/parallel_reduction_messages.c | 13 +- clang/test/OpenMP/scan_ast_print.cpp | 4 +- clang/test/OpenMP/scan_messages.cpp | 30 +- clang/test/Sema/arm-cmse.c | 30 + clang/test/Sema/arm-no-cmse.c | 7 + clang/test/Sema/attr-noreturn.c | 31 + clang/test/SemaCUDA/bad-calls-on-same-line.cu | 4 +- clang/test/SemaCUDA/call-device-fn-from-host.cu | 4 +- clang/test/SemaCUDA/call-host-fn-from-device.cu | 4 +- clang/test/SemaCUDA/openmp-target.cu | 4 +- clang/test/SemaCUDA/trace-through-global.cu | 2 +- clang/test/SemaCXX/arm-cmse.cpp | 5 + clang/test/SemaCXX/pseudo-destructors.cpp | 5 +- clang/test/SemaObjC/method-direct-one-definition.m | 11 + clang/test/SemaObjC/method-direct.m | 4 + .../test/SemaTemplate/recovery-tree-transform.cpp | 4 + clang/tools/driver/CMakeLists.txt | 2 +- clang/tools/libclang/CIndex.cpp | 3 + clang/tools/libclang/CXCursor.cpp | 1 + clang/unittests/Format/FormatTestCSharp.cpp | 22 + clang/utils/TableGen/ClangAttrEmitter.cpp | 23 +- compiler-rt/include/fuzzer/FuzzedDataProvider.h | 5 + .../fuzzer/tests/FuzzedDataProviderUnittest.cpp | 18 +- compiler-rt/lib/msan/msan_interceptors.cpp | 25 - .../sanitizer_common_interceptors.inc | 39 +- .../lib/sanitizer_common/sanitizer_linux_s390.cpp | 13 +- .../sanitizer_platform_interceptors.h | 2 + compiler-rt/lib/scudo/standalone/CMakeLists.txt | 5 +- compiler-rt/lib/scudo/standalone/combined.h | 3 +- compiler-rt/lib/scudo/standalone/flags.cpp | 3 +- .../standalone/{ => include/scudo}/interface.h | 12 +- .../lib/scudo/standalone/tests/CMakeLists.txt | 1 + compiler-rt/lib/tsan/go/test.c | 2 + compiler-rt/lib/tsan/go/tsan_go.cpp | 4 + compiler-rt/lib/tsan/rtl/tsan_clock.cpp | 38 + compiler-rt/lib/tsan/rtl/tsan_clock.h | 1 + compiler-rt/lib/tsan/rtl/tsan_rtl.h | 2 + compiler-rt/lib/tsan/rtl/tsan_rtl_mutex.cpp | 21 + compiler-rt/lib/tsan/rtl/tsan_stat.h | 1 + compiler-rt/test/msan/sigaltstack.cpp | 7 +- .../test/sanitizer_common/TestCases/Posix/uname.c | 13 + libc/src/.clang-tidy | 6 + libc/src/math/round_redirector.cpp | 2 + libcxx/docs/index.rst | 2 +- .../new.delete.array/new_align_val_t.pass.cpp | 3 - .../new_align_val_t_nothrow.pass.cpp | 3 - .../new_align_val_t_nothrow_replace.pass.cpp | 2 - .../new_align_val_t_replace.pass.cpp | 3 - .../new.delete.single/new_align_val_t.pass.cpp | 3 - .../new_align_val_t_nothrow.pass.cpp | 3 - .../new_align_val_t_nothrow_replace.pass.cpp | 3 - .../new_align_val_t_replace.pass.cpp | 3 - .../allocator.adaptor.members/construct.pass.cpp | 23 + libcxx/utils/libcxx/test/config.py | 4 - libcxx/www/cxx1z_status.html | 2 +- lld/ELF/Writer.cpp | 26 +- lld/test/ELF/linkerscript/data-commands-gc.s | 2 +- lld/test/ELF/linkerscript/icf-output-sections.s | 14 +- lld/test/ELF/linkerscript/linkorder.s | 4 +- lld/test/ELF/linkerscript/linkorder2.s | 2 +- lld/test/ELF/linkerscript/memory3.s | 2 +- lld/test/ELF/linkerscript/orphan-report.s | 2 +- .../linkerscript/symbol-assign-many-passes2.test | 2 +- lld/test/ELF/mips-npic-call-pic-script.s | 34 +- lld/test/ELF/shuffle-sections-init-fini.s | 4 +- lld/test/ELF/text-section-prefix.s | 54 +- lld/tools/lld/CMakeLists.txt | 4 + lld/tools/lld/lld.cpp | 1 + lldb/bindings/headers.swig | 1 + lldb/bindings/interface/SBEnvironment.i | 48 ++ lldb/bindings/interface/SBLaunchInfo.i | 6 + lldb/bindings/interface/SBPlatform.i | 3 + lldb/bindings/interface/SBTarget.i | 3 + lldb/bindings/interfaces.swig | 1 + lldb/include/lldb/API/LLDB.h | 1 + lldb/include/lldb/API/SBDefines.h | 1 + lldb/include/lldb/API/SBEnvironment.h | 137 ++++ lldb/include/lldb/API/SBLaunchInfo.h | 33 + lldb/include/lldb/API/SBPlatform.h | 8 + lldb/include/lldb/API/SBTarget.h | 17 +- .../lldb/DataFormatters/FormattersHelpers.h | 2 + lldb/include/lldb/Expression/ExpressionVariable.h | 10 +- lldb/include/lldb/Target/Target.h | 10 +- lldb/include/lldb/Utility/Environment.h | 1 + lldb/include/lldb/lldb-forward.h | 1 + lldb/source/API/CMakeLists.txt | 1 + lldb/source/API/SBEnvironment.cpp | 99 +++ lldb/source/API/SBLaunchInfo.cpp | 21 +- lldb/source/API/SBPlatform.cpp | 14 + lldb/source/API/SBTarget.cpp | 26 +- lldb/source/Commands/CommandObjectExpression.cpp | 3 +- lldb/source/Commands/CommandObjectExpression.h | 10 + lldb/source/Commands/CommandObjectTarget.cpp | 38 + lldb/source/Core/ValueObject.cpp | 4 +- lldb/source/DataFormatters/FormattersHelpers.cpp | 11 + lldb/source/Expression/ExpressionVariable.cpp | 10 - lldb/source/Expression/Materializer.cpp | 8 +- .../Clang/ClangPersistentVariables.cpp | 11 + .../Clang/ClangPersistentVariables.h | 10 +- .../ExpressionParser/Clang/ClangUserExpression.cpp | 4 +- .../Language/CPlusPlus/CPlusPlusLanguage.cpp | 13 + lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp | 98 +++ lldb/source/Plugins/Language/CPlusPlus/LibCxx.h | 28 + .../Plugins/Language/CPlusPlus/LibCxxList.cpp | 13 +- .../Plugins/Platform/MacOSX/PlatformDarwin.cpp | 11 + .../Plugins/Platform/MacOSX/PlatformDarwin.h | 5 + lldb/source/Target/ABI.cpp | 4 +- lldb/source/Target/Target.cpp | 119 ++- lldb/source/Target/TargetProperties.td | 5 +- .../{dont_allow_jit => result_numbering}/Makefile | 0 .../result_numbering/TestResultNumbering.py | 48 ++ .../commands/expression/result_numbering/main.c | 18 + lldb/test/API/commands/settings/TestSettings.py | 134 +++- .../API/commands/statistics/basic/TestStats.py | 14 + .../data-formatter-stl/libcxx/unique_ptr/Makefile | 6 + .../unique_ptr/TestDataFormatterLibcxxUniquePtr.py | 47 ++ .../data-formatter-stl/libcxx/unique_ptr/main.cpp | 13 + .../python_api/sbenvironment/TestSBEnvironment.py | 125 ++++ .../Functionalities/TestDataFormatter.test | 2 +- .../Functionalities/TestExpressionEvaluation.test | 2 +- .../Reproducer/Functionalities/TestImageList.test | 2 +- .../Reproducer/Functionalities/TestStepping.test | 2 +- .../Shell/Reproducer/TestCaptureEnvOverride.test | 1 - lldb/test/Shell/Reproducer/TestCrash.test | 1 - lldb/test/Shell/Reproducer/TestDiscard.test | 1 - lldb/test/Shell/Reproducer/TestDump.test | 1 - lldb/test/Shell/Reproducer/TestGDBRemoteRepro.test | 2 +- .../test/Shell/Reproducer/TestMultipleTargets.test | 2 +- lldb/test/Shell/Reproducer/TestRelativePath.test | 1 - lldb/test/Shell/Reproducer/TestReuseDirectory.test | 2 +- lldb/test/Shell/Reproducer/TestSynchronous.test | 1 - lldb/test/Shell/Reproducer/TestWorkingDir.test | 2 - lldb/test/Shell/Reproducer/lit.local.cfg | 3 + lldb/tools/lldb-vscode/package.json | 5 + llvm/cmake/modules/AddLLVM.cmake | 7 + llvm/docs/GlobalISel/GenericOpcode.rst | 9 + .../CMakeLists.txt | 1 + llvm/include/llvm/Analysis/VectorUtils.h | 33 +- .../llvm/CodeGen/GlobalISel/CombinerHelper.h | 10 + .../llvm/CodeGen/GlobalISel/GISelKnownBits.h | 3 + llvm/include/llvm/CodeGen/TargetLowering.h | 10 + llvm/include/llvm/Frontend/OpenMP/OMPContext.h | 10 +- llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 13 +- llvm/include/llvm/IR/CallSite.h | 7 + llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 4 +- llvm/include/llvm/Support/LockFileManager.h | 4 +- llvm/include/llvm/Support/OptimalLayout.h | 130 ++++ llvm/include/llvm/Support/TargetOpcodes.def | 12 + llvm/include/llvm/Target/GenericOpcodes.td | 36 + llvm/include/llvm/Target/GlobalISel/Combine.td | 13 +- llvm/include/llvm/Transforms/IPO/Attributor.h | 59 +- llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 35 + llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp | 41 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 8 + llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 6 +- llvm/lib/CodeGen/MIRParser/MILexer.cpp | 1 + llvm/lib/CodeGen/MIRParser/MILexer.h | 1 + llvm/lib/CodeGen/MIRParser/MIParser.cpp | 6 + llvm/lib/CodeGen/MIRPrinter.cpp | 5 + llvm/lib/CodeGen/MachineFunction.cpp | 2 +- llvm/lib/CodeGen/PrologEpilogInserter.cpp | 8 +- llvm/lib/CodeGen/RegUsageInfoPropagate.cpp | 9 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 18 +- .../CodeGen/SelectionDAG/FunctionLoweringInfo.cpp | 20 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 22 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 6 + llvm/lib/Frontend/OpenMP/OMPContext.cpp | 39 +- llvm/lib/Support/CMakeLists.txt | 1 + llvm/lib/Support/LockFileManager.cpp | 64 +- llvm/lib/Support/OptimalLayout.cpp | 452 ++++++++++++ llvm/lib/Support/Windows/Path.inc | 5 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 23 + llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 6 + llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h | 8 + llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 7 + .../Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 25 +- .../AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp | 6 + .../AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.h | 4 + llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 9 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.td | 13 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 27 + llvm/lib/Target/ARM/ARMInstrFormats.td | 2 + llvm/lib/Target/ARM/ARMInstrMVE.td | 5 + llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | 111 ++- llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h | 4 + llvm/lib/Target/AVR/AVRFrameLowering.cpp | 2 +- llvm/lib/Target/MSP430/MSP430FrameLowering.cpp | 4 +- llvm/lib/Target/Mips/MipsCallLowering.cpp | 5 +- llvm/lib/Target/PowerPC/PPC.td | 2 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 2 +- llvm/lib/Target/PowerPC/PPCInstrVSX.td | 85 +++ llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp | 10 +- llvm/lib/Target/RISCV/RISCVFrameLowering.cpp | 3 +- llvm/lib/Target/SystemZ/SystemZShortenInst.cpp | 43 ++ llvm/lib/Target/X86/X86.h | 1 + llvm/lib/Target/X86/X86AvoidTrailingCall.cpp | 97 ++- llvm/lib/Target/X86/X86CallFrameOptimization.cpp | 4 +- llvm/lib/Target/X86/X86FastISel.cpp | 6 +- llvm/lib/Target/X86/X86FrameLowering.cpp | 8 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 4 +- llvm/lib/Target/X86/X86ISelLowering.h | 26 - llvm/lib/Target/X86/X86InstrInfo.cpp | 52 +- llvm/lib/Target/X86/X86InstrInfo.h | 4 +- llvm/lib/Target/X86/X86TargetMachine.cpp | 1 + llvm/lib/Transforms/Coroutines/CoroFrame.cpp | 36 +- llvm/lib/Transforms/Coroutines/CoroSplit.cpp | 13 +- llvm/lib/Transforms/IPO/Attributor.cpp | 135 ++-- llvm/lib/Transforms/IPO/GlobalOpt.cpp | 3 - llvm/lib/Transforms/IPO/OpenMPOpt.cpp | 67 +- .../Transforms/InstCombine/InstCombineCalls.cpp | 24 +- llvm/lib/Transforms/Scalar/ConstantHoisting.cpp | 2 +- llvm/lib/Transforms/Scalar/GVNSink.cpp | 1 + llvm/lib/Transforms/Utils/Local.cpp | 36 +- llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 13 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 2 +- llvm/lib/Transforms/Vectorize/VPlan.cpp | 2 +- .../GlobalISel/legalizer-info-validation.mir | 12 + .../GlobalISel/prelegalizercombiner-select.mir | 95 +++ .../CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll | 318 ++++++++ .../AMDGPU/GlobalISel/legalize-implicit-def.mir | 104 +++ llvm/test/CodeGen/PowerPC/atomics-fences.ll | 1 + llvm/test/CodeGen/PowerPC/build-vector-tests.ll | 409 +++++++++++ .../test/CodeGen/PowerPC/reduce_scalarization02.ll | 34 +- .../CodeGen/PowerPC/vec_conv_fp32_to_i64_elts.ll | 814 ++++++++------------- llvm/test/CodeGen/PowerPC/vsx.ll | 14 +- llvm/test/CodeGen/SystemZ/ipra-04.ll | 3 +- llvm/test/CodeGen/SystemZ/shorten-fused-fp-ops.mir | 60 ++ llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll | 461 ++++++++++++ llvm/test/CodeGen/Thumb2/mve-vmull.ll | 99 +++ llvm/test/CodeGen/X86/win64-eh-empty-block-2.mir | 223 ++++++ llvm/test/CodeGen/X86/win64-eh-empty-block.ll | 2 +- llvm/test/CodeGen/X86/wineh-coreclr.ll | 8 +- .../Attributor/IPConstantProp/musttail-call.ll | 7 +- llvm/test/Transforms/Attributor/range.ll | 102 +++ llvm/test/Transforms/Coroutines/coro-split-02.ll | 10 + llvm/test/Transforms/GVNSink/indirect-call.ll | 24 + llvm/test/Transforms/GVNSink/sink-common-code.ll | 67 ++ .../GlobalOpt/null-check-is-use-pr35760.ll | 41 ++ llvm/test/Transforms/InstCombine/ctpop-cttz.ll | 72 +- llvm/test/Transforms/InstCombine/select.ll | 23 + llvm/test/Transforms/OpenMP/rtf_type_checking.ll | 63 ++ llvm/test/Transforms/SCCP/conditions-ranges.ll | 489 ++++++++++++- llvm/test/Transforms/SLPVectorizer/AMDGPU/round.ll | 38 + .../Transforms/SimplifyCFG/sink-common-code.ll | 123 +++- .../Transforms/VectorCombine/X86/extract-binop.ll | 68 ++ .../Transforms/VectorCombine/X86/extract-cmp.ll | 37 + llvm/test/tools/llvm-objcopy/tool-name.test | 33 + llvm/test/tools/llvm-readobj/ELF/all.test | 3 +- .../ELF/dyn-symbols-size-from-hash-table.test | 314 ++++++++ llvm/tools/bugpoint/CMakeLists.txt | 2 +- llvm/tools/llc/CMakeLists.txt | 2 +- llvm/tools/llvm-objcopy/llvm-objcopy.cpp | 24 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 117 ++- llvm/tools/llvm-stress/CMakeLists.txt | 1 - llvm/tools/opt/CMakeLists.txt | 2 +- llvm/unittests/Analysis/VectorUtilsTest.cpp | 8 + llvm/unittests/CodeGen/GlobalISel/CSETest.cpp | 4 +- .../CodeGen/GlobalISel/ConstantFoldingTest.cpp | 4 +- llvm/unittests/CodeGen/GlobalISel/GISelMITest.cpp | 76 ++ llvm/unittests/CodeGen/GlobalISel/GISelMITest.h | 67 +- .../unittests/CodeGen/GlobalISel/KnownBitsTest.cpp | 61 +- .../CodeGen/GlobalISel/LegalizerHelperTest.cpp | 114 +-- .../unittests/CodeGen/GlobalISel/LegalizerTest.cpp | 6 +- .../CodeGen/GlobalISel/MachineIRBuilderTest.cpp | 27 +- .../CodeGen/GlobalISel/PatternMatchTest.cpp | 18 +- llvm/unittests/MC/AMDGPU/CMakeLists.txt | 11 + llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp | 77 ++ llvm/unittests/MC/CMakeLists.txt | 7 + llvm/unittests/Passes/CMakeLists.txt | 2 +- llvm/unittests/Support/CMakeLists.txt | 1 + llvm/unittests/Support/OptimalLayoutTest.cpp | 132 ++++ llvm/unittests/Support/Path.cpp | 4 +- llvm/unittests/Support/VirtualFileSystemTest.cpp | 56 ++ llvm/unittests/Target/AMDGPU/CMakeLists.txt | 16 + llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp | 88 +++ llvm/unittests/Target/ARM/MachineInstrTest.cpp | 101 ++- llvm/unittests/Transforms/Utils/LocalTest.cpp | 60 ++ .../clang/lib/StaticAnalyzer/Core/BUILD.gn | 1 + .../compiler-rt/lib/scudo/standalone/BUILD.gn | 5 +- .../utils/gn/secondary/llvm/lib/Target/targets.gni | 5 +- llvm/utils/gn/secondary/llvm/unittests/BUILD.gn | 6 + .../gn/secondary/llvm/unittests/MC/AMDGPU/BUILD.gn | 14 + .../llvm/unittests/Target/AMDGPU/BUILD.gn | 17 + mlir/include/mlir/Analysis/AffineStructures.h | 15 +- mlir/include/mlir/Dialect/LoopOps/LoopOps.td | 9 +- mlir/include/mlir/Dialect/Vector/VectorOps.h | 4 +- mlir/include/mlir/Dialect/Vector/VectorOps.td | 96 +-- mlir/include/mlir/IR/OpImplementation.h | 19 + mlir/include/mlir/Transforms/FoldUtils.h | 19 +- mlir/lib/Analysis/AffineStructures.cpp | 66 +- mlir/lib/Dialect/AVX512/CMakeLists.txt | 1 + mlir/lib/Dialect/Affine/Transforms/CMakeLists.txt | 4 + mlir/lib/Dialect/Affine/Transforms/LoopTiling.cpp | 35 +- .../Dialect/Affine/Transforms/LoopUnrollAndJam.cpp | 129 ---- mlir/lib/Dialect/LoopOps/LoopOps.cpp | 15 +- mlir/lib/Dialect/Vector/VectorTransforms.cpp | 65 +- mlir/lib/IR/AsmPrinter.cpp | 22 +- mlir/lib/Parser/Lexer.cpp | 2 +- mlir/lib/Parser/Parser.cpp | 63 +- mlir/lib/Parser/Token.cpp | 3 - mlir/lib/Parser/Token.h | 4 +- mlir/lib/Parser/TokenKinds.def | 60 +- mlir/lib/Transforms/Utils/FoldUtils.cpp | 20 +- mlir/lib/Transforms/Utils/LoopUtils.cpp | 129 ++++ .../Dialect/Vector/vector-contract-transforms.mlir | 22 + mlir/test/IR/parser.mlir | 46 ++ mlir/test/lib/TestDialect/CMakeLists.txt | 1 + mlir/test/lib/TestDialect/TestDialect.cpp | 81 ++ mlir/test/lib/TestDialect/TestOps.td | 12 + .../lib/Transforms/TestConvertGPUKernelToCubin.cpp | 5 +- openmp/runtime/src/kmp_tasking.cpp | 9 +- .../runtime/test/tasking/omp_task_red_taskloop.c | 57 ++ 439 files changed, 11554 insertions(+), 3036 deletions(-) create mode 100644 clang/lib/StaticAnalyzer/Core/TextDiagnostics.cpp create mode 100644 clang/test/AST/ast-dump-expr-errors.cpp create mode 100644 clang/test/AST/ast-dump-recovery.cpp create mode 100644 clang/test/CodeGen/arm-cmse-attr.c create mode 100644 clang/test/CodeGen/arm-cmse-call.c create mode 100644 clang/test/CodeGen/attr-noreturn.c create mode 100644 clang/test/CodeGenCoroutines/coro-always-inline.cpp create mode 100644 clang/test/Index/getcursor-recovery.cpp create mode 100644 clang/test/Sema/arm-cmse.c create mode 100644 clang/test/Sema/arm-no-cmse.c create mode 100644 clang/test/SemaCXX/arm-cmse.cpp create mode 100644 clang/test/SemaTemplate/recovery-tree-transform.cpp rename compiler-rt/lib/scudo/standalone/{ => include/scudo}/interface.h (65%) create mode 100644 compiler-rt/test/sanitizer_common/TestCases/Posix/uname.c create mode 100644 libc/src/.clang-tidy create mode 100644 lldb/bindings/interface/SBEnvironment.i create mode 100644 lldb/include/lldb/API/SBEnvironment.h create mode 100644 lldb/source/API/SBEnvironment.cpp copy lldb/test/API/commands/expression/{dont_allow_jit => result_numbering}/Makefi [...] create mode 100644 lldb/test/API/commands/expression/result_numbering/TestResultNu [...] create mode 100644 lldb/test/API/commands/expression/result_numbering/main.c create mode 100644 lldb/test/API/functionalities/data-formatter/data-formatter-stl [...] create mode 100644 lldb/test/API/functionalities/data-formatter/data-formatter-stl [...] create mode 100644 lldb/test/API/functionalities/data-formatter/data-formatter-stl [...] create mode 100644 lldb/test/API/python_api/sbenvironment/TestSBEnvironment.py create mode 100644 llvm/include/llvm/Support/OptimalLayout.h create mode 100644 llvm/lib/Support/OptimalLayout.cpp create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-select.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll create mode 100644 llvm/test/CodeGen/SystemZ/shorten-fused-fp-ops.mir create mode 100644 llvm/test/CodeGen/Thumb2/mve-vmovnstore.ll create mode 100644 llvm/test/CodeGen/X86/win64-eh-empty-block-2.mir create mode 100644 llvm/test/Transforms/GlobalOpt/null-check-is-use-pr35760.ll create mode 100644 llvm/test/Transforms/OpenMP/rtf_type_checking.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/AMDGPU/round.ll create mode 100644 llvm/test/tools/llvm-objcopy/tool-name.test create mode 100644 llvm/test/tools/llvm-readobj/ELF/dyn-symbols-size-from-hash-table.test create mode 100644 llvm/unittests/MC/AMDGPU/CMakeLists.txt create mode 100644 llvm/unittests/MC/AMDGPU/DwarfRegMappings.cpp create mode 100644 llvm/unittests/Support/OptimalLayoutTest.cpp create mode 100644 llvm/unittests/Target/AMDGPU/CMakeLists.txt create mode 100644 llvm/unittests/Target/AMDGPU/DwarfRegMappings.cpp create mode 100644 llvm/utils/gn/secondary/llvm/unittests/MC/AMDGPU/BUILD.gn create mode 100644 llvm/utils/gn/secondary/llvm/unittests/Target/AMDGPU/BUILD.gn create mode 100644 openmp/runtime/test/tasking/omp_task_red_taskloop.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allnoconfig updated (14e0aa1e -> a63c40a3)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allnoconfig in repository toolchain/ci/base-artifacts. discards 14e0aa1e 0: update: llvm-linux: boot new a63c40a3 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (14e0aa1e) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 134 +- 02-build_llvm/console.log | 12761 +++++++++++++-------------- 03-build_linux/console.log | 892 +- 04-boot_linux/console.log | 4 +- 05-check_regression/console.log | 2 +- 05-check_regression/results.regressions | 2 +- 06-update_baseline/console.log | 2 +- console.log | 13795 +++++++++++++++--------------- jenkins/manifest.sh | 8 +- 9 files changed, 13807 insertions(+), 13793 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-defconfig updated (ecce469d89e -> 95c969e58f7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-defconfig in repository toolchain/ci/gcc. from ecce469d89e Daily bump. adds 938de7cbb1c Daily bump. adds a5ef37f868b Daily bump. adds 46de8b3eb1a Darwin: Fix i686 bootstrap when the assembler supports GOTO [...] adds 5c7bd28d1cb backport PR90763: PowerPC vec_xl_len should take const argument. adds c7bc3b65623 Remove wrongly committed file. adds 2e432a97839 Daily bump. new 95c969e58f7 backport PR94125: Update post order number for merged SCC. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: a | 81 --------------------------- gcc/ChangeLog | 29 ++++++++++ gcc/DATESTAMP | 2 +- gcc/config/i386/darwin.h | 10 ++++ gcc/config/i386/i386.h | 5 +- gcc/config/rs6000/rs6000-c.c | 13 +++++ gcc/testsuite/ChangeLog | 16 ++++++ gcc/testsuite/gcc.dg/tree-ssa/pr94125.c | 41 ++++++++++++++ gcc/testsuite/gcc.target/powerpc/pr90763.c | 88 ++++++++++++++++++++++++++++++ gcc/tree-loop-distribution.c | 13 ++--- 10 files changed, 205 insertions(+), 93 deletions(-) delete mode 100644 a create mode 100644 gcc/testsuite/gcc.dg/tree-ssa/pr94125.c create mode 100644 gcc/testsuite/gcc.target/powerpc/pr90763.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-defconfig updated (b3c21d4e -> 56799672)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-defconfig in repository toolchain/ci/base-artifacts. discards b3c21d4e 0: update: binutils-gcc-linux: boot new 56799672 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (b3c21d4e) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 132 +- 02-prepare_abe/console.log | 418 +- 03-build_abe-binutils/console.log | 11372 ++++++------- 04-build_abe-stage1/console.log | 13715 +++++++-------- 05-build_linux/console.log | 730 +- 06-boot_linux/console.log | 404 +- 07-check_regression/console.log | 15 +- 07-check_regression/results.regressions | 3 + 08-update_baseline/console.log | 15 +- 08-update_baseline/results.regressions | 4 + console.log | 26801 +++++++++++++++--------------- jenkins/manifest.sh | 10 +- regressions.txt | 3 - 13 files changed, 26830 insertions(+), 26792 deletions(-) create mode 100644 07-check_regression/results.regressions create mode 100644 08-update_baseline/results.regressions delete mode 100644 regressions.txt -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

[gcc] branch master updated (596c90d3559 -> 906b3eb9df6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 596c90d3559 arm: Fix arm {,u}subvdi4 and usubvsi4 expanders [PR94286] new 906b3eb9df6 Improve endianess detection. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: include/ChangeLog | 5 ++++ include/plugin-api.h | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 68 insertions(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 2 months

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

Tcwg-commits March 2020