Tcwg-commits February 2020

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[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allyesconfig updated (f55bf4ddbfa -> 8b3c0979ea1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allyesconfig in repository toolchain/ci/gcc. from f55bf4ddbfa i386: Skip ENDBR32 at the target function entry adds bd2537ed5d4 i386: Fix *vec_extractv2sf_1 and *vec_extractv2sf_1 shufps [...] adds 8b3c0979ea1 Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 7 +++++++ gcc/DATESTAMP | 2 +- gcc/config/i386/mmx.md | 8 ++++---- 3 files changed, 12 insertions(+), 5 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 4 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allyesconfig updated (27147410 -> 3e6589d9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards 27147410 0: update: binutils-gcc-linux: all new 3e6589d9 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (27147410) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 130 +- 02-prepare_abe/console.log | 413 +- 03-build_abe-binutils/console.log | 11588 ++++++++-------- 04-build_abe-stage1/console.log | 13393 +++++++++--------- 05-build_linux/console.log | 856 +- 06-boot_linux/console.log | 8 +- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 2 +- console.log | 26402 ++++++++++++++++++------------------ jenkins/manifest.sh | 8 +- 10 files changed, 26381 insertions(+), 26421 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 4 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allyesconfig updated (da181d4ba0c -> dc046c70de9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allyesconfig in repository toolchain/ci/llvm-project. from da181d4ba0c [PowerPC][NFC] Cleanup some of the Darwin mentions in the R [...] adds 064cd2ecdb3 [x86] allow peeking through an extract_subvector to find a [...] adds 5d2baa956ac [libc] Add Initial Support for Signals adds 8928c6dbbf7 Fix some typos in the MLIR documentation. adds 6de21c556d1 [ORC][examples] Fix ThinLtoJIT example after changes in 85f [...] adds 813b1b9fd6c [ORC] Add a convenience method for setting the ExecutionSes [...] adds e2c2eb0a550 [X86] Fix NSW/NUW typo in avg test (PR44973) adds a11ff39ba2a [clang-format] Merge name and colon into a single token for [...] adds 7a7c753b0cc libclang: Make shared object symbol exporting by default adds 967eeb109be [AIX] Pack BasicBlockBits adds 2f56789c8fe [clang][doxygen] Fix false -Wdocumentation warning for tag [...] adds e4a9225f5d1 [GISel][KnownBits] Give up on PHI analysis as soon as we do [...] adds 6d34a87bae6 [cxx_status] Update -std= instructions for C++20. adds 0c8fa6db90a [llvm][build] Fix shared lib builds. [NFC] adds 3d0564c7e07 Revert "[NFCI][DebugInfo]: Corrected a Typo." adds 7ddbf802cf6 [ConstantFold] add/move tests for FP with undef operand; NFC adds 6f4d9d10293 Revert "[AArch64][SVE] Add intrinsics for SVE2 bitwise tern [...] adds e84444781aa Revert "libclang: Add static build support for Windows" and [...] adds 714265dabb6 [X86] Replace a bad use of MVT::getVectorVT with EVT::getVectorVT adds 1d8860f90bc Revert 714265dabb606bfef2f85694234f152edbfa91ac "[X86] Repl [...] adds c7b54a196e1 Recommit "[X86] Replace a bad use of MVT::getVectorVT with [...] adds 9e0c95572e5 [AIX] Improve 32/64-bit build configuration adds bf3f427ba23 [ASTImporter] Add linkage check to ASTNodeImporter::hasSame [...] adds 6123074d0c0 [Driver] Escape the program path for -frecord-command-line adds c767cf24e48 [SVE] Add support for lowering GEPs involving scalable vectors. adds 99809f98d7b [SCCP] Do not mark unknown loads as overdefined. adds ee260c1a0f1 [mlir] [VectorOps] Multi-dim reductions for lowering vector [...] adds 6d60d8695d2 [mlir] Use LLJIT::getMainJITDylib instead of hardcoding '<main>' adds 3ee28108273 [lldb/Plugin] Don't mark ProcessNetBSD as a plugin adds 577d9ce3553 Revert "[Driver] Escape the program path for -frecord-comma [...] adds 51bf5d3cc19 [mlir][Parser] Update DenseElementsAttr to print in hex whe [...] adds 0d19b016226 [lldb/Test] Remove stale README in test/API adds 07c559caef9 [libc++] Explain XFAILs with std::uncaught_exceptions test adds d95a10a7f97 [X86] Custom legalize v1i1 add/sub/mul to xor/xor/and with avx512. adds 5228a5544b2 [X86] Fix a couple copy mistakes in v4i1 or/and/xor isel patterns. adds b00ef8951b5 [X86] Custom legalize v1i1 UADDSAT/USUBSAT/SADDSAT/UADDSAT [...] adds 7e927698621 [X86] Expand vselect of v1i1 under avx512. adds e5782377f3f [X86] Add CMOV_VK1 pseudo so we don't crash on v1i1 ISD::SELECT adds 72ce0c8073b [libc++][regex] Validate backreferences in the constructor. adds d4ded05ba85 [libunwind][CMake] Treat S files as C to work around CMake bug. adds 2fe457690da Filter callbr insts from critical edge splitting adds 7593a480dbc [Dominators] Use Instruction::comesBefore for block-local q [...] adds e27b61c1ea3 [XCore] Add instruction pattern for bitrev adds 4b540fa8a1c [OpenMP][NFC] Remove leftover debug messages adds c32c8fd1437 [mlir] Use getOperation()->setAttr when generating attribut [...] adds d8969a1cb96 Split _LIBCPP_STRING_EXTERN_TEMPLATE_LIST up into a V1 and [...] adds 78be6187170 [X86] Add CMOV_VR64 pseudo instruction for MMX. Remove mmx [...] adds efeafa1bdaa libclc: Use acos implementation from amd_builtins adds 45766068315 [X86] Remove unnecessary isNullConstant in LowerSelect. NFC adds df74033ec9f [WebAssembly] Remove unneeded getWasmKindForNamedSection function adds 3bc525af235 [X86] Autogenerate complete checks. NFC adds 263bef2bbcb [X86] Make combineCMov not create unsupported FCMOVs when f [...] adds 97f11600e0b [X86] Don't bother avoiding illegal FCMOVs if we don't have [...] adds e326f524304 [clangd] Fix the incomplete template specialization in findTarget. adds 0e5ed1b2626 [lldb][NFC] Split up ClangASTSource::FindExternalVisibleDecls adds bc498198b55 [clangd] Allow renaming class templates in cross-file rename. adds e5eeb8465f2 Make unittests include path relative adds d0b09f89e0e [NFC][mlir] Adding more operators to EDSC TemplatedIndexedValue adds 32e4e719663 test/CodeGen/AMDGPU: Add a test case that shows a miscompilation adds a24d46318f6 [NFC] Corrected a minor typo in a comment adds 99b03c1c18d Detect and disable openmp tests that require multiple hardw [...] adds d799190851f [ConstantFold] fold fsub -0.0, undef to undef rather than NaN adds b0761bbc763 [DependenceAnalysis] Memory dependence analysis internal ca [...] adds c51b0bede82 [Hexagon] Introduce noop intrinsic to cast between vector p [...] adds 35b685270b4 [mlir] Add a signedness semantics bit to IntegerType adds 86c52af05a6 [TargetLowering] SimplifyDemandedBits - use getValidShiftAm [...] adds d33e96b68c6 [X86] Regenerate hi reg tests adds b55c58a2d56 [Error/unittests] Add a FailedWithMessage gtest matcher adds 4fdaac0e1eb [PowerPC][NFC] Remove Darwin specific logic in frame finalization. adds a49a41e7855 [AST][NFC] Update outdated comments in ASTStructuralEquival [...] adds 175f6e309ab [PowerPC][NFC] Add a test for vrsave usage iinline asm. adds de8793b9184 [lldb/DWARF] Add support for type units in dwp files adds f0c642e8227 Remove unused functions in llvm-ml adds 5125803d344 [mlir] Silence error: call to constructor of 'llvm::APInt' [...] adds b64aa8c7151 AMDGPU/GlobalISel: Fix constant bus violation with source m [...] adds fab4cdea391 AMDGPU/GlobalISel: Select llvm.amdgcn.fmul.legacy adds 79ff188adde AMDGPU/GlobalISel: Legalize G_FPOW adds ac7abe0ba9a AMDGPU/GlobalISel: Manually select G_BUILD_VECTOR_TRUNC adds 83012cb2171 [ARM] Correct Formatting. NFC adds 89dc8fe6222 AMDGPU/GlobalISel: Precommit xnor matching test adds 6ed8e201433 [ELF] Ignore the maximum of input section alignments for two cases adds de0dda54d38 [ELF] Warn changed output section address adds c47e0e2d37d [lldb-vscode] Use libOption with tablegen to parse command [...] adds dbd7281aa77 [ELF] Shuffle .init_array/.fini_array with --shuffle-sections= adds 42ec6fdce92 [TargetLowering] Apply basic shift combines before recursiv [...] adds 043ed2e22ac AMDGPU/GlobalISel: Fix xnor matching adds 6a479220b5e AMDGPU/GlobalISel: Commit test changes I forgot to squash adds cab39e4b8c8 GlobalISel: Fix narrowing of (G_ASHR i64:x, 32) adds 9fff6e823cf [AArch64][SVE] Add +fullfp16 to sve-vector-splat.ll adds 134bab7cd56 [DSE,MSSA] Add debug counter. adds 23444edf30b [AST matchers] Add basic matchers for googletest EXPECT/ASS [...] adds fc4455891c0 [VectorCombine] refactor matching code to reduce duplication; NFC adds db9c40f5624 [AArch64][SVE] Add intrinsics for SVE2 bitwise ternary operations adds 60023e34711 AMDGPU: Use default operand for VOP3P clamp adds 41bd9ead35f [SystemZ] Return scalarized costs for vector instructions [...] adds 8c70a2597f5 [gn build] Port 23444edf30b adds a8db806d52c [SimplifyLibCalls][IRBuilder] Accept any IRBuilder in Simpl [...] adds c90ea87cfd7 [X86] Fix SDLoc initialization adds 98f5268a729 [VectorUtils] Move ToVectorTy to VectorUtils.h (NFC). adds deb0a8bfc49 [DSE,MSSA] Dbg counters required assertions. Mark test acco [...] adds 656dff9af48 [InstCombine] Use replaceOperand() in more places adds e4df934ca7b [Clang interpreter] Rename Block.{h,cpp} to InterpBlock.{h,cpp} adds 0e3e242209c [BFI] Fix missed BFI updates in MachineSink. adds b178555318c [InstCombine] Improve simplify demanded bits worklist management adds 31ec721516b [llvm][CodeGen] DAG Combiner folds for vscale. adds bc7b26c333f [MLIR] Allow Loop dialect IfOp and ForOp to define values adds 6b4a193defb [XCOFF][AIX] Put undefined symbol name into StringTable whe [...] adds 2769fb90f0a [LoopVectorize][X86] Regenerate tests. NFCI. adds 1723f219939 Fix MSVC "not all control paths return a value" warning. NFCI. adds 72eef820d52 AMDGPU/GlobalISel: Select G_SHUFFLE_VECTOR adds dfce5fd50a0 AMDGPU/GlobalISel: Select VOP3P instructions adds 4c1c9422a3a AMDGPU/GlobalISel: Select llvm.amdgcn.fdot2 adds db06870dbd5 AMDGPU: Move dot intrinsic patterns to instruction def adds 07d2cdae116 [lldb/cmake] Enable more verbose find_package output. adds 00955a62e43 AMDGPU/GlobalISel: Fix SALU mapping for v2s16 min/max adds 73d8d83a6d9 [ARM] Change ARMAttributeParser::Parse to use support::endi [...] adds 7dd6a862e5e [libc++] Do not set the `availability=XXX` feature when not [...] adds 266959c0f72 [AArch64][SVE] Add backend support for splats of immediates adds 0781e93a6ea [CodeGen][RISCV] Fix clang/test/CodeGen/atomic_ops.c for RISC-V adds 29ad9d6b26e [mlir][spirv] Add lowering for load/store zero-rank memref [...] adds 042d97eda9f [MLIR] Remove constexpr from LoopOps.td adds d2b7c09e79a [Hexagon] Simplify intrinsic (vandvrt (vandqrt q b) m) -> q [...] adds 69d757c0e8f Move StandardOps/Ops.h to StandardOps/IR/Ops.h adds e2ed1d14d6c [llvm][aarch64] SVE addressing modes. adds 34e3485560c [VectorCombine] refactor cost calcs to reduce duplication; NFC adds 33bf1196475 [llvm][CodeGen][aarch64] Add contiguous prefetch intrinsics [...] adds 446b150065c [IR] Update BasicBlock::validateInstrOrdering comments, NFC adds 8875ee18d72 [X86] Add a new format type for instructions that represent [...] new 1874dee5662 [macho][NFC] Extract all CPU_(SUB_)TYPE logic to BinaryFormat new 0bb90628b5f Allow customized relative PYTHONHOME new 8fa776b8ed0 [gn build] Port 1874dee5662 new e9c79a7aef1 [VectorCombine] refactor to reduce duplicated code; NFC new b72f1448ce4 AMDGPU/GlobalISel: Better code for one case of G_SHUFFLE_VE [...] new a5b22b768f5 [AArch64][SVE] Add support for DestructiveBinary and Destru [...] new dc046c70de9 [llvm-objcopy][MachO] Change the storage of sections The 7 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang-tools-extra/clangd/FindTarget.cpp | 10 +- clang-tools-extra/clangd/refactor/Rename.cpp | 7 - .../clangd/unittests/FindTargetTests.cpp | 10 + clang-tools-extra/clangd/unittests/RenameTests.cpp | 17 + clang-tools-extra/clangd/unittests/XRefsTests.cpp | 6 + clang/include/clang-c/Platform.h | 20 +- clang/include/clang/AST/CommentSema.h | 3 + clang/include/clang/ASTMatchers/GtestMatchers.h | 45 + clang/lib/AST/ASTImporter.cpp | 26 +- clang/lib/AST/ASTStructuralEquivalence.cpp | 12 +- clang/lib/AST/CMakeLists.txt | 2 +- clang/lib/AST/CommentSema.cpp | 48 +- .../lib/AST/Interp/{Block.cpp => InterpBlock.cpp} | 2 +- clang/lib/AST/Interp/{Block.h => InterpBlock.h} | 2 +- clang/lib/AST/Interp/Pointer.cpp | 2 +- clang/lib/AST/Interp/Pointer.h | 4 +- clang/lib/ASTMatchers/CMakeLists.txt | 1 + clang/lib/ASTMatchers/GtestMatchers.cpp | 104 ++ clang/lib/CodeGen/CGOpenMPRuntime.cpp | 2 - clang/lib/Format/FormatToken.h | 1 + clang/lib/Format/FormatTokenLexer.cpp | 35 + clang/lib/Format/FormatTokenLexer.h | 1 + clang/test/CodeGen/atomic_ops.c | 55 +- clang/test/Sema/warn-documentation-tag-typedef.cpp | 13 + clang/tools/libclang/CMakeLists.txt | 5 +- clang/unittests/ASTMatchers/CMakeLists.txt | 1 + clang/unittests/ASTMatchers/GtestMatchersTest.cpp | 191 +++ clang/unittests/Format/FormatTestCSharp.cpp | 17 +- clang/www/cxx_status.html | 2 +- libc/config/linux/api.td | 10 + libc/config/linux/signal.h.in | 11 + libc/include/CMakeLists.txt | 10 + libc/include/signal.h.def | 18 + libc/lib/CMakeLists.txt | 3 + libc/spec/linux.td | 45 + libc/spec/stdc.td | 24 + libc/src/CMakeLists.txt | 1 + libc/src/signal/CMakeLists.txt | 4 + libc/src/signal/linux/CMakeLists.txt | 14 + libc/src/signal/linux/raise.cpp | 26 + libc/src/signal/linux/signal.h | 49 + libc/src/signal/raise.h | 20 + libc/test/src/CMakeLists.txt | 1 + libc/test/src/signal/CMakeLists.txt | 12 + libc/test/src/signal/raise_test.cpp | 17 + libclc/generic/lib/math/acos.cl | 173 ++- libclc/generic/lib/math/acos.inc | 36 - libcxx/include/__string | 66 +- libcxx/include/regex | 2 + libcxx/include/string | 9 +- libcxx/src/string.cpp | 9 +- .../uncaught/uncaught_exceptions.pass.cpp | 16 +- .../re.regex.construct/bad_backref.pass.cpp | 56 +- libcxx/utils/libcxx/test/config.py | 2 +- libunwind/src/CMakeLists.txt | 4 +- lld/ELF/InputFiles.cpp | 3 +- lld/ELF/LinkerScript.cpp | 22 +- lld/ELF/LinkerScript.h | 4 + lld/ELF/Writer.cpp | 40 +- lld/test/ELF/linkerscript/lma-align.test | 12 +- lld/test/ELF/linkerscript/outsections-addr.s | 6 +- lld/test/ELF/linkerscript/section-align2.test | 36 + lld/test/ELF/shuffle-sections-init-fini.s | 62 + lldb/cmake/modules/FindLuaAndSwig.cmake | 4 +- lldb/cmake/modules/FindPythonInterpAndLibs.cmake | 8 +- lldb/cmake/modules/LLDBConfig.cmake | 15 +- lldb/include/lldb/Host/Config.h.cmake | 2 + .../ExpressionParser/Clang/ClangASTSource.cpp | 187 +-- .../ExpressionParser/Clang/ClangASTSource.h | 5 + lldb/source/Plugins/Process/NetBSD/CMakeLists.txt | 2 +- .../Python/ScriptInterpreterPython.cpp | 32 +- .../Plugins/SymbolFile/DWARF/DWARFContext.cpp | 6 + .../source/Plugins/SymbolFile/DWARF/DWARFContext.h | 2 + lldb/test/API/README.md | 4 - lldb/test/Shell/SymbolFile/DWARF/dwp-debug-types.s | 211 +++ lldb/test/Shell/VSCode/TestOptions.test | 8 + lldb/test/Shell/helper/toolchain.py | 1 + lldb/tools/lldb-vscode/CMakeLists.txt | 4 + lldb/tools/lldb-vscode/Options.td | 25 + lldb/tools/lldb-vscode/lldb-vscode.cpp | 105 +- llvm/CMakeLists.txt | 2 +- llvm/cmake/modules/GetHostTriple.cmake | 10 +- llvm/cmake/modules/HandleLLVMOptions.cmake | 11 - llvm/examples/ThinLtoJIT/ThinLtoJIT.cpp | 2 +- .../llvm/Analysis/MemoryDependenceAnalysis.h | 3 +- llvm/include/llvm/Analysis/VectorUtils.h | 9 + llvm/include/llvm/BinaryFormat/MachO.h | 7 + .../llvm/CodeGen/MachineBlockFrequencyInfo.h | 2 + llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h | 7 + llvm/include/llvm/IR/BasicBlock.h | 26 +- llvm/include/llvm/IR/IRBuilder.h | 23 + llvm/include/llvm/IR/IntrinsicsAArch64.td | 8 + llvm/include/llvm/IR/IntrinsicsHexagon.td | 10 +- llvm/include/llvm/Object/ELFObjectFile.h | 2 +- llvm/include/llvm/Support/ARMAttributeParser.h | 3 +- llvm/include/llvm/Testing/Support/Error.h | 42 + .../llvm/Transforms/Utils/SimplifyLibCalls.h | 4 +- llvm/lib/Analysis/MemoryDependenceAnalysis.cpp | 29 +- llvm/lib/BinaryFormat/CMakeLists.txt | 1 + llvm/lib/BinaryFormat/MachO.cpp | 101 ++ llvm/lib/CodeGen/CodeGenPrepare.cpp | 3 +- llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 4 +- llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp | 4 + llvm/lib/CodeGen/MachineBlockFrequencyInfo.cpp | 6 + llvm/lib/CodeGen/MachineSink.cpp | 7 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 39 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 89 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 93 +- llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp | 12 - .../DWARF/DWARFAbbreviationDeclaration.cpp | 2 +- llvm/lib/IR/BasicBlock.cpp | 2 +- llvm/lib/IR/ConstantFold.cpp | 6 +- llvm/lib/IR/Dominators.cpp | 14 +- llvm/lib/MC/MCParser/MasmParser.cpp | 77 +- llvm/lib/MC/XCOFFObjectWriter.cpp | 26 +- llvm/lib/Support/ARMAttributeParser.cpp | 8 +- llvm/lib/Support/YAMLTraits.cpp | 2 +- .../Target/AArch64/AArch64ExpandPseudoInsts.cpp | 183 +++ llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp | 168 ++ llvm/lib/Target/AArch64/AArch64InstrFormats.td | 26 +- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 19 + llvm/lib/Target/AArch64/AArch64InstrInfo.h | 31 +- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 205 ++- llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 3 + .../AArch64/MCTargetDesc/AArch64AsmBackend.cpp | 20 +- .../MCTargetDesc/AArch64MachObjectWriter.cpp | 2 +- llvm/lib/Target/AArch64/MCTargetDesc/LLVMBuild.txt | 2 +- llvm/lib/Target/AArch64/SVEInstrFormats.td | 93 +- llvm/lib/Target/AMDGPU/AMDGPUGISel.td | 4 + llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp | 9 + llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.h | 1 + llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 13 - llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td | 12 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 328 +++- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 13 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 54 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 1 + llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 93 +- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 5 +- llvm/lib/Target/AMDGPU/VOP3Instructions.td | 24 +- llvm/lib/Target/AMDGPU/VOP3PInstructions.td | 61 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 9 +- llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp | 35 +- .../Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h | 12 +- llvm/lib/Target/ARM/MCTargetDesc/LLVMBuild.txt | 2 +- llvm/lib/Target/ARM/README-Thumb.txt | 2 +- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 2 +- llvm/lib/Target/Hexagon/HexagonISelLowering.h | 2 + llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp | 40 +- llvm/lib/Target/PowerPC/MCTargetDesc/LLVMBuild.txt | 2 +- .../Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp | 9 +- llvm/lib/Target/PowerPC/PPCFrameLowering.cpp | 16 +- .../Target/SystemZ/SystemZTargetTransformInfo.cpp | 261 ++-- llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp | 306 ++-- llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h | 10 + .../Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp | 2 + llvm/lib/Target/X86/X86ISelLowering.cpp | 57 +- llvm/lib/Target/X86/X86InstrAVX512.td | 4 +- llvm/lib/Target/X86/X86InstrCompiler.td | 8 +- llvm/lib/Target/X86/X86InstrFormats.td | 1 + llvm/lib/Target/X86/X86InstrInfo.td | 10 +- llvm/lib/Target/X86/X86InstrSystem.td | 12 +- llvm/lib/Target/X86/X86InstrTSX.td | 4 +- llvm/lib/Target/XCore/XCoreISelLowering.cpp | 1 + llvm/lib/Target/XCore/XCoreInstrInfo.td | 3 + .../Transforms/InstCombine/InstCombineCalls.cpp | 97 +- .../InstCombine/InstCombineSimplifyDemanded.cpp | 4 +- .../InstCombine/InstructionCombining.cpp | 36 +- .../lib/Transforms/Scalar/DeadStoreElimination.cpp | 7 + llvm/lib/Transforms/Scalar/LICM.cpp | 3 +- llvm/lib/Transforms/Scalar/SCCP.cpp | 7 + llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | 3 +- llvm/lib/Transforms/Utils/InjectTLIMappings.cpp | 9 - llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp | 29 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 9 - llvm/lib/Transforms/Vectorize/VectorCombine.cpp | 213 +-- .../ConstantFolding}/fp-undef.ll | 314 ++-- .../Analysis/CostModel/SystemZ/oldarch-vectors.ll | 13 + .../MemoryDependenceAnalysis/memdep_with_tbaa.ll | 125 ++ llvm/test/CodeGen/AArch64/O0-pipeline.ll | 1 + llvm/test/CodeGen/AArch64/O3-pipeline.ll | 1 + llvm/test/CodeGen/AArch64/sve-gep.ll | 139 ++ .../sve-intrinsics-contiguous-prefetches.ll | 252 +++ .../AArch64/sve-intrinsics-fp-arith-merging.ll | 261 ++++ ...pred-contiguous-ldst-addressing-mode-reg-imm.ll | 622 ++++++++ ...pred-contiguous-ldst-addressing-mode-reg-reg.ll | 610 ++++++++ ...ed-non-temporal-ldst-addressing-mode-reg-imm.ll | 171 +++ ...ed-non-temporal-ldst-addressing-mode-reg-reg.ll | 145 ++ llvm/test/CodeGen/AArch64/sve-vector-splat.ll | 101 +- llvm/test/CodeGen/AArch64/sve-vscale-combine.ll | 97 ++ .../AMDGPU/GlobalISel/combine-ashr-narrow.mir | 4 +- .../AMDGPU/GlobalISel/constant-bus-restriction.ll | 67 + llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll | 542 +++++++ llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll | 619 ++++++++ .../CodeGen/AMDGPU/GlobalISel/inst-select-and.mir | 12 +- .../AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir | 54 +- .../inst-select-build-vector-trunc.v2s16.mir | 272 +++- .../AMDGPU/GlobalISel/inst-select-fadd.s32.mir | 90 +- .../AMDGPU/GlobalISel/inst-select-fadd.s64.mir | 90 +- .../GlobalISel/inst-select-fcanonicalize.mir | 14 +- .../GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir | 11 +- .../GlobalISel/inst-select-fmaxnum.v2s16.mir | 11 +- .../GlobalISel/inst-select-fminnum-ieee.v2s16.mir | 10 +- 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.../CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll | 94 ++ .../AMDGPU/GlobalISel/regbankselect-smax.mir | 94 +- .../AMDGPU/GlobalISel/regbankselect-smin.mir | 94 +- .../AMDGPU/GlobalISel/regbankselect-umax.mir | 96 +- .../AMDGPU/GlobalISel/regbankselect-umin.mir | 96 +- llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll | 272 ++++ llvm/test/CodeGen/AMDGPU/skip-if-dead.ll | 35 + .../Hexagon/autohvx/vector-predicate-typecast.ll | 31 + llvm/test/CodeGen/PowerPC/aix-undef-func-call.ll | 20 + llvm/test/CodeGen/PowerPC/vrsave-inline-asm.ll | 42 + llvm/test/CodeGen/X86/avg.ll | 4 +- llvm/test/CodeGen/X86/avx-intrinsics-fast-isel.ll | 2 +- llvm/test/CodeGen/X86/avx-splat.ll | 2 +- llvm/test/CodeGen/X86/avx512-mask-op.ll | 433 ++++++ llvm/test/CodeGen/X86/avx512-select.ll | 178 +++ .../CodeGen/X86/avx512-shuffles/partial_permute.ll | 28 +- .../CodeGen/X86/bitcast-int-to-vector-bool-sext.ll | 10 +- .../CodeGen/X86/bitcast-int-to-vector-bool-zext.ll | 10 +- llvm/test/CodeGen/X86/cmov-fp.ll | 1608 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.../unittests/CodeGen/GlobalISel/KnownBitsTest.cpp | 38 + llvm/unittests/IR/DominatorTreeTest.cpp | 31 + llvm/unittests/Support/ARMAttributeParser.cpp | 2 +- llvm/unittests/Support/ErrorTest.cpp | 40 + llvm/unittests/TableGen/CMakeLists.txt | 2 +- llvm/utils/TableGen/X86RecognizableInstr.cpp | 3 + llvm/utils/TableGen/X86RecognizableInstr.h | 1 + llvm/utils/gn/secondary/clang/lib/AST/BUILD.gn | 2 +- .../gn/secondary/clang/lib/ASTMatchers/BUILD.gn | 1 + .../secondary/clang/unittests/ASTMatchers/BUILD.gn | 1 + .../gn/secondary/llvm/lib/BinaryFormat/BUILD.gn | 5 +- mlir/docs/LangRef.md | 11 +- mlir/docs/Rationale.md | 19 +- mlir/docs/Tutorials/Toy/Ch-4.md | 2 +- mlir/docs/Tutorials/Toy/Ch-5.md | 2 +- mlir/docs/Tutorials/Toy/Ch-6.md | 2 +- mlir/docs/WritingAPass.md | 2 +- mlir/examples/toy/Ch5/mlir/LowerToAffineLoops.cpp | 2 +- mlir/examples/toy/Ch6/mlir/LowerToAffineLoops.cpp | 2 +- mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp | 4 +- mlir/examples/toy/Ch7/mlir/LowerToAffineLoops.cpp | 2 +- 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mlir/include/mlir/IR/Matchers.h | 2 +- mlir/include/mlir/IR/OpBase.td | 19 +- mlir/include/mlir/IR/OpDefinition.h | 24 +- mlir/include/mlir/IR/OpImplementation.h | 10 + mlir/include/mlir/IR/Operation.h | 2 +- mlir/include/mlir/IR/StandardTypes.h | 51 +- mlir/include/mlir/IR/Types.h | 22 +- mlir/include/mlir/InitAllDialects.h | 2 +- mlir/include/mlir/Transforms/Utils.h | 2 +- mlir/lib/Analysis/AffineAnalysis.cpp | 2 +- mlir/lib/Analysis/AffineStructures.cpp | 2 +- mlir/lib/Analysis/NestedMatcher.cpp | 2 +- mlir/lib/Analysis/Utils.cpp | 6 +- .../AffineToStandard/AffineToStandard.cpp | 4 +- .../Conversion/GPUCommon/OpToFuncCallLowering.h | 2 +- .../Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp | 2 +- .../Conversion/GPUToSPIRV/ConvertGPUToSPIRV.cpp | 9 +- .../GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp | 2 +- .../lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp | 2 +- .../LoopToStandard/ConvertLoopToStandard.cpp | 2 +- mlir/lib/Conversion/LoopsToGPU/LoopsToGPU.cpp | 2 +- mlir/lib/Conversion/LoopsToGPU/LoopsToGPUPass.cpp | 2 +- .../StandardToLLVM/ConvertStandardToLLVM.cpp | 2 +- .../StandardToSPIRV/ConvertStandardToSPIRV.cpp | 2 +- .../StandardToSPIRV/LegalizeStandardForSPIRV.cpp | 2 +- .../Conversion/StandardToSPIRV/StandardToSPIRV.td | 2 +- .../VectorToLLVM/ConvertVectorToLLVM.cpp | 10 +- mlir/lib/Dialect/AffineOps/AffineOps.cpp | 2 +- mlir/lib/Dialect/AffineOps/EDSC/Builders.cpp | 6 +- .../FxpMathOps/Transforms/LowerUniformRealMath.cpp | 2 +- .../FxpMathOps/Transforms/UniformKernelUtils.h | 6 +- mlir/lib/Dialect/GPU/IR/GPUDialect.cpp | 4 +- .../Dialect/GPU/Transforms/AllReduceLowering.cpp | 2 +- .../lib/Dialect/GPU/Transforms/KernelOutlining.cpp | 2 +- .../Dialect/Linalg/Analysis/DependenceAnalysis.cpp | 2 +- mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp | 4 +- mlir/lib/Dialect/Linalg/Transforms/Promotion.cpp | 2 +- mlir/lib/Dialect/Linalg/Utils/Utils.cpp | 8 +- mlir/lib/Dialect/LoopOps/LoopOps.cpp | 146 +- .../LoopOps/Transforms/ParallelLoopFusion.cpp | 2 +- .../Dialect/QuantOps/Transforms/ConvertConst.cpp | 2 +- mlir/lib/Dialect/SPIRV/SPIRVLowering.cpp | 11 +- mlir/lib/Dialect/SPIRV/SPIRVOps.cpp | 8 +- .../Dialect/SPIRV/Serialization/Deserializer.cpp | 4 +- mlir/lib/Dialect/SPIRV/TargetAndABI.cpp | 2 +- mlir/lib/Dialect/StandardOps/CMakeLists.txt | 3 +- mlir/lib/Dialect/StandardOps/{ => IR}/Ops.cpp | 21 +- mlir/lib/Dialect/VectorOps/VectorOps.cpp | 8 +- mlir/lib/Dialect/VectorOps/VectorTransforms.cpp | 103 +- mlir/lib/Dialect/VectorOps/VectorUtils.cpp | 2 +- mlir/lib/ExecutionEngine/ExecutionEngine.cpp | 16 +- mlir/lib/IR/AsmPrinter.cpp | 42 +- mlir/lib/IR/Attributes.cpp | 79 +- mlir/lib/IR/Builders.cpp | 18 +- mlir/lib/IR/MLIRContext.cpp | 52 +- mlir/lib/IR/Operation.cpp | 10 +- mlir/lib/IR/StandardTypes.cpp | 71 +- mlir/lib/IR/TypeDetail.h | 47 +- mlir/lib/Parser/Lexer.cpp | 21 +- mlir/lib/Parser/Parser.cpp | 180 ++- mlir/lib/Parser/Token.cpp | 15 +- mlir/lib/Parser/Token.h | 5 + mlir/lib/Parser/TokenKinds.def | 2 +- .../lib/Quantizer/Configurations/FxpMathConfig.cpp | 2 +- .../Transforms/AffineLoopInvariantCodeMotion.cpp | 2 +- mlir/lib/Transforms/LoopCoalescing.cpp | 2 +- mlir/lib/Transforms/LoopFusion.cpp | 4 +- mlir/lib/Transforms/MemRefDataFlowOpt.cpp | 2 +- mlir/lib/Transforms/PipelineDataTransfer.cpp | 2 +- mlir/lib/Transforms/Utils/FoldUtils.cpp | 2 +- .../Utils/GreedyPatternRewriteDriver.cpp | 2 +- mlir/lib/Transforms/Utils/LoopFusionUtils.cpp | 2 +- mlir/lib/Transforms/Utils/Utils.cpp | 2 +- mlir/lib/Transforms/Vectorize.cpp | 2 +- mlir/test/Conversion/LoopsToGPU/parallel_loop.mlir | 4 +- .../Conversion/StandardToSPIRV/std-to-spirv.mlir | 38 + mlir/test/Dialect/Linalg/parallel_loops.mlir | 2 +- mlir/test/Dialect/Loops/invalid.mlir | 110 +- mlir/test/Dialect/Loops/ops.mlir | 132 +- mlir/test/Dialect/Loops/parallel-loop-fusion.mlir | 56 +- .../Dialect/SPIRV/Serialization/memory-ops.mlir | 34 + .../VectorOps/vector-contract-transforms.mlir | 81 + mlir/test/IR/dense-elements-hex.mlir | 28 + mlir/test/IR/invalid.mlir | 28 +- mlir/test/IR/parser.mlir | 6 + .../TestVectorTransformPatterns.td | 2 +- mlir/test/lib/IR/TestMatchers.cpp | 2 +- mlir/test/lib/TestDialect/TestDialect.cpp | 6 +- mlir/test/lib/TestDialect/TestPatterns.cpp | 6 +- mlir/test/lib/Transforms/TestConstantFold.cpp | 2 +- mlir/test/lib/Transforms/TestInlining.cpp | 2 +- mlir/test/lib/Transforms/TestLoopFusion.cpp | 2 +- mlir/test/lib/Transforms/TestMemRefBoundCheck.cpp | 2 +- .../lib/Transforms/TestMemRefDependenceCheck.cpp | 2 +- .../lib/Transforms/TestMemRefStrideCalculation.cpp | 2 +- mlir/test/lib/Transforms/TestOpaqueLoc.cpp | 2 +- mlir/test/lib/Transforms/TestVectorTransforms.cpp | 2 +- mlir/test/mlir-tblgen/op-attribute.td | 10 +- mlir/test/mlir-tblgen/predicate.td | 2 +- mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp | 2 +- openmp/runtime/test/lit.cfg | 7 + openmp/runtime/test/ompt/teams/parallel_team.c | 2 +- openmp/runtime/test/ompt/teams/serial_teams.c | 2 +- 420 files changed, 16594 insertions(+), 3214 deletions(-) create mode 100644 clang/include/clang/ASTMatchers/GtestMatchers.h rename clang/lib/AST/Interp/{Block.cpp => InterpBlock.cpp} (98%) rename clang/lib/AST/Interp/{Block.h => InterpBlock.h} (98%) create mode 100644 clang/lib/ASTMatchers/GtestMatchers.cpp create mode 100644 clang/test/Sema/warn-documentation-tag-typedef.cpp create mode 100644 clang/unittests/ASTMatchers/GtestMatchersTest.cpp create mode 100644 libc/config/linux/signal.h.in create mode 100644 libc/include/signal.h.def create mode 100644 libc/src/signal/CMakeLists.txt create mode 100644 libc/src/signal/linux/CMakeLists.txt create mode 100644 libc/src/signal/linux/raise.cpp create mode 100644 libc/src/signal/linux/signal.h create mode 100644 libc/src/signal/raise.h create mode 100644 libc/test/src/signal/CMakeLists.txt create mode 100644 libc/test/src/signal/raise_test.cpp delete mode 100644 libclc/generic/lib/math/acos.inc create mode 100644 lld/test/ELF/linkerscript/section-align2.test create mode 100644 lld/test/ELF/shuffle-sections-init-fini.s delete mode 100644 lldb/test/API/README.md create mode 100644 lldb/test/Shell/SymbolFile/DWARF/dwp-debug-types.s create mode 100644 lldb/test/Shell/VSCode/TestOptions.test create mode 100644 lldb/tools/lldb-vscode/Options.td create mode 100644 llvm/lib/BinaryFormat/MachO.cpp copy llvm/test/{Transforms/InstSimplify => Analysis/ConstantFolding}/fp-undef.ll (70%) create mode 100644 llvm/test/Analysis/CostModel/SystemZ/oldarch-vectors.ll create mode 100644 llvm/test/Analysis/MemoryDependenceAnalysis/memdep_with_tbaa.ll create mode 100644 llvm/test/CodeGen/AArch64/sve-gep.ll create mode 100644 llvm/test/CodeGen/AArch64/sve-intrinsics-contiguous-prefetches.ll create mode 100644 llvm/test/CodeGen/AArch64/sve-intrinsics-fp-arith-merging.ll create mode 100644 llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-m [...] create mode 100644 llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-m [...] create mode 100644 llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing [...] create mode 100644 llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing [...] create mode 100644 llvm/test/CodeGen/AArch64/sve-vscale-combine.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/fmul.v2f16.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shuffle-vector. [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll create mode 100644 llvm/test/CodeGen/Hexagon/autohvx/vector-predicate-typecast.ll create mode 100644 llvm/test/CodeGen/PowerPC/vrsave-inline-asm.ll create mode 100644 llvm/test/CodeGen/X86/pr44976.ll create mode 100644 llvm/test/CodeGen/XCore/bitrev.ll create mode 100644 llvm/test/Transforms/DeadStoreElimination/MSSA/debug-counter.ll copy llvm/test/{CodeGen => Transforms/InstCombine}/Hexagon/lit.local.cfg (100%) create mode 100644 llvm/test/Transforms/InstCombine/Hexagon/simplify-hvx-qvq.ll create mode 100644 llvm/test/Transforms/LICM/callbr-crash.ll create mode 100644 llvm/test/Transforms/SCCP/loadtest2.ll copy mlir/include/mlir/Dialect/StandardOps/{ => IR}/CMakeLists.txt (100%) rename mlir/include/mlir/Dialect/StandardOps/{ => IR}/Ops.h (98%) rename mlir/include/mlir/Dialect/StandardOps/{ => IR}/Ops.td (98%) rename mlir/lib/Dialect/StandardOps/{ => IR}/Ops.cpp (99%) create mode 100644 mlir/test/IR/dense-elements-hex.mlir -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 4 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-allyesconfig updated (ea9e9a73 -> 16b2dd77)

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5 years, 4 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allmodconfig updated (f55bf4ddbfa -> 8b3c0979ea1)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allmodconfig in repository toolchain/ci/gcc. from f55bf4ddbfa i386: Skip ENDBR32 at the target function entry adds bd2537ed5d4 i386: Fix *vec_extractv2sf_1 and *vec_extractv2sf_1 shufps [...] adds 8b3c0979ea1 Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 7 +++++++ gcc/DATESTAMP | 2 +- gcc/config/i386/mmx.md | 8 ++++---- 3 files changed, 12 insertions(+), 5 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 4 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allmodconfig updated (f8877ae7 -> 7a7b8ad7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-allmodconfig in repository toolchain/ci/base-artifacts. discards f8877ae7 0: update: binutils-gcc-linux: all new 7a7b8ad7 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (f8877ae7) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 172 +- 02-prepare_abe/console.log | 438 +- 03-build_abe-binutils/console.log | 11562 ++++++------- 04-build_abe-stage1/console.log | 18047 +++++++++++---------- 05-build_linux/console.log | 896 +- 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 10 +- console.log | 31397 ++++++++++++++++++------------------ jenkins/manifest.sh | 8 +- 10 files changed, 31232 insertions(+), 31302 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 4 months

[binutils-gdb] branch master updated (755251522af -> d4d947ae37f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository binutils-gdb. from 755251522af [gdb/testsuite] Fix gdb.go/methods.exp new d4d947ae37f Update partial_symtab comment The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gdb/ChangeLog | 4 ++++ gdb/psympriv.h | 3 +-- 2 files changed, 5 insertions(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 4 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-defconfig updated (f55bf4ddbfa -> 8b3c0979ea1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-defconfig in repository toolchain/ci/gcc. from f55bf4ddbfa i386: Skip ENDBR32 at the target function entry adds bd2537ed5d4 i386: Fix *vec_extractv2sf_1 and *vec_extractv2sf_1 shufps [...] adds 8b3c0979ea1 Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 7 +++++++ gcc/DATESTAMP | 2 +- gcc/config/i386/mmx.md | 8 ++++---- 3 files changed, 12 insertions(+), 5 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 4 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-defconfig updated (d6e75efd -> 27020c2e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-lts-defconfig in repository toolchain/ci/base-artifacts. discards d6e75efd 0: update: binutils-gcc-linux: boot new 27020c2e 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (d6e75efd) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 24 +- 02-prepare_abe/console.log | 418 +- 03-build_abe-binutils/console.log | 10617 ++++++------- 04-build_abe-stage1/console.log | 18146 +++++++++++---------- 05-build_linux/console.log | 828 +- 06-boot_linux/console.log | 472 +- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 2 +- console.log | 30503 ++++++++++++++++++------------------ jenkins/manifest.sh | 8 +- 10 files changed, 30489 insertions(+), 30531 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 4 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allnoconfig updated (d75ce45777d -> 3a91c12e7aa)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allnoconfig in repository toolchain/ci/llvm-project. from d75ce45777d Revert "[CMake] CheckAtomic.cmake: catch false positives in [...] adds da0fe2ade36 Filter callbr insts from critical edge splitting adds 3a91c12e7aa [docs] Add some LLDB release notes No new revisions were added by this update. Summary of changes: llvm/docs/ReleaseNotes.rst | 9 +++++++++ llvm/lib/Transforms/Scalar/LICM.cpp | 3 ++- llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | 3 ++- llvm/test/Transforms/LICM/callbr-crash.ll | 18 ++++++++++++++++++ 4 files changed, 31 insertions(+), 2 deletions(-) create mode 100644 llvm/test/Transforms/LICM/callbr-crash.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 4 months

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Tcwg-commits February 2020