Tcwg-commits December 2020

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[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-next-allyesconfig updated (9423103f54 -> 62fa7b3c6a)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-next-allyesconfig in repository toolchain/ci/binutils-gdb. from 9423103f54 Automatic date update in version.in adds dca11eb872 hurd: Fix getting VM_MIN/MAX_ADDRESS adds 06f6f78f62 hurd: Add changelog for dca11eb872c9 adds 05ecfa4726 Add myself to gdb/MAINTAINERS adds 016382f8a4 gdb: delete unused function print_char_chars adds 2c75ccb24c gdb: avoid accessing global C++ language implementation functions adds c5ee319e6c gdb: rename c_printchar as language_defn::printchar adds 76ca72bc5b gdb: remove LA_EMIT_CHAR macro adds 82fc57fd6b gdb: move go_language class declaration into header file adds 46157d77c3 gdb: move pascal_language into p-lang.h adds ed5797ee2c gdb/objc: fix bug in objc_language::opcode_print_table adds 1c4852651c gdb: move rust_language into rust-lang.h adds 5cc0917c38 gdb: remove some uses of LA_PRINT_STRING adds 279d901e5a x86-64: Add Intel LAM property support adds f37059ea22 Clarify language for the '?' packet adds 62fa7b3c6a Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 12 + bfd/elf-linker-x86.h | 28 +- bfd/elfxx-x86.c | 97 ++++-- bfd/version.h | 2 +- binutils/ChangeLog | 13 + binutils/NEWS | 2 + binutils/doc/binutils.texi | 3 +- binutils/elfedit.c | 8 +- binutils/readelf.c | 6 + binutils/testsuite/binutils-all/x86-64/lam-u48.d | 12 + binutils/testsuite/binutils-all/x86-64/lam-u48.s | 27 ++ binutils/testsuite/binutils-all/x86-64/lam-u57.d | 12 + binutils/testsuite/binutils-all/x86-64/lam-u57.s | 27 ++ gdb/ChangeLog | 172 ++++++++++ gdb/MAINTAINERS | 1 + gdb/c-lang.c | 7 +- gdb/c-lang.h | 2 - gdb/doc/ChangeLog | 4 + gdb/doc/gdb.texinfo | 7 +- gdb/dwarf2/read.c | 7 +- gdb/expprint.c | 19 +- gdb/f-lang.h | 2 +- gdb/f-valprint.c | 10 +- gdb/gnu-nat.c | 1 + gdb/go-exp.y | 4 +- gdb/go-lang.c | 164 +++------- gdb/go-lang.h | 94 +++++- gdb/go-typeprint.c | 6 +- gdb/go-valprint.c | 5 +- gdb/guile/scm-pretty-print.c | 4 +- gdb/language.c | 9 - gdb/language.h | 2 - gdb/objc-lang.c | 2 +- gdb/p-exp.y | 11 +- gdb/p-lang.c | 384 ++++++++-------------- gdb/p-lang.h | 245 ++++++++++++-- gdb/p-typeprint.c | 214 +++++------- gdb/p-valprint.c | 30 +- gdb/python/py-prettyprint.c | 4 +- gdb/rust-exp.y | 2 +- gdb/rust-lang.c | 397 +++++++---------------- gdb/rust-lang.h | 198 ++++++++++- gdb/symtab.c | 3 +- gdb/valprint.c | 37 --- gdb/valprint.h | 3 - include/ChangeLog | 5 + include/elf/common.h | 2 + ld/ChangeLog | 25 ++ ld/NEWS | 13 + ld/emulparams/cet.sh | 14 +- ld/emulparams/elf_x86_64.sh | 1 + ld/emulparams/x86-64-lam.sh | 69 ++++ ld/ld.texi | 44 +++ ld/testsuite/ld-x86-64/property-x86-lam-u48-1a.d | 11 + ld/testsuite/ld-x86-64/property-x86-lam-u48-1b.d | 11 + ld/testsuite/ld-x86-64/property-x86-lam-u48-2.d | 11 + ld/testsuite/ld-x86-64/property-x86-lam-u48-3a.d | 12 + ld/testsuite/ld-x86-64/property-x86-lam-u48-3b.d | 12 + ld/testsuite/ld-x86-64/property-x86-lam-u48-4.d | 11 + ld/testsuite/ld-x86-64/property-x86-lam-u48-5.d | 11 + ld/testsuite/ld-x86-64/property-x86-lam-u48.s | 27 ++ ld/testsuite/ld-x86-64/property-x86-lam-u57-1a.d | 11 + ld/testsuite/ld-x86-64/property-x86-lam-u57-1b.d | 11 + ld/testsuite/ld-x86-64/property-x86-lam-u57-2.d | 11 + ld/testsuite/ld-x86-64/property-x86-lam-u57-3a.d | 12 + ld/testsuite/ld-x86-64/property-x86-lam-u57-3b.d | 12 + ld/testsuite/ld-x86-64/property-x86-lam-u57-4.d | 11 + ld/testsuite/ld-x86-64/property-x86-lam-u57-5.d | 11 + ld/testsuite/ld-x86-64/property-x86-lam-u57.s | 27 ++ ld/testsuite/ld-x86-64/x86-64.exp | 14 + 70 files changed, 1719 insertions(+), 979 deletions(-) create mode 100644 binutils/testsuite/binutils-all/x86-64/lam-u48.d create mode 100644 binutils/testsuite/binutils-all/x86-64/lam-u48.s create mode 100644 binutils/testsuite/binutils-all/x86-64/lam-u57.d create mode 100644 binutils/testsuite/binutils-all/x86-64/lam-u57.s create mode 100644 ld/emulparams/x86-64-lam.sh create mode 100644 ld/testsuite/ld-x86-64/property-x86-lam-u48-1a.d create mode 100644 ld/testsuite/ld-x86-64/property-x86-lam-u48-1b.d create mode 100644 ld/testsuite/ld-x86-64/property-x86-lam-u48-2.d create mode 100644 ld/testsuite/ld-x86-64/property-x86-lam-u48-3a.d create mode 100644 ld/testsuite/ld-x86-64/property-x86-lam-u48-3b.d create mode 100644 ld/testsuite/ld-x86-64/property-x86-lam-u48-4.d create mode 100644 ld/testsuite/ld-x86-64/property-x86-lam-u48-5.d create mode 100644 ld/testsuite/ld-x86-64/property-x86-lam-u48.s create mode 100644 ld/testsuite/ld-x86-64/property-x86-lam-u57-1a.d create mode 100644 ld/testsuite/ld-x86-64/property-x86-lam-u57-1b.d create mode 100644 ld/testsuite/ld-x86-64/property-x86-lam-u57-2.d create mode 100644 ld/testsuite/ld-x86-64/property-x86-lam-u57-3a.d create mode 100644 ld/testsuite/ld-x86-64/property-x86-lam-u57-3b.d create mode 100644 ld/testsuite/ld-x86-64/property-x86-lam-u57-4.d create mode 100644 ld/testsuite/ld-x86-64/property-x86-lam-u57-5.d create mode 100644 ld/testsuite/ld-x86-64/property-x86-lam-u57.s -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-next-allyesconfig updated (34d8f5c06 -> c031294dd)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-next-allyesconfig in repository toolchain/ci/base-artifacts. discards 34d8f5c06 4: update: binutils-gcc-linux-qemu: 22 new c031294dd 4: update: binutils-gcc-linux-qemu: 22 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (34d8f5c06) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-ne [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-prepare_abe/console.log | 110 +- 03-build_abe-binutils/console.log | 11652 ++++---- 04-build_abe-stage1/console.log | 20763 ++++++------- 05-build_linux/console.log | 13902 +++++---- 08-check_regression/console.log | 12 +- 08-check_regression/results.regressions | 20 +- 09-update_baseline/console.log | 146 +- 09-update_baseline/results.regressions | 20 +- console.log | 46871 +++++++++++++++--------------- jenkins/manifest.sh | 12 +- 11 files changed, 46871 insertions(+), 46857 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allnoconfig updated (614cb5894306 -> 58cf05f597b0)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allnoconfig in repository toolchain/ci/linux. from 614cb5894306 Merge tag 'acpi-5.11-rc1-2' of git://git.kernel.org/pub/sc [...] adds 7f6f1dfb2dcb watchdog: armada_37xx: Add missing dependency on HAS_IOMEM adds 8ae2511112d2 watchdog: sirfsoc: Add missing dependency on HAS_IOMEM adds f61a59acb462 watchdog: sprd: remove watchdog disable from resume fail path adds 3e07d2409398 watchdog: sprd: check busy bit before new loading rather t [...] adds 2a6c9c65b2fe watchdog: sprd: change to use usleep_range() instead of busy loop adds 7c7164f935c8 watchdog: stm32_iwdg: don't print an error on probe deferral adds 4600736f050f watchdog: remove pnx83xx driver adds 8650d0f9e933 watchdog: qcom_wdt: set WDOG_HW_RUNNING bit when appropriate adds 8711071e9700 watchdog: rti-wdt: fix reference leak in rti_wdt_probe adds 9747f12b5be9 watchdog: geodewdt: remove unneeded break adds 347755d2a88e watchdog: sbc_fitpc2_wdt: add __user annotations adds 42e967f3c6cb wdt: sp805: add watchdog_stop on reboot adds acc195bd2cc4 watchdog/hpwdt: Disable NMI in Crash Kernel adds 5674b74e52c0 watchdog/hpwdt: Reflect changes adds 24f98562bb5b watchdog: wdat_wdt: Fix missing kerneldoc reported by W=1 adds 6f733cb2e7db watchdog: Fix potential dereferencing of null pointer adds 89c866f5a238 watchdog: iTCO_wdt: use module_platform_device() macro adds 7948fab26bcc watchdog: qcom: Avoid context switch in restart handler adds 8cbd82d62f45 dt-bindings: watchdog: sun4i: Add A100 compatible adds 36c47df85ee8 watchdog: coh901327: add COMMON_CLK dependency adds e629fffcc333 dt-binding: watchdog: add Rockchip compatibles to snps,dw- [...] adds c21172b3a73e watchdog: iTCO_wdt: use dev_*() instead of pr_*() for logging adds 0b9491b62119 watchdog: convert comma to semicolon adds 6755f4563144 Merge tag 'linux-watchdog-5.11-rc1' of git://www.linux-wat [...] adds 853c1a789f5f platform/chrome: Don't treat RTC events as wakeup sources adds 0498710be002 platform/chrome: cros_ec_typec: Relocate set_port_params_v [...] adds 7ab5a673f4ce platform/chrome: cros_ec_typec: Fix remove partner logic adds 514acf1cefd0 platform/chrome: cros_ec_typec: Clear partner identity on [...] adds cd2c40ff90b0 platform/chrome: cros_ec: Import Type C host commands adds 80f8cef60d79 platform/chrome: cros_ec_typec: Introduce TYPEC_STATUS adds f6f668118918 platform/chrome: cros_ec_typec: Parse partner PD ID VDOs adds de0f49487db3 platform/chrome: cros_ec_typec: Register partner altmodes adds 6ae9b5ffcaeb platform/chrome: cros_ec_typec: Tolerate unrecognized mux flags adds a0881596757f Merge tag 'tag-chrome-platform-for-v5.11' of git://git.ker [...] adds 34cdf405aa5d ALSA: hda/realtek: Remove dummy lineout on Acer TravelMate [...] adds 150927c3674d ALSA: hda/realtek - Supported Dell fixed type headset adds 74c64efa1557 ALSA: core: memalloc: add page alignment for iram adds 725124d10d00 ALSA: usb-audio: Add VID to support native DSD reproductio [...] adds f2283366c291 ALSA: pcm: Remove snd_pcm_lib_preallocate_dma_free() adds 9df28edce7c6 ALSA: usb-audio: Disable sample read check if firmware doe [...] adds 5c1733e33c88 ALSA: memalloc: Align buffer allocations in page size adds 618de0f4ef11 ALSA: pcm: Clear the full allocated memory at hw_params adds 11cb881bf075 ALSA: pcm: oss: Fix a few more UBSAN fixes adds 09926202e939 ALSA: hda/realtek: Add quirk for MSI-GP73 adds 8b7c764e0644 ALSA: core: Remove redundant comments adds 525d9c57d0ee ALSA: usb-audio: Add alias entry for ASUS PRIME TRX40 PRO-S adds 43877226829e ALSA: usb-audio: Add implicit feeback support for the BOSS GT-1 adds 6ca653e3f73a ALSA: hda/realtek: Apply jack fixup for Quanta NL3 adds 13be30f156fd ALSA/hda: apply jack fixup for the Acer Veriton N4640G/N66 [...] adds 58cf05f597b0 Merge tag 'sound-fix-5.11-rc1' of git://git.kernel.org/pub [...] No new revisions were added by this update. Summary of changes: .../bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 3 + .../devicetree/bindings/watchdog/snps,dw-wdt.yaml | 10 +- drivers/platform/chrome/cros_ec_proto.c | 14 +- drivers/platform/chrome/cros_ec_typec.c | 336 ++++++++++++++++----- drivers/watchdog/Kconfig | 14 +- drivers/watchdog/Makefile | 1 - drivers/watchdog/geodewdt.c | 2 - drivers/watchdog/hpwdt.c | 8 +- drivers/watchdog/iTCO_wdt.c | 34 +-- drivers/watchdog/mpc8xxx_wdt.c | 4 +- drivers/watchdog/pnx833x_wdt.c | 277 ----------------- drivers/watchdog/qcom-wdt.c | 20 +- drivers/watchdog/rti_wdt.c | 4 +- drivers/watchdog/sbc_fitpc2_wdt.c | 12 +- drivers/watchdog/sp805_wdt.c | 1 + drivers/watchdog/sprd_wdt.c | 43 ++- drivers/watchdog/stm32_iwdg.c | 13 +- drivers/watchdog/watchdog_core.c | 22 +- drivers/watchdog/wdat_wdt.c | 6 +- include/linux/platform_data/cros_ec_commands.h | 155 ++++++++++ sound/core/init.c | 2 - sound/core/memalloc.c | 4 +- sound/core/oss/pcm_oss.c | 22 +- sound/core/pcm_memory.c | 10 +- sound/core/pcm_native.c | 9 +- sound/pci/hda/patch_realtek.c | 33 ++ sound/usb/card.c | 3 + sound/usb/clock.c | 6 + sound/usb/implicit.c | 2 + sound/usb/quirks.c | 1 + 30 files changed, 601 insertions(+), 470 deletions(-) delete mode 100644 drivers/watchdog/pnx833x_wdt.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allnoconfig updated (c5f162785 -> 8ad5ed0c8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-mainline-allnoconfig in repository toolchain/ci/base-artifacts. discards c5f162785 0: update: llvm-linux-qemu: boot new 8ad5ed0c8 0: update: llvm-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (c5f162785) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 172 +- 02-prepare_abe/console.log | 440 +- 03-build_llvm/console.log | 13166 ++++++++++++++-------------- 04-build_linux/console.log | 648 +- 05-build_abe-qemu/console.log | 3400 ++++---- 06-boot_linux/console.log | 4 +- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 2 +- console.log | 17834 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 10 files changed, 17838 insertions(+), 17838 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig updated (3c707d73f26 -> 30365472489)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig in repository toolchain/ci/llvm-project. from 3c707d73f26 [NewGVN] Remove for_each_found (NFC) adds 0219cf7dfaf [NewPM] Fix objc-arc-apelim pass typo adds 4d479443934 [RISCV] Define the vfmin, vfmax RVV intrinsics adds 032600b9aef [RISCV] Define vmerge/vfmerge intrinsics. adds bdef1f87aba [llvm-readobj] - Dump the ELF file type better. adds 6301871d06d [RISCV] Add intrinsics for vfwmacc, vfwnmacc, vfwmsac, vfwn [...] adds 221fdedc692 [AMDGPU][GlobalISel] Fold flat vgpr + constant addresses adds 65ba0cd3955 [mlir] Modernize std-to-llvm operation conversion doc adds 8451d4872ed [mlir] NFC: Remove ConvertToLLVMPattern::getDataPtr(). All [...] adds 32a884c9c52 [mlir] Add translation of omp.wsloop to LLVM IR adds 19a0d0a40ce [mlir] Rename ConvertToLLVMPattern::isSupportedMemRefType() [...] adds 25a02c3d1a6 Revert "PR24076, PR33655, C++ CWG 1558: Consider the instan [...] adds eb9483b2105 [format] Add overload to parseConfiguration that accept llv [...] adds 7ed9cfc7b19 [mlir] Remove static constructors from LLVMType adds c3acda0798f [VE] Vector 'and' isel and tests adds acaa6e4260c [NFC] Uniquify 'const' in TargetTransformInfoImpl.h adds a9f14cdc620 [ARM] Add bank conflict hazarding adds 6e603464959 [OpenMP] Fixing Typo in Documentation adds 5426b2f9ed9 [clang-format] PR48535 clang-format Incorrectly Removes Spa [...] adds 031743cb5b3 [clang-format] PR48539 ReflowComments breaks Qt translation [...] adds 1d0dc9be6d7 [MLIR][SPIRV] Add rewrite pattern to convert select+cmp int [...] adds 2522fa053b6 [clangd] Do not take stale definition from the static index. adds 9fb074e7bb1 [BPI] Improve static heuristics for "cold" paths. adds e122a71a0a2 [TableGen] Add the !substr() bang operator adds 9d1140e18e6 [lld-macho] Simulator & DriverKit executables should always be PIE adds 631501b1f90 [OpenMP] Fixing typo on memory size in Documenation adds 7ad666798f1 Revert 741978d727 and things that landed on top of it. adds 42980a789d2 [mlir][spirv] Convert functions returning one value adds fcf9479f7d6 [lldb] Don't instrument demangling. adds a9448872fec [lldb] Refactor and simplify GetCommandSPExact interface adds e0110a47402 [RISCV] Add intrinsics for vfmv.v.f adds b920adf3b4f This is a test commit adds 3b3a9d24188 Updated GettingInvolved.md to reflect Flang Biweekly Call changes adds b1191c84380 [IROutliner] Adding support for elevating constants that ar [...] adds bbd758a7913 Revert "This is a test commit" adds 1876a2914fe Revert more changes that landed on top of 741978d727 adds 74186880ba9 [mlir][vector] Add more vector Ops canonicalization adds 4c37453a04f clang: Build and run FrontendTests with CLANG_ENABLE_STATIC [...] adds e1248447092 [LoopIdiom] Introduce 'left-shift until bittest' idiom adds cb2e5980bae [LoopIdiom] 'left-shift until bittest' idiom: support const [...] adds a0ddc61c5b9 [LoopIdiom] 'left-shift until bittest' idiom: support canon [...] adds 2b61e7c68cd [LoopIdiom] 'left-shift until bittest' idiom: support rewri [...] adds a16fbff17d3 [mlir][spirv] Create a pass for testing SCFToSPIRV patterns adds 34e70d722df Append ".__part." to every basic block section symbol. adds 930c74f12d7 [mlir][spirv] NFC: rename SPIR-V conversion files for consistency adds 897990e614c [IROutliner] Use isa instead of dyn_cast where the casted v [...] adds ae895ac4b9f [mlir][spirv] De-template deserialization adds fc41777702a [mlir][spirv] De-template serialization adds de127d83d81 [InstCombine] Add tests for PR48577 (NFC) adds 899faa50f20 [InstCombine] Check inbounds in load/store of gep null tran [...] adds 1a7ac29a89f [RISCV] Add ISel support for RVV vector/scalar forms adds c7e825b910a [format][NFC] Use unsigned char as the base of all enums in [...] adds 87087a02ae4 [InstCombine] Add tests for gep of null (NFC) adds eb79fd3c928 [InstCombine] Fold gep inbounds of null to null adds 759b8c11c39 [InstCombine] Handle different pointer types when folding g [...] adds cce473e0c56 [IRSim] Adding commutativity matching to structure checking adds 05039266024 [IRSim] Adding support for isomorphic predicates adds f8079355c60 [InstCombine] canonicalizeAbsNabs(): don't propagate NSW fl [...] adds 374f1d81feb [clang-format] Fix handling of TextProto comments adds 47877c9079c [clang-format] Add SpaceBeforeCaseColon option adds 45a4f34bd19 Revert "[IRSim] Adding support for isomorphic predicates" adds 74b3acefc7b [clangd] Fix case mismatch crash on in CDB on windows after [...] adds d97e9f1a3d8 [lldb] Simplify ObjectFile::FindPlugin (NFC) adds 7143923f86b Fix lldb test failure due to D93082. adds be89d7460b6 [lld][test] Relax test assertion of cmake defaults appearin [...] adds 747f67e034a [AMDGPU] Fix adjustWritemask subreg handling adds 245218bb355 Basic: Support named pipes natively in SourceManager and Fi [...] adds 3ee43adfb20 Basic: Add native support for stdin to SourceManager and Fi [...] adds ca1ab0c66d1 [mlir] Add tensor passes to passes.md adds d29f93bda51 [DAGCombiner] Don't create sexts of deleted xors when they [...] adds 69132d12dea [Clang] Reverse test to save on indentation. NFC. adds 48ad8194a56 [IRSim] Adding support for isomorphic predicates adds db7a2f347f1 Precommit transform tests that have poison as insertelement [...] adds 30365472489 Precommit analysis/etc tests for inselt poison placeholder No new revisions were added by this update. Summary of changes: .../clangd/GlobalCompilationDatabase.cpp | 11 +- clang-tools-extra/clangd/index/Merge.cpp | 6 + clang-tools-extra/clangd/unittests/IndexTests.cpp | 34 + clang/docs/ClangFormatStyleOptions.rst | 10 + clang/docs/ReleaseNotes.rst | 3 + clang/docs/tools/dump_format_style.py | 2 +- clang/include/clang/AST/Type.h | 4 +- clang/include/clang/Basic/CodeGenOptions.h | 2 - clang/include/clang/Basic/DiagnosticDriverKinds.td | 2 + .../include/clang/Basic/DiagnosticFrontendKinds.td | 2 + clang/include/clang/Basic/FileEntry.h | 9 + clang/include/clang/Basic/FileManager.h | 11 + clang/include/clang/Driver/Options.td | 1362 +++---- clang/include/clang/Format/Format.h | 81 +- clang/lib/AST/ItaniumMangle.cpp | 4 - clang/lib/Basic/FileEntry.cpp | 1 + clang/lib/Basic/FileManager.cpp | 25 +- clang/lib/Basic/SourceManager.cpp | 50 +- clang/lib/CodeGen/CodeGenAction.cpp | 126 +- clang/lib/Format/BreakableToken.cpp | 13 +- clang/lib/Format/Format.cpp | 18 +- clang/lib/Format/TokenAnnotator.cpp | 15 +- clang/lib/Frontend/CompilerInstance.cpp | 58 +- clang/lib/Frontend/CompilerInvocation.cpp | 902 ++++- clang/test/CXX/drs/dr15xx.cpp | 14 - clang/test/CodeGen/basic-block-sections.c | 10 +- clang/test/CodeGenCXX/mangle-template.cpp | 20 - clang/test/Format/error-config.cpp | 4 +- clang/test/Misc/dev-fd-fs.c | 13 + clang/test/Profile/c-generate.c | 2 +- .../test/SemaTemplate/instantiation-dependence.cpp | 74 - .../test/SemaTemplate/partial-spec-instantiate.cpp | 18 +- clang/unittests/CMakeLists.txt | 2 +- clang/unittests/Format/FormatTest.cpp | 135 + clang/unittests/Format/FormatTestComments.cpp | 6 + clang/unittests/Format/FormatTestTextProto.cpp | 16 +- .../unittests/Frontend/CompilerInvocationTest.cpp | 84 +- clang/www/cxx_dr_status.html | 2 +- flang/docs/GettingInvolved.md | 6 +- lld/MachO/Driver.cpp | 33 +- lld/test/ELF/lto/basic-block-sections.ll | 8 +- lld/test/MachO/driver.test | 2 +- lld/test/MachO/platform-version.s | 2 +- lld/test/MachO/x86-64-reloc-unsigned.s | 4 + lldb/include/lldb/Interpreter/CommandInterpreter.h | 2 +- lldb/source/Commands/CommandObjectCommands.cpp | 7 +- lldb/source/Core/Mangled.cpp | 9 - lldb/source/Interpreter/CommandInterpreter.cpp | 139 +- lldb/source/Symbol/ObjectFile.cpp | 228 +- lldb/test/Shell/Unwind/basic-block-sections.test | 14 +- llvm/docs/TableGen/ProgRef.rst | 10 +- llvm/include/llvm/Analysis/BranchProbabilityInfo.h | 153 +- .../include/llvm/Analysis/IRSimilarityIdentifier.h | 37 +- .../llvm/Analysis/LazyBranchProbabilityInfo.h | 2 +- .../llvm/Analysis/TargetTransformInfoImpl.h | 196 +- llvm/include/llvm/IR/IntrinsicsRISCV.td | 15 + llvm/include/llvm/Option/OptParser.td | 18 +- llvm/include/llvm/TableGen/Record.h | 2 +- llvm/include/llvm/Transforms/IPO/IROutliner.h | 13 +- llvm/lib/Analysis/BranchProbabilityInfo.cpp | 645 ++-- llvm/lib/Analysis/IRSimilarityIdentifier.cpp | 226 +- llvm/lib/Analysis/OptimizationRemarkEmitter.cpp | 2 +- llvm/lib/CodeGen/MachineBasicBlock.cpp | 5 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 14 +- llvm/lib/Passes/PassRegistry.def | 2 +- llvm/lib/TableGen/Record.cpp | 28 +- llvm/lib/TableGen/TGLexer.cpp | 1 + llvm/lib/TableGen/TGLexer.h | 6 +- llvm/lib/TableGen/TGParser.cpp | 95 +- llvm/lib/TableGen/TGParser.h | 1 + .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 18 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 4 +- llvm/lib/Target/ARM/ARM.td | 4 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 25 + llvm/lib/Target/ARM/ARMBaseInstrInfo.h | 4 + llvm/lib/Target/ARM/ARMHazardRecognizer.cpp | 173 + llvm/lib/Target/ARM/ARMHazardRecognizer.h | 32 + llvm/lib/Target/ARM/ARMSubtarget.cpp | 1 + llvm/lib/Target/ARM/ARMSubtarget.h | 2 + llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 46 + llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h | 3 + llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 57 + llvm/lib/Target/RISCV/RISCVISelLowering.h | 4 + llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 191 +- llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td | 166 + llvm/lib/Target/VE/VVPInstrInfo.td | 3 + llvm/lib/Target/VE/VVPInstrPatternsVec.td | 3 + llvm/lib/Target/VE/VVPNodes.def | 1 + llvm/lib/Transforms/IPO/IROutliner.cpp | 209 +- .../InstCombine/InstCombineLoadStoreAlloca.cpp | 24 +- .../Transforms/InstCombine/InstCombineSelect.cpp | 7 +- .../InstCombine/InstructionCombining.cpp | 7 + llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 326 +- llvm/lib/Transforms/Scalar/LoopPredication.cpp | 2 +- .../Analysis/BlockFrequencyInfo/redundant_edges.ll | 2 +- llvm/test/Analysis/BranchProbabilityInfo/basic.ll | 40 +- .../BranchProbabilityInfo/deopt-intrinsic.ll | 4 +- .../Analysis/BranchProbabilityInfo/deopt-invoke.ll | 107 + llvm/test/Analysis/BranchProbabilityInfo/loop.ll | 209 +- .../Analysis/BranchProbabilityInfo/noreturn.ll | 35 +- .../Analysis/BranchProbabilityInfo/unreachable.ll | 154 + .../CostModel/AArch64/kryo-inseltpoison.ll | 26 + .../PowerPC/insert_extract-inseltpoison.ll | 187 + .../CostModel/SystemZ/vectorinstrs-inseltpoison.ll | 56 + .../X86/insert-extract-at-zero-inseltpoison.ll | 40 + .../Analysis/CostModel/X86/loop_v2-inseltpoison.ll | 39 + .../X86/masked-intrinsic-cost-inseltpoison.ll | 1911 ++++++++++ .../CostModel/X86/uniformshift-inseltpoison.ll | 39 + .../CostModel/X86/vector-insert-inseltpoison.ll | 1270 +++++++ .../CostModel/X86/vector_gep-inseltpoison.ll | 17 + .../CostModel/X86/vshift-ashr-cost-inseltpoison.ll | 1843 ++++++++++ .../CostModel/X86/vshift-lshr-cost-inseltpoison.ll | 1867 ++++++++++ .../CostModel/X86/vshift-shl-cost-inseltpoison.ll | 2197 +++++++++++ .../Analysis/DemandedBits/vectors-inseltpoison.ll | 136 + .../irtranslator-invoke-probabilities.ll | 2 +- .../GlobalISel/extractelement-stack-lower.ll | 1675 +++++---- .../CodeGen/AMDGPU/GlobalISel/extractelement.ll | 16 +- .../test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll | 64 +- .../AMDGPU/GlobalISel/llvm.amdgcn.atomic.inc.ll | 260 +- .../GlobalISel/llvm.amdgcn.global.atomic.fadd.ll | 30 +- .../CodeGen/AMDGPU/GlobalISel/load-constant.96.ll | 89 +- .../transform-block-with-return-to-epilog.ll | 4 +- llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll | 2 +- llvm/test/CodeGen/ARM/sub-cmp-peephole.ll | 2 +- .../CodeGen/ARM/v8m.base-jumptable_alignment.ll | 22 +- llvm/test/CodeGen/PowerPC/p10-spill-crgt.ll | 182 +- llvm/test/CodeGen/PowerPC/pr36292.ll | 5 +- llvm/test/CodeGen/PowerPC/sms-cpy-1.ll | 1 + llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv32.ll | 822 +++++ llvm/test/CodeGen/RISCV/rvv/vadd-sdnode-rv64.ll | 794 ++++ llvm/test/CodeGen/RISCV/rvv/vfmax-rv32.ll | 881 +++++ llvm/test/CodeGen/RISCV/rvv/vfmax-rv64.ll | 1201 ++++++ llvm/test/CodeGen/RISCV/rvv/vfmerge-rv32.ll | 441 +++ llvm/test/CodeGen/RISCV/rvv/vfmerge-rv64.ll | 601 +++ llvm/test/CodeGen/RISCV/rvv/vfmin-rv32.ll | 881 +++++ llvm/test/CodeGen/RISCV/rvv/vfmin-rv64.ll | 1201 ++++++ llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv32.ll | 421 +++ llvm/test/CodeGen/RISCV/rvv/vfmv.v.f-rv64.ll | 421 +++ llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv32.ll | 482 +++ llvm/test/CodeGen/RISCV/rvv/vfwmacc-rv64.ll | 868 +++++ llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv32.ll | 482 +++ llvm/test/CodeGen/RISCV/rvv/vfwmsac-rv64.ll | 868 +++++ llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv32.ll | 482 +++ llvm/test/CodeGen/RISCV/rvv/vfwnmacc-rv64.ll | 868 +++++ llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv32.ll | 482 +++ llvm/test/CodeGen/RISCV/rvv/vfwnmsac-rv64.ll | 868 +++++ llvm/test/CodeGen/RISCV/rvv/vmerge-rv32.ll | 973 +++++ llvm/test/CodeGen/RISCV/rvv/vmerge-rv64.ll | 1189 ++++++ llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv32.ll | 1109 ++++++ llvm/test/CodeGen/RISCV/rvv/vor-sdnode-rv64.ll | 1081 ++++++ llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv32.ll | 845 +++++ llvm/test/CodeGen/RISCV/rvv/vshl-sdnode-rv64.ll | 817 +++++ llvm/test/CodeGen/RISCV/rvv/vsplats-i64.ll | 266 ++ llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv32.ll | 845 +++++ llvm/test/CodeGen/RISCV/rvv/vsrl-sdnode-rv64.ll | 817 +++++ llvm/test/CodeGen/SPARC/missinglabel.ll | 2 +- llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir | 4 +- llvm/test/CodeGen/SystemZ/sext-zext.ll | 19 + llvm/test/CodeGen/Thumb2/schedm7-hazard.ll | 38 + llvm/test/CodeGen/VE/Vector/vec_and.ll | 132 + .../WebAssembly/switch-unreachable-default.ll | 4 +- llvm/test/CodeGen/X86/2008-04-17-CoalescerBug.ll | 19 +- .../X86/basic-block-sections-blockaddress-taken.ll | 4 +- .../X86/basic-block-sections-clusters-branches.ll | 8 +- .../X86/basic-block-sections-clusters-eh.ll | 4 +- .../CodeGen/X86/basic-block-sections-clusters.ll | 8 +- .../X86/basic-block-sections-directjumps.ll | 14 +- llvm/test/CodeGen/X86/basic-block-sections-eh.ll | 4 +- llvm/test/CodeGen/X86/basic-block-sections-list.ll | 16 +- .../CodeGen/X86/basic-block-sections-listbb.ll | 4 +- .../CodeGen/X86/basic-block-sections-mir-parse.mir | 6 +- .../X86/basic-block-sections-unreachable.ll | 2 +- llvm/test/CodeGen/X86/basic-block-sections.ll | 12 +- llvm/test/CodeGen/X86/basic-block-sections_2.ll | 61 + llvm/test/CodeGen/X86/block-placement.ll | 4 +- .../test/CodeGen/X86/cfi-basic-block-sections-1.ll | 8 +- ...r-basic-block-sections-callee-save-registers.ll | 4 +- .../CodeGen/X86/gcc_except_table_bb_sections.ll | 22 +- .../CodeGen/X86/misched_phys_reg_assign_order.ll | 6 +- llvm/test/CodeGen/X86/pr27501.ll | 10 +- llvm/test/CodeGen/X86/pr37916.ll | 2 +- llvm/test/CodeGen/X86/ragreedy-hoist-spill.ll | 117 +- llvm/test/DebugInfo/X86/basic-block-sections_1.ll | 24 +- .../X86/stack-value-piece-inseltpoison.ll | 114 + llvm/test/Object/elf-unknown-type.test | 10 - llvm/test/Other/scalable-vectors-core-ir.ll | 12 +- llvm/test/TableGen/substr.td | 81 + .../Attributor/dereferenceable-2-inseltpoison.ll | 847 +++++ llvm/test/Transforms/BDCE/vectors-inseltpoison.ll | 102 + .../AArch64/gather-scatter-opt-inseltpoison.ll | 113 + .../bypass-slow-div-debug-info-inseltpoison.ll | 76 + .../ARM/sink-add-mul-shufflevector-inseltpoison.ll | 219 ++ .../CodeGenPrepare/ARM/sinkchain-inseltpoison.ll | 107 + .../X86/gather-scatter-opt-inseltpoison.ll | 113 + .../X86/sink-addrmode-inseltpoison.ll | 321 ++ .../CodeGenPrepare/X86/vec-shift-inseltpoison.ll | 406 +++ .../X86/x86-shuffle-sink-inseltpoison.ll | 257 ++ .../2016-08-30-MaskedScatterGather-inseltpoison.ll | 42 + ...xpr-vector-constainsundef-crash-inseltpoison.ll | 25 + .../GVN/non-integral-pointers-inseltpoison.ll | 456 +++ .../IROutliner/outlining-commutative-fp.ll | 107 + .../Transforms/IROutliner/outlining-commutative.ll | 254 ++ .../IROutliner/outlining-constants-vs-registers.ll | 42 +- .../IROutliner/outlining-different-constants.ll | 24 +- .../IROutliner/outlining-different-globals.ll | 14 +- .../IROutliner/outlining-isomorphic-predicates.ll | 170 + .../AMDGPU/old-pass-regressions-inseltpoison.ll | 143 + .../dereferenceable-inseltpoison.ll | 357 ++ .../AArch64/sve-bitcast-inseltpoison.ll | 13 + .../amdgcn-demanded-vector-elts-inseltpoison.ll | 3828 ++++++++++++++++++++ .../InstCombine/X86/x86-addsub-inseltpoison.ll | 194 + .../InstCombine/X86/x86-avx512-inseltpoison.ll | 3407 +++++++++++++++++ .../InstCombine/X86/x86-pack-inseltpoison.ll | 635 ++++ .../InstCombine/X86/x86-sse-inseltpoison.ll | 694 ++++ .../InstCombine/X86/x86-sse2-inseltpoison.ll | 541 +++ .../InstCombine/X86/x86-sse41-inseltpoison.ll | 124 + .../X86/x86-vec_demanded_elts-inseltpoison.ll | 110 + .../X86/x86-vector-shifts-inseltpoison.ll | 3783 +++++++++++++++++++ .../InstCombine/X86/x86-xop-inseltpoison.ll | 305 ++ llvm/test/Transforms/InstCombine/abs-1.ll | 6 +- llvm/test/Transforms/InstCombine/abs_abs.ll | 148 +- .../Transforms/InstCombine/bitcast-inseltpoison.ll | 573 +++ .../InstCombine/bitcast-vec-canon-inseltpoison.ll | 167 + .../InstCombine/broadcast-inseltpoison.ll | 179 + .../InstCombine/extractelement-inseltpoison.ll | 332 ++ .../InstCombine/fold-vector-zero-inseltpoison.ll | 35 + llvm/test/Transforms/InstCombine/getelementptr.ll | 34 + .../InstCombine/icmp-bc-vec-inseltpoison.ll | 127 + .../InstCombine/inselt-binop-inseltpoison.ll | 635 ++++ .../insert-extract-shuffle-inseltpoison.ll | 735 ++++ llvm/test/Transforms/InstCombine/load.ll | 19 +- .../InstCombine/masked_intrinsics-inseltpoison.ll | 271 ++ .../Transforms/InstCombine/pr38984-inseltpoison.ll | 41 + .../InstCombine/scalarization-inseltpoison.ll | 335 ++ .../select-extractelement-inseltpoison.ll | 213 ++ llvm/test/Transforms/InstCombine/select_meta.ll | 4 +- .../InstCombine/shift-add-inseltpoison.ll | 122 + .../shufflevector-div-rem-inseltpoison.ll | 122 + llvm/test/Transforms/InstCombine/store.ll | 26 +- .../trunc-extractelement-inseltpoison.ll | 195 + .../InstCombine/udiv-pow2-vscale-inseltpoison.ll | 27 + .../InstCombine/vec_demanded_elts-inseltpoison.ll | 850 +++++ .../vec_extract_var_elt-inseltpoison.ll | 26 + .../InstCombine/vec_gep_scalar_arg-inseltpoison.ll | 16 + .../InstCombine/vec_phi_extract-inseltpoison.ll | 107 + .../InstCombine/vec_shuffle-inseltpoison.ll | 1790 +++++++++ .../InstCombine/vector-casts-inseltpoison.ll | 413 +++ .../InstCombine/vector_gep1-inseltpoison.ll | 74 + .../vector_insertelt_shuffle-inseltpoison.ll | 93 + .../vscale_extractelement-inseltpoison.ll | 185 + .../vscale_insertelement-inseltpoison.ll | 102 + .../ConstProp/InsertElement-inseltpoison.ll | 52 + .../InstSimplify/ConstProp/vscale-inseltpoison.ll | 301 ++ .../ConstProp/vscale-shufflevector-inseltpoison.ll | 39 + .../Transforms/InstSimplify/select-inseltpoison.ll | 1007 +++++ .../Transforms/InstSimplify/vscale-inseltpoison.ll | 199 + .../test/Transforms/JumpThreading/thread-prob-3.ll | 4 +- .../AMDGPU/selects-inseltpoison.ll | 95 + .../X86/load-width-inseltpoison.ll | 40 + .../X86/vectorize-i8-nested-add-inseltpoison.ll | 165 + .../LoopIdiom/X86/left-shift-until-bittest.ll | 1049 ++++-- .../ARM/vctp-chains-inseltpoison.ll | 257 ++ .../p8-unrolling-legalize-vectors-inseltpoison.ll | 256 ++ ...08-30-MaskedScatterGather-xfail-inseltpoison.ll | 43 + .../PGOProfile/counter_promo_nest-inseltpoison.ll | 165 + .../PhaseOrdering/X86/addsub-inseltpoison.ll | 101 + .../PhaseOrdering/X86/horiz-math-inseltpoison.ll | 153 + .../X86/scalarization-inseltpoison.ll | 71 + .../PhaseOrdering/vector-trunc-inseltpoison.ll | 23 + .../base-vector-inseltpoison.ll | 279 ++ .../check_traversal_order-inseltpoison.ll | 38 + .../live-vector-nosplit-inseltpoison.ll | 119 + .../accelerate-vector-functions-inseltpoison.ll | 1300 +++++++ .../AArch64/insertelement-inseltpoison.ll | 44 + .../AArch64/transpose-inseltpoison.ll | 294 ++ .../AMDGPU/add_sub_sat-inseltpoison.ll | 336 ++ .../SLPVectorizer/AMDGPU/bswap-inseltpoison.ll | 38 + .../SLPVectorizer/AMDGPU/round-inseltpoison.ll | 38 + .../ARM/extract-insert-inseltpoison.ll | 31 + .../non-vectorizable-intrinsic-inseltpoison.ll | 57 + .../SLPVectorizer/X86/PR35865-inseltpoison.ll | 29 + .../X86/alternate-calls-inseltpoison.ll | 65 + .../X86/alternate-cast-inseltpoison.ll | 466 +++ .../SLPVectorizer/X86/alternate-fp-inseltpoison.ll | 179 + .../X86/alternate-int-inseltpoison.ll | 497 +++ .../SLPVectorizer/X86/arith-fp-inseltpoison.ll | 1365 +++++++ .../X86/blending-shuffle-inseltpoison.ll | 200 + .../SLPVectorizer/X86/cmp_commute-inseltpoison.ll | 283 ++ .../X86/crash_scheduling-inseltpoison.ll | 81 + .../X86/external_user_jumbled_load-inseltpoison.ll | 43 + .../X86/extract-shuffle-inseltpoison.ll | 22 + .../SLPVectorizer/X86/fptosi-inseltpoison.ll | 534 +++ .../SLPVectorizer/X86/hadd-inseltpoison.ll | 433 +++ .../SLPVectorizer/X86/hsub-inseltpoison.ll | 433 +++ .../insert-element-build-vector-inseltpoison.ll | 540 +++ .../SLPVectorizer/X86/load-merge-inseltpoison.ll | 208 ++ .../SLPVectorizer/X86/pr31599-inseltpoison.ll | 30 + .../SLPVectorizer/X86/pr42022-inseltpoison.ll | 278 ++ .../SLPVectorizer/X86/pr44067-inseltpoison.ll | 118 + .../SLPVectorizer/X86/pr47629-inseltpoison.ll | 664 ++++ .../SLPVectorizer/X86/sext-inseltpoison.ll | 1039 ++++++ .../SLPVectorizer/X86/sign-extend-inseltpoison.ll | 62 + .../SLPVectorizer/X86/sitofp-inseltpoison.ll | 1331 +++++++ .../SLPVectorizer/X86/value-bug-inseltpoison.ll | 108 + .../X86/vec_list_bias-inseltpoison.ll | 105 + .../SLPVectorizer/X86/zext-inseltpoison.ll | 1123 ++++++ .../vectorizable-functions-inseltpoison.ll | 78 + .../Transforms/Scalarizer/basic-inseltpoison.ll | 561 +++ .../Scalarizer/dbgloc-bug-inseltpoison.ll | 44 + .../Scalarizer/order-bug-inseltpoison.ll | 24 + .../ARM/speculate-vector-ops-inseltpoison.ll | 112 + .../speculate-vector-ops-inseltpoison.ll | 60 + .../spec-other-inseltpoison.ll | 88 + .../rebuild-ssa-infinite-loop-inseltpoison.ll | 53 + .../AMDGPU/as-transition-inseltpoison.ll | 36 + .../VectorCombine/Hexagon/load-inseltpoison.ll | 17 + .../X86/extract-binop-inseltpoison.ll | 575 +++ .../VectorCombine/X86/insert-binop-inseltpoison.ll | 234 ++ .../X86/insert-binop-with-constant-inseltpoison.ll | 728 ++++ .../VectorCombine/X86/load-inseltpoison.ll | 649 ++++ .../X86/scalarize-cmp-inseltpoison.ll | 290 ++ llvm/test/tools/llvm-readobj/ELF/file-types.test | 10 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 37 +- .../Analysis/IRSimilarityIdentifierTest.cpp | 190 +- llvm/utils/gn/secondary/clang/unittests/BUILD.gn | 2 +- mlir/docs/ConversionToLLVMDialect.md | 467 --- mlir/docs/Dialects/SPIR-V.md | 2 +- mlir/docs/LLVMDialectMemRefConvention.md | 439 +++ mlir/docs/Passes.md | 4 + mlir/examples/toy/Ch6/mlir/LowerToLLVM.cpp | 21 +- mlir/examples/toy/Ch7/mlir/LowerToLLVM.cpp | 21 +- .../{ConvertGPUToSPIRV.h => GPUToSPIRV.h} | 10 +- .../{ConvertGPUToSPIRVPass.h => GPUToSPIRVPass.h} | 19 +- .../mlir/Conversion/LinalgToSPIRV/LinalgToSPIRV.h | 4 +- .../Conversion/LinalgToSPIRV/LinalgToSPIRVPass.h | 4 +- mlir/include/mlir/Conversion/Passes.h | 9 +- mlir/include/mlir/Conversion/Passes.td | 17 + .../mlir/Conversion/SCFToSPIRV/SCFToSPIRV.h | 4 +- .../SCFToSPIRVPass.h} | 14 +- .../{ConvertSPIRVToLLVM.h => SPIRVToLLVM.h} | 8 +- ...{ConvertSPIRVToLLVMPass.h => SPIRVToLLVMPass.h} | 10 +- .../StandardToLLVM/ConvertStandardToLLVM.h | 10 +- ...{ConvertStandardToSPIRV.h => StandardToSPIRV.h} | 16 +- ...StandardToSPIRVPass.h => StandardToSPIRVPass.h} | 14 +- .../{ConvertVectorToSPIRV.h => VectorToSPIRV.h} | 10 +- ...vertVectorToSPIRVPass.h => VectorToSPIRVPass.h} | 12 +- mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td | 4 +- mlir/include/mlir/Dialect/LLVMIR/LLVMTypes.h | 109 +- mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td | 5 + .../Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.h | 31 + mlir/include/mlir/Dialect/Vector/VectorOps.td | 1 + .../include/mlir/Target/LLVMIR/ModuleTranslation.h | 3 + mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp | 54 +- .../GPUCommon/ConvertLaunchFuncToRuntimeCalls.cpp | 31 +- mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h | 6 +- .../GPUCommon/IndexIntrinsicsOpLowering.h | 13 +- .../Conversion/GPUCommon/OpToFuncCallLowering.h | 5 +- .../Conversion/GPUToNVVM/LowerGpuOpsToNVVMOps.cpp | 8 +- mlir/lib/Conversion/GPUToSPIRV/CMakeLists.txt | 8 +- .../{ConvertGPUToSPIRV.cpp => GPUToSPIRV.cpp} | 7 +- ...onvertGPUToSPIRVPass.cpp => GPUToSPIRVPass.cpp} | 15 +- .../GPUToVulkan/ConvertLaunchFuncToVulkanCalls.cpp | 61 +- mlir/lib/Conversion/LinalgToLLVM/LinalgToLLVM.cpp | 2 +- mlir/lib/Conversion/LinalgToSPIRV/CMakeLists.txt | 2 +- .../lib/Conversion/LinalgToSPIRV/LinalgToSPIRV.cpp | 2 +- .../Conversion/LinalgToSPIRV/LinalgToSPIRVPass.cpp | 2 +- mlir/lib/Conversion/SCFToSPIRV/CMakeLists.txt | 5 +- mlir/lib/Conversion/SCFToSPIRV/SCFToSPIRV.cpp | 5 +- .../SCFToSPIRVPass.cpp} | 25 +- mlir/lib/Conversion/SPIRVToLLVM/CMakeLists.txt | 4 +- .../SPIRVToLLVM/ConvertLaunchFuncToLLVMCalls.cpp | 11 +- .../{ConvertSPIRVToLLVM.cpp => SPIRVToLLVM.cpp} | 26 +- ...vertSPIRVToLLVMPass.cpp => SPIRVToLLVMPass.cpp} | 6 +- .../Conversion/StandardToLLVM/StandardToLLVM.cpp | 110 +- mlir/lib/Conversion/StandardToSPIRV/CMakeLists.txt | 6 +- .../StandardToSPIRV/LegalizeStandardForSPIRV.cpp | 4 +- ...vertStandardToSPIRV.cpp => StandardToSPIRV.cpp} | 12 +- ...dardToSPIRVPass.cpp => StandardToSPIRVPass.cpp} | 9 +- .../VectorToLLVM/ConvertVectorToLLVM.cpp | 26 +- .../lib/Conversion/VectorToROCDL/VectorToROCDL.cpp | 4 +- mlir/lib/Conversion/VectorToSPIRV/CMakeLists.txt | 1 + .../lib/Conversion/VectorToSPIRV/VectorToSPIRV.cpp | 43 +- .../VectorToSPIRVPass.cpp} | 33 +- mlir/lib/Dialect/LLVMIR/IR/LLVMDialect.cpp | 45 +- mlir/lib/Dialect/LLVMIR/IR/LLVMTypes.cpp | 121 +- mlir/lib/Dialect/LLVMIR/IR/NVVMDialect.cpp | 17 +- mlir/lib/Dialect/LLVMIR/IR/ROCDLDialect.cpp | 12 +- mlir/lib/Dialect/SPIRV/IR/CMakeLists.txt | 1 + mlir/lib/Dialect/SPIRV/IR/SPIRVCanonicalization.td | 30 + .../Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.cpp | 35 + .../Dialect/SPIRV/Transforms/SPIRVConversion.cpp | 12 +- mlir/lib/Dialect/Vector/VectorOps.cpp | 99 +- mlir/lib/Target/LLVMIR/ModuleTranslation.cpp | 132 +- mlir/lib/Target/SPIRV/Deserialization.cpp | 106 + mlir/lib/Target/SPIRV/Serialization.cpp | 62 +- ...est_spirv_entry_point.mlir => entry-point.mlir} | 0 mlir/test/Conversion/GPUToSPIRV/if.mlir | 167 - mlir/test/Conversion/GPUToSPIRV/loop.mlir | 98 - mlir/test/Conversion/SCFToSPIRV/for.mlir | 86 + mlir/test/Conversion/SCFToSPIRV/if.mlir | 156 + .../StandardToSPIRV/std-ops-to-spirv.mlir | 26 + .../SPIRV/Transforms/glsl_canonicalize.mlir | 113 + mlir/test/Dialect/Vector/canonicalize.mlir | 47 + mlir/test/Target/openmp-llvm.mlir | 34 +- mlir/test/lib/Dialect/SPIRV/CMakeLists.txt | 1 + .../lib/Dialect/SPIRV/TestGLSLCanonicalization.cpp | 39 + mlir/test/lib/Transforms/TestConvertCallOp.cpp | 3 +- mlir/tools/mlir-opt/mlir-opt.cpp | 2 + .../mlir-spirv-cpu-runner.cpp | 4 +- mlir/tools/mlir-tblgen/SPIRVUtilsGen.cpp | 50 +- .../mlir-vulkan-runner/mlir-vulkan-runner.cpp | 4 +- openmp/docs/design/Runtimes.rst | 4 +- 412 files changed, 85182 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llvm/test/Transforms/SLPVectorizer/X86/zext-inseltpoison.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/vectorizable-functions-insel [...] create mode 100644 llvm/test/Transforms/Scalarizer/basic-inseltpoison.ll create mode 100644 llvm/test/Transforms/Scalarizer/dbgloc-bug-inseltpoison.ll create mode 100644 llvm/test/Transforms/Scalarizer/order-bug-inseltpoison.ll create mode 100644 llvm/test/Transforms/SimplifyCFG/ARM/speculate-vector-ops-insel [...] create mode 100644 llvm/test/Transforms/SimplifyCFG/speculate-vector-ops-inseltpoison.ll create mode 100644 llvm/test/Transforms/SpeculativeExecution/spec-other-inseltpoison.ll create mode 100644 llvm/test/Transforms/StructurizeCFG/rebuild-ssa-infinite-loop-i [...] create mode 100644 llvm/test/Transforms/VectorCombine/AMDGPU/as-transition-inseltp [...] create mode 100644 llvm/test/Transforms/VectorCombine/Hexagon/load-inseltpoison.ll create mode 100644 llvm/test/Transforms/VectorCombine/X86/extract-binop-inseltpoison.ll create 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[...] rename mlir/include/mlir/Conversion/GPUToSPIRV/{ConvertGPUToSPIRVPass.h => GPUToSP [...] copy mlir/include/mlir/Conversion/{LinalgToSPIRV/LinalgToSPIRVPass.h => SCFToSPIRV [...] rename mlir/include/mlir/Conversion/SPIRVToLLVM/{ConvertSPIRVToLLVM.h => SPIRVToLL [...] rename mlir/include/mlir/Conversion/SPIRVToLLVM/{ConvertSPIRVToLLVMPass.h => SPIRV [...] rename mlir/include/mlir/Conversion/StandardToSPIRV/{ConvertStandardToSPIRV.h => S [...] rename mlir/include/mlir/Conversion/StandardToSPIRV/{ConvertStandardToSPIRVPass.h [...] rename mlir/include/mlir/Conversion/VectorToSPIRV/{ConvertVectorToSPIRV.h => Vecto [...] rename mlir/include/mlir/Conversion/VectorToSPIRV/{ConvertVectorToSPIRVPass.h => V [...] create mode 100644 mlir/include/mlir/Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.h rename mlir/lib/Conversion/GPUToSPIRV/{ConvertGPUToSPIRV.cpp => GPUToSPIRV.cpp} (98%) rename mlir/lib/Conversion/GPUToSPIRV/{ConvertGPUToSPIRVPass.cpp => GPUToSPIRVPass [...] copy mlir/lib/Conversion/{StandardToSPIRV/ConvertStandardToSPIRVPass.cpp => SCFToS [...] rename mlir/lib/Conversion/SPIRVToLLVM/{ConvertSPIRVToLLVM.cpp => SPIRVToLLVM.cpp} (98%) rename mlir/lib/Conversion/SPIRVToLLVM/{ConvertSPIRVToLLVMPass.cpp => SPIRVToLLVMP [...] rename mlir/lib/Conversion/StandardToSPIRV/{ConvertStandardToSPIRV.cpp => Standard [...] rename mlir/lib/Conversion/StandardToSPIRV/{ConvertStandardToSPIRVPass.cpp => Stan [...] copy mlir/lib/Conversion/{LinalgToSPIRV/LinalgToSPIRVPass.cpp => VectorToSPIRV/Vec [...] create mode 100644 mlir/lib/Dialect/SPIRV/IR/SPIRVGLSLCanonicalization.cpp rename mlir/test/Conversion/GPUToSPIRV/{test_spirv_entry_point.mlir => entry-point [...] delete mode 100644 mlir/test/Conversion/GPUToSPIRV/if.mlir delete mode 100644 mlir/test/Conversion/GPUToSPIRV/loop.mlir create mode 100644 mlir/test/Conversion/SCFToSPIRV/for.mlir create mode 100644 mlir/test/Conversion/SCFToSPIRV/if.mlir create mode 100644 mlir/test/Dialect/SPIRV/Transforms/glsl_canonicalize.mlir create mode 100644 mlir/test/lib/Dialect/SPIRV/TestGLSLCanonicalization.cpp -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig updated (691d6b441 -> 9e579e027)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allmodconfig in repository toolchain/ci/base-artifacts. discards 691d6b441 0: update: llvm-linux-qemu: all new 9e579e027 0: update: llvm-linux-qemu: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (691d6b441) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 31 +- 02-prepare_abe/console.log | 270 +- 03-build_llvm/console.log | 13650 ++++++++++++------------ 04-build_linux/console.log | 888 +- 05-build_abe-qemu/console.log | 6726 ++++++------ 06-boot_linux/console.log | 2 +- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 2 +- console.log | 21571 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 10 files changed, 21578 insertions(+), 21572 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-allmodconfig updated (65fcf1c2d7f -> e73caa0fc12)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-allmodconfig in repository toolchain/ci/gcc. from 65fcf1c2d7f Daily bump. adds a5bcb9487dd i386: Fix __builtin_trunc with FE_DOWNWARD rounding directi [...] adds ec498ed3d0f rs6000: Update the processor defaults for FreeBSD adds 97014e4ada4 c++: Copy elision and [[no_unique_address]]. [PR93711] adds f5cea9c5c4f c++: Fix constexpr array ICE [PR98332] adds e73caa0fc12 Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 13 +++++++ gcc/DATESTAMP | 2 +- gcc/config/i386/i386-expand.c | 27 +++++++------- gcc/config/rs6000/freebsd64.h | 5 ++- gcc/cp/ChangeLog | 17 +++++++++ gcc/cp/call.c | 45 +++++++++++++++--------- gcc/cp/constexpr.c | 4 +-- gcc/cp/cp-tree.h | 1 + gcc/cp/init.c | 3 +- gcc/cp/typeck2.c | 12 ++++++- gcc/testsuite/ChangeLog | 18 ++++++++++ gcc/testsuite/g++.dg/cpp0x/constexpr-overflow3.C | 7 ++++ gcc/testsuite/g++.dg/cpp1z/aggr-base10.C | 16 +++++++++ gcc/testsuite/g++.dg/cpp2a/no_unique_address7.C | 13 +++++++ gcc/testsuite/g++.dg/cpp2a/no_unique_address7a.C | 14 ++++++++ gcc/testsuite/gcc.target/i386/pr96793-1.c | 28 +++++++++++++++ 16 files changed, 187 insertions(+), 38 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp0x/constexpr-overflow3.C create mode 100644 gcc/testsuite/g++.dg/cpp1z/aggr-base10.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/no_unique_address7.C create mode 100644 gcc/testsuite/g++.dg/cpp2a/no_unique_address7a.C create mode 100644 gcc/testsuite/gcc.target/i386/pr96793-1.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-allmodconfig updated (8f9eec44b3 -> abd0dcd37f)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-allmodconfig in repository toolchain/ci/binutils-gdb. from 8f9eec44b3 Automatic date update in version.in adds abd0dcd37f Automatic date update in version.in No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-allmodconfig updated (8b02ad1c7 -> 41f996142)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-next-allmodconfig in repository toolchain/ci/base-artifacts. discards 8b02ad1c7 0: update: binutils-gcc-linux-qemu: boot new 41f996142 0: update: binutils-gcc-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (8b02ad1c7) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-prepare_abe/console.log | 436 +- 03-build_abe-binutils/console.log | 11782 +++++------ 04-build_abe-stage1/console.log | 13787 +++++++------ 05-build_linux/console.log | 700 +- 06-build_abe-qemu/console.log | 4667 +++-- 07-boot_linux/console.log | 8 +- 08-check_regression/console.log | 14 +- 08-check_regression/results.regressions | 2 +- 09-update_baseline/console.log | 54 +- 09-update_baseline/results.regressions | 2 +- console.log | 31698 +++++++++++++++--------------- jenkins/manifest.sh | 12 +- 13 files changed, 31655 insertions(+), 31727 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

[glibc] branch release/2.31/master updated (df31c7ca92 -> 568c86274a)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch release/2.31/master in repository glibc. from df31c7ca92 iconv: Accept redundant shift sequences in IBM1364 [BZ #26224] new 568c86274a tests-mcheck: New variable to run tests with MALLOC_CHECK_=3 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: Rules | 19 ++++++++++++++++++- malloc/Makefile | 20 ++++++++++++++++++++ 2 files changed, 38 insertions(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 8 months

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Tcwg-commits December 2020