Tcwg-commits December 2020

tcwg-commits@lists.linaro.org

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11568 discussions

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allmodconfig updated (4c67b6490 -> c625321b8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-arm-mainline-allmodconfig in repository toolchain/ci/base-artifacts. discards 4c67b6490 2: update: linux-58cf05f597b03a8212d9ecf2c79ee046d3ee8ad9: 21245 new c625321b8 2: update: binutils-gcc-linux-qemu: 21245 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (4c67b6490) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-arm-m [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 129 +- 02-prepare_abe/console.log | 402 +- 03-build_abe-binutils/console.log | 11222 +++++------ 04-build_abe-stage1/console.log | 18231 +++++++++--------- 05-build_linux/console.log | 986 +- 08-check_regression/console.log | 8 +- 08-check_regression/results.regressions | 16 +- 09-update_baseline/console.log | 104 +- 09-update_baseline/results.regressions | 16 +- console.log | 31098 +++++++++++++++--------------- jenkins/manifest.sh | 20 +- 11 files changed, 31749 insertions(+), 30483 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

[toolchain/ci/linux] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allyesconfig updated (b65054597872 -> 1e860048c53e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allyesconfig in repository toolchain/ci/linux. from b65054597872 Linux 5.10-rc6 adds af2d22254e8e gcc-plugins: remove code for GCC versions older than 4.9 adds 1e860048c53e gcc-plugins: simplify GCC plugin-dev capability test No new revisions were added by this update. Summary of changes: scripts/gcc-plugin.sh | 19 - scripts/gcc-plugins/Kconfig | 2 +- scripts/gcc-plugins/gcc-common.h | 407 --------------------- scripts/gcc-plugins/gcc-generate-gimple-pass.h | 12 - scripts/gcc-plugins/gcc-generate-ipa-pass.h | 23 -- scripts/gcc-plugins/gcc-generate-rtl-pass.h | 17 - scripts/gcc-plugins/gcc-generate-simple_ipa-pass.h | 17 - scripts/gcc-plugins/latent_entropy_plugin.c | 12 - scripts/gcc-plugins/randomize_layout_plugin.c | 4 - scripts/gcc-plugins/sancov_plugin.c | 6 - scripts/gcc-plugins/stackleak_plugin.c | 4 +- scripts/gcc-plugins/structleak_plugin.c | 4 - 12 files changed, 2 insertions(+), 525 deletions(-) delete mode 100755 scripts/gcc-plugin.sh -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allyesconfig updated (449250491 -> 6280547e2)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allyesconfig in repository toolchain/ci/base-artifacts. from 449250491 4: update: binutils-gcc-qemu: 19206 new 6280547e2 5: reset: linux-1e860048c53ee77ee9870dcce94847a28544b753: 22 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 72 +- 02-prepare_abe/console.log | 440 +- 03-build_abe-binutils/console.log | 11402 +++++---- 04-build_abe-stage1/console.log | 15922 ++++++------ 05-build_linux/console.log | 11525 +++++---- 08-check_regression/console.log | 92 +- 08-check_regression/results.regressions | 12 +- 08-check_regression/trigger-bisect | 3 + 09-update_baseline/console.log | 63 +- 09-update_baseline/results.regressions | 12 +- console.log | 39528 ++++++++++++++++-------------- jenkins/manifest.sh | 18 +- reset-baseline | 0 results | 13 +- 14 files changed, 41512 insertions(+), 37590 deletions(-) create mode 100644 08-check_regression/trigger-bisect create mode 100644 reset-baseline -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_bmk_tk1/gnu-release-arm-spec2k6-Os-vs-Os_LTO updated (b8301e0973f -> dba421da877)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-release-arm-spec2k6-Os-vs-Os_LTO in repository toolchain/ci/gcc. from b8301e0973f Daily bump. adds 34f70625ce5 Daily bump. adds 80ffeaec54d Daily bump. adds ac03093140b Daily bump. adds a6a15fc45e2 Daily bump. adds 25b33ea27b1 Daily bump. adds 66d3e6b8911 Daily bump. adds c40b640ebce i386: Fix __builtin_floor with FE_DOWNWARD rounding directi [...] adds ea8d2c77e11 PR fortran/98307 - Dependency check fails when using "allocatable" adds 38e0d26587e Daily bump. adds 2435878321b modulo-sched: Carefully process loop counter initialization [...] adds dba421da877 Daily bump. No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 21 ++++++++ gcc/DATESTAMP | 2 +- gcc/config/i386/i386.c | 25 +++++++-- gcc/fortran/ChangeLog | 9 ++++ gcc/fortran/trans-stmt.c | 5 +- gcc/modulo-sched.c | 71 ++++++++++++++----------- gcc/testsuite/ChangeLog | 23 ++++++++ gcc/testsuite/gcc.c-torture/execute/pr97421-1.c | 23 ++++++++ gcc/testsuite/gcc.c-torture/execute/pr97421-2.c | 18 +++++++ gcc/testsuite/gcc.c-torture/execute/pr97421-3.c | 22 ++++++++ gcc/testsuite/gcc.target/i386/pr96793.c | 28 ++++++++++ gcc/testsuite/gfortran.dg/forall_19.f90 | 32 +++++++++++ 12 files changed, 240 insertions(+), 39 deletions(-) create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr97421-1.c create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr97421-2.c create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr97421-3.c create mode 100644 gcc/testsuite/gcc.target/i386/pr96793.c create mode 100644 gcc/testsuite/gfortran.dg/forall_19.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_bmk_tk1/gnu-release-arm-spec2k6-Os-vs-Os_LTO updated (ec997c263 -> 213a5e9fc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tk1/gnu-release-arm-spec2k6-Os-vs-Os_LTO in repository toolchain/ci/base-artifacts. discards ec997c263 2: update: binutils-gcc-glibc: 1 discards 379890dca 1: reset: gcc-6b7ab0e565d79a7e6ae5dbbf17a5eb4eafe56dc8: 1 discards f1eb54a67 0: update: binutils-glibc: 1 new 213a5e9fc 0: update: binutils-gcc-glibc: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (ec997c263) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_bmk_tk1/gnu-release-arm- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 95 +- 02-prepare_abe/console.log | 382 +- 03-build_abe-binutils/console.log | 10302 +-- 04-build_abe-stage1/console.log | 18160 ++-- 05-build_abe-linux/console.log | 186 +- 06-build_abe-glibc/console.log | 11975 +-- 07-build_abe-stage2/console.log | 44413 +++++----- 08-benchmark--Os_mthumb/benchmark-start.log | 2 +- 08-benchmark--Os_mthumb/benchmark.log | 13 +- 08-benchmark--Os_mthumb/console.log | 157 +- 09-benchmark--Os_LTO_mthumb/benchmark-start.log | 2 +- 09-benchmark--Os_LTO_mthumb/benchmark.log | 19 +- 09-benchmark--Os_LTO_mthumb/console.log | 161 +- 11-check_regression/console.log | 2379 +- 11-check_regression/new-results-0.csv | 56 +- 11-check_regression/new-results-1.csv | 59 +- 11-check_regression/new-results-brief.csv | 58 +- 11-check_regression/new-results-compare.csv | 2 +- 11-check_regression/new-results-full.csv | 58 +- 11-check_regression/new-results.csv | 58 +- 11-check_regression/new-results.log | 4741 +- 11-check_regression/new-results.regressions | 1 - 11-check_regression/ref-results-0.csv | 56 +- 11-check_regression/ref-results-1.csv | 58 +- 11-check_regression/ref-results-brief.csv | 58 +- 11-check_regression/ref-results-full.csv | 58 +- 11-check_regression/ref-results.csv | 58 +- 11-check_regression/ref-results.log | 4890 +- 11-check_regression/results-compare.csv | 2 +- 12-update_baseline/console.log | 7279 +- 12-update_baseline/extra-bisect-params | 2 +- 12-update_baseline/new-results-0.csv | 56 +- 12-update_baseline/new-results-1.csv | 59 +- 12-update_baseline/new-results-brief.csv | 58 +- 12-update_baseline/new-results-compare.csv | 2 +- 12-update_baseline/new-results-full.csv | 58 +- 12-update_baseline/new-results.csv | 58 +- 12-update_baseline/new-results.log | 4785 +- 12-update_baseline/new-results.regressions | 1 - 12-update_baseline/ref-results.log | 2044 +- 12-update_baseline/results-compare.csv | 2 +- 12-update_baseline/results.regressions | 1 - console.log | 95813 +++++++++++----------- jenkins/manifest.sh | 12 +- results_id-1 | 2 +- results_id-2 | 2 +- 46 files changed, 104182 insertions(+), 104511 deletions(-) delete mode 100644 11-check_regression/new-results.regressions delete mode 100644 12-update_baseline/new-results.regressions delete mode 100644 12-update_baseline/results.regressions -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allnoconfig updated (e457896a6ef -> 46bea9b2971)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allnoconfig in repository toolchain/ci/llvm-project. from e457896a6ef [CodeGen] Remove unused function hasInlineAsmMemConstraint (NFC) adds ff3749fc793 [NFC] SimplifyCFGOpt::simplifyUnreachable(): pacify unused [...] adds b3021a72a6d [IR][InstCombine] Add m_ImmConstant(), that matches on non- [...] adds da4c7e15df3 [NFC][InstCombine] Autogenerate check lines in vec_shuffle.ll test adds 1fda23367d4 [NFC][InstCombine] Add test for `a & ~(a ^ b)` pattern adds 5b78303433c [InstCombine] Fold `a & ~(a ^ b)` to `x & y` adds 8001dcbd50c [NFC][InstCombine] Add test coverage for `(x ^ C) ^ y` pattern adds d9ebaeeb468 [InstCombine] Hoist xor-by-constant from xor-by-value adds 6e074a8324d [NFC][LoopIdiom] Improve test coverage for 'left-shift-unti [...] adds 25aebe2ccfb [LoopIdiom] 'left-shift-until-bittest': keep no-wrap flags [...] adds afd03cd3358 [RISCV] Define vector single-width reduction intrinsic. adds 912740a864f [RISCV] Add intrinsics for vrgather instruction adds 351c216f36a [RISCV] Define vector mask-register logical intrinsics. adds d6ff5cf995d [Target] Use llvm::any_of (NFC) adds da4a637e991 [RISCV] Define vpopc/vfirst intrinsics. adds e0721a09922 [AArch64][GlobalISel] Notify observer of mutated instructio [...] adds 438bc157a47 [libObject] - Add more ELF types to LLVM_ELF_IMPORT_TYPES_E [...] adds 177779e8dd9 [llvm-readelf/obj] - Improve the warning reported when unab [...] adds 893c84d71c4 [obj2yaml] - Dump the content of a broken hash table properly. adds a2ca6bbda61 [Flang][OpenMP] Add semantic check for OpenMP Private, Firs [...] adds 621ad468d99 [mlir] Async: lowering async.value to LLVM adds 61422c8b661 [mlir] Async: add support for lowering async value operands [...] adds b96a6ea0a94 [BasicAA] Make sure context instruction is symmetric adds a3614a31c46 [BasicAA] Pass context instruction to isKnownNonZero() adds b0e6007c825 [InstCombine] Add additional tests for known non zero (NFC) adds 35676a4f9a5 [InstCombine] Generalize icmp handling in isKnownNonZero() adds ea399912514 [llvm-nm, llvm-objdump] Use llvm::is_contained (NFC) adds c795dd19265 [BasicAA] Pass AC/DT to isKnownNonEqual() adds 46bea9b2971 [Local] Remove unused function RemovePredecessorAndSimplify (NFC) No new revisions were added by this update. Summary of changes: flang/lib/Semantics/resolve-directives.cpp | 41 +- flang/test/Semantics/omp-private03.f90 | 39 + llvm/include/llvm/Analysis/BasicAliasAnalysis.h | 3 + llvm/include/llvm/IR/IntrinsicsRISCV.td | 74 + llvm/include/llvm/IR/PatternMatch.h | 43 +- llvm/include/llvm/Object/ELF.h | 26 - llvm/include/llvm/Object/ELFObjectFile.h | 9 - llvm/include/llvm/Object/ELFTypes.h | 30 +- llvm/include/llvm/Transforms/Utils/Local.h | 14 - llvm/lib/Analysis/BasicAliasAnalysis.cpp | 13 +- llvm/lib/Analysis/ValueTracking.cpp | 77 +- .../ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp | 7 - llvm/lib/ObjectYAML/ELFEmitter.cpp | 16 +- llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 6 +- .../Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 2 + .../Target/AMDGPU/AMDGPURewriteOutArguments.cpp | 7 +- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 5 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 364 +- .../Transforms/InstCombine/InstCombineAddSub.cpp | 4 +- .../Transforms/InstCombine/InstCombineAndOrXor.cpp | 15 + .../Transforms/InstCombine/InstCombineCalls.cpp | 4 +- .../Transforms/InstCombine/InstCombineNegator.cpp | 3 +- .../InstCombine/InstructionCombining.cpp | 7 +- llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 50 +- llvm/lib/Transforms/Utils/Local.cpp | 28 - llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 1 + .../test/Analysis/BasicAA/assume-index-positive.ll | 16 + llvm/test/Analysis/BasicAA/sequential-gep.ll | 22 + llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll | 3624 +++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll | 4630 ++++++++++++++++++++ llvm/test/Transforms/Attributor/nonnull.ll | 50 +- llvm/test/Transforms/InstCombine/and-xor-or.ll | 43 + .../hoist-xor-by-constant-from-xor-by-value.ll | 75 + .../invert-variable-mask-in-masked-merge-scalar.ll | 5 +- .../invert-variable-mask-in-masked-merge-vector.ll | 5 +- llvm/test/Transforms/InstCombine/known-non-zero.ll | 100 +- llvm/test/Transforms/InstCombine/or-xor.ll | 68 +- .../unfold-masked-merge-with-const-mask-scalar.ll | 6 +- .../unfold-masked-merge-with-const-mask-vector.ll | 6 +- .../InstCombine/vec_shuffle-inseltpoison.ll | 4 +- llvm/test/Transforms/InstCombine/vec_shuffle.ll | 12 +- llvm/test/Transforms/InstCombine/xor2.ll | 44 +- .../LoopIdiom/X86/left-shift-until-bittest.ll | 1875 ++++---- llvm/test/tools/llvm-readobj/ELF/stack-sizes.test | 10 +- llvm/test/tools/obj2yaml/ELF/hash-section.yaml | 21 + llvm/tools/llvm-lipo/llvm-lipo.cpp | 5 +- llvm/tools/llvm-nm/llvm-nm.cpp | 7 +- llvm/tools/llvm-objdump/MachODump.cpp | 4 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 66 +- llvm/tools/obj2yaml/elf2yaml.cpp | 22 +- mlir/include/mlir/ExecutionEngine/AsyncRuntime.h | 30 + mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp | 576 ++- mlir/lib/Conversion/AsyncToLLVM/CMakeLists.txt | 2 + mlir/lib/ExecutionEngine/AsyncRuntime.cpp | 69 +- .../Conversion/AsyncToLLVM/convert-to-llvm.mlir | 92 + mlir/test/mlir-cpu-runner/async-value.mlir | 81 + 101 files changed, 31264 insertions(+), 1344 deletions(-) create mode 100644 flang/test/Semantics/omp-private03.f90 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll create mode 100644 llvm/test/Transforms/InstCombine/hoist-xor-by-constant-from-xor [...] create mode 100644 mlir/test/mlir-cpu-runner/async-value.mlir -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allnoconfig updated (4f9e71edd -> 71ed6aaa0)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allnoconfig in repository toolchain/ci/base-artifacts. discards 4f9e71edd 0: update: llvm-linux-qemu: boot new 71ed6aaa0 0: update: llvm-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (4f9e71edd) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 85 +- 02-prepare_abe/console.log | 440 +- 03-build_llvm/console.log | 13770 ++++++++++++------------ 04-build_linux/console.log | 574 +- 05-build_abe-qemu/console.log | 6798 ++++++------ 06-boot_linux/console.log | 8 +- 07-check_regression/console.log | 12 +- 08-update_baseline/console.log | 12 +- console.log | 21725 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 10 files changed, 21688 insertions(+), 21744 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig updated (e457896a6ef -> 46bea9b2971)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig in repository toolchain/ci/llvm-project. from e457896a6ef [CodeGen] Remove unused function hasInlineAsmMemConstraint (NFC) adds ff3749fc793 [NFC] SimplifyCFGOpt::simplifyUnreachable(): pacify unused [...] adds b3021a72a6d [IR][InstCombine] Add m_ImmConstant(), that matches on non- [...] adds da4c7e15df3 [NFC][InstCombine] Autogenerate check lines in vec_shuffle.ll test adds 1fda23367d4 [NFC][InstCombine] Add test for `a & ~(a ^ b)` pattern adds 5b78303433c [InstCombine] Fold `a & ~(a ^ b)` to `x & y` adds 8001dcbd50c [NFC][InstCombine] Add test coverage for `(x ^ C) ^ y` pattern adds d9ebaeeb468 [InstCombine] Hoist xor-by-constant from xor-by-value adds 6e074a8324d [NFC][LoopIdiom] Improve test coverage for 'left-shift-unti [...] adds 25aebe2ccfb [LoopIdiom] 'left-shift-until-bittest': keep no-wrap flags [...] adds afd03cd3358 [RISCV] Define vector single-width reduction intrinsic. adds 912740a864f [RISCV] Add intrinsics for vrgather instruction adds 351c216f36a [RISCV] Define vector mask-register logical intrinsics. adds d6ff5cf995d [Target] Use llvm::any_of (NFC) adds da4a637e991 [RISCV] Define vpopc/vfirst intrinsics. adds e0721a09922 [AArch64][GlobalISel] Notify observer of mutated instructio [...] adds 438bc157a47 [libObject] - Add more ELF types to LLVM_ELF_IMPORT_TYPES_E [...] adds 177779e8dd9 [llvm-readelf/obj] - Improve the warning reported when unab [...] adds 893c84d71c4 [obj2yaml] - Dump the content of a broken hash table properly. adds a2ca6bbda61 [Flang][OpenMP] Add semantic check for OpenMP Private, Firs [...] adds 621ad468d99 [mlir] Async: lowering async.value to LLVM adds 61422c8b661 [mlir] Async: add support for lowering async value operands [...] adds b96a6ea0a94 [BasicAA] Make sure context instruction is symmetric adds a3614a31c46 [BasicAA] Pass context instruction to isKnownNonZero() adds b0e6007c825 [InstCombine] Add additional tests for known non zero (NFC) adds 35676a4f9a5 [InstCombine] Generalize icmp handling in isKnownNonZero() adds ea399912514 [llvm-nm, llvm-objdump] Use llvm::is_contained (NFC) adds c795dd19265 [BasicAA] Pass AC/DT to isKnownNonEqual() new 46bea9b2971 [Local] Remove unused function RemovePredecessorAndSimplify (NFC) The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: flang/lib/Semantics/resolve-directives.cpp | 41 +- flang/test/Semantics/omp-private03.f90 | 39 + llvm/include/llvm/Analysis/BasicAliasAnalysis.h | 3 + llvm/include/llvm/IR/IntrinsicsRISCV.td | 74 + llvm/include/llvm/IR/PatternMatch.h | 43 +- llvm/include/llvm/Object/ELF.h | 26 - llvm/include/llvm/Object/ELFObjectFile.h | 9 - llvm/include/llvm/Object/ELFTypes.h | 30 +- llvm/include/llvm/Transforms/Utils/Local.h | 14 - llvm/lib/Analysis/BasicAliasAnalysis.cpp | 13 +- llvm/lib/Analysis/ValueTracking.cpp | 77 +- .../ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp | 7 - llvm/lib/ObjectYAML/ELFEmitter.cpp | 16 +- llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 6 +- .../Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 2 + .../Target/AMDGPU/AMDGPURewriteOutArguments.cpp | 7 +- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 5 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 364 +- .../Transforms/InstCombine/InstCombineAddSub.cpp | 4 +- .../Transforms/InstCombine/InstCombineAndOrXor.cpp | 15 + .../Transforms/InstCombine/InstCombineCalls.cpp | 4 +- .../Transforms/InstCombine/InstCombineNegator.cpp | 3 +- .../InstCombine/InstructionCombining.cpp | 7 +- llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp | 50 +- llvm/lib/Transforms/Utils/Local.cpp | 28 - llvm/lib/Transforms/Utils/SimplifyCFG.cpp | 1 + .../test/Analysis/BasicAA/assume-index-positive.ll | 16 + llvm/test/Analysis/BasicAA/sequential-gep.ll | 22 + llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll | 3624 +++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll | 4630 ++++++++++++++++++++ llvm/test/Transforms/Attributor/nonnull.ll | 50 +- llvm/test/Transforms/InstCombine/and-xor-or.ll | 43 + .../hoist-xor-by-constant-from-xor-by-value.ll | 75 + .../invert-variable-mask-in-masked-merge-scalar.ll | 5 +- .../invert-variable-mask-in-masked-merge-vector.ll | 5 +- llvm/test/Transforms/InstCombine/known-non-zero.ll | 100 +- llvm/test/Transforms/InstCombine/or-xor.ll | 68 +- .../unfold-masked-merge-with-const-mask-scalar.ll | 6 +- .../unfold-masked-merge-with-const-mask-vector.ll | 6 +- .../InstCombine/vec_shuffle-inseltpoison.ll | 4 +- llvm/test/Transforms/InstCombine/vec_shuffle.ll | 12 +- llvm/test/Transforms/InstCombine/xor2.ll | 44 +- .../LoopIdiom/X86/left-shift-until-bittest.ll | 1875 ++++---- llvm/test/tools/llvm-readobj/ELF/stack-sizes.test | 10 +- llvm/test/tools/obj2yaml/ELF/hash-section.yaml | 21 + llvm/tools/llvm-lipo/llvm-lipo.cpp | 5 +- llvm/tools/llvm-nm/llvm-nm.cpp | 7 +- llvm/tools/llvm-objdump/MachODump.cpp | 4 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 66 +- llvm/tools/obj2yaml/elf2yaml.cpp | 22 +- mlir/include/mlir/ExecutionEngine/AsyncRuntime.h | 30 + mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp | 576 ++- mlir/lib/Conversion/AsyncToLLVM/CMakeLists.txt | 2 + mlir/lib/ExecutionEngine/AsyncRuntime.cpp | 69 +- .../Conversion/AsyncToLLVM/convert-to-llvm.mlir | 92 + mlir/test/mlir-cpu-runner/async-value.mlir | 81 + 101 files changed, 31264 insertions(+), 1344 deletions(-) create mode 100644 flang/test/Semantics/omp-private03.f90 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll create mode 100644 llvm/test/Transforms/InstCombine/hoist-xor-by-constant-from-xor [...] create mode 100644 mlir/test/mlir-cpu-runner/async-value.mlir -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig updated (1c3b4fc21 -> 5b0c7c3ec)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-lts-defconfig in repository toolchain/ci/base-artifacts. discards 1c3b4fc21 0: update: llvm-linux-qemu: boot new 5b0c7c3ec 0: update: llvm-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (1c3b4fc21) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 130 +- 02-prepare_abe/console.log | 322 +- 03-build_llvm/console.log | 13544 +++++++++++------------ 04-build_linux/console.log | 790 +- 05-build_abe-qemu/console.log | 6797 ++++++------ 06-boot_linux/console.log | 492 +- 07-check_regression/console.log | 12 +- 08-update_baseline/console.log | 18 +- console.log | 22105 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 10 files changed, 22106 insertions(+), 22112 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

[toolchain/ci/interesting-commits] branch linaro-local/ci/tcwg_kernel updated (21e324c -> 3182417)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel in repository toolchain/ci/interesting-commits. from 21e324c Add regression 886c8121659dddb6dbfab4cdeb58d75e2d928731 from [...] new 3182417 Add regression 1e860048c53ee77ee9870dcce94847a28544b753 from [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: linux | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

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