Tcwg-commits December 2020

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig updated (e34e20a10 -> f6e6be0bd)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-defconfig in repository toolchain/ci/base-artifacts. discards e34e20a10 0: update: llvm-linux-qemu: boot new f6e6be0bd 0: update: llvm-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (e34e20a10) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 14 +- 02-prepare_abe/console.log | 436 +- 03-build_llvm/console.log | 13670 +++++++++++------------ 04-build_linux/console.log | 798 +- 05-build_abe-qemu/console.log | 6710 ++++++------ 06-boot_linux/console.log | 416 +- 07-check_regression/console.log | 2 +- 08-update_baseline/console.log | 10 +- console.log | 22084 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 10 files changed, 22055 insertions(+), 22093 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allyesconfig updated (25aebe2ccfb -> e334c52addc)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allyesconfig in repository toolchain/ci/llvm-project. from 25aebe2ccfb [LoopIdiom] 'left-shift-until-bittest': keep no-wrap flags [...] adds afd03cd3358 [RISCV] Define vector single-width reduction intrinsic. adds 912740a864f [RISCV] Add intrinsics for vrgather instruction adds 351c216f36a [RISCV] Define vector mask-register logical intrinsics. adds d6ff5cf995d [Target] Use llvm::any_of (NFC) adds da4a637e991 [RISCV] Define vpopc/vfirst intrinsics. adds e0721a09922 [AArch64][GlobalISel] Notify observer of mutated instructio [...] adds 438bc157a47 [libObject] - Add more ELF types to LLVM_ELF_IMPORT_TYPES_E [...] adds 177779e8dd9 [llvm-readelf/obj] - Improve the warning reported when unab [...] adds 893c84d71c4 [obj2yaml] - Dump the content of a broken hash table properly. adds a2ca6bbda61 [Flang][OpenMP] Add semantic check for OpenMP Private, Firs [...] adds 621ad468d99 [mlir] Async: lowering async.value to LLVM adds 61422c8b661 [mlir] Async: add support for lowering async value operands [...] adds b96a6ea0a94 [BasicAA] Make sure context instruction is symmetric adds a3614a31c46 [BasicAA] Pass context instruction to isKnownNonZero() adds b0e6007c825 [InstCombine] Add additional tests for known non zero (NFC) adds 35676a4f9a5 [InstCombine] Generalize icmp handling in isKnownNonZero() adds ea399912514 [llvm-nm, llvm-objdump] Use llvm::is_contained (NFC) adds c795dd19265 [BasicAA] Pass AC/DT to isKnownNonEqual() adds 46bea9b2971 [Local] Remove unused function RemovePredecessorAndSimplify (NFC) adds e334c52addc [llvm-objcopy] Use llvm::erase_if (NFC) No new revisions were added by this update. Summary of changes: flang/lib/Semantics/resolve-directives.cpp | 41 +- flang/test/Semantics/omp-private03.f90 | 39 + llvm/include/llvm/Analysis/BasicAliasAnalysis.h | 3 + llvm/include/llvm/IR/IntrinsicsRISCV.td | 74 + llvm/include/llvm/Object/ELF.h | 26 - llvm/include/llvm/Object/ELFObjectFile.h | 9 - llvm/include/llvm/Object/ELFTypes.h | 30 +- llvm/include/llvm/Transforms/Utils/Local.h | 14 - llvm/lib/Analysis/BasicAliasAnalysis.cpp | 13 +- llvm/lib/Analysis/ValueTracking.cpp | 77 +- .../ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp | 7 - llvm/lib/ObjectYAML/ELFEmitter.cpp | 16 +- llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 6 +- .../Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 2 + .../Target/AMDGPU/AMDGPURewriteOutArguments.cpp | 7 +- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 5 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 364 +- llvm/lib/Transforms/Utils/Local.cpp | 28 - .../test/Analysis/BasicAA/assume-index-positive.ll | 16 + llvm/test/Analysis/BasicAA/sequential-gep.ll | 22 + llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll | 3624 +++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll | 4630 ++++++++++++++++++++ llvm/test/Transforms/Attributor/nonnull.ll | 50 +- llvm/test/Transforms/InstCombine/known-non-zero.ll | 100 +- llvm/test/tools/llvm-readobj/ELF/stack-sizes.test | 10 +- llvm/test/tools/obj2yaml/ELF/hash-section.yaml | 21 + llvm/tools/llvm-lipo/llvm-lipo.cpp | 5 +- llvm/tools/llvm-nm/llvm-nm.cpp | 7 +- llvm/tools/llvm-objcopy/COFF/Object.cpp | 19 +- llvm/tools/llvm-objcopy/MachO/Object.cpp | 4 +- llvm/tools/llvm-objcopy/wasm/Object.cpp | 4 +- llvm/tools/llvm-objdump/MachODump.cpp | 4 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 66 +- llvm/tools/obj2yaml/elf2yaml.cpp | 22 +- mlir/include/mlir/ExecutionEngine/AsyncRuntime.h | 30 + mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp | 576 ++- mlir/lib/Conversion/AsyncToLLVM/CMakeLists.txt | 2 + mlir/lib/ExecutionEngine/AsyncRuntime.cpp | 69 +- .../Conversion/AsyncToLLVM/convert-to-llvm.mlir | 92 + mlir/test/mlir-cpu-runner/async-value.mlir | 81 + 85 files changed, 29891 insertions(+), 474 deletions(-) create mode 100644 flang/test/Semantics/omp-private03.f90 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll create mode 100644 mlir/test/mlir-cpu-runner/async-value.mlir -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allyesconfig updated (43a6ee698 -> c4b58a587)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-lts-allyesconfig in repository toolchain/ci/base-artifacts. discards 43a6ee698 0: update: llvm-linux-qemu: 19158 new c4b58a587 0: update: llvm-linux-qemu: 19158 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (43a6ee698) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-l [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 174 +- 02-prepare_abe/console.log | 428 +- 03-build_llvm/console.log | 13822 +++++++++++++-------------- 04-build_linux/console.log | 888 +- 07-check_regression/console.log | 12 +- 07-check_regression/results.regressions | 2 +- 08-update_baseline/console.log | 12 +- 08-update_baseline/results.regressions | 2 +- console.log | 15365 +++++++++++++++--------------- jenkins/manifest.sh | 8 +- 10 files changed, 15336 insertions(+), 15377 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-bootstrap_O1 updated (96de87b99bf -> a746898dff8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-bootstrap_O1 in repository toolchain/ci/gcc. from 96de87b99bf Darwin : Adjust handling of MACOSX_DEPLOYMENT_TARGET for macOS 11. adds 6b7d53a2593 c++: Fix constexpr array ICE [PR98332] adds 550880a3168 c++: Fix up floating point complex handling in build_zero_i [...] adds 0a541e746c7 c++: Improve testcase [PR98332] adds 3932785450f compiler: nil-checked pointers and index expressions can trap adds 612cf351c70 c++: Fix initializing empty base from prvalue [PR97597] adds 745f22096c3 c++: EOF location [PR 96045] adds 36c08a8f212 mark some tests in gcc.target/arm as requiring "fpic" support adds eb81c997d81 Account for VxWorks headers in libstdc++ test on names adds fdd8560cce9 PR c++/98413 - ICE on placement new and member pointer adds 0df311657dc PR middle-end/98160 - ICE in warn_dealloc_offset on member [...] adds 85d8ebcfc23 Daily bump. adds 085fd2a46e5 compiler: parenthesize channel type strings if necessary adds 168be2b3afd RISC-V: Fix python3 compatibility for multilib-generator adds 662b9c55cf0 C++ : Add the -stdlib= option. adds 8daa719bdca Daily bump. adds 4ee8e5949a9 libstdc++: Convert three doxygen.nl links to https adds 6e36772ba6a PR93685 - ICE in gfc_constructor_append_expr, at fortran/co [...] adds 6a25dda42d4 doc: Fix reference to libcody adds a746898dff8 libstdc++: Update link to Java docs No new revisions were added by this update. Summary of changes: c++tools/ChangeLog | 7 ++ gcc/ChangeLog | 44 ++++++++++ gcc/DATESTAMP | 2 +- gcc/Makefile.in | 6 ++ gcc/builtins.c | 7 +- gcc/c-family/ChangeLog | 5 ++ gcc/c-family/c.opt | 14 ++++ gcc/config.in | 6 ++ gcc/config/riscv/multilib-generator | 2 +- gcc/configure | 57 ++++++++++++- gcc/configure.ac | 44 ++++++++++ gcc/cp/ChangeLog | 33 ++++++++ gcc/cp/call.c | 4 + gcc/cp/class.c | 31 ++++++- gcc/cp/constexpr.c | 4 +- gcc/cp/cp-tree.h | 1 + gcc/cp/g++spec.c | 74 +++++++++++++++-- gcc/cp/init.c | 2 +- gcc/cp/parser.c | 10 +++ gcc/cppdefault.c | 5 ++ gcc/cppdefault.h | 7 +- gcc/d/ChangeLog | 7 ++ gcc/doc/invoke.texi | 12 ++- gcc/fortran/data.c | 7 +- gcc/fortran/trans-expr.c | 12 +-- gcc/go/gofrontend/MERGE | 2 +- gcc/go/gofrontend/expressions.cc | 10 +-- gcc/go/gofrontend/types.cc | 15 ++++ gcc/incpath.c | 6 +- gcc/testsuite/ChangeLog | 97 ++++++++++++++++++++++ gcc/testsuite/c-c++-common/goacc/pr79428-1.c | 4 +- gcc/testsuite/c-c++-common/gomp/pr79428-2.c | 3 +- gcc/testsuite/c-c++-common/raw-string-6.c | 3 +- gcc/testsuite/g++.dg/cpp0x/constexpr-overflow3.C | 7 ++ gcc/testsuite/g++.dg/cpp0x/decltype63.C | 3 +- gcc/testsuite/g++.dg/cpp0x/gen-attrs-64.C | 1 - gcc/testsuite/g++.dg/cpp0x/pr68726.C | 1 - gcc/testsuite/g++.dg/cpp0x/pr78341.C | 1 - gcc/testsuite/g++.dg/cpp1y/pr65202.C | 3 +- gcc/testsuite/g++.dg/cpp1y/pr65340.C | 2 +- gcc/testsuite/g++.dg/cpp1y/pr68578.C | 2 +- gcc/testsuite/g++.dg/cpp1z/class-deduction44.C | 1 - gcc/testsuite/g++.dg/diagnostic/pr96045-1.C | 4 + gcc/testsuite/g++.dg/diagnostic/pr96045-2.C | 6 ++ gcc/testsuite/g++.dg/diagnostic/pr96045-3.C | 6 ++ .../g++.dg/diagnostic/unclosed-extern-c.C | 2 +- .../g++.dg/diagnostic/unclosed-function.C | 3 +- .../g++.dg/diagnostic/unclosed-namespace.C | 3 +- gcc/testsuite/g++.dg/diagnostic/unclosed-struct.C | 3 +- gcc/testsuite/g++.dg/ext/pr84598.C | 4 +- gcc/testsuite/g++.dg/init/empty3.C | 18 ++++ gcc/testsuite/g++.dg/other/switch4.C | 3 +- gcc/testsuite/g++.dg/parse/attr4.C | 1 - gcc/testsuite/g++.dg/parse/cond4.C | 3 +- gcc/testsuite/g++.dg/parse/crash10.C | 1 - gcc/testsuite/g++.dg/parse/crash18.C | 2 +- gcc/testsuite/g++.dg/parse/crash27.C | 2 +- gcc/testsuite/g++.dg/parse/crash34.C | 2 +- gcc/testsuite/g++.dg/parse/crash35.C | 2 +- gcc/testsuite/g++.dg/parse/crash52.C | 2 +- gcc/testsuite/g++.dg/parse/crash59.C | 2 +- gcc/testsuite/g++.dg/parse/crash61.C | 1 - gcc/testsuite/g++.dg/parse/crash67.C | 2 +- gcc/testsuite/g++.dg/parse/error14.C | 2 +- gcc/testsuite/g++.dg/parse/error56.C | 1 - gcc/testsuite/g++.dg/parse/invalid1.C | 2 +- .../g++.dg/parse/parameter-declaration-1.C | 4 +- gcc/testsuite/g++.dg/parse/parser-pr28152-2.C | 2 +- gcc/testsuite/g++.dg/parse/parser-pr28152.C | 2 +- gcc/testsuite/g++.dg/parse/pr68722.C | 1 - gcc/testsuite/g++.dg/parse/pr96258.C | 4 +- gcc/testsuite/g++.dg/pr46852.C | 1 - gcc/testsuite/g++.dg/pr46868.C | 1 - gcc/testsuite/g++.dg/template/crash115.C | 1 - gcc/testsuite/g++.dg/template/crash43.C | 1 - gcc/testsuite/g++.dg/template/crash90.C | 3 +- gcc/testsuite/g++.dg/template/error-recovery1.C | 1 - gcc/testsuite/g++.dg/template/error57.C | 2 +- gcc/testsuite/g++.dg/warn/pr98160.C | 30 +++++++ gcc/testsuite/g++.dg/warn/pr98413.C | 23 +++++ gcc/testsuite/g++.old-deja/g++.other/crash31.C | 3 +- gcc/testsuite/gcc.target/arm/data-rel-1.c | 1 + gcc/testsuite/gcc.target/arm/data-rel-2.c | 1 + gcc/testsuite/gcc.target/arm/data-rel-3.c | 1 + gcc/testsuite/gcc.target/arm/pr44788.c | 1 + gcc/testsuite/gcc.target/arm/pr52006.c | 1 + gcc/testsuite/gcc.target/arm/pr59858.c | 1 + .../gcc.target/arm/require-pic-register-loc.c | 17 ++-- gcc/testsuite/gcc.target/arm/tlscall.c | 1 + gcc/testsuite/gfortran.dg/pr93685_1.f90 | 20 +++++ gcc/testsuite/gfortran.dg/pr93685_2.f90 | 18 ++++ libcody/ChangeLog | 12 +++ libstdc++-v3/ChangeLog | 4 + .../doc/html/manual/documentation_hacking.html | 6 +- libstdc++-v3/doc/html/manual/facets.html | 2 +- .../doc/xml/manual/documentation_hacking.xml | 6 +- libstdc++-v3/doc/xml/manual/messages.xml | 2 +- libstdc++-v3/testsuite/17_intro/names.cc | 41 +++++++++ 98 files changed, 741 insertions(+), 114 deletions(-) create mode 100644 gcc/testsuite/g++.dg/cpp0x/constexpr-overflow3.C create mode 100644 gcc/testsuite/g++.dg/diagnostic/pr96045-1.C create mode 100644 gcc/testsuite/g++.dg/diagnostic/pr96045-2.C create mode 100644 gcc/testsuite/g++.dg/diagnostic/pr96045-3.C create mode 100644 gcc/testsuite/g++.dg/init/empty3.C create mode 100644 gcc/testsuite/g++.dg/warn/pr98160.C create mode 100644 gcc/testsuite/g++.dg/warn/pr98413.C create mode 100644 gcc/testsuite/gfortran.dg/pr93685_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93685_2.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-bootstrap_O1 updated (0b8e5f58d -> 9d43a0da0)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_gnu/gnu-master-aarch64-bootstrap_O1 in repository toolchain/ci/base-artifacts. discards 0b8e5f58d 0: update: gcc-96de87b99bf8fd1c46df373bbcc2f7d76db716ad: 1 new 9d43a0da0 0: update: gcc-a746898dff8d92646b007fec3eb971ec5e8be9e0: 1 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (0b8e5f58d) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_gnu/gnu-master-aarch64-b [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 78 +- 02-prepare_abe/console.log | 442 +- 04-build_abe-bootstrap_O1/console.log | 68094 ++++++++++++++++--------------- 05-check_regression/console.log | 2 +- 06-update_baseline/console.log | 2 +- console.log | 68618 ++++++++++++++++---------------- jenkins/manifest.sh | 8 +- 7 files changed, 68614 insertions(+), 68630 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allyesconfig updated (25aebe2ccfb -> e334c52addc)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allyesconfig in repository toolchain/ci/llvm-project. from 25aebe2ccfb [LoopIdiom] 'left-shift-until-bittest': keep no-wrap flags [...] adds afd03cd3358 [RISCV] Define vector single-width reduction intrinsic. adds 912740a864f [RISCV] Add intrinsics for vrgather instruction adds 351c216f36a [RISCV] Define vector mask-register logical intrinsics. adds d6ff5cf995d [Target] Use llvm::any_of (NFC) adds da4a637e991 [RISCV] Define vpopc/vfirst intrinsics. adds e0721a09922 [AArch64][GlobalISel] Notify observer of mutated instructio [...] adds 438bc157a47 [libObject] - Add more ELF types to LLVM_ELF_IMPORT_TYPES_E [...] adds 177779e8dd9 [llvm-readelf/obj] - Improve the warning reported when unab [...] adds 893c84d71c4 [obj2yaml] - Dump the content of a broken hash table properly. adds a2ca6bbda61 [Flang][OpenMP] Add semantic check for OpenMP Private, Firs [...] adds 621ad468d99 [mlir] Async: lowering async.value to LLVM adds 61422c8b661 [mlir] Async: add support for lowering async value operands [...] adds b96a6ea0a94 [BasicAA] Make sure context instruction is symmetric adds a3614a31c46 [BasicAA] Pass context instruction to isKnownNonZero() adds b0e6007c825 [InstCombine] Add additional tests for known non zero (NFC) adds 35676a4f9a5 [InstCombine] Generalize icmp handling in isKnownNonZero() adds ea399912514 [llvm-nm, llvm-objdump] Use llvm::is_contained (NFC) adds c795dd19265 [BasicAA] Pass AC/DT to isKnownNonEqual() adds 46bea9b2971 [Local] Remove unused function RemovePredecessorAndSimplify (NFC) adds e334c52addc [llvm-objcopy] Use llvm::erase_if (NFC) No new revisions were added by this update. Summary of changes: flang/lib/Semantics/resolve-directives.cpp | 41 +- flang/test/Semantics/omp-private03.f90 | 39 + llvm/include/llvm/Analysis/BasicAliasAnalysis.h | 3 + llvm/include/llvm/IR/IntrinsicsRISCV.td | 74 + llvm/include/llvm/Object/ELF.h | 26 - llvm/include/llvm/Object/ELFObjectFile.h | 9 - llvm/include/llvm/Object/ELFTypes.h | 30 +- llvm/include/llvm/Transforms/Utils/Local.h | 14 - llvm/lib/Analysis/BasicAliasAnalysis.cpp | 13 +- llvm/lib/Analysis/ValueTracking.cpp | 77 +- .../ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp | 7 - llvm/lib/ObjectYAML/ELFEmitter.cpp | 16 +- llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp | 6 +- .../Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 2 + .../Target/AMDGPU/AMDGPURewriteOutArguments.cpp | 7 +- llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 5 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +- llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td | 364 +- llvm/lib/Transforms/Utils/Local.cpp | 28 - .../test/Analysis/BasicAA/assume-index-positive.ll | 16 + llvm/test/Analysis/BasicAA/sequential-gep.ll | 22 + llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll | 463 ++ llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll | 631 +++ llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll | 127 + llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll | 239 + llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll | 715 +++ llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll | 883 ++++ llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll | 3624 +++++++++++++++ llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll | 4630 ++++++++++++++++++++ llvm/test/Transforms/Attributor/nonnull.ll | 50 +- llvm/test/Transforms/InstCombine/known-non-zero.ll | 100 +- llvm/test/tools/llvm-readobj/ELF/stack-sizes.test | 10 +- llvm/test/tools/obj2yaml/ELF/hash-section.yaml | 21 + llvm/tools/llvm-lipo/llvm-lipo.cpp | 5 +- llvm/tools/llvm-nm/llvm-nm.cpp | 7 +- llvm/tools/llvm-objcopy/COFF/Object.cpp | 19 +- llvm/tools/llvm-objcopy/MachO/Object.cpp | 4 +- llvm/tools/llvm-objcopy/wasm/Object.cpp | 4 +- llvm/tools/llvm-objdump/MachODump.cpp | 4 +- llvm/tools/llvm-readobj/ELFDumper.cpp | 66 +- llvm/tools/obj2yaml/elf2yaml.cpp | 22 +- mlir/include/mlir/ExecutionEngine/AsyncRuntime.h | 30 + mlir/lib/Conversion/AsyncToLLVM/AsyncToLLVM.cpp | 576 ++- mlir/lib/Conversion/AsyncToLLVM/CMakeLists.txt | 2 + mlir/lib/ExecutionEngine/AsyncRuntime.cpp | 69 +- .../Conversion/AsyncToLLVM/convert-to-llvm.mlir | 92 + mlir/test/mlir-cpu-runner/async-value.mlir | 81 + 85 files changed, 29891 insertions(+), 474 deletions(-) create mode 100644 flang/test/Semantics/omp-private03.f90 create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfirst-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfirst-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmax-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredmin-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredosum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredsum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vfredsum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmandnot-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmandnot-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmnor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmornot-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmornot-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxnor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxnor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vmxor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vpopc-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vpopc-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredand-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredand-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmax-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmax-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmaxu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmin-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredmin-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredminu-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredminu-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredsum-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredsum-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredxor-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vredxor-rv64.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vrgather-rv32.ll create mode 100644 llvm/test/CodeGen/RISCV/rvv/vrgather-rv64.ll create mode 100644 mlir/test/mlir-cpu-runner/async-value.mlir -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allyesconfig updated (9a09018cb -> dbe6cbf37)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-next-allyesconfig in repository toolchain/ci/base-artifacts. discards 9a09018cb 2: update: llvm-linux-qemu: 19388 new dbe6cbf37 2: update: llvm-linux-qemu: 19388 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (9a09018cb) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-prepare_abe/console.log | 414 +- 03-build_llvm/console.log | 13786 +++++++++++++-------------- 04-build_linux/console.log | 752 +- 07-check_regression/console.log | 12 +- 07-check_regression/results.regressions | 6 +- 08-update_baseline/console.log | 32 +- 08-update_baseline/results.regressions | 6 +- console.log | 15216 +++++++++++++++--------------- jenkins/manifest.sh | 8 +- 10 files changed, 15226 insertions(+), 15226 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig updated (662b9c55cf0 -> a746898dff8)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig in repository toolchain/ci/gcc. from 662b9c55cf0 C++ : Add the -stdlib= option. adds 8daa719bdca Daily bump. adds 4ee8e5949a9 libstdc++: Convert three doxygen.nl links to https adds 6e36772ba6a PR93685 - ICE in gfc_constructor_append_expr, at fortran/co [...] adds 6a25dda42d4 doc: Fix reference to libcody adds a746898dff8 libstdc++: Update link to Java docs No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 20 ++++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/c-family/ChangeLog | 5 +++++ gcc/cp/ChangeLog | 8 ++++++++ gcc/doc/invoke.texi | 2 +- gcc/fortran/data.c | 7 +++---- gcc/fortran/trans-expr.c | 12 +++++++----- gcc/testsuite/gfortran.dg/pr93685_1.f90 | 20 ++++++++++++++++++++ gcc/testsuite/gfortran.dg/pr93685_2.f90 | 18 ++++++++++++++++++ .../doc/html/manual/documentation_hacking.html | 6 +++--- libstdc++-v3/doc/html/manual/facets.html | 2 +- .../doc/xml/manual/documentation_hacking.xml | 6 +++--- libstdc++-v3/doc/xml/manual/messages.xml | 2 +- 13 files changed, 91 insertions(+), 19 deletions(-) create mode 100644 gcc/testsuite/gfortran.dg/pr93685_1.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr93685_2.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig updated (b7874836c3 -> a12f86b9a6)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig in repository toolchain/ci/binutils-gdb. from b7874836c3 gdb: avoid resolving dynamic properties for non-allocated arrays adds e142715391 Automatic date update in version.in adds a12f86b9a6 gas: Update 80387 floating point 's' suffix No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- gas/doc/c-i386.texi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig updated (2c09540c0 -> 303b7d892)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-lts-defconfig in repository toolchain/ci/base-artifacts. discards 2c09540c0 0: update: binutils-gcc-linux-qemu: boot new 303b7d892 0: update: binutils-gcc-linux-qemu: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (2c09540c0) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-lt [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 128 +- 02-prepare_abe/console.log | 290 +- 03-build_abe-binutils/console.log | 11782 +++++---- 04-build_abe-stage1/console.log | 20891 ++++++++------- 05-build_linux/console.log | 486 +- 06-build_abe-qemu/console.log | 6732 ++--- 07-boot_linux/console.log | 492 +- 08-check_regression/console.log | 2 +- 08-check_regression/results.regressions | 2 +- 09-update_baseline/console.log | 2 +- 09-update_baseline/results.regressions | 2 +- console.log | 40805 +++++++++++++++--------------- jenkins/manifest.sh | 12 +- 13 files changed, 40708 insertions(+), 40918 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

4 years, 7 months

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