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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allmodconfig
in repository toolchain/ci/llvm-project.
from 99464b7eb1d [clangd][Hover] Change arrow in return type back to â
adds 01fd650ba3d [RISCV] Pass target-abi via module flag metadata
adds 7c5784746cf [RISCV] Check the target-abi module flag matches the option
adds 4d342b7d8e9 Revert "[RISCV] Support ABI checking with per function targ [...]
adds 72882ca30d8 [RISCV] Support ABI checking with per function target-features
adds c23212a438f [IR] Keep a double break between functions when printing a module
adds 87c7863c3ec Reland "[StackColoring] Remap PseudoSourceValue frame indic [...]
adds 6472fec9a69 [clangd][Hover] Handle uninstantiated templates
adds 54b022d3444 [lldb] Fix nondeterminism in TestCppBitfields
No new revisions were added by this update.
Summary of changes:
clang-tools-extra/clangd/Hover.cpp | 27 ++++++++++++++--------
clang-tools-extra/clangd/unittests/HoverTests.cpp | 19 +++++++++++++++
clang/lib/CodeGen/CodeGenModule.cpp | 7 ++++++
clang/test/CodeGen/riscv-metadata.c | 14 +++++++++++
.../test/lang/cpp/bitfields/TestCppBitfields.py | 2 +-
.../lldbsuite/test/lang/cpp/bitfields/main.cpp | 2 +-
llvm/lib/CodeGen/StackColoring.cpp | 16 +++++++------
llvm/lib/IR/AsmWriter.cpp | 4 +++-
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 5 ++--
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 14 +++++++++--
llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp | 24 +++++++++++--------
llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h | 2 ++
llvm/test/CodeGen/RISCV/module-target-abi.ll | 24 +++++++++++++++++++
llvm/test/CodeGen/RISCV/module-target-abi2.ll | 27 ++++++++++++++++++++++
llvm/test/Feature/undefined.ll | 13 +++++++++++
15 files changed, 167 insertions(+), 33 deletions(-)
create mode 100644 clang/test/CodeGen/riscv-metadata.c
create mode 100644 llvm/test/CodeGen/RISCV/module-target-abi.ll
create mode 100644 llvm/test/CodeGen/RISCV/module-target-abi2.ll
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allmodconfig
in repository toolchain/ci/base-artifacts.
discards 7f444757 0: update: llvm-linux: all
new 00c3ae22 0: update: llvm-linux: all
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Summary of changes:
01-reset_artifacts/console.log | 220 +-
02-build_llvm/console.log | 12678 +++++++++++++++++------------------
03-build_linux/console.log | 849 +--
04-boot_linux/console.log | 4 +-
05-check_regression/console.log | 10 +-
06-update_baseline/console.log | 16 +-
console.log | 13777 +++++++++++++++++++-------------------
jenkins/manifest.sh | 14 +-
results | 2 +-
9 files changed, 13812 insertions(+), 13758 deletions(-)
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unknown user pushed a change to branch master
in repository gcc.
from 3d056cbfb34 preprocessor: Make __has_include a builtin macro [PR93452]
new a83b5cc5828 Allow concatenated module+submodule names.
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gcc/fortran/ChangeLog | 7 +++++++
gcc/fortran/parse.c | 5 +++--
gcc/testsuite/gfortran.dg/pr93473.f90 | 28 ++++++++++++++++++++++++++++
3 files changed, 38 insertions(+), 2 deletions(-)
create mode 100644 gcc/testsuite/gfortran.dg/pr93473.f90
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1_Os_LTO
in repository toolchain/ci/interesting-commits.
from 458e158 Add last-good 777c02825229f14cf91c6044827ea42a77ded4a3 from h [...]
new 9160180 Add regression d74a8b0579edd0c42921eccc45ab986d24f2fef0 from [...]
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Summary of changes:
gcc | 1 +
1 file changed, 1 insertion(+)
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk_tx1_Os_LTO
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from 2e48571 Add regression 4e55aefa3ee19167a41892e4920a3e8c520aee42 from [...]
new 458e158 Add last-good 777c02825229f14cf91c6044827ea42a77ded4a3 from h [...]
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gcc | 1 +
1 file changed, 1 insertion(+)
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig
in repository toolchain/ci/base-artifacts.
discards bd794121 0: update: llvm-linux: boot
new 5e6dfd9a 0: update: llvm-linux: boot
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Summary of changes:
01-reset_artifacts/console.log | 184 +-
02-build_llvm/console.log | 12677 ++++++++++++++++-----------------
03-build_linux/console.log | 842 +--
04-boot_linux/console.log | 482 +-
05-check_regression/console.log | 10 +-
06-update_baseline/console.log | 29 -
console.log | 14224 +++++++++++++++++++-------------------
jenkins/manifest.sh | 10 +-
8 files changed, 14203 insertions(+), 14255 deletions(-)
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-lts-allyesconfig
in repository toolchain/ci/llvm-project.
from 99464b7eb1d [clangd][Hover] Change arrow in return type back to â
adds 01fd650ba3d [RISCV] Pass target-abi via module flag metadata
adds 7c5784746cf [RISCV] Check the target-abi module flag matches the option
adds 4d342b7d8e9 Revert "[RISCV] Support ABI checking with per function targ [...]
adds 72882ca30d8 [RISCV] Support ABI checking with per function target-features
adds c23212a438f [IR] Keep a double break between functions when printing a module
adds 87c7863c3ec Reland "[StackColoring] Remap PseudoSourceValue frame indic [...]
adds 6472fec9a69 [clangd][Hover] Handle uninstantiated templates
adds 54b022d3444 [lldb] Fix nondeterminism in TestCppBitfields
No new revisions were added by this update.
Summary of changes:
clang-tools-extra/clangd/Hover.cpp | 27 ++++++++++++++--------
clang-tools-extra/clangd/unittests/HoverTests.cpp | 19 +++++++++++++++
clang/lib/CodeGen/CodeGenModule.cpp | 7 ++++++
clang/test/CodeGen/riscv-metadata.c | 14 +++++++++++
.../test/lang/cpp/bitfields/TestCppBitfields.py | 2 +-
.../lldbsuite/test/lang/cpp/bitfields/main.cpp | 2 +-
llvm/lib/CodeGen/StackColoring.cpp | 16 +++++++------
llvm/lib/IR/AsmWriter.cpp | 4 +++-
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 5 ++--
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 14 +++++++++--
llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp | 24 +++++++++++--------
llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h | 2 ++
llvm/test/CodeGen/RISCV/module-target-abi.ll | 24 +++++++++++++++++++
llvm/test/CodeGen/RISCV/module-target-abi2.ll | 27 ++++++++++++++++++++++
llvm/test/Feature/undefined.ll | 13 +++++++++++
15 files changed, 167 insertions(+), 33 deletions(-)
create mode 100644 clang/test/CodeGen/riscv-metadata.c
create mode 100644 llvm/test/CodeGen/RISCV/module-target-abi.ll
create mode 100644 llvm/test/CodeGen/RISCV/module-target-abi2.ll
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-lts-allyesconfig
in repository toolchain/ci/base-artifacts.
discards 47fb4226 0: update: llvm-linux: 16
new 66dcf72e 0: update: llvm-linux: 16
This update added new revisions after undoing existing revisions.
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Summary of changes:
01-reset_artifacts/console.log | 166 +-
02-build_llvm/console.log | 12630 +++++++++++++++++------------------
03-build_linux/console.log | 812 ++-
05-check_regression/console.log | 2 +-
06-update_baseline/console.log | 32 -
console.log | 13642 +++++++++++++++++++-------------------
jenkins/manifest.sh | 10 +-
7 files changed, 13613 insertions(+), 13681 deletions(-)
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