Tcwg-commits September 2019

tcwg-commits@lists.linaro.org

5 participants
14312 discussions

[llvm] branch master updated (21dbe0be4a7 -> f8a9932a8ba)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 21dbe0be4a7 [InstCombine] rename variable for readability; NFC new f8a9932a8ba [TableGen] Skip CRLF conversion when writing output The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/TableGen/Main.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[llvm] branch master updated (06de30684d5 -> 21dbe0be4a7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 06de30684d5 PR43278: Temporarily disable llvm-reduce tests due to exhau [...] new 9294c897b22 Add some missing changes to GSYM that was addressing a gcc [...] new 21dbe0be4a7 [InstCombine] rename variable for readability; NFC The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: include/llvm/DebugInfo/GSYM/FunctionInfo.h | 12 +++---- lib/DebugInfo/GSYM/FunctionInfo.cpp | 2 +- lib/Transforms/InstCombine/InstCombineCasts.cpp | 42 ++++++++++++------------- unittests/DebugInfo/GSYM/GSYMTest.cpp | 14 ++++----- 4 files changed, 35 insertions(+), 35 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig updated (73ec745793a -> 9703f46fc1b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig in repository toolchain/ci/llvm-project. from 73ec745793a [ARM] Take into account -mcpu and -mfpu options while handl [...] adds 57256af307a Revert "clang-misexpect: Profile Guided Validation of Perfo [...] adds 3a4781bbf4f [LLDB][ELF] Load both, .symtab and .dynsym sections adds 813f05915d2 [LLDB][ELF] Fixup for comments in D67390 adds e79381c3f7a [LoopInterchange] Drop unused splitInnerLoopHeader declaration. adds 4dae283cd3e [InstCombine] Fixed handling of isOpNewLike (PR11748) adds 57ebb50a0ad [NFC] Fixed test adds af5ba2873f5 [NFC] Updated objsize-64.ll test adds 3240ad4ced0 [Diagnostics] Add -Wsizeof-array-div adds e0d9a0bd59d Fix -Wdocumentation warning - void function doesn't need a [...] adds d811d9115b0 [mips][msa] Fix infinite loop for mips.nori.b intrinsic adds 48904e9452d [Alignment] Use llvm::Align in MachineFunction and TargetLo [...] adds 80bea345d11 [InstCombine] fold sign-bit compares of srem adds f78474ba8ae gn build: add include_dir that's necessary after r371564 adds b3b2064c518 [LangRef] fix punctuation; NFC adds 9703f46fc1b [lldb][NFC] Sort files in unittests/Expression/CMakeLists.txt No new revisions were added by this update. Summary of changes: .../include/clang/Basic/DiagnosticFrontendKinds.td | 7 +- clang/include/clang/Basic/DiagnosticGroups.td | 1 - clang/include/clang/Basic/DiagnosticSemaKinds.td | 4 + clang/lib/CodeGen/CodeGenAction.cpp | 26 - clang/lib/Frontend/CompilerInvocation.cpp | 3 - clang/lib/Sema/SemaExpr.cpp | 31 +- .../misexpect-branch-nonconst-expect-arg.proftext | 9 - .../test/Profile/Inputs/misexpect-branch.proftext | 9 - .../Inputs/misexpect-switch-default-only.proftext | 12 - .../Inputs/misexpect-switch-default.proftext | 16 - .../Inputs/misexpect-switch-nonconst.proftext | 17 - .../test/Profile/Inputs/misexpect-switch.proftext | 16 - clang/test/Profile/misexpect-branch-cold.c | 26 - .../misexpect-branch-nonconst-expected-val.c | 23 - .../test/Profile/misexpect-branch-unpredictable.c | 25 - clang/test/Profile/misexpect-branch.c | 28 - clang/test/Profile/misexpect-switch-default.c | 40 -- clang/test/Profile/misexpect-switch-nonconst.c | 43 -- .../Profile/misexpect-switch-only-default-case.c | 35 - clang/test/Profile/misexpect-switch.c | 41 -- clang/test/Sema/div-sizeof-array.cpp | 28 + compiler-rt/lib/profile/xxhash.c | 138 ---- compiler-rt/lib/profile/xxhash.h | 47 -- .../Modules/ELF/Inputs/load-from-dynsym-alone.c | 7 + .../Modules/ELF/Inputs/load-symtab-and-dynsym.c | 12 + lldb/lit/Modules/ELF/load-from-dynsym-alone.test | 33 + lldb/lit/Modules/ELF/load-symtab-and-dynsym.test | 48 ++ lldb/lit/helper/toolchain.py | 2 +- .../Plugins/ObjectFile/ELF/ObjectFileELF.cpp | 31 +- lldb/unittests/Expression/CMakeLists.txt | 2 +- llvm/docs/LangRef.rst | 2 +- llvm/include/llvm/CodeGen/MachineFunction.h | 18 +- llvm/include/llvm/CodeGen/TargetLowering.h | 8 +- llvm/include/llvm/IR/DiagnosticInfo.h | 22 +- llvm/include/llvm/IR/FixedMetadataKinds.def | 1 - llvm/include/llvm/IR/MDBuilder.h | 5 - llvm/include/llvm/Transforms/Utils/MisExpect.h | 43 -- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 2 +- llvm/lib/CodeGen/AsmPrinter/WinException.cpp | 2 +- llvm/lib/CodeGen/BranchRelaxation.cpp | 15 +- llvm/lib/CodeGen/MIRParser/MIRParser.cpp | 2 +- llvm/lib/CodeGen/MIRPrinter.cpp | 2 +- llvm/lib/CodeGen/MachineFunction.cpp | 8 +- llvm/lib/CodeGen/PatchableFunction.cpp | 2 +- llvm/lib/IR/DiagnosticInfo.cpp | 11 - llvm/lib/IR/MDBuilder.cpp | 12 - llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp | 2 +- llvm/lib/Target/AMDGPU/R600AsmPrinter.cpp | 2 +- llvm/lib/Target/ARC/ARCMachineFunctionInfo.h | 4 +- llvm/lib/Target/ARM/ARMBasicBlockInfo.cpp | 2 +- llvm/lib/Target/ARM/ARMConstantIslandPass.cpp | 11 +- llvm/lib/Target/Mips/MipsAsmPrinter.cpp | 3 +- llvm/lib/Target/Mips/MipsConstantIslandPass.cpp | 4 +- llvm/lib/Target/Mips/MipsSEISelLowering.cpp | 1 + llvm/lib/Target/PowerPC/PPCBranchSelector.cpp | 13 +- llvm/lib/Target/SystemZ/SystemZLongBranch.cpp | 6 +- llvm/lib/Transforms/IPO/SampleProfile.cpp | 3 - .../Transforms/InstCombine/InstCombineCalls.cpp | 15 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 42 ++ .../Transforms/InstCombine/InstCombineInternal.h | 2 + .../Instrumentation/PGOInstrumentation.cpp | 4 - llvm/lib/Transforms/Scalar/LoopInterchange.cpp | 1 - .../lib/Transforms/Scalar/LowerExpectIntrinsic.cpp | 31 +- llvm/lib/Transforms/Utils/CMakeLists.txt | 1 - llvm/lib/Transforms/Utils/MisExpect.cpp | 177 ----- .../AArch64/GlobalISel/arm64-regbankselect.mir | 10 +- .../AArch64/GlobalISel/combine-anyext-crash.mir | 2 +- .../CodeGen/AArch64/GlobalISel/fold-fp-select.mir | 22 +- .../CodeGen/AArch64/GlobalISel/fold-select.mir | 4 +- .../GlobalISel/fp128-legalize-crash-pr35690.mir | 2 +- .../CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir | 6 +- .../CodeGen/AArch64/GlobalISel/inline-memcpy.mir | 6 +- .../CodeGen/AArch64/GlobalISel/inline-memmove.mir | 8 +- .../CodeGen/AArch64/GlobalISel/inline-memset.mir | 8 +- .../AArch64/GlobalISel/inline-small-memcpy.mir | 4 +- .../CodeGen/AArch64/GlobalISel/legalize-add.mir | 4 +- .../AArch64/GlobalISel/legalize-blockaddress.mir | 2 +- .../CodeGen/AArch64/GlobalISel/legalize-ceil.mir | 4 +- .../CodeGen/AArch64/GlobalISel/legalize-cmp.mir | 2 +- .../CodeGen/AArch64/GlobalISel/legalize-cos.mir | 12 +- .../CodeGen/AArch64/GlobalISel/legalize-div.mir | 2 +- .../AArch64/GlobalISel/legalize-dyn-alloca.mir | 6 +- .../CodeGen/AArch64/GlobalISel/legalize-exp.mir | 12 +- .../CodeGen/AArch64/GlobalISel/legalize-ext.mir | 18 +- .../CodeGen/AArch64/GlobalISel/legalize-fexp2.mir | 12 +- .../CodeGen/AArch64/GlobalISel/legalize-fma.mir | 10 +- .../CodeGen/AArch64/GlobalISel/legalize-frint.mir | 16 +- .../GlobalISel/legalize-intrinsic-round.mir | 16 +- .../GlobalISel/legalize-intrinsic-trunc.mir | 12 +- .../GlobalISel/legalize-inttoptr-xfail-1.mir | 2 +- .../GlobalISel/legalize-inttoptr-xfail-2.mir | 2 +- .../legalize-load-store-vector-of-ptr.mir | 6 +- .../AArch64/GlobalISel/legalize-load-store.mir | 18 +- .../CodeGen/AArch64/GlobalISel/legalize-log.mir | 12 +- .../CodeGen/AArch64/GlobalISel/legalize-log10.mir | 12 +- .../CodeGen/AArch64/GlobalISel/legalize-log2.mir | 12 +- .../AArch64/GlobalISel/legalize-nearbyint.mir | 14 +- .../GlobalISel/legalize-non-pow2-load-store.mir | 2 +- .../CodeGen/AArch64/GlobalISel/legalize-phi.mir | 14 +- .../CodeGen/AArch64/GlobalISel/legalize-pow.mir | 10 +- .../AArch64/GlobalISel/legalize-s128-div.mir | 4 +- .../CodeGen/AArch64/GlobalISel/legalize-select.mir | 4 +- .../AArch64/GlobalISel/legalize-shuffle-vector.mir | 6 +- .../CodeGen/AArch64/GlobalISel/legalize-sin.mir | 12 +- .../CodeGen/AArch64/GlobalISel/legalize-sqrt.mir | 4 +- .../AArch64/GlobalISel/legalize-vector-icmp.mir | 128 ++-- .../legalizer-combiner-zext-trunc-crash.mir | 2 +- .../AArch64/GlobalISel/load-addressing-modes.mir | 42 +- .../GlobalISel/localizer-in-O0-pipeline.mir | 2 +- llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir | 2 +- .../GlobalISel/machine-cse-mid-pipeline.mir | 2 +- .../GlobalISel/non-pow-2-extload-combine.mir | 2 +- .../AArch64/GlobalISel/observer-change-crash.mir | 2 +- .../AArch64/GlobalISel/opt-fold-compare.mir | 30 +- .../AArch64/GlobalISel/opt-shuffle-splat.mir | 12 +- .../prelegalizercombiner-extending-loads-s1.mir | 2 +- .../GlobalISel/regbank-extract-vector-elt.mir | 8 +- .../CodeGen/AArch64/GlobalISel/regbank-extract.mir | 2 +- .../CodeGen/AArch64/GlobalISel/regbank-fma.mir | 4 +- .../GlobalISel/regbank-insert-vector-elt.mir | 12 +- .../AArch64/GlobalISel/regbank-intrinsic-round.mir | 16 +- .../AArch64/GlobalISel/regbank-intrinsic-trunc.mir | 4 +- .../AArch64/GlobalISel/regbank-nearbyint.mir | 14 +- .../CodeGen/AArch64/GlobalISel/regbank-select.mir | 12 +- .../AArch64/GlobalISel/regbank-trunc-s128.mir | 2 +- .../GlobalISel/regbankselect-build-vector.mir | 2 +- .../GlobalISel/regbankselect-unmerge-vec.mir | 4 +- .../GlobalISel/select-arith-extended-reg.mir | 50 +- .../GlobalISel/select-atomic-load-store.mir | 2 +- .../CodeGen/AArch64/GlobalISel/select-binop.mir | 4 +- .../AArch64/GlobalISel/select-blockaddress.mir | 2 +- .../CodeGen/AArch64/GlobalISel/select-bswap.mir | 6 +- .../AArch64/GlobalISel/select-build-vector.mir | 10 +- .../test/CodeGen/AArch64/GlobalISel/select-cbz.mir | 4 +- .../AArch64/GlobalISel/select-concat-vectors.mir | 4 +- .../CodeGen/AArch64/GlobalISel/select-ctlz.mir | 18 +- .../GlobalISel/select-extract-vector-elt.mir | 16 +- .../CodeGen/AArch64/GlobalISel/select-fcmp.mir | 4 +- .../AArch64/GlobalISel/select-frint-nofp16.mir | 6 +- .../CodeGen/AArch64/GlobalISel/select-frint.mir | 16 +- .../GlobalISel/select-insert-vector-elt.mir | 12 +- .../CodeGen/AArch64/GlobalISel/select-int-ext.mir | 18 +- .../AArch64/GlobalISel/select-intrinsic-round.mir | 16 +- .../AArch64/GlobalISel/select-intrinsic-trunc.mir | 16 +- .../AArch64/GlobalISel/select-jump-table-brjt.mir | 2 +- .../AArch64/GlobalISel/select-ldaxr-intrin.mir | 8 +- .../AArch64/GlobalISel/select-ldxr-intrin.mir | 8 +- .../GlobalISel/select-load-store-vector-of-ptr.mir | 4 +- .../CodeGen/AArch64/GlobalISel/select-load.mir | 8 +- .../AArch64/GlobalISel/select-nearbyint.mir | 14 +- .../test/CodeGen/AArch64/GlobalISel/select-phi.mir | 4 +- .../CodeGen/AArch64/GlobalISel/select-pr32733.mir | 2 +- .../CodeGen/AArch64/GlobalISel/select-select.mir | 4 +- .../AArch64/GlobalISel/select-shuffle-vector.mir | 8 +- .../select-shufflevec-undef-mask-elt.mir | 2 +- .../AArch64/GlobalISel/select-stlxr-intrin.mir | 8 +- .../CodeGen/AArch64/GlobalISel/select-store.mir | 8 +- .../test/CodeGen/AArch64/GlobalISel/select-stx.mir | 8 +- .../CodeGen/AArch64/GlobalISel/select-trap.mir | 2 +- .../CodeGen/AArch64/GlobalISel/select-uaddo.mir | 4 +- .../CodeGen/AArch64/GlobalISel/select-unmerge.mir | 14 +- .../AArch64/GlobalISel/select-vector-icmp.mir | 160 ++--- .../AArch64/GlobalISel/select-vector-shift.mir | 8 +- .../GlobalISel/select-with-no-legality-check.mir | 304 ++++----- .../AArch64/GlobalISel/store-addressing-modes.mir | 14 +- .../CodeGen/AArch64/aarch64-mov-debug-locs.mir | 2 +- llvm/test/CodeGen/AArch64/aarch64-vector-pcs.mir | 2 +- .../CodeGen/AArch64/branch-relax-block-size.mir | 2 +- .../dont-shrink-wrap-stack-mayloadorstore.mir | 4 +- llvm/test/CodeGen/AArch64/irg-nomem.mir | 2 +- llvm/test/CodeGen/AArch64/jump-table-compress.mir | 2 +- .../AArch64/machine-outliner-inline-asm-adrp.mir | 6 +- llvm/test/CodeGen/AArch64/movimm-wzr.mir | 2 +- .../CodeGen/AArch64/reverse-csr-restore-seq.mir | 2 +- llvm/test/CodeGen/AArch64/spill-undef.mir | 2 +- llvm/test/CodeGen/AArch64/wineh-frame0.mir | 2 +- llvm/test/CodeGen/AArch64/wineh-frame1.mir | 2 +- llvm/test/CodeGen/AArch64/wineh-frame2.mir | 2 +- llvm/test/CodeGen/AArch64/wineh-frame3.mir | 2 +- llvm/test/CodeGen/AArch64/wineh-frame4.mir | 2 +- llvm/test/CodeGen/AArch64/wineh-frame5.mir | 2 +- llvm/test/CodeGen/AArch64/wineh-frame6.mir | 2 +- llvm/test/CodeGen/AArch64/wineh-frame7.mir | 2 +- llvm/test/CodeGen/AArch64/wineh-frame8.mir | 2 +- llvm/test/CodeGen/AArch64/wineh1.mir | 2 +- llvm/test/CodeGen/AArch64/wineh2.mir | 2 +- llvm/test/CodeGen/AArch64/wineh3.mir | 2 +- llvm/test/CodeGen/AArch64/wineh4.mir | 2 +- llvm/test/CodeGen/AArch64/wineh5.mir | 2 +- llvm/test/CodeGen/AArch64/wineh6.mir | 2 +- llvm/test/CodeGen/AArch64/wineh7.mir | 2 +- llvm/test/CodeGen/AArch64/wineh8.mir | 2 +- llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir | 2 +- .../AMDGPU/GlobalISel/legalize-block-addr.mir | 2 +- .../AMDGPU/GlobalISel/regbankselect-block-addr.mir | 2 +- llvm/test/CodeGen/AMDGPU/coalescer-subreg-join.mir | 2 +- .../CodeGen/AMDGPU/constant-fold-imm-immreg.mir | 22 +- .../CodeGen/AMDGPU/couldnt-join-subrange-3.mir | 2 +- llvm/test/CodeGen/AMDGPU/fix-vgpr-copies.mir | 2 +- llvm/test/CodeGen/AMDGPU/flat-load-clustering.mir | 2 +- llvm/test/CodeGen/AMDGPU/fold-imm-f16-f32.mir | 18 +- llvm/test/CodeGen/AMDGPU/hazard.mir | 4 +- llvm/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir | 2 +- llvm/test/CodeGen/AMDGPU/inserted-wait-states.mir | 2 +- llvm/test/CodeGen/AMDGPU/invert-br-undef-vcc.mir | 2 +- llvm/test/CodeGen/AMDGPU/limit-coalesce.mir | 2 +- .../AMDGPU/memory-legalizer-atomic-insert-end.mir | 2 +- ...galizer-multiple-mem-operands-nontemporal-1.mir | 2 +- ...galizer-multiple-mem-operands-nontemporal-2.mir | 2 +- .../CodeGen/AMDGPU/merge-load-store-physreg.mir | 4 +- llvm/test/CodeGen/AMDGPU/merge-load-store.mir | 2 +- llvm/test/CodeGen/AMDGPU/opt-sgpr-to-vgpr-copy.mir | 6 +- .../rename-independent-subregs-mac-operands.mir | 4 +- llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir | 2 +- llvm/test/CodeGen/AMDGPU/schedule-regpressure.mir | 2 +- llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir | 4 +- llvm/test/CodeGen/AMDGPU/shrink-vop3-carry-out.mir | 12 +- .../CodeGen/AMDGPU/smem-no-clause-coalesced.mir | 2 +- .../AMDGPU/undefined-physreg-sgpr-spill.mir | 4 +- .../CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir | 4 +- llvm/test/CodeGen/AMDGPU/wqm.mir | 2 +- llvm/test/CodeGen/ARM/ARMLoadStoreDBG.mir | 2 +- llvm/test/CodeGen/ARM/cmp1-peephole-thumb.mir | 2 +- llvm/test/CodeGen/ARM/cmp2-peephole-thumb.mir | 2 +- llvm/test/CodeGen/ARM/constant-island-movwt.mir | 2 +- llvm/test/CodeGen/ARM/constant-islands-cfg.mir | 2 +- .../test/CodeGen/ARM/constant-islands-split-IT.mir | 2 +- llvm/test/CodeGen/ARM/dbg-range-extension.mir | 2 +- llvm/test/CodeGen/ARM/expand-pseudos.mir | 6 +- llvm/test/CodeGen/ARM/fp16-litpool-arm.mir | 2 +- llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir | 2 +- llvm/test/CodeGen/ARM/fp16-litpool2-arm.mir | 2 +- llvm/test/CodeGen/ARM/fp16-litpool3-arm.mir | 2 +- .../ARM/ifcvt-diamond-unanalyzable-common.mir | 2 +- llvm/test/CodeGen/ARM/misched-int-basic-thumb2.mir | 2 +- llvm/test/CodeGen/ARM/misched-int-basic.mir | 2 +- llvm/test/CodeGen/ARM/prera-ldst-aliasing.mir | 2 +- llvm/test/CodeGen/ARM/prera-ldst-insertpt.mir | 4 +- llvm/test/CodeGen/ARM/sched-it-debug-nodes.mir | 2 +- llvm/test/CodeGen/ARM/single-issue-r52.mir | 2 +- llvm/test/CodeGen/ARM/v6-jumptable-clobber.mir | 4 +- llvm/test/CodeGen/ARM/vldm-liveness.mir | 2 +- llvm/test/CodeGen/ARM/vldmia-sched.mir | 2 +- llvm/test/CodeGen/Hexagon/bank-conflict.mir | 2 +- .../CodeGen/Hexagon/early-if-conv-lifetime.mir | 2 +- llvm/test/CodeGen/Hexagon/early-if-predicator.mir | 2 +- llvm/test/CodeGen/Hexagon/ifcvt-live-subreg.mir | 2 +- .../CodeGen/Hexagon/pipeliner/swp-phi-start.mir | 2 +- llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir | 2 +- llvm/test/CodeGen/Lanai/peephole-compare.mir | 18 +- .../print-parse-verify-failedISel-property.mir | 2 +- .../CodeGen/MIR/AArch64/return-address-signing.mir | 4 +- llvm/test/CodeGen/MIR/AArch64/swp.mir | 2 +- llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir | 2 +- llvm/test/CodeGen/MIR/Generic/machine-function.mir | 8 +- .../MIR/PowerPC/peephole-miscompile-extswsli.mir | 2 +- .../test/CodeGen/MIR/PowerPC/prolog_vec_spills.mir | 4 +- .../CodeGen/MIR/X86/branch-folder-with-label.mir | 6 +- llvm/test/CodeGen/MIR/X86/diexpr-win32.mir | 4 +- .../test/CodeGen/MIR/X86/expected-stack-object.mir | 2 +- llvm/test/CodeGen/MIR/X86/fixed-stack-di.mir | 2 +- .../MIR/X86/fixed-stack-memory-operands.mir | 2 +- .../MIR/X86/frame-info-stack-references.mir | 2 +- .../Mips/GlobalISel/instruction-select/add.mir | 2 +- .../Mips/GlobalISel/instruction-select/bitwise.mir | 18 +- .../Mips/GlobalISel/instruction-select/branch.mir | 4 +- .../GlobalISel/instruction-select/constants.mir | 8 +- .../Mips/GlobalISel/instruction-select/fabs.mir | 4 +- .../Mips/GlobalISel/instruction-select/fcmp.mir | 64 +- .../Mips/GlobalISel/instruction-select/fence.mir | 2 +- .../GlobalISel/instruction-select/float_args.mir | 16 +- .../float_arithmetic_operations.mir | 16 +- .../instruction-select/float_constants.mir | 4 +- .../instruction-select/fpext_and_fptrunc.mir | 4 +- .../instruction-select/fptosi_and_fptoui.mir | 4 +- .../Mips/GlobalISel/instruction-select/fsqrt.mir | 4 +- .../instruction-select/gloal_address.mir | 2 +- .../instruction-select/gloal_address_pic.mir | 10 +- .../Mips/GlobalISel/instruction-select/icmp.mir | 22 +- .../instruction-select/inttoptr_and_ptrtoint.mir | 4 +- .../instruction-select/jump_table_and_brjt.mir | 2 +- .../Mips/GlobalISel/instruction-select/load.mir | 6 +- .../instruction-select/load_store_fold.mir | 16 +- .../Mips/GlobalISel/instruction-select/mul.mir | 4 +- .../Mips/GlobalISel/instruction-select/phi.mir | 8 +- .../GlobalISel/instruction-select/pointers.mir | 6 +- .../GlobalISel/instruction-select/rem_and_div.mir | 8 +- .../Mips/GlobalISel/instruction-select/select.mir | 8 +- .../instruction-select/sitofp_and_uitofp.mir | 4 +- .../GlobalISel/instruction-select/stack_args.mir | 2 +- .../Mips/GlobalISel/instruction-select/store.mir | 6 +- .../Mips/GlobalISel/instruction-select/sub.mir | 2 +- .../instruction-select/truncStore_and_aExtLoad.mir | 6 +- .../instruction-select/zextLoad_and_sextLoad.mir | 8 +- .../test/CodeGen/Mips/GlobalISel/legalizer/add.mir | 20 +- .../CodeGen/Mips/GlobalISel/legalizer/bitwise.mir | 56 +- .../CodeGen/Mips/GlobalISel/legalizer/branch.mir | 4 +- .../Mips/GlobalISel/legalizer/ceil_and_floor.mir | 8 +- .../Mips/GlobalISel/legalizer/constants.mir | 16 +- .../CodeGen/Mips/GlobalISel/legalizer/fabs.mir | 4 +- .../CodeGen/Mips/GlobalISel/legalizer/fcmp.mir | 4 +- .../CodeGen/Mips/GlobalISel/legalizer/fence.mir | 2 +- .../legalizer/float_arithmetic_operations.mir | 16 +- .../Mips/GlobalISel/legalizer/float_constants.mir | 4 +- .../GlobalISel/legalizer/fpext_and_fptrunc.mir | 4 +- .../GlobalISel/legalizer/fptosi_and_fptoui.mir | 32 +- .../CodeGen/Mips/GlobalISel/legalizer/fsqrt.mir | 4 +- .../Mips/GlobalISel/legalizer/global_address.mir | 2 +- .../CodeGen/Mips/GlobalISel/legalizer/icmp.mir | 28 +- .../GlobalISel/legalizer/inttoptr_and_ptrtoint.mir | 4 +- .../GlobalISel/legalizer/jump_table_and_brjt.mir | 2 +- .../CodeGen/Mips/GlobalISel/legalizer/load.mir | 8 +- .../test/CodeGen/Mips/GlobalISel/legalizer/mul.mir | 22 +- .../test/CodeGen/Mips/GlobalISel/legalizer/phi.mir | 14 +- .../CodeGen/Mips/GlobalISel/legalizer/pointers.mir | 6 +- .../Mips/GlobalISel/legalizer/rem_and_div.mir | 32 +- .../CodeGen/Mips/GlobalISel/legalizer/select.mir | 16 +- .../GlobalISel/legalizer/sitofp_and_uitofp.mir | 32 +- .../Mips/GlobalISel/legalizer/stack_args.mir | 2 +- .../CodeGen/Mips/GlobalISel/legalizer/store.mir | 8 +- .../test/CodeGen/Mips/GlobalISel/legalizer/sub.mir | 18 +- .../CodeGen/Mips/GlobalISel/legalizer/trap.mir | 2 +- .../CodeGen/Mips/GlobalISel/legalizer/trunc.mir | 2 +- .../legalizer/truncStore_and_aExtLoad.mir | 12 +- .../GlobalISel/legalizer/zextLoad_and_sextLoad.mir | 20 +- .../Mips/GlobalISel/legalizer/zext_and_sext.mir | 4 +- .../truncStore_and_aExtLoad.mir | 4 +- .../mips-prelegalizer-combiner/tryCombine.mir | 2 +- .../zextLoad_and_sextLoad.mir | 20 +- .../regbankselect/TypeInfoforMF_skipCopies.mir | 4 +- .../CodeGen/Mips/GlobalISel/regbankselect/add.mir | 2 +- .../Mips/GlobalISel/regbankselect/bitwise.mir | 18 +- .../Mips/GlobalISel/regbankselect/branch.mir | 4 +- .../CodeGen/Mips/GlobalISel/regbankselect/fabs.mir | 4 +- .../CodeGen/Mips/GlobalISel/regbankselect/fcmp.mir | 4 +- .../Mips/GlobalISel/regbankselect/fence.mir | 2 +- .../Mips/GlobalISel/regbankselect/float_args.mir | 16 +- .../regbankselect/float_arithmetic_operations.mir | 16 +- .../GlobalISel/regbankselect/float_constants.mir | 4 +- .../GlobalISel/regbankselect/fpext_and_fptrunc.mir | 4 +- .../GlobalISel/regbankselect/fptosi_and_fptoui.mir | 4 +- .../Mips/GlobalISel/regbankselect/fsqrt.mir | 4 +- .../GlobalISel/regbankselect/global_address.mir | 2 +- .../regbankselect/global_address_pic.mir | 2 +- .../CodeGen/Mips/GlobalISel/regbankselect/icmp.mir | 4 +- .../regbankselect/inttoptr_and_ptrtoint.mir | 4 +- .../regbankselect/jump_table_and_brjt.mir | 2 +- .../CodeGen/Mips/GlobalISel/regbankselect/load.mir | 12 +- .../regbankselect/long_ambiguous_chain_s32.mir | 8 +- .../regbankselect/long_ambiguous_chain_s64.mir | 8 +- .../CodeGen/Mips/GlobalISel/regbankselect/mul.mir | 4 +- .../CodeGen/Mips/GlobalISel/regbankselect/phi.mir | 12 +- .../Mips/GlobalISel/regbankselect/pointers.mir | 6 +- .../Mips/GlobalISel/regbankselect/rem_and_div.mir | 8 +- .../Mips/GlobalISel/regbankselect/select.mir | 14 +- .../GlobalISel/regbankselect/sitofp_and_uitofp.mir | 4 +- .../Mips/GlobalISel/regbankselect/stack_args.mir | 2 +- .../Mips/GlobalISel/regbankselect/store.mir | 8 +- .../CodeGen/Mips/GlobalISel/regbankselect/sub.mir | 2 +- .../regbankselect/test_TypeInfoforMF.mir | 16 +- .../regbankselect/truncStore_and_aExtLoad.mir | 6 +- .../regbankselect/zextLoad_and_sextLoad.mir | 12 +- .../GlobalISel/regbankselect/zext_and_sext.mir | 4 +- llvm/test/CodeGen/Mips/cconv/vector.ll | 732 +++++++++------------ .../compact-branch-implicit-def.mir | 2 +- .../CodeGen/Mips/compactbranches/empty-block.mir | 2 +- .../indirect-jump-hazard/guards-verify-call.mir | 2 +- .../guards-verify-tailcall.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dext-pos.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dext-size.mir | 2 +- .../CodeGen/Mips/instverify/dextm-pos-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dextm-pos.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dextm-size.mir | 2 +- .../CodeGen/Mips/instverify/dextu-pos-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dextu-pos.mir | 2 +- .../CodeGen/Mips/instverify/dextu-size-valid.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dextu-size.mir | 2 +- .../test/CodeGen/Mips/instverify/dins-pos-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dins-pos.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dins-size.mir | 2 +- .../CodeGen/Mips/instverify/dinsm-pos-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dinsm-pos.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dinsm-size.mir | 2 +- .../CodeGen/Mips/instverify/dinsu-pos-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dinsu-pos.mir | 2 +- llvm/test/CodeGen/Mips/instverify/dinsu-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/ext-pos-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/ext-pos.mir | 2 +- llvm/test/CodeGen/Mips/instverify/ext-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/ins-pos-size.mir | 2 +- llvm/test/CodeGen/Mips/instverify/ins-pos.mir | 2 +- llvm/test/CodeGen/Mips/instverify/ins-size.mir | 2 +- .../Mips/longbranch/branch-limits-fp-micromips.mir | 4 +- .../longbranch/branch-limits-fp-micromipsr6.mir | 4 +- .../Mips/longbranch/branch-limits-fp-mips.mir | 4 +- .../Mips/longbranch/branch-limits-fp-mipsr6.mir | 4 +- .../longbranch/branch-limits-int-microMIPS.mir | 16 +- .../longbranch/branch-limits-int-micromipsr6.mir | 24 +- .../Mips/longbranch/branch-limits-int-mips64.mir | 12 +- .../Mips/longbranch/branch-limits-int-mips64r6.mir | 24 +- .../Mips/longbranch/branch-limits-int-mipsr6.mir | 24 +- .../CodeGen/Mips/longbranch/branch-limits-int.mir | 12 +- .../CodeGen/Mips/longbranch/branch-limits-msa.mir | 20 +- llvm/test/CodeGen/Mips/micromips-eva.mir | 4 +- .../CodeGen/Mips/micromips-short-delay-slot.mir | 2 +- .../micromips-sizereduction/micromips-lwp-swp.mir | 8 +- .../micromips-no-lwp-swp.mir | 8 +- .../Mips/mirparser/target-flags-pic-mxgot-tls.mir | 2 +- .../Mips/mirparser/target-flags-pic-o32.mir | 2 +- .../CodeGen/Mips/mirparser/target-flags-pic.mir | 2 +- .../Mips/mirparser/target-flags-static-tls.mir | 2 +- llvm/test/CodeGen/Mips/msa/2r_vector_scalar.ll | 5 +- llvm/test/CodeGen/Mips/msa/emergency-spill.mir | 2 +- llvm/test/CodeGen/Mips/msa/nori.b.ll | 26 + .../CodeGen/Mips/sll-micromips-r6-encoding.mir | 2 +- .../test/CodeGen/Mips/unaligned-memops-mapping.mir | 12 +- .../PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir | 2 +- llvm/test/CodeGen/PowerPC/aantidep-def-ec.mir | 2 +- llvm/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir | 2 +- llvm/test/CodeGen/PowerPC/block-placement-1.mir | 4 +- llvm/test/CodeGen/PowerPC/block-placement.mir | 2 +- llvm/test/CodeGen/PowerPC/collapse-rotates.mir | 2 +- ...convert-rr-to-ri-instrs-R0-special-handling.mir | 14 +- .../convert-rr-to-ri-instrs-out-of-range.mir | 40 +- .../CodeGen/PowerPC/convert-rr-to-ri-instrs.mir | 176 ++--- .../CodeGen/PowerPC/convert-rr-to-ri-p9-vector.mir | 6 +- llvm/test/CodeGen/PowerPC/expand-isel-1.mir | 2 +- llvm/test/CodeGen/PowerPC/expand-isel-10.mir | 2 +- llvm/test/CodeGen/PowerPC/expand-isel-2.mir | 2 +- llvm/test/CodeGen/PowerPC/expand-isel-3.mir | 2 +- llvm/test/CodeGen/PowerPC/expand-isel-4.mir | 2 +- llvm/test/CodeGen/PowerPC/expand-isel-5.mir | 2 +- llvm/test/CodeGen/PowerPC/expand-isel-6.mir | 2 +- llvm/test/CodeGen/PowerPC/expand-isel-7.mir | 2 +- llvm/test/CodeGen/PowerPC/expand-isel-8.mir | 2 +- llvm/test/CodeGen/PowerPC/expand-isel-9.mir | 2 +- .../CodeGen/PowerPC/no-rlwimi-trivial-commute.mir | 2 +- .../test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir | 2 +- .../CodeGen/PowerPC/remove-copy-crunsetcrbit.mir | 2 +- llvm/test/CodeGen/PowerPC/remove-implicit-use.mir | 2 +- .../CodeGen/PowerPC/remove-redundant-load-imm.mir | 28 +- llvm/test/CodeGen/PowerPC/remove-self-copies.mir | 2 +- .../test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir | 12 +- llvm/test/CodeGen/PowerPC/schedule-addi-load.mir | 2 +- llvm/test/CodeGen/PowerPC/setcr_bc.mir | 2 +- llvm/test/CodeGen/PowerPC/setcr_bc2.mir | 2 +- llvm/test/CodeGen/PowerPC/setcr_bc3.mir | 2 +- llvm/test/CodeGen/PowerPC/shrink-wrap.mir | 2 +- llvm/test/CodeGen/PowerPC/tls_get_addr_fence1.mir | 2 +- llvm/test/CodeGen/PowerPC/tls_get_addr_fence2.mir | 2 +- .../CodeGen/RISCV/select-optimize-multiple.mir | 4 +- .../CodeGen/SystemZ/RAbasic-invalid-LR-update.mir | 2 +- .../CodeGen/SystemZ/clear-liverange-spillreg.mir | 2 +- llvm/test/CodeGen/SystemZ/cond-move-04.mir | 2 +- llvm/test/CodeGen/SystemZ/cond-move-05.mir | 2 +- llvm/test/CodeGen/SystemZ/cond-move-08.mir | 2 +- .../CodeGen/SystemZ/cond-move-regalloc-hints.mir | 2 +- llvm/test/CodeGen/SystemZ/debuginstr-00.mir | 2 +- llvm/test/CodeGen/SystemZ/debuginstr-01.mir | 2 +- llvm/test/CodeGen/SystemZ/debuginstr-02.mir | 2 +- llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir | 2 +- llvm/test/CodeGen/SystemZ/fp-conv-17.mir | 2 +- .../CodeGen/SystemZ/load-and-test-RA-hints.mir | 2 +- llvm/test/CodeGen/SystemZ/misched-readadvances.mir | 2 +- .../CodeGen/SystemZ/postra-sched-expandedops.mir | 2 +- llvm/test/CodeGen/SystemZ/regalloc-GR128-02.mir | 2 +- .../SystemZ/regalloc-fast-invalid-kill-flag.mir | 2 +- .../regcoal-undef-lane-4-rm-cp-commuting-def.mir | 2 +- llvm/test/CodeGen/SystemZ/subregliveness-06.mir | 2 +- llvm/test/CodeGen/SystemZ/subregliveness-07.mir | 2 +- llvm/test/CodeGen/Thumb/PR36658.mir | 2 +- llvm/test/CodeGen/Thumb/tbb-reuse.mir | 2 +- .../CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir | 2 +- .../LowOverheadLoops/end-positive-offset.mir | 2 +- .../CodeGen/Thumb2/LowOverheadLoops/massive.mir | 2 +- .../Thumb2/LowOverheadLoops/multiblock-massive.mir | 2 +- .../Thumb2/LowOverheadLoops/revert-after-call.mir | 2 +- .../Thumb2/LowOverheadLoops/revert-after-read.mir | 2 +- .../Thumb2/LowOverheadLoops/revert-after-spill.mir | 2 +- .../Thumb2/LowOverheadLoops/revert-after-write.mir | 2 +- .../Thumb2/LowOverheadLoops/revert-non-header.mir | 2 +- .../Thumb2/LowOverheadLoops/revert-non-loop.mir | 2 +- .../Thumb2/LowOverheadLoops/revert-while.mir | 2 +- .../CodeGen/Thumb2/LowOverheadLoops/size-limit.mir | 2 +- .../CodeGen/Thumb2/LowOverheadLoops/switch.mir | 2 +- .../LowOverheadLoops/while-negative-offset.mir | 2 +- .../test/CodeGen/Thumb2/LowOverheadLoops/while.mir | 2 +- llvm/test/CodeGen/Thumb2/m4-sched-ldr.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-block.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-block2.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-block3.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-block4.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-block5.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-block6.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-block7.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-block8.mir | 2 +- llvm/test/CodeGen/Thumb2/mve-vpt-nots.mir | 12 +- llvm/test/CodeGen/Thumb2/tbb-removeadd.mir | 2 +- .../X86/GlobalISel/avoid-matchtable-crash.mir | 2 +- .../CodeGen/X86/GlobalISel/legalize-add-v128.mir | 8 +- .../CodeGen/X86/GlobalISel/legalize-add-v256.mir | 8 +- .../CodeGen/X86/GlobalISel/legalize-add-v512.mir | 10 +- llvm/test/CodeGen/X86/GlobalISel/legalize-add.mir | 6 +- .../CodeGen/X86/GlobalISel/legalize-and-scalar.mir | 10 +- .../X86/GlobalISel/legalize-ashr-scalar.mir | 4 +- .../CodeGen/X86/GlobalISel/legalize-brcond.mir | 2 +- llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir | 10 +- .../CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir | 24 +- llvm/test/CodeGen/X86/GlobalISel/legalize-ext.mir | 36 +- .../X86/GlobalISel/legalize-fadd-scalar.mir | 4 +- .../X86/GlobalISel/legalize-fdiv-scalar.mir | 4 +- .../X86/GlobalISel/legalize-fmul-scalar.mir | 4 +- .../X86/GlobalISel/legalize-fpext-scalar.mir | 2 +- .../X86/GlobalISel/legalize-fptrunc-scalar.mir | 2 +- .../X86/GlobalISel/legalize-fsub-scalar.mir | 4 +- .../X86/GlobalISel/legalize-insert-vec256.mir | 2 +- .../X86/GlobalISel/legalize-insert-vec512.mir | 4 +- .../X86/GlobalISel/legalize-lshr-scalar.mir | 4 +- .../X86/GlobalISel/legalize-memop-scalar-32.mir | 4 +- .../X86/GlobalISel/legalize-memop-scalar-64.mir | 4 +- .../CodeGen/X86/GlobalISel/legalize-mul-scalar.mir | 8 +- .../CodeGen/X86/GlobalISel/legalize-mul-v128.mir | 6 +- .../CodeGen/X86/GlobalISel/legalize-mul-v256.mir | 6 +- .../CodeGen/X86/GlobalISel/legalize-mul-v512.mir | 6 +- .../CodeGen/X86/GlobalISel/legalize-or-scalar.mir | 10 +- llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir | 14 +- .../CodeGen/X86/GlobalISel/legalize-shl-scalar.mir | 4 +- .../CodeGen/X86/GlobalISel/legalize-sub-v128.mir | 8 +- .../CodeGen/X86/GlobalISel/legalize-sub-v256.mir | 8 +- .../CodeGen/X86/GlobalISel/legalize-sub-v512.mir | 8 +- llvm/test/CodeGen/X86/GlobalISel/legalize-sub.mir | 4 +- .../CodeGen/X86/GlobalISel/legalize-xor-scalar.mir | 10 +- .../CodeGen/X86/GlobalISel/regbankselect-AVX2.mir | 10 +- .../X86/GlobalISel/regbankselect-AVX512.mir | 10 +- .../CodeGen/X86/GlobalISel/regbankselect-X32.mir | 2 +- .../X86/GlobalISel/regbankselect-X86_64.mir | 164 ++--- llvm/test/CodeGen/X86/GlobalISel/select-GV-32.mir | 4 +- llvm/test/CodeGen/X86/GlobalISel/select-GV-64.mir | 4 +- .../CodeGen/X86/GlobalISel/select-add-v128.mir | 8 +- .../CodeGen/X86/GlobalISel/select-add-v256.mir | 8 +- .../CodeGen/X86/GlobalISel/select-add-v512.mir | 8 +- .../test/CodeGen/X86/GlobalISel/select-add-x32.mir | 2 +- llvm/test/CodeGen/X86/GlobalISel/select-add.mir | 8 +- .../CodeGen/X86/GlobalISel/select-and-scalar.mir | 8 +- .../CodeGen/X86/GlobalISel/select-ashr-scalar.mir | 24 +- llvm/test/CodeGen/X86/GlobalISel/select-blsi.mir | 4 +- llvm/test/CodeGen/X86/GlobalISel/select-blsr.mir | 4 +- llvm/test/CodeGen/X86/GlobalISel/select-br.mir | 2 +- llvm/test/CodeGen/X86/GlobalISel/select-brcond.mir | 2 +- llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir | 26 +- .../CodeGen/X86/GlobalISel/select-constant.mir | 4 +- llvm/test/CodeGen/X86/GlobalISel/select-copy.mir | 12 +- .../CodeGen/X86/GlobalISel/select-ext-x86-64.mir | 14 +- llvm/test/CodeGen/X86/GlobalISel/select-ext.mir | 26 +- .../X86/GlobalISel/select-extract-vec256.mir | 4 +- .../X86/GlobalISel/select-extract-vec512.mir | 8 +- .../CodeGen/X86/GlobalISel/select-fadd-scalar.mir | 4 +- .../CodeGen/X86/GlobalISel/select-fconstant.mir | 4 +- .../CodeGen/X86/GlobalISel/select-fdiv-scalar.mir | 4 +- .../CodeGen/X86/GlobalISel/select-fmul-scalar.mir | 4 +- .../CodeGen/X86/GlobalISel/select-fpext-scalar.mir | 2 +- .../X86/GlobalISel/select-fptrunc-scalar.mir | 2 +- .../CodeGen/X86/GlobalISel/select-fsub-scalar.mir | 4 +- llvm/test/CodeGen/X86/GlobalISel/select-gep.mir | 2 +- .../X86/GlobalISel/select-insert-vec256.mir | 8 +- .../X86/GlobalISel/select-insert-vec512.mir | 16 +- .../CodeGen/X86/GlobalISel/select-lshr-scalar.mir | 24 +- .../GlobalISel/select-memop-scalar-unordered.mir | 36 +- .../X86/GlobalISel/select-memop-scalar-x32.mir | 16 +- .../CodeGen/X86/GlobalISel/select-memop-scalar.mir | 36 +- .../CodeGen/X86/GlobalISel/select-memop-v128.mir | 8 +- .../CodeGen/X86/GlobalISel/select-memop-v256.mir | 8 +- .../CodeGen/X86/GlobalISel/select-memop-v512.mir | 8 +- .../CodeGen/X86/GlobalISel/select-merge-vec256.mir | 2 +- .../CodeGen/X86/GlobalISel/select-merge-vec512.mir | 4 +- .../CodeGen/X86/GlobalISel/select-mul-scalar.mir | 6 +- .../test/CodeGen/X86/GlobalISel/select-mul-vec.mir | 30 +- .../CodeGen/X86/GlobalISel/select-or-scalar.mir | 8 +- llvm/test/CodeGen/X86/GlobalISel/select-phi.mir | 12 +- .../CodeGen/X86/GlobalISel/select-shl-scalar.mir | 24 +- .../CodeGen/X86/GlobalISel/select-sub-v128.mir | 8 +- .../CodeGen/X86/GlobalISel/select-sub-v256.mir | 8 +- .../CodeGen/X86/GlobalISel/select-sub-v512.mir | 8 +- llvm/test/CodeGen/X86/GlobalISel/select-sub.mir | 4 +- llvm/test/CodeGen/X86/GlobalISel/select-trunc.mir | 12 +- llvm/test/CodeGen/X86/GlobalISel/select-undef.mir | 6 +- .../X86/GlobalISel/select-unmerge-vec256.mir | 2 +- .../X86/GlobalISel/select-unmerge-vec512.mir | 4 +- .../CodeGen/X86/GlobalISel/select-xor-scalar.mir | 8 +- .../CodeGen/X86/GlobalISel/x86-legalize-GV.mir | 2 +- .../X86/GlobalISel/x86-legalize-inttoptr.mir | 2 +- .../X86/GlobalISel/x86-legalize-ptrtoint.mir | 8 +- .../CodeGen/X86/GlobalISel/x86-legalize-sdiv.mir | 6 +- .../CodeGen/X86/GlobalISel/x86-legalize-srem.mir | 6 +- .../CodeGen/X86/GlobalISel/x86-legalize-udiv.mir | 6 +- .../CodeGen/X86/GlobalISel/x86-legalize-urem.mir | 6 +- .../CodeGen/X86/GlobalISel/x86-select-inttoptr.mir | 2 +- .../CodeGen/X86/GlobalISel/x86-select-ptrtoint.mir | 8 +- .../CodeGen/X86/GlobalISel/x86-select-sdiv.mir | 6 +- .../CodeGen/X86/GlobalISel/x86-select-srem.mir | 6 +- .../CodeGen/X86/GlobalISel/x86-select-trap.mir | 2 +- .../CodeGen/X86/GlobalISel/x86-select-udiv.mir | 6 +- .../CodeGen/X86/GlobalISel/x86-select-urem.mir | 6 +- .../CodeGen/X86/GlobalISel/x86_64-legalize-GV.mir | 2 +- .../X86/GlobalISel/x86_64-legalize-fcmp.mir | 56 +- .../X86/GlobalISel/x86_64-legalize-fptosi.mir | 16 +- .../X86/GlobalISel/x86_64-legalize-inttoptr.mir | 2 +- .../X86/GlobalISel/x86_64-legalize-ptrtoint.mir | 10 +- .../X86/GlobalISel/x86_64-legalize-sdiv.mir | 8 +- .../X86/GlobalISel/x86_64-legalize-sitofp.mir | 16 +- .../X86/GlobalISel/x86_64-legalize-srem.mir | 8 +- .../X86/GlobalISel/x86_64-legalize-udiv.mir | 8 +- .../X86/GlobalISel/x86_64-legalize-urem.mir | 8 +- .../X86/GlobalISel/x86_64-legalize-zext.mir | 20 +- .../CodeGen/X86/GlobalISel/x86_64-select-fcmp.mir | 56 +- .../X86/GlobalISel/x86_64-select-fptosi.mir | 16 +- .../X86/GlobalISel/x86_64-select-inttoptr.mir | 2 +- .../X86/GlobalISel/x86_64-select-ptrtoint.mir | 10 +- .../CodeGen/X86/GlobalISel/x86_64-select-sdiv.mir | 8 +- .../X86/GlobalISel/x86_64-select-sitofp.mir | 8 +- .../CodeGen/X86/GlobalISel/x86_64-select-srem.mir | 8 +- .../CodeGen/X86/GlobalISel/x86_64-select-udiv.mir | 8 +- .../CodeGen/X86/GlobalISel/x86_64-select-urem.mir | 8 +- .../CodeGen/X86/GlobalISel/x86_64-select-zext.mir | 20 +- llvm/test/CodeGen/X86/PR37310.mir | 2 +- llvm/test/CodeGen/X86/adx-commute.mir | 8 +- llvm/test/CodeGen/X86/avoid-sfb-g-no-change.mir | 4 +- llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir | 2 +- llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir | 2 +- llvm/test/CodeGen/X86/avoid-sfb-kill-flags.mir | 2 +- llvm/test/CodeGen/X86/avoid-sfb-offset.mir | 2 +- llvm/test/CodeGen/X86/avx512f-256-set0.mir | 2 +- llvm/test/CodeGen/X86/bad-tls-fold.mir | 4 +- llvm/test/CodeGen/X86/block-placement.mir | 2 +- .../CodeGen/X86/conditional-tailcall-samedest.mir | 2 +- .../X86/dbg-changes-codegen-branch-folding2.mir | 2 +- llvm/test/CodeGen/X86/domain-reassignment.mir | 16 +- llvm/test/CodeGen/X86/fixup-bw-inst.mir | 10 +- llvm/test/CodeGen/X86/implicit-null-checks.mir | 54 +- .../CodeGen/X86/implicit-null-chk-reg-rewrite.mir | 2 +- llvm/test/CodeGen/X86/late-remat-update.mir | 2 +- llvm/test/CodeGen/X86/lea-opt-with-debug.mir | 2 +- llvm/test/CodeGen/X86/leaFixup32.mir | 24 +- llvm/test/CodeGen/X86/leaFixup64.mir | 50 +- llvm/test/CodeGen/X86/limit-split-cost.mir | 2 +- llvm/test/CodeGen/X86/movtopush.mir | 2 +- llvm/test/CodeGen/X86/non-value-mem-operand.mir | 2 +- llvm/test/CodeGen/X86/opt_phis2.mir | 2 +- llvm/test/CodeGen/X86/peephole-fold-testrr.mir | 4 +- llvm/test/CodeGen/X86/postra-ignore-dbg-instrs.mir | 2 +- llvm/test/CodeGen/X86/pr30821.mir | 2 +- llvm/test/CodeGen/X86/pr38952.mir | 2 +- llvm/test/CodeGen/X86/pre-coalesce.mir | 2 +- llvm/test/CodeGen/X86/regalloc-copy-hints.mir | 2 +- llvm/test/CodeGen/X86/shrink_wrap_dbg_value.mir | 2 +- .../CodeGen/X86/sjlj-shadow-stack-liveness.mir | 2 +- llvm/test/CodeGen/X86/stack-folding-adx.mir | 8 +- llvm/test/CodeGen/X86/stack-folding-bmi2.mir | 4 +- .../CodeGen/X86/win_coreclr_chkstk_liveins.mir | 2 +- llvm/test/DebugInfo/AArch64/asan-stack-vars.mir | 4 +- .../AArch64/compiler-gen-bbs-livedebugvalues.mir | 2 +- llvm/test/DebugInfo/ARM/cfi-eof-prologue.mir | 4 +- llvm/test/DebugInfo/MIR/AArch64/clobber-sp.mir | 2 +- .../MIR/AArch64/implicit-def-dead-scope.mir | 2 +- .../MIR/ARM/live-debug-values-reg-copy.mir | 2 +- .../DebugInfo/MIR/ARM/split-superreg-complex.mir | 2 +- .../DebugInfo/MIR/ARM/split-superreg-piece.mir | 2 +- llvm/test/DebugInfo/MIR/ARM/split-superreg.mir | 2 +- llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir | 2 +- .../MIR/Mips/live-debug-values-reg-copy.mir | 2 +- llvm/test/DebugInfo/MIR/X86/DW_OP_entry_value.mir | 2 +- .../MIR/X86/avoid-single-entry-value-location.mir | 2 +- llvm/test/DebugInfo/MIR/X86/bit-piece-dh.mir | 2 +- .../DebugInfo/MIR/X86/dbg-stack-value-range.mir | 2 +- llvm/test/DebugInfo/MIR/X86/dbginfo-entryvals.mir | 2 +- llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir | 2 +- llvm/test/DebugInfo/MIR/X86/empty-inline.mir | 2 +- llvm/test/DebugInfo/MIR/X86/kill-after-spill.mir | 2 +- .../DebugInfo/MIR/X86/live-debug-values-3preds.mir | 2 +- .../MIR/X86/live-debug-values-reg-copy.mir | 2 +- .../MIR/X86/live-debug-values-restore-collide.mir | 2 +- .../MIR/X86/live-debug-values-restore.mir | 8 +- .../DebugInfo/MIR/X86/live-debug-values-spill.mir | 2 +- llvm/test/DebugInfo/MIR/X86/live-debug-values.mir | 2 +- .../X86/live-debug-vars-unused-arg-debugonly.mir | 2 +- .../MIR/X86/live-debug-vars-unused-arg.mir | 2 +- .../DebugInfo/MIR/X86/livedebugvalues-limit.mir | 4 +- .../MIR/X86/livedebugvars-crossbb-interval.mir | 2 +- llvm/test/DebugInfo/MIR/X86/mlicm-hoist.mir | 2 +- .../MIR/X86/multiple-param-dbg-value-entry.mir | 2 +- llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir | 2 +- .../MIR/X86/prolog-epilog-indirection.mir | 2 +- llvm/test/DebugInfo/MIR/X86/regcoalescer.mir | 2 +- llvm/test/DebugInfo/X86/debug-loc-asan.mir | 2 +- llvm/test/DebugInfo/X86/debug-loc-offset.mir | 10 +- llvm/test/DebugInfo/X86/dw_op_minus.mir | 2 +- .../DebugInfo/X86/live-debug-values-constprop.mir | 8 +- llvm/test/DebugInfo/X86/live-debug-vars-dse.mir | 2 +- llvm/test/DebugInfo/X86/pr19307.mir | 2 +- llvm/test/ThinLTO/X86/lazyload_metadata.ll | 4 +- .../test/Transforms/InstCombine/deref-alloc-fns.ll | 12 +- .../Transforms/InstCombine/icmp-div-constant.ll | 28 +- .../Transforms/InstCombine/malloc-free-delete.ll | 4 +- llvm/test/Transforms/InstCombine/objsize-64.ll | 2 +- llvm/test/Transforms/LowerExpectIntrinsic/basic.ll | 31 +- .../Inputs/misexpect-branch-correct.proftext | 38 -- .../PGOProfile/Inputs/misexpect-branch.proftext | 38 -- .../Inputs/misexpect-switch-correct.proftext | 16 - .../PGOProfile/Inputs/misexpect-switch.proftext | 16 - .../PGOProfile/misexpect-branch-correct.ll | 94 --- .../PGOProfile/misexpect-branch-stripped.ll | 115 ---- .../PGOProfile/misexpect-branch-unpredictable.ll | 89 --- .../test/Transforms/PGOProfile/misexpect-branch.ll | 130 ---- .../PGOProfile/misexpect-switch-default.ll | 196 ------ .../test/Transforms/PGOProfile/misexpect-switch.ll | 293 --------- llvm/tools/llvm-reduce/deltas/ReduceMetadata.cpp | 1 - .../gn/secondary/llvm/tools/llvm-reduce/BUILD.gn | 1 + 717 files changed, 3203 insertions(+), 4933 deletions(-) delete mode 100644 clang/test/Profile/Inputs/misexpect-branch-nonconst-expect-arg. [...] delete mode 100644 clang/test/Profile/Inputs/misexpect-branch.proftext delete mode 100644 clang/test/Profile/Inputs/misexpect-switch-default-only.proftext delete mode 100644 clang/test/Profile/Inputs/misexpect-switch-default.proftext delete mode 100644 clang/test/Profile/Inputs/misexpect-switch-nonconst.proftext delete mode 100644 clang/test/Profile/Inputs/misexpect-switch.proftext delete mode 100644 clang/test/Profile/misexpect-branch-cold.c delete mode 100644 clang/test/Profile/misexpect-branch-nonconst-expected-val.c delete mode 100644 clang/test/Profile/misexpect-branch-unpredictable.c delete mode 100644 clang/test/Profile/misexpect-branch.c delete mode 100644 clang/test/Profile/misexpect-switch-default.c delete mode 100644 clang/test/Profile/misexpect-switch-nonconst.c delete mode 100644 clang/test/Profile/misexpect-switch-only-default-case.c delete mode 100644 clang/test/Profile/misexpect-switch.c create mode 100644 clang/test/Sema/div-sizeof-array.cpp delete mode 100644 compiler-rt/lib/profile/xxhash.c delete mode 100644 compiler-rt/lib/profile/xxhash.h create mode 100644 lldb/lit/Modules/ELF/Inputs/load-from-dynsym-alone.c create mode 100644 lldb/lit/Modules/ELF/Inputs/load-symtab-and-dynsym.c create mode 100644 lldb/lit/Modules/ELF/load-from-dynsym-alone.test create mode 100644 lldb/lit/Modules/ELF/load-symtab-and-dynsym.test delete mode 100644 llvm/include/llvm/Transforms/Utils/MisExpect.h delete mode 100644 llvm/lib/Transforms/Utils/MisExpect.cpp create mode 100644 llvm/test/CodeGen/Mips/msa/nori.b.ll delete mode 100644 llvm/test/Transforms/PGOProfile/Inputs/misexpect-branch-correct [...] delete mode 100644 llvm/test/Transforms/PGOProfile/Inputs/misexpect-branch.proftext delete mode 100644 llvm/test/Transforms/PGOProfile/Inputs/misexpect-switch-correct [...] delete mode 100644 llvm/test/Transforms/PGOProfile/Inputs/misexpect-switch.proftext delete mode 100644 llvm/test/Transforms/PGOProfile/misexpect-branch-correct.ll delete mode 100644 llvm/test/Transforms/PGOProfile/misexpect-branch-stripped.ll delete mode 100644 llvm/test/Transforms/PGOProfile/misexpect-branch-unpredictable.ll delete mode 100644 llvm/test/Transforms/PGOProfile/misexpect-branch.ll delete mode 100644 llvm/test/Transforms/PGOProfile/misexpect-switch-default.ll delete mode 100644 llvm/test/Transforms/PGOProfile/misexpect-switch.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig updated (a5b8346f0 -> b4ff9f40f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allyesconfig in repository toolchain/ci/base-artifacts. from a5b8346f0 1: reset: llvm-73ec745793acdddc505610ae6a1087ada3140ef2: 18047 new b4ff9f40f 2: update: llvm-9703f46fc1ba216e576c8ad044176749a7d10bb5: 18047 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 177 +- 02-build_llvm/console.log | 12150 ++++++++++++++++++----------------- 03-build_linux/console.log | 712 ++- 05-check_regression/console.log | 20 +- 06-update_baseline/console.log | 51 + console.log | 13110 +++++++++++++++++++------------------- jenkins/manifest.sh | 10 +- reset-baseline | 0 8 files changed, 13183 insertions(+), 13047 deletions(-) delete mode 100644 reset-baseline -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[llvm] branch master updated (e79a44af114 -> 06de30684d5)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from e79a44af114 [X86] Fix latent bugs in 32-bit CMPXCHG8B inserter new 06de30684d5 PR43278: Temporarily disable llvm-reduce tests due to exhau [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: test/Reduce/remove-funcs.ll | 4 ++-- test/Reduce/remove-global-vars.ll | 4 ++-- test/Reduce/remove-metadata.ll | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[compiler-rt] branch master updated (8915a0b66 -> d40d1324c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository compiler-rt. from 8915a0b66 Update compiler-rt cpplint.py https://github.com/cpplint/cppl [...] new d40d1324c Fix mac build The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/sanitizer_common/sanitizer_procmaps_mac.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[llvm] branch master updated (c809898d84c -> e79a44af114)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from c809898d84c [ConstantFolding] Refactor math functions to use LLVM ones (NFC) new e79a44af114 [X86] Fix latent bugs in 32-bit CMPXCHG8B inserter The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/X86/X86ISelLowering.cpp | 12 +++-- lib/Target/X86/X86InstrBuilder.h | 6 +-- .../X86/cmpxchg8b_alloca_regalloc_handling.ll | 61 ++++++++++++++++++++++ 3 files changed, 72 insertions(+), 7 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[glibc] branch google/grte/v5-2.27/master updated (d271633c64 -> 45078f3e70)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch google/grte/v5-2.27/master in repository glibc. from d271633c64 Remove -no-integrated-as option from the build new 45078f3e70 Redesign the fastload support for additional performance The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: elf/dl-close.c | 3 + elf/dl-load.c | 248 +++++++++++++++---- elf/dl-lookup.c | 583 +++++++++++++++++---------------------------- elf/dl-object.c | 9 +- elf/dl-sort-maps.c | 27 ++- elf/dl-support.c | 3 - elf/rtld.c | 8 +- include/link.h | 3 +- sysdeps/generic/ldsodefs.h | 24 +- 9 files changed, 474 insertions(+), 434 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allmodconfig updated (cdbc7c281 -> 8cc53d885)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-next-allmodconfig in repository toolchain/ci/base-artifacts. discards cdbc7c281 0: update: llvm-linux: 19841 new 8cc53d885 0: update: linux-35394d031b710e832849fca60d0f53b513f0c390: 19841 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (cdbc7c281) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-n [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 16 +- 02-build_llvm/console.log | 11992 ++++++++++++++++++------------------ 03-build_linux/console.log | 862 +-- console.log | 12870 +++++++++++++++++++-------------------- jenkins/manifest.sh | 9 +- 5 files changed, 12708 insertions(+), 13041 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[llvm] branch master updated (c50052e27b6 -> c809898d84c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from c50052e27b6 Revert [llvm-nm] Add tapi file support new c809898d84c [ConstantFolding] Refactor math functions to use LLVM ones (NFC) The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Analysis/ConstantFolding.cpp | 79 +++++++++++++++++++++------------------- 1 file changed, 42 insertions(+), 37 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

Tcwg-commits September 2019