Tcwg-commits September 2019

tcwg-commits@lists.linaro.org

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14312 discussions

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allnoconfig updated (44c685cd -> 93816d58)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-lts-allnoconfig in repository toolchain/ci/base-artifacts. discards 44c685cd 0: update: binutils-gcc-linux: boot new 93816d58 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (44c685cd) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-release-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 58 +- 02-prepare_abe/console.log | 168 +- 03-build_abe-binutils/console.log | 11120 +++++++-------- 04-build_abe-stage1/console.log | 13981 +++++++++---------- 05-build_linux/console.log | 722 +- 06-boot_linux/console.log | 4 +- console.log | 26057 ++++++++++++++++++------------------ jenkins/manifest.sh | 8 +- 8 files changed, 26062 insertions(+), 26056 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 1 month

[llvm] branch master updated (ca6e7338d6e -> 132df1d1cd7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from ca6e7338d6e [TargetLowering] Simplify expansion of S{ADD,SUB}O new 132df1d1cd7 [ARM][MVE] Change VCTP operand The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/ARM/MVETailPredication.cpp | 6 ++-- .../Thumb2/LowOverheadLoops/basic-tail-pred.ll | 14 ++++----- .../cond-vector-reduce-mve-codegen.ll | 28 ++++++++++-------- .../Thumb2/LowOverheadLoops/mve-tail-data-types.ll | 21 ++++++------- test/CodeGen/Thumb2/LowOverheadLoops/nested.ll | 2 +- .../Thumb2/LowOverheadLoops/tail-pred-widen.ll | 2 +- .../CodeGen/Thumb2/LowOverheadLoops/tail-reduce.ll | 4 +-- .../LowOverheadLoops/vector-arith-codegen.ll | 34 +++++++++++++++------- .../LowOverheadLoops/vector-reduce-mve-tail.ll | 4 +-- 9 files changed, 66 insertions(+), 49 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 1 month

[gcc] branch master updated (70f0835d2a9 -> 9ce1ca72088)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 70f0835d2a9 PR target/91931 * config/i386/i386-expand.c (ix86_expand_ [...] new 9ce1ca72088 2019-09-30 Andreas Tobler <andreast(a)gcc.gnu.org> The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 8 ++++++++ gcc/config.gcc | 6 ++++++ gcc/config/rs6000/t-freebsd64 | 3 +++ 3 files changed, 17 insertions(+) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 1 month

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allyesconfig updated (1e8c0850b1f -> 5951e3f8134)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allyesconfig in repository toolchain/ci/llvm-project. from 1e8c0850b1f For now, disallow lifetime-extended temporaries with non-tr [...] adds 9bc1c6ecc56 [cxx_status] Mark P0784R7 as partially complete. adds 120a5e9a745 [ARM] Cortex-M4 schedule additions adds 72b544e656b [PowerPC] Fix conditions of assert in PPCAsmPrinter adds 83476b813e2 [clang-format] Reference qualifiers in member templates cau [...] adds 8b1eeafb913 [SLP] Fix for PR31847: Assertion failed: (isLoopInvariant(O [...] adds d30093bb8a3 [DivRemPairs] Don't assert that we won't ever get expanded- [...] adds c5133606627 [MC] Emit unused undefined symbol even if its binding is not set adds eb78dea4ccd [Docs] Moves article links to new pages adds a6d9d31279c [LLVM-C][Ocaml] Add MergeFunctions and DCE pass adds aabf8cbfca8 Add test case peeking through vector concat when combining [...] adds 0e3f6591371 [X86] Add custom isel logic to match VPTERNLOG from 2 logic ops. adds 00966d1791f Don't crash if a variable with a constexpr destructor has a [...] adds 1069c019241 [X86] Remove -x86-experimental-vector-widening-legalization [...] adds 6c320b22cd2 [X86] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off [...] adds 9a5e3d39f69 Undef the macros after their use adds 1b0ea0a12e7 [X86] Split v16i32/v8i64 bitreverse on avx512f targets with [...] adds 4006434ed1d [ELF][test] Change llvm-readobj --arm-attributes to --arch- [...] adds 34f9e98aaec [test] Change llvm-readobj --arm-attributes to --arch-speci [...] adds 317d991fa51 AMDGPU/GlobalISel: Fix select for v2s16 and/or/xor adds 5951e3f8134 [X86] Remove some redundant isel patterns. NFCI No new revisions were added by this update. Summary of changes: clang/lib/Format/TokenAnnotator.cpp | 25 +- clang/lib/Sema/SemaDeclCXX.cpp | 3 +- clang/test/SemaCXX/constant-expression-cxx2a.cpp | 9 + clang/unittests/Format/FormatTest.cpp | 68 + clang/www/cxx_status.html | 2 +- lld/test/ELF/arm-attributes.s | 6 +- lld/test/ELF/ppc64-abs64-dyn.s | 8 +- lld/test/ELF/ppc64-relocs.s | 4 +- llvm/bindings/ocaml/transforms/ipo/ipo_ocaml.c | 6 + llvm/bindings/ocaml/transforms/ipo/llvm_ipo.ml | 3 + llvm/bindings/ocaml/transforms/ipo/llvm_ipo.mli | 5 + .../transforms/scalar_opts/llvm_scalar_opts.ml | 3 + .../transforms/scalar_opts/llvm_scalar_opts.mli | 5 + .../transforms/scalar_opts/scalar_opts_ocaml.c | 5 + llvm/docs/ProgrammingDocumentation.rst | 5 + llvm/docs/Reference.rst | 24 +- llvm/docs/SubsystemDocumentation.rst | 28 +- llvm/docs/_templates/indexsidebar.html | 2 + llvm/docs/index.rst | 3 - llvm/include/llvm-c/Transforms/IPO.h | 3 + llvm/include/llvm-c/Transforms/Scalar.h | 3 + llvm/include/llvm/MC/MCLinkerOptimizationHint.h | 2 + .../llvm/Transforms/Vectorize/SLPVectorizer.h | 9 +- llvm/lib/MC/ELFObjectWriter.cpp | 3 - llvm/lib/Target/AMDGPU/VOP2Instructions.td | 32 +- llvm/lib/Target/ARM/ARMInstrFormats.td | 1 + llvm/lib/Target/ARM/ARMInstrInfo.td | 18 +- llvm/lib/Target/ARM/ARMInstrThumb2.td | 3 +- llvm/lib/Target/ARM/ARMInstrVFP.td | 11 +- llvm/lib/Target/ARM/ARMScheduleM4.td | 24 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 2 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 80 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 1330 +++----------------- llvm/lib/Target/X86/X86InstrAVX512.td | 78 -- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 86 +- llvm/lib/Transforms/IPO/IPO.cpp | 4 + llvm/lib/Transforms/Scalar/DivRemPairs.cpp | 2 - llvm/lib/Transforms/Scalar/Scalar.cpp | 4 + llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 152 ++- .../CodeGen/AMDGPU/GlobalISel/inst-select-and.mir | 30 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-or.mir | 30 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir | 30 +- .../CodeGen/ARM/ParallelDSP/complex_dot_prod.ll | 6 +- .../CodeGen/ARM/ParallelDSP/multi-use-loads.ll | 52 +- .../CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll | 1 - .../ARM/build-attributes-optimization-minsize.ll | 6 +- .../ARM/build-attributes-optimization-mixed.ll | 6 +- .../ARM/build-attributes-optimization-optnone.ll | 6 +- .../ARM/build-attributes-optimization-optsize.ll | 6 +- .../CodeGen/ARM/build-attributes-optimization.ll | 6 +- llvm/test/CodeGen/X86/avx512-cvt.ll | 17 +- llvm/test/CodeGen/X86/avx512-gfni-intrinsics.ll | 144 +-- llvm/test/CodeGen/X86/machine-combiner-int-vec.ll | 117 +- llvm/test/CodeGen/X86/midpoint-int-vec-128.ll | 12 +- llvm/test/CodeGen/X86/midpoint-int-vec-256.ll | 24 +- llvm/test/CodeGen/X86/midpoint-int-vec-512.ll | 84 +- llvm/test/CodeGen/X86/sadd_sat_vec.ll | 57 +- llvm/test/CodeGen/X86/ssub_sat_vec.ll | 57 +- llvm/test/CodeGen/X86/vec_int_to_fp.ll | 16 +- llvm/test/CodeGen/X86/vector-bitreverse.ll | 100 +- llvm/test/CodeGen/X86/vector-fshl-256.ll | 9 +- llvm/test/CodeGen/X86/vector-fshl-512.ll | 56 +- llvm/test/CodeGen/X86/vector-fshl-rot-256.ll | 20 +- llvm/test/CodeGen/X86/vector-fshl-rot-512.ll | 42 +- llvm/test/CodeGen/X86/vector-fshr-256.ll | 29 +- llvm/test/CodeGen/X86/vector-fshr-512.ll | 154 ++- llvm/test/CodeGen/X86/vector-fshr-rot-256.ll | 20 +- llvm/test/CodeGen/X86/vector-fshr-rot-512.ll | 82 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll | 6 +- llvm/test/CodeGen/X86/vector-rotate-128.ll | 77 +- llvm/test/CodeGen/X86/vector-rotate-256.ll | 69 +- llvm/test/CodeGen/X86/vector-rotate-512.ll | 92 +- llvm/test/CodeGen/X86/vector-shift-ashr-128.ll | 3 +- llvm/test/CodeGen/X86/vector-shift-ashr-256.ll | 18 +- llvm/test/CodeGen/X86/vector-shift-ashr-512.ll | 18 +- llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll | 9 +- llvm/test/CodeGen/X86/vector-shuffle-combining.ll | 71 ++ llvm/test/MC/ARM/directive-arch-armv2.s | 2 +- llvm/test/MC/ARM/directive-arch-armv2a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv3.s | 2 +- llvm/test/MC/ARM/directive-arch-armv3m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv4.s | 2 +- llvm/test/MC/ARM/directive-arch-armv4t.s | 2 +- llvm/test/MC/ARM/directive-arch-armv5.s | 2 +- llvm/test/MC/ARM/directive-arch-armv5t.s | 2 +- llvm/test/MC/ARM/directive-arch-armv5te.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6-m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6k.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6t2.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6z.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7-a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7-m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7-r.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7e-m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7em.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7r.s | 2 +- llvm/test/MC/ARM/directive-arch-armv8-a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv8.2-a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv8a.s | 2 +- llvm/test/MC/ARM/directive-arch-iwmmxt.s | 2 +- llvm/test/MC/ARM/directive-arch-iwmmxt2.s | 2 +- .../MC/ARM/directive-eabi_attribute-overwrite.s | 2 +- llvm/test/MC/ARM/directive-eabi_attribute.s | 2 +- llvm/test/MC/ARM/directive-fpu-multiple.s | 2 +- llvm/test/MC/ARM/directive-object_arch-2.s | 2 +- llvm/test/MC/ARM/directive-object_arch.s | 2 +- llvm/test/MC/ELF/undef.s | 22 + llvm/test/MC/ELF/weakref.s | 9 + .../DivRemPairs/X86/div-expanded-rem-pair.ll | 36 + .../SLPVectorizer/AArch64/gather-root.ll | 102 +- .../Transforms/SLPVectorizer/AArch64/horizontal.ll | 16 - .../SLPVectorizer/AArch64/spillcost-di.ll | 4 +- llvm/test/Transforms/SLPVectorizer/X86/PR31847.ll | 153 +++ .../test/Transforms/SLPVectorizer/X86/PR35628_1.ll | 13 +- .../test/Transforms/SLPVectorizer/X86/PR35628_2.ll | 5 - llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll | 72 +- llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll | 16 - .../Transforms/SLPVectorizer/X86/bad-reduction.ll | 28 - .../SLPVectorizer/X86/horizontal-list.ll | 354 +----- .../SLPVectorizer/X86/horizontal-minmax.ll | 476 ++----- .../Transforms/SLPVectorizer/X86/horizontal.ll | 148 --- .../Transforms/SLPVectorizer/X86/long_chains.ll | 8 +- .../SLPVectorizer/X86/reassociated-loads.ll | 31 - .../SLPVectorizer/X86/reduction_loads.ll | 24 - .../SLPVectorizer/X86/reduction_unrolled.ll | 35 +- .../Transforms/SLPVectorizer/X86/remark_horcost.ll | 4 - .../SLPVectorizer/X86/reorder_repeated_ops.ll | 22 - .../Transforms/SLPVectorizer/X86/undef_vect.ll | 10 - .../SLPVectorizer/X86/used-reduced-op.ll | 529 ++++++++ .../SLPVectorizer/X86/vectorize-reorder-reuse.ll | 42 - 134 files changed, 2370 insertions(+), 3498 deletions(-) create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/PR31847.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 1 month

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allyesconfig updated (6650494b -> da6e78be)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards 6650494b 0: update: llvm-linux: 17869 new da6e78be 0: update: llvm-linux: 17869 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (6650494b) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-build_llvm/console.log | 12094 +- 03-build_linux/console.log | 1270656 +++++++++++++++++------------------ 05-check_regression/console.log | 8 +- 06-update_baseline/console.log | 8 +- console.log | 1282926 ++++++++++++++++++------------------ jenkins/manifest.sh | 8 +- 7 files changed, 1282960 insertions(+), 1282960 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 1 month

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig updated (9bc1c6ecc56 -> e794c049b3e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig in repository toolchain/ci/llvm-project. from 9bc1c6ecc56 [cxx_status] Mark P0784R7 as partially complete. adds 120a5e9a745 [ARM] Cortex-M4 schedule additions adds 72b544e656b [PowerPC] Fix conditions of assert in PPCAsmPrinter adds 83476b813e2 [clang-format] Reference qualifiers in member templates cau [...] adds 8b1eeafb913 [SLP] Fix for PR31847: Assertion failed: (isLoopInvariant(O [...] adds d30093bb8a3 [DivRemPairs] Don't assert that we won't ever get expanded- [...] adds c5133606627 [MC] Emit unused undefined symbol even if its binding is not set adds eb78dea4ccd [Docs] Moves article links to new pages adds a6d9d31279c [LLVM-C][Ocaml] Add MergeFunctions and DCE pass adds aabf8cbfca8 Add test case peeking through vector concat when combining [...] adds 0e3f6591371 [X86] Add custom isel logic to match VPTERNLOG from 2 logic ops. adds 00966d1791f Don't crash if a variable with a constexpr destructor has a [...] adds 1069c019241 [X86] Remove -x86-experimental-vector-widening-legalization [...] adds 6c320b22cd2 [X86] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off [...] adds 9a5e3d39f69 Undef the macros after their use adds 1b0ea0a12e7 [X86] Split v16i32/v8i64 bitreverse on avx512f targets with [...] adds 4006434ed1d [ELF][test] Change llvm-readobj --arm-attributes to --arch- [...] adds 34f9e98aaec [test] Change llvm-readobj --arm-attributes to --arch-speci [...] adds 317d991fa51 AMDGPU/GlobalISel: Fix select for v2s16 and/or/xor adds 5951e3f8134 [X86] Remove some redundant isel patterns. NFCI new e794c049b3e [SystemZ] Add SystemZPostRewrite in addPostRegAlloc() inst [...] The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang/lib/Format/TokenAnnotator.cpp | 25 +- clang/lib/Sema/SemaDeclCXX.cpp | 3 +- clang/test/SemaCXX/constant-expression-cxx2a.cpp | 9 + clang/unittests/Format/FormatTest.cpp | 68 + lld/test/ELF/arm-attributes.s | 6 +- lld/test/ELF/ppc64-abs64-dyn.s | 8 +- lld/test/ELF/ppc64-relocs.s | 4 +- llvm/bindings/ocaml/transforms/ipo/ipo_ocaml.c | 6 + llvm/bindings/ocaml/transforms/ipo/llvm_ipo.ml | 3 + llvm/bindings/ocaml/transforms/ipo/llvm_ipo.mli | 5 + .../transforms/scalar_opts/llvm_scalar_opts.ml | 3 + .../transforms/scalar_opts/llvm_scalar_opts.mli | 5 + .../transforms/scalar_opts/scalar_opts_ocaml.c | 5 + llvm/docs/ProgrammingDocumentation.rst | 5 + llvm/docs/Reference.rst | 24 +- llvm/docs/SubsystemDocumentation.rst | 28 +- llvm/docs/_templates/indexsidebar.html | 2 + llvm/docs/index.rst | 3 - llvm/include/llvm-c/Transforms/IPO.h | 3 + llvm/include/llvm-c/Transforms/Scalar.h | 3 + llvm/include/llvm/MC/MCLinkerOptimizationHint.h | 2 + .../llvm/Transforms/Vectorize/SLPVectorizer.h | 9 +- llvm/lib/MC/ELFObjectWriter.cpp | 3 - llvm/lib/Target/AMDGPU/VOP2Instructions.td | 32 +- llvm/lib/Target/ARM/ARMInstrFormats.td | 1 + llvm/lib/Target/ARM/ARMInstrInfo.td | 18 +- llvm/lib/Target/ARM/ARMInstrThumb2.td | 3 +- llvm/lib/Target/ARM/ARMInstrVFP.td | 11 +- llvm/lib/Target/ARM/ARMScheduleM4.td | 24 +- llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp | 2 +- llvm/lib/Target/SystemZ/SystemZTargetMachine.cpp | 5 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 80 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 1330 +++----------------- llvm/lib/Target/X86/X86InstrAVX512.td | 78 -- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 86 +- llvm/lib/Transforms/IPO/IPO.cpp | 4 + llvm/lib/Transforms/Scalar/DivRemPairs.cpp | 2 - llvm/lib/Transforms/Scalar/Scalar.cpp | 4 + llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 152 ++- .../CodeGen/AMDGPU/GlobalISel/inst-select-and.mir | 30 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-or.mir | 30 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir | 30 +- .../CodeGen/ARM/ParallelDSP/complex_dot_prod.ll | 6 +- .../CodeGen/ARM/ParallelDSP/multi-use-loads.ll | 52 +- .../CodeGen/ARM/ParallelDSP/unroll-n-jam-smlad.ll | 1 - .../ARM/build-attributes-optimization-minsize.ll | 6 +- .../ARM/build-attributes-optimization-mixed.ll | 6 +- .../ARM/build-attributes-optimization-optnone.ll | 6 +- .../ARM/build-attributes-optimization-optsize.ll | 6 +- .../CodeGen/ARM/build-attributes-optimization.ll | 6 +- llvm/test/CodeGen/SystemZ/cond-move-09.mir | 29 + llvm/test/CodeGen/X86/avx512-cvt.ll | 17 +- llvm/test/CodeGen/X86/avx512-gfni-intrinsics.ll | 144 +-- llvm/test/CodeGen/X86/machine-combiner-int-vec.ll | 117 +- llvm/test/CodeGen/X86/midpoint-int-vec-128.ll | 12 +- llvm/test/CodeGen/X86/midpoint-int-vec-256.ll | 24 +- llvm/test/CodeGen/X86/midpoint-int-vec-512.ll | 84 +- llvm/test/CodeGen/X86/sadd_sat_vec.ll | 57 +- llvm/test/CodeGen/X86/ssub_sat_vec.ll | 57 +- llvm/test/CodeGen/X86/vec_int_to_fp.ll | 16 +- llvm/test/CodeGen/X86/vector-bitreverse.ll | 100 +- llvm/test/CodeGen/X86/vector-fshl-256.ll | 9 +- llvm/test/CodeGen/X86/vector-fshl-512.ll | 56 +- llvm/test/CodeGen/X86/vector-fshl-rot-256.ll | 20 +- llvm/test/CodeGen/X86/vector-fshl-rot-512.ll | 42 +- llvm/test/CodeGen/X86/vector-fshr-256.ll | 29 +- llvm/test/CodeGen/X86/vector-fshr-512.ll | 154 ++- llvm/test/CodeGen/X86/vector-fshr-rot-256.ll | 20 +- llvm/test/CodeGen/X86/vector-fshr-rot-512.ll | 82 +- llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll | 6 +- llvm/test/CodeGen/X86/vector-rotate-128.ll | 77 +- llvm/test/CodeGen/X86/vector-rotate-256.ll | 69 +- llvm/test/CodeGen/X86/vector-rotate-512.ll | 92 +- llvm/test/CodeGen/X86/vector-shift-ashr-128.ll | 3 +- llvm/test/CodeGen/X86/vector-shift-ashr-256.ll | 18 +- llvm/test/CodeGen/X86/vector-shift-ashr-512.ll | 18 +- llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll | 9 +- llvm/test/CodeGen/X86/vector-shuffle-combining.ll | 71 ++ llvm/test/MC/ARM/directive-arch-armv2.s | 2 +- llvm/test/MC/ARM/directive-arch-armv2a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv3.s | 2 +- llvm/test/MC/ARM/directive-arch-armv3m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv4.s | 2 +- llvm/test/MC/ARM/directive-arch-armv4t.s | 2 +- llvm/test/MC/ARM/directive-arch-armv5.s | 2 +- llvm/test/MC/ARM/directive-arch-armv5t.s | 2 +- llvm/test/MC/ARM/directive-arch-armv5te.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6-m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6k.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6t2.s | 2 +- llvm/test/MC/ARM/directive-arch-armv6z.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7-a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7-m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7-r.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7e-m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7em.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7m.s | 2 +- llvm/test/MC/ARM/directive-arch-armv7r.s | 2 +- llvm/test/MC/ARM/directive-arch-armv8-a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv8.2-a.s | 2 +- llvm/test/MC/ARM/directive-arch-armv8a.s | 2 +- llvm/test/MC/ARM/directive-arch-iwmmxt.s | 2 +- llvm/test/MC/ARM/directive-arch-iwmmxt2.s | 2 +- .../MC/ARM/directive-eabi_attribute-overwrite.s | 2 +- llvm/test/MC/ARM/directive-eabi_attribute.s | 2 +- llvm/test/MC/ARM/directive-fpu-multiple.s | 2 +- llvm/test/MC/ARM/directive-object_arch-2.s | 2 +- llvm/test/MC/ARM/directive-object_arch.s | 2 +- llvm/test/MC/ELF/undef.s | 22 + llvm/test/MC/ELF/weakref.s | 9 + .../DivRemPairs/X86/div-expanded-rem-pair.ll | 36 + .../SLPVectorizer/AArch64/gather-root.ll | 102 +- .../Transforms/SLPVectorizer/AArch64/horizontal.ll | 16 - .../SLPVectorizer/AArch64/spillcost-di.ll | 4 +- llvm/test/Transforms/SLPVectorizer/X86/PR31847.ll | 153 +++ .../test/Transforms/SLPVectorizer/X86/PR35628_1.ll | 13 +- .../test/Transforms/SLPVectorizer/X86/PR35628_2.ll | 5 - llvm/test/Transforms/SLPVectorizer/X86/PR39774.ll | 72 +- llvm/test/Transforms/SLPVectorizer/X86/PR40310.ll | 16 - .../Transforms/SLPVectorizer/X86/bad-reduction.ll | 28 - .../SLPVectorizer/X86/horizontal-list.ll | 354 +----- .../SLPVectorizer/X86/horizontal-minmax.ll | 476 ++----- .../Transforms/SLPVectorizer/X86/horizontal.ll | 148 --- .../Transforms/SLPVectorizer/X86/long_chains.ll | 8 +- .../SLPVectorizer/X86/reassociated-loads.ll | 31 - .../SLPVectorizer/X86/reduction_loads.ll | 24 - .../SLPVectorizer/X86/reduction_unrolled.ll | 35 +- .../Transforms/SLPVectorizer/X86/remark_horcost.ll | 4 - .../SLPVectorizer/X86/reorder_repeated_ops.ll | 22 - .../Transforms/SLPVectorizer/X86/undef_vect.ll | 10 - .../SLPVectorizer/X86/used-reduced-op.ll | 529 ++++++++ .../SLPVectorizer/X86/vectorize-reorder-reuse.ll | 42 - 135 files changed, 2402 insertions(+), 3498 deletions(-) create mode 100644 llvm/test/CodeGen/SystemZ/cond-move-09.mir create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/PR31847.ll create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/used-reduced-op.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig updated (f7a9227e -> fb5717a4)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allmodconfig in repository toolchain/ci/base-artifacts. discards f7a9227e 0: update: llvm-linux: 19650 new fb5717a4 0: update: llvm-linux: 19650 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (f7a9227e) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 68 +- 02-build_llvm/console.log | 12176 +- 03-build_linux/console.log | 1506496 ++++++++++++++++++------------------ console.log | 1518724 ++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 5 files changed, 1518736 insertions(+), 1518736 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-defconfig updated (49f75e008c0 -> 70f0835d2a9)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-defconfig in repository toolchain/ci/gcc. from 49f75e008c0 This patch is to add the support for float from/to long con [...] adds 56f22142aba gcc/ChangeLog adds e9eb6ea5605 PR bootstrap/90543 * optc-save-gen.awk: Fix up printing s [...] adds e020479cd65 2019-09-29 Paul Thomas <pault(a)gcc.gnu.org> adds a3310563550 2019-09-29 Steven G. Kargl <kargl(a)gcc.gnu.org> adds 0c7c01cf936 [Darwin, PPC, Mode Iterators 5/n] Update macho_low. adds ef6064d4ff4 2019-09-29 Steven G. Kargl <kargl(a)gcc.gnu.org> adds ed76597323f Daily bump. adds 70f0835d2a9 PR target/91931 * config/i386/i386-expand.c (ix86_expand_ [...] No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 26 ++++++++++++++++++ gcc/DATESTAMP | 2 +- gcc/config/darwin.c | 4 +-- gcc/config/i386/i386-expand.c | 2 +- gcc/config/rs6000/darwin.md | 29 +++----------------- gcc/config/rs6000/rs6000.c | 8 ++++-- gcc/fortran/ChangeLog | 30 +++++++++++++++++++- gcc/fortran/check.c | 9 +++++- gcc/fortran/decl.c | 22 +++++++++++++-- gcc/fortran/resolve.c | 4 +++ gcc/fortran/trans-array.c | 3 +- gcc/fortran/trans-expr.c | 23 ++++++++++++++-- gcc/fortran/trans-stmt.c | 36 ++++++++++++++++++++++++ gcc/fortran/trans.h | 1 + gcc/optc-save-gen.awk | 2 +- gcc/testsuite/ChangeLog | 21 ++++++++++++++ gcc/testsuite/gcc.target/i386/pr91931.c | 5 ++++ gcc/testsuite/gfortran.dg/coarray_poly_9.f90 | 38 ++++++++++++++++++++++++++ gcc/testsuite/gfortran.dg/dec_type_print_3.f90 | 4 +-- gcc/testsuite/gfortran.dg/pr91641.f90 | 7 +++++ gcc/testsuite/gfortran.dg/pr91714.f90 | 10 +++++++ 21 files changed, 244 insertions(+), 42 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr91931.c create mode 100644 gcc/testsuite/gfortran.dg/coarray_poly_9.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr91641.f90 create mode 100644 gcc/testsuite/gfortran.dg/pr91714.f90 -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-defconfig updated (612aac65e6 -> 663f67df1e)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-defconfig in repository toolchain/ci/binutils-gdb. from 612aac65e6 Automatic date update in version.in adds 73d9a918c6 [gdb/testsuite] Make pass message unique in gdb-index.exp fo [...] adds 0df0352ad0 [gdb/contrib] cc-with-tweaks.sh: Create .dwz file in .tmp subdir adds 0925bc8441 Automatic date update in version.in adds 663f67df1e PR25046, readelf "Reading xxx bytes extends past end of file [...] No new revisions were added by this update. Summary of changes: bfd/version.h | 2 +- binutils/ChangeLog | 6 ++++++ binutils/readelf.c | 6 +++--- gdb/ChangeLog | 6 ++++++ gdb/contrib/cc-with-tweaks.sh | 16 ++++++++++++---- gdb/testsuite/ChangeLog | 8 ++++++++ gdb/testsuite/gdb.dwarf2/gdb-index.exp | 24 ++++++++++++++---------- 7 files changed, 50 insertions(+), 18 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-defconfig updated (55f51c5e -> 801fdb33)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-stable-defconfig in repository toolchain/ci/base-artifacts. discards 55f51c5e 0: update: binutils-gcc-linux: boot new 801fdb33 0: update: binutils-gcc-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (55f51c5e) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 182 +- 02-prepare_abe/console.log | 120 +- 03-build_abe-binutils/console.log | 10794 +++++++------- 04-build_abe-stage1/console.log | 15616 ++++++++++---------- 05-build_linux/console.log | 746 +- 06-boot_linux/console.log | 436 +- 07-check_regression/console.log | 8 +- 08-update_baseline/console.log | 8 +- console.log | 28012 ++++++++++++++++++------------------ jenkins/manifest.sh | 12 +- 10 files changed, 27957 insertions(+), 27977 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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