Tcwg-commits September 2019

tcwg-commits@lists.linaro.org

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14312 discussions

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-next-defconfig updated (c168b4b2a96 -> 5cbaa56ac5f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-next-defconfig in repository toolchain/ci/llvm-project. from c168b4b2a96 Fix release notes for the MinGW frontend adds 7b927f75f22 Merging r369705 and r369713 for PR43243: adds 9523a1c62d0 Merging r371262: ------------------------------------------ [...] adds 8cdf289f45f Merging r371111: ------------------------------------------ [...] adds 1c21c1972f9 Merging r371305 and r371307: adds b508b4ba067 Merging r371221 and r371224: adds 5cbaa56ac5f Merging r370592: ------------------------------------------ [...] No new revisions were added by this update. Summary of changes: clang/lib/CodeGen/CodeGenModule.cpp | 13 +++-- clang/test/CodeGen/alias.c | 11 ++++ llvm/include/llvm/IR/Instructions.h | 13 +++-- llvm/lib/CodeGen/IfConversion.cpp | 10 +++- llvm/lib/IR/Instructions.cpp | 11 ++++ llvm/lib/Target/X86/X86ISelLowering.cpp | 29 ++++++----- llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp | 4 +- .../ARM/ifcvt-diamond-unanalyzable-common.mir | 58 +++++++++++++++++++++ llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll | 41 +++++++++++++++ llvm/test/CodeGen/X86/vector-shuffle-avx512.ll | 38 ++++++++++++++ llvm/test/Transforms/InstCombine/pow-0.ll | 60 ++++++++++++++++++++++ llvm/test/Transforms/InstCombine/pow-4.ll | 10 ++++ llvm/unittests/IR/InstructionsTest.cpp | 51 ++++++++++++++++++ 13 files changed, 324 insertions(+), 25 deletions(-) create mode 100644 llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir create mode 100644 llvm/test/Transforms/InstCombine/pow-0.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-next-defconfig updated (36b9f5acc -> 926a5142e)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-next-defconfig in repository toolchain/ci/base-artifacts. discards 36b9f5acc 0: update: llvm-linux: boot new 926a5142e 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (36b9f5acc) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-arm- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 193 +- 02-build_llvm/console.log | 11964 +++++++++++++++++----------------- 03-build_linux/console.log | 676 +- 04-boot_linux/console.log | 480 +- 05-check_regression/console.log | 8 +- 06-update_baseline/console.log | 8 +- console.log | 13329 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 13324 insertions(+), 13342 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allnoconfig updated (c168b4b2a96 -> 5cbaa56ac5f)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allnoconfig in repository toolchain/ci/llvm-project. from c168b4b2a96 Fix release notes for the MinGW frontend adds 7b927f75f22 Merging r369705 and r369713 for PR43243: adds 9523a1c62d0 Merging r371262: ------------------------------------------ [...] adds 8cdf289f45f Merging r371111: ------------------------------------------ [...] adds 1c21c1972f9 Merging r371305 and r371307: adds b508b4ba067 Merging r371221 and r371224: adds 5cbaa56ac5f Merging r370592: ------------------------------------------ [...] No new revisions were added by this update. Summary of changes: clang/lib/CodeGen/CodeGenModule.cpp | 13 +++-- clang/test/CodeGen/alias.c | 11 ++++ llvm/include/llvm/IR/Instructions.h | 13 +++-- llvm/lib/CodeGen/IfConversion.cpp | 10 +++- llvm/lib/IR/Instructions.cpp | 11 ++++ llvm/lib/Target/X86/X86ISelLowering.cpp | 29 ++++++----- llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp | 4 +- .../ARM/ifcvt-diamond-unanalyzable-common.mir | 58 +++++++++++++++++++++ llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll | 41 +++++++++++++++ llvm/test/CodeGen/X86/vector-shuffle-avx512.ll | 38 ++++++++++++++ llvm/test/Transforms/InstCombine/pow-0.ll | 60 ++++++++++++++++++++++ llvm/test/Transforms/InstCombine/pow-4.ll | 10 ++++ llvm/unittests/IR/InstructionsTest.cpp | 51 ++++++++++++++++++ 13 files changed, 324 insertions(+), 25 deletions(-) create mode 100644 llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir create mode 100644 llvm/test/Transforms/InstCombine/pow-0.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allnoconfig updated (8bebb9f58 -> b21e65359)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-aarch64-lts-allnoconfig in repository toolchain/ci/base-artifacts. discards 8bebb9f58 0: update: llvm-linux: boot new b21e65359 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (8bebb9f58) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-aarc [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 186 +- 02-build_llvm/console.log | 12082 +++++++++++++++++------------------ 03-build_linux/console.log | 814 +-- 05-check_regression/console.log | 8 +- 06-update_baseline/console.log | 25 - console.log | 13115 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 7 files changed, 13104 insertions(+), 13134 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-allmodconfig updated (e2b06c85d -> 33c8b36ad)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-allmodconfig in repository toolchain/ci/base-artifacts. discards e2b06c85d 2: update: binutils-6715fe29ffcdbef026908fed62e993b238d04d77: 18886 new 33c8b36ad 2: update: linux-35394d031b710e832849fca60d0f53b513f0c390: 18886 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (e2b06c85d) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 183 +- 02-prepare_abe/console.log | 260 +- 03-build_abe-binutils/console.log | 11359 ++++++++------- 04-build_abe-stage1/console.log | 14505 ++++++++++--------- 05-build_linux/console.log | 688 +- 07-check_regression/console.log | 8 +- 08-update_baseline/console.log | 56 +- console.log | 26863 ++++++++++++++++++------------------ jenkins/manifest.sh | 6 +- 9 files changed, 26713 insertions(+), 27215 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[llvm] branch master updated (7d3778229e9 -> 2cfa868dbfd)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 7d3778229e9 AMDGPU: Make VReg_1 size be 1 new 2cfa868dbfd AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR v2s16 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 21 +++-- lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 77 +++++++++++------ .../regbankselect-build-vector.v2s16.mir | 99 ++++++++++++++++++++++ 3 files changed, 163 insertions(+), 34 deletions(-) create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.v2s16.mir -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[compiler-rt] branch master updated (111bf961e -> a5142c0c4)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository compiler-rt. from 111bf961e compiler-rt: use fp_t instead of long double, for consistency new a5142c0c4 [TSan] Add interceptors for mach_vm_[de]allocate The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/tsan/CMakeLists.txt | 1 + lib/tsan/rtl/tsan_interceptors.cpp | 14 ++---- lib/tsan/rtl/tsan_interceptors_mach_vm.cpp | 52 +++++++++++++++++++++ lib/tsan/rtl/tsan_rtl.cpp | 17 +++++++ lib/tsan/rtl/tsan_rtl.h | 3 ++ test/tsan/Darwin/mach_vm_allocate.c | 73 ++++++++++++++++++++++++++++++ 6 files changed, 150 insertions(+), 10 deletions(-) create mode 100644 lib/tsan/rtl/tsan_interceptors_mach_vm.cpp create mode 100644 test/tsan/Darwin/mach_vm_allocate.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[llvm] branch master updated (6d85c15b5ff -> 7d3778229e9)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 6d85c15b5ff AMDGPU/GlobalISel: Select llvm.amdgcn.class new 7d3778229e9 AMDGPU: Make VReg_1 size be 1 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Target/AMDGPU/SILowerI1Copies.cpp | 11 +++++++++- lib/Target/AMDGPU/SIRegisterInfo.cpp | 9 +++++--- lib/Target/AMDGPU/SIRegisterInfo.td | 2 +- .../AMDGPU/coalescer-extend-pruned-subrange.mir | 6 +++--- .../coalescer-subranges-another-prune-error.mir | 24 +++++++++++----------- .../coalescer-with-subregs-bad-identical.mir | 6 +++--- 6 files changed, 35 insertions(+), 23 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 10 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allnoconfig updated (64965430db5 -> c195bde3d4d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allnoconfig in repository toolchain/ci/llvm-project. from 64965430db5 [NFC][InstSimplify] Some tests for dropping null check afte [...] adds aff5bee35fb [InstCombine] fold extract+insert into identity shuffle adds 080ecafdd8b Move prop-sink branch to monorepo. adds 30837abd962 [X86] Teach materializeVectorConstant to not call getZeroVe [...] adds dac34f52d3f [DAGCombiner][X86][ARM] Teach visitMULO to fold multiplies [...] adds 97d41b89174 [X86] Use DAG.getConstant instead of getZeroVector in combi [...] adds 94db67f0e1c [X86] X86DAGToDAGISel::combineIncDecVector(): call getSplat [...] adds 354a46444ce [InstCombine] add tests for icmp with srem operand; NFC adds 6e2c5c87103 [InstSimplify] simplifyUnsignedRangeCheck(): if we know tha [...] adds 9c119012566 [X86] Remove call to getZeroVector from materializeVectorCo [...] adds 77dd86ee4aa [X86] Add a hack to combineVSelectWithAllOnesOrZeros to tur [...] adds 139a9d6c0e0 [InstCombine][NFC] Some tests for usub overflow+nonzero che [...] adds e0ea746215c [X86][SSE] SimplifyDemandedVectorEltsForTargetNode - add fa [...] adds dd0c00b5f8b Enable LSan for NetBSD/i386 in test/asan/lit.cfg.py adds debac75deae Relax opcode checks in test to check for only a number inst [...] adds 861d3439493 [X86] Add avx and avx512f RUN lines to fp128-cast.ll adds 72624b0e59d [X86] Use xorps to create fp128 +0.0 constants. adds fb1e77505ae [X86] Add test cases for fptoui/fptosi/sitofp/uitofp betwee [...] adds 9115c477bb6 [MachineCopyPropagation] Remove redundant copies after Tail [...] adds 197901081bc [X86] Add fp128 test cases for ceil/floor/trunc/nearbyint/r [...] adds 88796a79885 [ELF][test] Improve and reorganize another set of tests adds 8d42a796c2a [X86] Add broadcast load unfolding tests for vmaxps/pd and [...] adds ad7822329fd [X86] Add broadcast load unfolding support for VMAXPS/PD an [...] adds acc95714062 AMDGPU: Remove pointless wrapper nodes for init.exec intrinsics adds 68b2e1973fc [X86] Add broadcast load unfolding tests for smin/umin/smax/smin. adds 8c2ab1c4cbc [X86] Add broadcast load unfold support for smin/umin/smax/umax. adds 667f039c8ca [X86] Add broadcast load unfolding tests for vpcmpeq/vpcmpg [...] adds a88f58ff0e8 [X86] Add broadcast load unfolding support for vpcmpeq/vpcm [...] adds ca6f4522992 [SystemZ] NFC: use clearRegisterDeads() in SystemZElimCompare.cpp adds c363deb5750 [ARM][ParallelDSP] Fix for sext input adds ad3841fcae6 [clangd] Improve output of semantic highlighting tests in c [...] adds 6b9aedaec68 [ARM][MVE] Decoding of uqrshl and sqrshl accepts unpredicta [...] adds 63d5d162377 [clangd] Replace HighlightingKind::NumKinds with LastKind. NFC adds d5588293a8c [clangd] Highlight typedefs to template parameters as templ [...] adds 3212ecfea8c [lib/ObjectYAML] - Improve and cleanup error reporting in E [...] adds c11af417e0d [yaml2obj] - Fix BB after r371380 adds 36147adc0b1 GlobalISel: add combiner to form indexed loads. adds 06d93e0a25d GlobalISel: fix unused warnings in release builds. adds d936a6301bd [ARM] Prevent generating NEON stack accesses under MVE. adds 55244beeee8 [AArch64][SVE] Implement abs and neg intrinsics adds 298c7a09de3 [ELF][AArch64] Apply some NFC cleanups to AArch64ErrataFix.cpp adds 7c5697c8b24 [clangd] Update clangd-vscode docs to be more user-focused. adds 5b270932cc6 [clangd] Support multifile edits as output of Tweaks adds 462e3d8050f Revert rL371198 from llvm/trunk: [DFAPacketizer] Track reso [...] adds ff354de2944 [clang-doc] sys::fs::F_None -> OF_None. NFC adds 1ad508e8e2d [ARM][MVE] VCTP instruction selection adds f9ce864558a [clang-tidy] Fix bug in bugprone-use-after-move check adds 388b9794b61 [Inliner][NFC] Make test less brittle. adds e8c0d933603 [ELF] nmagic or omagic: don't allocate PT_PHDR or PF_R PT_L [...] adds b6c7fce67ad [DFAPacketizer] Reapply: Track resources for packetized ins [...] adds 1a3dd638c4a compiler-rt: use fp_t instead of long double, for consistency adds 59608c00495 [NFC][InstCombine] Fixup test i added in rL371352. adds e237520a8f5 [clangd] Add a new highlighting kind for typedefs adds 783fc95f3ee Merge note_ovl_builtin_candidate diagnostics; NFC adds 508dff2ce15 AMDGPU/GlobalISel: Remove dead patterns adds 0e48bd24e21 [ARM] Remove some spurious MVE reduction instructions. adds d50f937378c AMDGPU/GlobalISel: Try generated matcher before add/sub code adds 8e3bc9b5722 AMDGPU/GlobalISel: Legalize wavefrontsize intrinsic adds 8b76709bac3 [clangd] Use pre-populated mappings for standard symbols adds 2dd088ec7d8 AMDGPU/GlobalISel: Use known bits for selection adds 3c8644666c4 [NFC] Add aacps bitfields access test adds fdb70301172 AMDGPU/GlobalISel: Fix reg bank for uniform LDS loads adds c34b4036ffe AMDGPU/GlobalISel: Select G_PTR_MASK adds ebbd6e49768 AMDGPU: Remove code address space predicates adds 02eb308387d AMDGPU/GlobalISel: Fix regbankselect for uniform extloads adds 9ede7c03956 Fix typo in comment noticed in D60295. NFCI. adds d8409b178ed AMDGPU/GlobalISel: Fix RegBankSelect for unaligned, uniform [...] adds f707dac742f LLDB - Simplify GetProgramFileSpec adds 63e6d8db1cb AMDGPU/GlobalISel: Select atomic loads adds 2b7089949ed [ARM] Fix loads and stores for predicate vectors adds c28f3e6e2c3 [yaml2obj] Simplify p_filesz/p_memsz computing adds d9c4060bd5c Revert "[MachineCopyPropagation] Remove redundant copies af [...] adds 6d7fba6aae2 [clangd] Attempt to fix failing Windows buildbots. adds 182f9248e8f AMDGPU/GlobalISel: Legalize G_BUILD_VECTOR_TRUNC adds 64ecca90d42 AMDGPU/GlobalISel: Implement LDS G_GLOBAL_VALUE adds bfb00e3d536 [GlobalISel][AArch64] Handle tail calls with non-void return types adds c0728eac15b [SLP] add test for over-vectorization (PR33958); NFC adds d2a9516a6d0 AMDGPU: Move MnemonicAlias out of instruction def hierarchy adds 56e4ea2bff9 [mips] Fix decoding of microMIPS JALX instruction adds a85d9ef11ae [Remarks] Add parser for bitstream remarks adds ce2cb0f09e7 [X86] Allow _MM_FROUND_CUR_DIRECTION and _MM_FROUND_NO_EXC [...] adds 5ebd0a6e88a [SelectionDAG] Remove ISD::FP_ROUND_INREG new 6ebf605851d AMDGPU: Use PatFrags to allow selecting custom nodes or intrinsics new c195bde3d4d [x86] add test for false dependency with minsize (PR43239); NFC The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang-tools-extra/clang-doc/HTMLGenerator.cpp | 4 +- clang-tools-extra/clang-doc/tool/ClangDocMain.cpp | 2 +- .../clang-tidy/utils/ExprSequence.cpp | 17 +- clang-tools-extra/clangd/ClangdLSPServer.cpp | 61 +- clang-tools-extra/clangd/ClangdServer.cpp | 50 +- clang-tools-extra/clangd/ParsedAST.cpp | 2 +- clang-tools-extra/clangd/Preamble.cpp | 2 +- clang-tools-extra/clangd/SemanticHighlighting.cpp | 84 +- clang-tools-extra/clangd/SemanticHighlighting.h | 5 +- clang-tools-extra/clangd/SourceCode.cpp | 62 +- clang-tools-extra/clangd/SourceCode.h | 28 +- .../clangd-vscode/{README.md => DEVELOPING.md} | 44 +- .../clangd/clients/clangd-vscode/README.md | 134 +- .../clients/clangd-vscode/doc-assets/complete.png | Bin 0 -> 45024 bytes .../clangd-vscode/doc-assets/diagnostics.png | Bin 0 -> 29566 bytes .../clients/clangd-vscode/doc-assets/extract.png | Bin 0 -> 21101 bytes .../clients/clangd-vscode/doc-assets/format.png | Bin 0 -> 23948 bytes .../clients/clangd-vscode/doc-assets/include.png | Bin 0 -> 21077 bytes .../clangd-vscode/doc-assets/symbolsearch.png | Bin 0 -> 29427 bytes .../clients/clangd-vscode/doc-assets/xrefs.png | Bin 0 -> 114451 bytes .../clangd/index/CanonicalIncludes.cpp | 84 +- clang-tools-extra/clangd/index/CanonicalIncludes.h | 43 +- clang-tools-extra/clangd/index/IndexAction.cpp | 2 +- clang-tools-extra/clangd/refactor/Tweak.cpp | 29 + clang-tools-extra/clangd/refactor/Tweak.h | 29 +- .../refactor/tweaks/AnnotateHighlightings.cpp | 6 +- .../clangd/refactor/tweaks/ExpandAutoType.cpp | 2 +- .../clangd/refactor/tweaks/ExpandMacro.cpp | 10 +- .../clangd/refactor/tweaks/ExtractFunction.cpp | 2 +- .../clangd/refactor/tweaks/ExtractVariable.cpp | 2 +- .../clangd/refactor/tweaks/RawStringLiteral.cpp | 6 +- .../clangd/refactor/tweaks/SwapIfBranches.cpp | 2 +- .../clangd/test/semantic-highlighting.test | 11 +- .../clangd/unittests/CanonicalIncludesTests.cpp | 28 +- .../clangd/unittests/SemanticHighlightingTests.cpp | 60 +- .../clangd/unittests/SymbolCollectorTests.cpp | 2 +- .../clangd/unittests/TweakTesting.cpp | 20 +- clang-tools-extra/clangd/unittests/TweakTests.cpp | 32 + .../test/clang-tidy/bugprone-use-after-move.cpp | 34 +- clang/include/clang/Basic/DiagnosticSemaKinds.td | 5 +- clang/lib/Sema/SemaChecking.cpp | 4 +- clang/lib/Sema/SemaOverload.cpp | 4 +- .../Checkers/GenericTaintChecker.cpp | 94 +- clang/test/Analysis/taint-generic.c | 42 + clang/test/CodeGen/aapcs-bitfield.c | 824 ++++++++ clang/test/Sema/builtins-x86.c | 13 + compiler-rt/lib/builtins/addtf3.c | 2 +- compiler-rt/lib/builtins/divtf3.c | 2 +- compiler-rt/lib/builtins/extenddftf2.c | 2 +- compiler-rt/lib/builtins/extendsftf2.c | 2 +- compiler-rt/test/asan/lit.cfg.py | 2 +- lld/ELF/AArch64ErrataFix.cpp | 20 +- lld/ELF/Writer.cpp | 39 +- lld/test/ELF/Inputs/canonical-plt-pcrel.s | 5 + lld/test/ELF/Inputs/copy-rel-pie.s | 12 - lld/test/ELF/Inputs/copy-rel.s | 11 + lld/test/ELF/Inputs/gnu-ifunc-dso.s | 4 +- lld/test/ELF/Inputs/gnu-ifunc-gotpcrel.s | 4 - lld/test/ELF/Inputs/protected-function-access.s | 5 - lld/test/ELF/Inputs/startstop-shared2.s | 2 - lld/test/ELF/{plt-aarch64.s => aarch64-plt.s} | 0 lld/test/ELF/canonical-plt-pcrel.s | 33 + lld/test/ELF/canonical-plt-symbolic.s | 24 + lld/test/ELF/compatible-section-types.s | 26 +- lld/test/ELF/copy-rel-pie.s | 30 - lld/test/ELF/copy-rel-pie2.s | 13 - lld/test/ELF/copy-rel.s | 25 + lld/test/ELF/dynsym-pie.s | 8 +- lld/test/ELF/emit-relocs-shared.s | 16 - lld/test/ELF/executable-undefined-ignoreall.s | 15 +- lld/test/ELF/gc-sections-local-sym.s | 5 +- lld/test/ELF/global-offset-table-position.s | 8 +- lld/test/ELF/gnu-ifunc-dso.s | 20 +- lld/test/ELF/gnu-ifunc-gotpcrel.s | 14 - lld/test/ELF/{plt-i686.s => i386-plt.s} | 0 lld/test/ELF/linkerscript/symbol-reserved.s | 3 + lld/test/ELF/magic-page-combo-warn.s | 12 +- lld/test/ELF/merge-section-types.s | 20 - lld/test/ELF/mips-micro-cross-calls.s | 4 +- lld/test/ELF/nmagic.s | 12 +- lld/test/ELF/protected-data-access.s | 7 +- lld/test/ELF/protected-function-access.s | 13 +- lld/test/ELF/relro-omagic.s | 24 +- lld/test/ELF/relro-tls.s | 1 + lld/test/ELF/segments.s | 12 +- lld/test/ELF/startstop-gccollect.s | 8 +- lld/test/ELF/startstop-shared2.s | 9 +- lld/test/ELF/symbol-ordering-file.s | 8 +- lld/test/ELF/tls-opt.s | 46 +- lld/test/ELF/typed-undef.s | 11 - ...ptible.s => version-script-local-preemptible.s} | 8 +- lld/test/ELF/{pie-weak.s => weak-undef-got-pie.s} | 12 +- lld/test/ELF/wrap-entry.s | 8 +- lld/test/ELF/wrap-no-real.s | 4 +- lld/test/ELF/wrap-plt.s | 26 +- lld/test/ELF/{plt.s => x86-64-plt.s} | 0 lld/test/ELF/x86-64-reloc-size-shared.s | 57 +- lldb/source/Host/freebsd/HostInfoFreeBSD.cpp | 11 +- llvm/docs/ReleaseNotes.rst | 2 + llvm/include/llvm-c/Remarks.h | 17 +- llvm/include/llvm/Bitstream/BitstreamReader.h | 1 + llvm/include/llvm/CodeGen/DFAPacketizer.h | 6 +- .../llvm/CodeGen/GlobalISel/CombinerHelper.h | 63 +- llvm/include/llvm/CodeGen/ISDOpcodes.h | 7 - llvm/include/llvm/CodeGen/SwitchLoweringUtils.h | 2 +- llvm/include/llvm/CodeGen/TargetLowering.h | 8 + llvm/include/llvm/IR/IntrinsicsAArch64.td | 23 +- llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 1 + llvm/include/llvm/Remarks/BitstreamRemarkParser.h | 116 ++ llvm/include/llvm/Support/TargetOpcodes.def | 12 + llvm/include/llvm/Target/GenericOpcodes.td | 35 + .../llvm/Target/GlobalISel/SelectionDAGCompat.td | 6 + llvm/lib/Analysis/InstructionSimplify.cpp | 33 +- llvm/lib/CodeGen/DFAPacketizer.cpp | 8 +- llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp | 222 +- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 40 +- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 14 - .../lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp | 4 - .../CodeGen/SelectionDAG/LegalizeVectorTypes.cpp | 3 - llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 20 +- .../CodeGen/SelectionDAG/SelectionDAGDumper.cpp | 1 - llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 2 +- llvm/lib/ObjectYAML/ELFEmitter.cpp | 337 ++- llvm/lib/Remarks/BitstreamRemarkParser.cpp | 586 ++++++ llvm/lib/Remarks/BitstreamRemarkParser.h | 83 + llvm/lib/Remarks/CMakeLists.txt | 1 + llvm/lib/Remarks/LLVMBuild.txt | 2 +- llvm/lib/Remarks/RemarkParser.cpp | 16 +- llvm/lib/Target/AArch64/AArch64.h | 2 +- llvm/lib/Target/AArch64/AArch64CallLowering.cpp | 24 +- .../Target/AArch64/AArch64PreLegalizerCombiner.cpp | 37 +- llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td | 4 +- llvm/lib/Target/AArch64/AArch64TargetMachine.cpp | 3 +- llvm/lib/Target/AArch64/SVEInstrFormats.td | 16 +- llvm/lib/Target/AMDGPU/AMDGPUGISel.td | 28 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 4 +- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 3 +- llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td | 58 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 84 +- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 1 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 61 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 3 + llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 85 +- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h | 4 + llvm/lib/Target/AMDGPU/DSInstructions.td | 4 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 8 - llvm/lib/Target/AMDGPU/SIInstrInfo.td | 68 +- llvm/lib/Target/AMDGPU/SIInstructions.td | 13 +- llvm/lib/Target/AMDGPU/VOP1Instructions.td | 7 + llvm/lib/Target/AMDGPU/VOP2Instructions.td | 6 +- llvm/lib/Target/AMDGPU/VOP3Instructions.td | 25 +- llvm/lib/Target/AMDGPU/VOPInstructions.td | 11 +- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 12 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 65 + llvm/lib/Target/ARM/ARMInstrMVE.td | 188 +- llvm/lib/Target/ARM/ARMParallelDSP.cpp | 12 +- .../Target/ARM/Disassembler/ARMDisassembler.cpp | 6 + .../Target/Mips/Disassembler/MipsDisassembler.cpp | 16 + llvm/lib/Target/Mips/MicroMipsInstrInfo.td | 9 +- llvm/lib/Target/PowerPC/PPCISelLowering.cpp | 1 - llvm/lib/Target/SystemZ/SystemZElimCompare.cpp | 7 +- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp | 9 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 117 +- llvm/lib/Target/X86/X86InstrAVX512.td | 13 +- llvm/lib/Target/X86/X86InstrFoldTables.cpp | 72 + llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 4 + llvm/lib/Target/X86/X86InstrInfo.cpp | 14 +- llvm/lib/Target/X86/X86InstrSSE.td | 10 +- .../InstCombine/InstCombineVectorOps.cpp | 52 + .../CodeGen/AArch64/GlobalISel/arm64-fallback.ll | 2 +- .../GlobalISel/call-translator-tail-call.ll | 7 +- .../GlobalISel/combiner-load-store-indexing.ll | 182 ++ .../AArch64/GlobalISel/gisel-commandline-option.ll | 7 +- .../GlobalISel/legalizer-info-validation.mir | 14 +- llvm/test/CodeGen/AArch64/dllimport.ll | 4 +- .../CodeGen/AArch64/sve-intrinsics-int-arith.ll | 99 + .../AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir | 43 + .../GlobalISel/inst-select-amdgcn.cos.s16.mir | 47 + .../AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir | 83 + .../GlobalISel/inst-select-amdgcn.fract.s16.mir | 47 + .../AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir | 128 ++ .../GlobalISel/inst-select-amdgcn.ldexp.s16.mir | 73 + .../GlobalISel/inst-select-amdgcn.rcp.legacy.mir | 48 + .../AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir | 83 + .../GlobalISel/inst-select-amdgcn.rcp.s16.mir | 47 + .../GlobalISel/inst-select-amdgcn.rsq.clamp.mir | 48 + .../GlobalISel/inst-select-amdgcn.rsq.legacy.mir | 48 + .../AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir | 83 + .../GlobalISel/inst-select-amdgcn.rsq.s16.mir | 47 + .../AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir | 43 + .../GlobalISel/inst-select-amdgcn.sin.s16.mir | 47 + .../CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir | 37 +- .../GlobalISel/inst-select-load-atomic-flat.mir | 308 +++ .../GlobalISel/inst-select-load-atomic-global.mir | 363 ++++ .../GlobalISel/inst-select-load-atomic-local.mir | 314 +++ .../AMDGPU/GlobalISel/inst-select-load-flat.mir | 76 - .../AMDGPU/GlobalISel/inst-select-load-global.mir | 76 - .../AMDGPU/GlobalISel/inst-select-load-local.mir | 87 +- .../AMDGPU/GlobalISel/inst-select-load-private.mir | 40 + .../CodeGen/AMDGPU/GlobalISel/inst-select-lshr.mir | 36 +- .../AMDGPU/GlobalISel/inst-select-ptr-mask.mir | 475 +++++ .../CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir | 36 +- .../AMDGPU/GlobalISel/inst-select-store-local.mir | 304 +++ .../AMDGPU/GlobalISel/lds-global-non-entry-func.ll | 13 + .../CodeGen/AMDGPU/GlobalISel/lds-global-value.ll | 35 + llvm/test/CodeGen/AMDGPU/GlobalISel/lds-size.ll | 1 + .../AMDGPU/GlobalISel/lds-zero-initializer.ll | 5 + .../GlobalISel/legalize-amdgcn.wavefrontsize.mir | 18 + .../GlobalISel/legalize-build-vector-trunc.mir | 19 + .../regbankselect-build-vector-trunc.mir | 83 + .../AMDGPU/GlobalISel/regbankselect-load.mir | 189 +- llvm/test/CodeGen/ARM/ParallelDSP/blocks.ll | 2 +- llvm/test/CodeGen/ARM/ParallelDSP/sext-acc.ll | 186 ++ llvm/test/CodeGen/ARM/select.ll | 4 +- llvm/test/CodeGen/Thumb2/mve-masked-ldst.ll | 626 +++++- llvm/test/CodeGen/Thumb2/mve-masked-load.ll | 1310 +++++++++--- llvm/test/CodeGen/Thumb2/mve-masked-store.ll | 1180 ++++++++--- llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll | 489 +++-- llvm/test/CodeGen/Thumb2/mve-pred-loadstore.ll | 178 +- llvm/test/CodeGen/Thumb2/mve-vctp.ll | 54 + llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll | 2148 ++++++++++++++++++++ llvm/test/CodeGen/X86/avx512-intrinsics.ll | 2 +- llvm/test/CodeGen/X86/combineIncDecVector-crash.ll | 51 + llvm/test/CodeGen/X86/fold-load-vec.ll | 2 +- llvm/test/CodeGen/X86/fp128-cast.ll | 846 ++++++-- llvm/test/CodeGen/X86/fp128-libcalls.ll | 89 + llvm/test/CodeGen/X86/sqrt-partial.ll | 18 +- llvm/test/CodeGen/X86/vector-reduce-mul.ll | 573 +++--- .../CodeGen/X86/vector-shuffle-combining-ssse3.ll | 6 +- llvm/test/CodeGen/X86/xmulo.ll | 12 +- llvm/test/MC/ARM/mve-reductions.s | 36 + llvm/test/MC/Disassembler/ARM/mve-reductions.txt | 39 +- .../ARM/mve-scalar-shift-unpredictable.txt | 42 + .../Disassembler/Mips/micromips32r3/valid-el.txt | 1 + .../MC/Disassembler/Mips/micromips32r3/valid.txt | 1 + llvm/test/Transforms/Inline/inline_minisize.ll | 2 +- .../Transforms/InstCombine/icmp-div-constant.ll | 124 +- .../InstCombine/insert-extract-shuffle.ll | 17 +- .../result-of-usub-is-non-zero-and-no-overflow.ll | 343 ++++ ...l-check-in-uadd_with_overflow-of-nonnull-ptr.ll | 66 +- .../SLPVectorizer/X86/consecutive-access.ll | 16 + .../tools/yaml2obj/duplicate-section-names.test | 7 +- .../tools/yaml2obj/duplicate-symbol-names.test | 13 +- .../yaml2obj/dynamic-section-raw-content.yaml | 16 +- llvm/test/tools/yaml2obj/dynamic-symbols.yaml | 65 +- .../dynsymtab-implicit-sections-size-content.yaml | 22 +- .../tools/yaml2obj/elf-comdat-broken-info.yaml | 34 +- .../tools/yaml2obj/elf-comdat-broken-members.yaml | 22 + .../tools/yaml2obj/elf-custom-null-section.yaml | 2 +- .../tools/yaml2obj/program-header-size-offset.yaml | 25 +- llvm/test/tools/yaml2obj/program-header.yaml | 13 +- llvm/test/tools/yaml2obj/reloc-sec-info.yaml | 32 +- .../tools/yaml2obj/relocation-missing-symbol.yaml | 14 +- llvm/test/tools/yaml2obj/section-link.yaml | 25 +- .../symtab-implicit-sections-size-content.yaml | 4 +- llvm/tools/remarks-shlib/Remarks.exports | 1 + .../Remarks/BitstreamRemarksParsingTest.cpp | 401 ++++ llvm/unittests/Remarks/CMakeLists.txt | 1 + llvm/utils/TableGen/CodeGenDAGPatterns.cpp | 1 + llvm/utils/TableGen/DFAPacketizerEmitter.cpp | 4 +- llvm/utils/TableGen/GlobalISelEmitter.cpp | 4 + 261 files changed, 15438 insertions(+), 2863 deletions(-) copy clang-tools-extra/clangd/clients/clangd-vscode/{README.md => DEVELOPING.md} (54%) create mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/doc-assets/complete.png create mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/doc-assets/diagn [...] create mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/doc-assets/extract.png create mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/doc-assets/format.png create mode 100644 clang-tools-extra/clangd/clients/clangd-vscode/doc-assets/include.png create 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lld/test/ELF/{plt-i686.s => i386-plt.s} (100%) delete mode 100644 lld/test/ELF/merge-section-types.s delete mode 100644 lld/test/ELF/typed-undef.s rename lld/test/ELF/{local-ver-preemptible.s => version-script-local-preemptible.s} (75%) rename lld/test/ELF/{pie-weak.s => weak-undef-got-pie.s} (53%) rename lld/test/ELF/{plt.s => x86-64-plt.s} (100%) create mode 100644 llvm/include/llvm/Remarks/BitstreamRemarkParser.h create mode 100644 llvm/lib/Remarks/BitstreamRemarkParser.cpp create mode 100644 llvm/lib/Remarks/BitstreamRemarkParser.h create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/combiner-load-store-indexing.ll create mode 100644 llvm/test/CodeGen/AArch64/sve-intrinsics-int-arith.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ldexp.s16.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ptr-mask.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-non-entry-func.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/lds-global-value.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/lds-size.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.wavefrontsize.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector-trunc.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector- [...] create mode 100644 llvm/test/CodeGen/ARM/ParallelDSP/sext-acc.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-vctp.ll create mode 100644 llvm/test/CodeGen/X86/combineIncDecVector-crash.ll create mode 100644 llvm/test/MC/Disassembler/ARM/mve-scalar-shift-unpredictable.txt create mode 100644 llvm/test/Transforms/InstCombine/result-of-usub-is-non-zero-and [...] create mode 100644 llvm/test/tools/yaml2obj/elf-comdat-broken-members.yaml create mode 100644 llvm/unittests/Remarks/BitstreamRemarksParsingTest.cpp -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allnoconfig updated (a9b303144 -> 8f96123eb)

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