Tcwg-commits July 2019

tcwg-commits@lists.linaro.org

6 participants
14175 discussions

[compiler-rt] branch master updated (86475d75a -> 8273937bb)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository compiler-rt. from 86475d75a [TSan] Improve handling of stack pointer mangling in {set,lon [...] new 8273937bb [TSan] Fix asm token error The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/tsan/rtl/tsan_platform_linux.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 2 months

[llvm] branch master updated (4783e3ce2b3 -> 243b4a424c7)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from 4783e3ce2b3 TableGen: Add address space to matchers new 59e121a7ce9 TableGen/GlobalISel: Fix handling of truncstore patterns new 243b4a424c7 [LoopUnroll+LoopUnswitch] do not transform loops containing callbr The 2 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Analysis/LoopInfo.cpp | 5 ++- test/TableGen/address-space-patfrags.td | 38 +++++++++++++++++++ test/Transforms/LoopUnroll/callbr.ll | 51 +++++++++++++++++++++++++ test/Transforms/LoopUnswitch/callbr.ll | 66 +++++++++++++++++++++++++++++++++ utils/TableGen/GlobalISelEmitter.cpp | 9 ++++- 5 files changed, 167 insertions(+), 2 deletions(-) create mode 100644 test/Transforms/LoopUnroll/callbr.ll create mode 100644 test/Transforms/LoopUnswitch/callbr.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 2 months

[gcc] branch master updated (258517c160d -> 0571a99556c)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 258517c160d rs6000: Always output .machine new 0571a99556c runtime: expose the g variable The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/go/gofrontend/MERGE | 2 +- libgo/runtime/proc.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 2 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allmodconfig updated (30ebb2f7 -> 9c62cd19)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-mainline-allmodconfig in repository toolchain/ci/base-artifacts. from 30ebb2f7 1: reset: linux-54dee406374ce8adb352c48e175176247cb8db7c: 19523 new 9c62cd19 2: update: linux-d7d170a8e357bd9926cc6bfea5c2385c2eac65b2: 19568 The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 233 +- 02-build_llvm/console.log | 11300 ++++++++++++++++---------------- 03-build_linux/console.log | 1845 +++--- 05-check_regression/console.log | 20 +- 06-update_baseline/console.log | 50 + console.log | 13448 +++++++++++++++++++------------------- jenkins/manifest.sh | 10 +- reset-baseline | 0 results | 2 +- 9 files changed, 13470 insertions(+), 13438 deletions(-) delete mode 100644 reset-baseline -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 2 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig updated (9428d95ce7f -> 39d888c1e42)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig in repository toolchain/ci/llvm-project. from 9428d95ce7f [LV] Exclude loop-invariant inputs from scalar cost computation. adds 951bb68ce26 [TargetParser][ARM] Account dependencies when processing ta [...] adds 3c0e2bb0cba Add test for variant construction with duplicate types. adds 4066978cb7a Improve compile time of variant. adds 635d103e0be [X86] Separate the memory size of vzext_load/vextract_store [...] adds 2d63fbb7b1f [ValueTracking] Look through constant Int2Ptr/Ptr2Int expressions adds 776ac79e88d [NFC][PowerPC] Add the test block-placement.mir adds c3805d761ea [BPF] add unit tests for preserve_{array,union,struct}_acce [...] adds 335f955dc49 [PowerPC] Support fp128 libcalls adds f1ee04c42a4 [LoopInfo] Introduce getUniqueNonLatchExitBlocks utility function adds 796ed134ccc Remove set but unused variable. adds 45c43e7d04d [LoopUtils] Extend the scope of getLoopEstimatedTripCount adds 54869ec907f [Attributor] Deduce "nonnull" attribute adds 6bd02a442c0 [PowerPC] Support -mabi=ieeelongdouble and -mabi=ibmlongdouble adds d02f17daed3 [clangd] Added highlighting to enum constants. adds ea36cdcec31 DeveloperPolicy: fix a typo adds 17b4a932fae [clangd] Added highlighting for members and methods. adds 3ed93b4673b [Loop Peeling] Enable peeling for loops with multiple exits adds 1d554b74412 [LoopVectorize] Pass unfiltered list of arguments to getInt [...] adds d021ad9fbeb [Loop Peeling] Fix the bug with IDom setting for exit loops adds da750b1688f [ARM] Adjust how NEON shifts are lowered adds 309246e4e2f [obj2yaml] - Rework tool's error reporting logic for ELF target. adds b91403d4670 Revert r366052 "[obj2yaml] - Rework tool's error reporting [...] adds f059147a108 [ARM] Move Shifts after Bits. NFC adds 0bf0b8ff7c7 [libFuzzer] Disable fork.test on AArch64 adds 6e89887642f [ARM] MVE Vector Shifts adds 8d9b9f6bf2c [LLD][ELF] - Minor simplification. NFC. adds 224816ba169 Recommit r366052 "[obj2yaml] - Rework tool's error reportin [...] adds 960ff0810da [OpenCL][PR41727] Prevent ICE on global dtors adds 7d5100115af PDB HashTable: Make iterator key type const adds 14d115ff98a [ASTImporter] Using Lang_CXX14 in ASTImporterVisibilityTest. adds 130df2c7e8f Fix uninitialized variable analyzer warning. NFCI. adds d6f34bf4d4a [OpenCL] Deduce addr space for pointee of dependent types i [...] adds 83ae0b5eb4f [mips] Remove "else-after-return". NFC adds 12400b97838 [Testing] Add missing "REQUIRES: asserts" adds 60fb5e97a0d [X86] isTargetShuffleEquivalent - assert the expected mask [...] adds 8d879c8d954 [AMDGPU][MC] Corrected encoding of src0 for DS_GWS_* instructions adds 63d00b19e5c [OPENMP]Add support for analysis of if clauses. adds cb238de456b [PatternMatch] Implement matching code for LibFunc adds 4e34a85aa2e [clangd] Fix duplicate highlighting tokens appearing in ini [...] adds 5153b1723a6 [AMDGPU][MC][GFX9][GFX10] Added support of GET_DOORBELL message adds 62cc16dac20 gn build: Add a note on how to locally tell git to ignore b [...] adds 1d91f94f095 [clangd] Fix doc adds fd08dcb9db0 [AMDGPU] fixed scheduler crash in gfx908 adds a13cca41c5c [ORC] Start adding ORCv1 to ORCv2 transition tips to the OR [...] adds e5086481b65 fix unnamed fiefield issue and add tests for __builtin_pres [...] adds 838c8e30c2f [X86][SSE] Add PACKSS with zero shuffle masks. adds 5a07a614c0f [X86][SSE] Regenerated packss.ll test file. adds 73e33368090 [docs][llvm-nm] Fix inconsistent grammar adds 7284d443c3b Revert "r366069: [PatternMatch] Implement matching code for [...] adds a53e779edc8 [x86] add tests for reductions that might be better with mo [...] adds 3329721e644 [lldb][doc] Document how our LLDB table gen initialized options adds 0e5f9157576 Use unique_ptr instead of manual delete in one place. No be [...] adds 05489f09522 Use a unique_ptr instead of manual memory management for Cu [...] adds cc02b170823 AMDGPU/GlobalISel: RegBankSelect for G_CONCAT_VECTORS adds a65913e752e AMDGPU/GlobalISel: Select easy cases for G_BUILD_VECTOR adds a2dcbd36439 Use a unique_ptr instead of manual memory management for LineTable adds 8e7eee617a0 [ARM] Minor formatting in ARMInstrMVE.td. NFC adds 3dcd7996f11 [FunctionAttrs] Remove readonly and writeonly assertion adds 56799837a41 Update __VERSION__ to remove the hardcoded 4.2.1 version adds 7938424eb92 [AMDGPU] Copy missing predicate from pseudo to real adds 269e4e1b601 Add some release notes for 9.0 release adds 49169a963e8 AMDGPU: Add 24-bit mul intrinsics adds 3e7c314b039 Reland "[COFF] Add null check in case of symbols defined in [...] adds 81971b2b79c [X86] Return UNDEF from LowerScalarImmediateShift when the [...] adds 032e3c468fa [llvm-lib] Add a dependency to intrinsics_gen to the LLVMLi [...] adds eb99165b97b [x86] try to keep FP casted+truncated+extracted vector elem [...] adds b390121efb3 AMDGPU/GlobalISel: Select llvm.amdgcn.end.cf adds ff1c5288cb6 AMDGPU: Remove reserved value accidentally left in for gfx908 adds 53fa759ff5a AMDGPU/GlobalISel: Handle llvm.amdgcn.if.break adds 90bdfb3daf7 AMDGPU/GlobalISel: Widen vector extracts adds b2a0745e2d5 [WebAssembly] Assembler: recognize .init_array as data section. adds 4885978e231 [sanitizers][windows][mingw32] Mingw32 RTL fixes RTL interc [...] adds dc56995c574 [ARM] MVE vector for 64bit types adds ac6375d99d1 Expand comment about how StringsToBuckets was computed, and [...] new 42e90ed7717 [cmake] Don't set install rules for tblgen if building util [...] new 99f2a108707 [FileCheck] Store line numbers as optional values new ba4373ea7d9 AMDGPU: Fix missing immarg from interp intrinsics new 434d664095b GlobalISel: Implement narrowScalar for vector extract/inser [...] new 5dfd4660329 AMDGPU/GlobalISel: Fix G_ICMP for wave32 new b0e04c018c3 AMDGPU/GlobalISel: Custom legalize G_EXTRACT_VECTOR_ELT new 6ed315f89be AMDGPU/GlobalISel: Custom legalize G_INSERT_VECTOR_ELT new 18b7133843b AMDGPU/GlobalISel: Fix handling of sgpr (not scc bank) s1 to VCC new 3bfdb54d88d AMDGPU/GlobalISel: Fix not constraining result reg of copie [...] new e1b52f41803 AMDGPU/GlobalISel: Fix selecting vcc->vcc bank copies new ad19b50c000 AMDGPU/GlobalISel: Don't constrain source register of VCC copies new c8291c94f83 AMDGPU/GlobalISel: Select G_AND/G_OR/G_XOR new c5d7b0c4547 Constrain workaround to avoid affecting other buildbots new c5e7f562496 ARM MTE stack sanitizer. new dfcd4384cbc [libc++] Implement P0433: deduction guides for <unordered_map> new 66ee934440c AMDGPU/GlobalISel: Allow scalar s1 and/or/xor new 39d888c1e42 [TSan] Improve handling of stack pointer mangling in {set,l [...] The 17 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: clang-tools-extra/clangd/SemanticHighlighting.cpp | 38 +- clang-tools-extra/clangd/SemanticHighlighting.h | 3 + .../clangd/test/semantic-highlighting.test | 11 +- .../clangd/unittests/SemanticHighlightingTests.cpp | 67 +- clang-tools-extra/docs/clangd/Installation.rst | 2 +- clang/docs/LanguageExtensions.rst | 2 + clang/docs/ReleaseNotes.rst | 6 + clang/include/clang/AST/OpenMPClause.h | 7 +- clang/include/clang/Basic/DiagnosticIDs.h | 2 +- clang/include/clang/Basic/Features.def | 1 + clang/include/clang/Basic/LangOptions.def | 1 + clang/include/clang/Basic/Sanitizers.def | 3 + clang/include/clang/Basic/SourceManager.h | 2 +- clang/include/clang/Driver/CC1Options.td | 2 + clang/lib/AST/ASTImporter.cpp | 2 +- clang/lib/AST/OpenMPClause.cpp | 19 + clang/lib/Basic/DiagnosticIDs.cpp | 8 +- clang/lib/Basic/SourceManager.cpp | 4 +- clang/lib/Basic/Targets/PPC.cpp | 4 +- clang/lib/CodeGen/CGDeclCXX.cpp | 24 +- clang/lib/CodeGen/CGExpr.cpp | 21 +- clang/lib/CodeGen/CodeGenFunction.cpp | 2 + clang/lib/CodeGen/CodeGenFunction.h | 3 + clang/lib/CodeGen/CodeGenModule.cpp | 14 +- clang/lib/CodeGen/ItaniumCXXABI.cpp | 21 +- clang/lib/CodeGen/SanitizerMetadata.cpp | 21 +- clang/lib/CodeGen/TargetInfo.h | 5 + clang/lib/Driver/Compilation.cpp | 12 +- clang/lib/Driver/SanitizerArgs.cpp | 10 +- clang/lib/Driver/ToolChains/Clang.cpp | 19 +- clang/lib/Driver/ToolChains/Linux.cpp | 2 + clang/lib/Frontend/CompilerInvocation.cpp | 1 + clang/lib/Frontend/InitPreprocessor.cpp | 7 +- clang/lib/Sema/TreeTransform.h | 17 + clang/test/Analysis/cfg-openmp.cpp | 532 +++-- clang/test/CodeGen/builtin-preserve-access-index.c | 177 ++ clang/test/CodeGen/memtag-attr.cpp | 19 + clang/test/CodeGen/ppc64-long-double.cpp | 11 + clang/test/CodeGenOpenCLCXX/atexit.cl | 11 + clang/test/Driver/fsanitize.c | 10 + clang/test/Driver/ppc-abi.c | 18 + clang/test/Lexer/has_feature_memtag_sanitizer.cpp | 11 + clang/test/OpenMP/cancel_if_messages.cpp | 10 + .../OpenMP/distribute_parallel_for_if_messages.cpp | 7 + .../distribute_parallel_for_simd_if_messages.cpp | 7 + clang/test/OpenMP/parallel_for_if_messages.cpp | 7 + .../test/OpenMP/parallel_for_simd_if_messages.cpp | 7 + clang/test/OpenMP/parallel_if_messages.cpp | 7 + .../test/OpenMP/parallel_sections_if_messages.cpp | 8 + clang/test/OpenMP/target_data_if_messages.cpp | 7 + .../test/OpenMP/target_enter_data_if_messages.cpp | 7 + clang/test/OpenMP/target_exit_data_if_messages.cpp | 7 + clang/test/OpenMP/target_if_messages.cpp | 7 + .../OpenMP/target_parallel_for_if_messages.cpp | 7 + .../target_parallel_for_simd_if_messages.cpp | 7 + clang/test/OpenMP/target_parallel_if_messages.cpp | 7 + clang/test/OpenMP/target_simd_if_messages.cpp | 7 + .../OpenMP/target_teams_distribute_if_messages.cpp | 7 + ...t_teams_distribute_parallel_for_if_messages.cpp | 7 + ...ms_distribute_parallel_for_simd_if_messages.cpp | 8 + .../target_teams_distribute_simd_if_messages.cpp | 7 + clang/test/OpenMP/target_teams_if_messages.cpp | 7 + clang/test/OpenMP/target_update_if_messages.cpp | 7 + clang/test/OpenMP/task_if_messages.cpp | 7 + .../teams_distribute_parallel_for_if_messages.cpp | 8 + ...ms_distribute_parallel_for_simd_if_messages.cpp | 8 + clang/test/Preprocessor/arm-target-features.c | 29 +- clang/test/Preprocessor/init.c | 4 +- clang/test/Sema/builtin-preserve-access-index.c | 13 + clang/test/SemaCXX/attr-no-sanitize.cpp | 5 + .../test/SemaOpenCLCXX/address-space-deduction.cl | 39 + clang/unittests/AST/ASTImporterVisibilityTest.cpp | 40 +- compiler-rt/lib/asan/asan_malloc_win.cc | 88 +- compiler-rt/lib/tsan/rtl/tsan_platform_linux.cc | 27 +- compiler-rt/test/fuzzer/fork.test | 2 +- libcxx/CMakeLists.txt | 6 +- libcxx/include/unordered_map | 146 +- libcxx/include/variant | 67 +- .../stress_test_variant_overloads_impl.sh.cpp | 118 + .../unord.map/unord.map.cnstr/deduct.fail.cpp | 106 + .../unord.map/unord.map.cnstr/deduct.pass.cpp | 204 ++ .../unord.map.cnstr/deduct_const.pass.cpp | 172 ++ .../unord.multimap.cnstr/deduct.fail.cpp | 106 + .../unord.multimap.cnstr/deduct.pass.cpp | 204 ++ .../unord.multimap.cnstr/deduct_const.pass.cpp | 173 ++ .../variant.variant/variant.ctor/T.pass.cpp | 12 + libcxx/www/cxx2a_status.html | 2 +- lld/COFF/SymbolTable.cpp | 2 +- lld/ELF/InputFiles.cpp | 10 +- lld/test/COFF/Inputs/undefined-symbol-lto-a.ll | 82 + lld/test/COFF/Inputs/undefined-symbol-lto-b.ll | 29 + lld/test/COFF/undefined-symbol-lto.test | 29 + lldb/source/Commands/OptionsBase.td | 98 + llvm/cmake/modules/TableGen.cmake | 2 +- llvm/docs/AMDGPU/gfx10_msg.rst | 2 + llvm/docs/AMDGPU/gfx9_msg.rst | 2 + llvm/docs/BitCodeFormat.rst | 1 + llvm/docs/CommandGuide/llvm-nm.rst | 2 +- llvm/docs/DeveloperPolicy.rst | 2 +- llvm/docs/LangRef.rst | 16 +- ...{ORCv2DesignAndImplementation.rst => ORCv2.rst} | 159 +- llvm/docs/ReleaseNotes.rst | 12 +- llvm/docs/index.rst | 6 +- llvm/include/llvm/Analysis/LoopInfo.h | 8 + llvm/include/llvm/Analysis/LoopInfoImpl.h | 32 +- llvm/include/llvm/BinaryFormat/ELF.h | 3 +- llvm/include/llvm/Bitcode/LLVMBitCodes.h | 3 +- llvm/include/llvm/DebugInfo/PDB/Native/HashTable.h | 16 +- llvm/include/llvm/IR/Attributes.td | 4 + llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 20 +- llvm/include/llvm/Object/ELF.h | 23 +- llvm/include/llvm/Support/ARMTargetParser.def | 4 +- llvm/include/llvm/Support/FileCheck.h | 46 +- llvm/include/llvm/Transforms/IPO/Attributor.h | 32 + llvm/lib/Analysis/ValueTracking.cpp | 9 + llvm/lib/AsmParser/LLLexer.cpp | 1 + llvm/lib/AsmParser/LLParser.cpp | 4 + llvm/lib/AsmParser/LLToken.h | 1 + llvm/lib/Bitcode/Reader/BitcodeReader.cpp | 8 +- llvm/lib/Bitcode/Writer/BitcodeWriter.cpp | 2 + llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 11 + llvm/lib/CodeGen/TargetLoweringBase.cpp | 28 + .../DebugInfo/PDB/Native/PDBStringTableBuilder.cpp | 15 +- llvm/lib/IR/Attributes.cpp | 2 + llvm/lib/IR/Verifier.cpp | 1 + llvm/lib/MC/MCParser/WasmAsmParser.cpp | 3 + llvm/lib/Support/ARMTargetParser.cpp | 26 +- llvm/lib/Support/FileCheck.cpp | 22 +- llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp | 127 ++ .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 162 +- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 1 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 78 +- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 4 + llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 112 +- llvm/lib/Target/AMDGPU/AMDGPUSubtarget.cpp | 4 +- llvm/lib/Target/AMDGPU/DSInstructions.td | 9 +- llvm/lib/Target/AMDGPU/SIDefines.h | 1 + llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 5 + llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp | 6 +- llvm/lib/Target/AMDGPU/Utils/AMDGPUAsmUtils.cpp | 2 +- llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp | 11 +- llvm/lib/Target/ARM/ARMISelLowering.cpp | 262 ++- llvm/lib/Target/ARM/ARMISelLowering.h | 38 +- llvm/lib/Target/ARM/ARMInstrInfo.td | 11 + llvm/lib/Target/ARM/ARMInstrMVE.td | 2316 ++++++++++---------- llvm/lib/Target/ARM/ARMInstrNEON.td | 194 +- llvm/lib/Target/Mips/MipsISelLowering.h | 2 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 121 +- llvm/lib/Target/X86/X86InstrAVX512.td | 96 +- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td | 26 +- llvm/lib/Target/X86/X86InstrSSE.td | 88 +- llvm/lib/ToolDrivers/llvm-lib/CMakeLists.txt | 3 + llvm/lib/Transforms/IPO/Attributor.cpp | 284 +++ llvm/lib/Transforms/IPO/ForceFunctionAttrs.cpp | 1 + llvm/lib/Transforms/IPO/FunctionAttrs.cpp | 7 +- llvm/lib/Transforms/Utils/CodeExtractor.cpp | 1 + llvm/lib/Transforms/Utils/LoopUnroll.cpp | 3 +- llvm/lib/Transforms/Utils/LoopUnrollPeel.cpp | 41 +- llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp | 20 +- llvm/lib/Transforms/Utils/LoopUtils.cpp | 20 +- llvm/lib/Transforms/Vectorize/LoopVectorize.cpp | 7 +- llvm/test/Bitcode/attributes.ll | 11 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-and.mir | 593 +++++ .../AMDGPU/GlobalISel/inst-select-build-vector.mir | 152 ++ .../CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir | 128 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir | 13 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-or.mir | 600 ++++- .../CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir | 593 +++++ .../GlobalISel/legalize-extract-vector-elt.mir | 478 +++- .../GlobalISel/legalize-insert-vector-elt.mir | 87 +- .../AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll | 39 + .../AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll | 36 + .../AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll | 27 + .../AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll | 26 + .../AMDGPU/GlobalISel/regbankselect-and-s1.mir | 527 +++++ .../AMDGPU/GlobalISel/regbankselect-and.mir | 145 +- .../GlobalISel/regbankselect-concat-vector.mir | 69 + .../CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir | 15 +- .../AMDGPU/GlobalISel/regbankselect-phi-s1.mir | 1333 +++++++++++ .../AMDGPU/GlobalISel/regbankselect-xor.mir | 15 +- .../CodeGen/AMDGPU/amdgpu-codegenprepare-mul24.ll | 494 +++++ llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll | 14 + llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll | 14 + llvm/test/CodeGen/AMDGPU/mad_uint24.ll | 76 + llvm/test/CodeGen/AMDGPU/mul.i16.ll | 18 +- llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll | 4 +- .../CodeGen/AMDGPU/power-sched-no-instr-sunit.mir | 22 + llvm/test/CodeGen/ARM/vpadd.ll | 47 +- llvm/test/CodeGen/ARM/vuzp.ll | 46 +- llvm/test/CodeGen/BPF/CORE/intrinsic-array.ll | 80 + llvm/test/CodeGen/BPF/CORE/intrinsic-struct.ll | 77 + llvm/test/CodeGen/BPF/CORE/intrinsic-union.ll | 76 + llvm/test/CodeGen/PowerPC/block-placement.mir | 217 ++ llvm/test/CodeGen/PowerPC/fp128-libcalls.ll | 164 ++ llvm/test/CodeGen/Thumb2/mve-abs.ll | 47 + llvm/test/CodeGen/Thumb2/mve-bitarith.ll | 65 + llvm/test/CodeGen/Thumb2/mve-div-expand.ll | 194 ++ llvm/test/CodeGen/Thumb2/mve-fmath.ll | 250 +++ llvm/test/CodeGen/Thumb2/mve-fp-negabs.ll | 57 + llvm/test/CodeGen/Thumb2/mve-frint.ll | 150 ++ llvm/test/CodeGen/Thumb2/mve-minmax.ll | 215 ++ llvm/test/CodeGen/Thumb2/mve-neg.ll | 23 + llvm/test/CodeGen/Thumb2/mve-sext.ll | 47 + llvm/test/CodeGen/Thumb2/mve-shifts.ll | 584 +++++ llvm/test/CodeGen/Thumb2/mve-shuffle.ll | 146 +- llvm/test/CodeGen/Thumb2/mve-simple-arith.ll | 166 ++ llvm/test/CodeGen/Thumb2/mve-soft-float-abi.ll | 68 + llvm/test/CodeGen/Thumb2/mve-vcvt.ll | 108 + llvm/test/CodeGen/Thumb2/mve-vdup.ll | 49 + llvm/test/CodeGen/Thumb2/mve-vmovimm.ll | 89 +- llvm/test/CodeGen/Thumb2/mve-vmvnimm.ll | 16 +- llvm/test/CodeGen/X86/haddsub.ll | 204 ++ llvm/test/CodeGen/X86/known-bits-vector.ll | 5 +- llvm/test/CodeGen/X86/known-signbits-vector.ll | 29 +- llvm/test/CodeGen/X86/packss.ll | 61 + llvm/test/CodeGen/X86/phaddsub-extract.ll | 363 +++ llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll | 73 +- llvm/test/CodeGen/X86/vector-shuffle-sse1.ll | 19 +- llvm/test/MC/AMDGPU/ds.s | 16 +- llvm/test/MC/AMDGPU/expressions.s | 2 +- llvm/test/MC/AMDGPU/gfx10_asm_all.s | 24 +- llvm/test/MC/AMDGPU/gfx7_asm_all.s | 30 +- llvm/test/MC/AMDGPU/gfx8_asm_all.s | 30 +- llvm/test/MC/AMDGPU/gfx9_asm_all.s | 30 +- llvm/test/MC/AMDGPU/sopp-gfx10.s | 17 + llvm/test/MC/AMDGPU/sopp-gfx9.s | 12 +- llvm/test/MC/Disassembler/AMDGPU/ds_vi.txt | 16 +- .../test/MC/Disassembler/AMDGPU/gfx10_dasm_all.txt | 36 +- llvm/test/MC/Disassembler/AMDGPU/gfx8_dasm_all.txt | 48 +- llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_all.txt | 48 +- llvm/test/MC/WebAssembly/basic-assembly.s | 15 +- llvm/test/Transforms/FunctionAttrs/nonnull.ll | 323 ++- llvm/test/Transforms/FunctionAttrs/nosync.ll | 2 +- .../Transforms/FunctionAttrs/read-write-scc.ll | 20 + llvm/test/Transforms/Inline/attributes.ll | 30 + .../LoopUnroll/peel-loop-pgo-deopt-idom.ll | 55 + .../Transforms/LoopUnroll/peel-loop-pgo-deopt.ll | 81 + .../LoopVectorize/vector-intrinsic-call-cost.ll | 30 + llvm/test/Verifier/AMDGPU/intrinsic-immarg.ll | 96 + llvm/test/tools/obj2yaml/section-group.test | 24 +- .../tools/obj2yaml/special-symbol-indices.yaml | 2 +- llvm/tools/obj2yaml/elf2yaml.cpp | 319 ++- llvm/tools/obj2yaml/obj2yaml.cpp | 13 +- llvm/tools/obj2yaml/obj2yaml.h | 2 +- llvm/unittests/Analysis/LoopInfoTest.cpp | 46 + llvm/unittests/Support/FileCheckTest.cpp | 14 +- llvm/utils/emacs/llvm-mode.el | 2 +- llvm/utils/gn/README.rst | 2 + 248 files changed, 15480 insertions(+), 2900 deletions(-) create mode 100644 clang/test/CodeGen/builtin-preserve-access-index.c create mode 100644 clang/test/CodeGen/memtag-attr.cpp create mode 100644 clang/test/CodeGenOpenCLCXX/atexit.cl create mode 100644 clang/test/Lexer/has_feature_memtag_sanitizer.cpp create mode 100644 clang/test/Sema/builtin-preserve-access-index.c create mode 100644 libcxx/test/libcxx/utilities/meta/stress_tests/stress_test_vari [...] create mode 100644 libcxx/test/std/containers/unord/unord.map/unord.map.cnstr/dedu [...] create mode 100644 libcxx/test/std/containers/unord/unord.map/unord.map.cnstr/dedu [...] create mode 100644 libcxx/test/std/containers/unord/unord.map/unord.map.cnstr/dedu [...] create mode 100644 libcxx/test/std/containers/unord/unord.multimap/unord.multimap. [...] create mode 100644 libcxx/test/std/containers/unord/unord.multimap/unord.multimap. [...] create mode 100644 libcxx/test/std/containers/unord/unord.multimap/unord.multimap. [...] create mode 100644 lld/test/COFF/Inputs/undefined-symbol-lto-a.ll create mode 100644 lld/test/COFF/Inputs/undefined-symbol-lto-b.ll create mode 100644 lld/test/COFF/undefined-symbol-lto.test rename llvm/docs/{ORCv2DesignAndImplementation.rst => ORCv2.rst} (64%) create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-and.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-xor.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i32.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.end.cf.i64.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i32.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.if.break.i64.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir create mode 100644 llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-mul24.ll create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.i24.ll create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.mul.u24.ll create mode 100644 llvm/test/CodeGen/AMDGPU/power-sched-no-instr-sunit.mir create mode 100644 llvm/test/CodeGen/BPF/CORE/intrinsic-array.ll create mode 100644 llvm/test/CodeGen/BPF/CORE/intrinsic-struct.ll create mode 100644 llvm/test/CodeGen/BPF/CORE/intrinsic-union.ll create mode 100644 llvm/test/CodeGen/PowerPC/block-placement.mir create mode 100644 llvm/test/CodeGen/PowerPC/fp128-libcalls.ll create mode 100644 llvm/test/CodeGen/Thumb2/mve-shifts.ll create mode 100644 llvm/test/MC/AMDGPU/sopp-gfx10.s create mode 100644 llvm/test/Transforms/FunctionAttrs/read-write-scc.ll create mode 100644 llvm/test/Transforms/LoopUnroll/peel-loop-pgo-deopt-idom.ll create mode 100644 llvm/test/Transforms/LoopUnroll/peel-loop-pgo-deopt.ll create mode 100644 llvm/test/Transforms/LoopVectorize/vector-intrinsic-call-cost.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig updated (388572e6 -> 16d83776)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-aarch64-stable-allyesconfig in repository toolchain/ci/base-artifacts. discards 388572e6 1: update: llvm-linux: 16550 new 16d83776 1: update: llvm-linux: 16550 This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (388572e6) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-aarch [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-build_llvm/console.log | 12044 +++++++++++++-------------- 03-build_linux/console.log | 4456 +++++----- 05-check_regression/console.log | 6 +- 06-update_baseline/console.log | 14 +- console.log | 16740 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 7 files changed, 16744 insertions(+), 16744 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 2 months

[gcc] branch master updated (65645bd5042 -> 258517c160d)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository gcc. from 65645bd5042 * config/i386/i386.md (@test<mode>_ccno_1): Rename from t [...] new 258517c160d rs6000: Always output .machine The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 6 ++++++ gcc/config/rs6000/rs6000.c | 4 +--- 2 files changed, 7 insertions(+), 3 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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[llvm] branch master updated (a985f4ba157 -> 4783e3ce2b3)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from a985f4ba157 AMDGPU/GlobalISel: Allow scalar s1 and/or/xor new 4783e3ce2b3 TableGen: Add address space to matchers The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../llvm/CodeGen/GlobalISel/InstructionSelector.h | 10 +++ .../CodeGen/GlobalISel/InstructionSelectorImpl.h | 39 ++++++++++ include/llvm/Target/TargetSelectionDAG.td | 6 ++ test/TableGen/address-space-patfrags.td | 85 ++++++++++++++++++++++ utils/TableGen/CodeGenDAGPatterns.cpp | 34 ++++++++- utils/TableGen/CodeGenDAGPatterns.h | 2 + utils/TableGen/GlobalISelEmitter.cpp | 81 ++++++++++++++++++++- 7 files changed, 253 insertions(+), 4 deletions(-) create mode 100644 test/TableGen/address-space-patfrags.td -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 2 months

[clang] branch master updated (647bdd3207 -> 15a1e7413a)

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This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository clang. from 647bdd3207 ARM MTE stack sanitizer. new 15a1e7413a [clang] allow -fthinlto-index= without -x ir The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: include/clang/Basic/DiagnosticDriverKinds.td | 2 ++ lib/Driver/Driver.cpp | 6 ++++++ lib/Driver/ToolChains/Clang.cpp | 3 +-- test/Driver/thinlto_backend.c | 13 ++++++++++--- 4 files changed, 19 insertions(+), 5 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 2 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allyesconfig updated (6573a818a8c -> 8958f1e9a81)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-release-aarch64-stable-allyesconfig in repository toolchain/ci/gcc. from 6573a818a8c Daily bump. adds 47fe74a5166 Daily bump. adds b76459ba3b0 Backport fix for PR85711 adds 8958f1e9a81 S/390: Fix vector shift count operand No new revisions were added by this update. Summary of changes: gcc/ChangeLog | 17 +++++++++++++++ gcc/DATESTAMP | 2 +- gcc/config/s390/vector.md | 2 +- gcc/recog.c | 16 +++++++++++---- gcc/testsuite/ChangeLog | 7 +++++++ gcc/testsuite/gcc.target/s390/vector/vec-shift-2.c | 24 ++++++++++++++++++++++ 6 files changed, 62 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/s390/vector/vec-shift-2.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

6 years, 2 months

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