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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk/gnu-release-arm-spec2k6-Os_LTO
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discards 24b762a9c 0: update: binutils-gcc-glibc: -5
new f65813333 0: update: binutils-gcc-glibc: -5
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01-reset_artifacts/console.log | 184 +-
02-prepare_abe/console.log | 236 +-
03-build_abe-binutils/console.log | 9658 +--
04-build_abe-stage1/console.log | 17558 +++---
05-build_abe-linux/console.log | 296 +-
06-build_abe-glibc/console.log | 38145 ++++++------
07-build_abe-stage2/console.log | 46806 ++++++++-------
08-benchmark/benchmark-start.log | 2 +-
08-benchmark/benchmark.log | 6 +-
08-benchmark/console.log | 240 +-
09-check_regression/console.log | 6 +-
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_bmk
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from 1cbe46e Add commits from https://ci.linaro.org/job/tcwg_bmk-bisect-ll [...]
new 2cbea50 Add commits from https://ci.linaro.org/job/tcwg_bmk-bisect-ll [...]
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gcc | 2 ++
1 file changed, 2 insertions(+)
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unknown user pushed a change to branch master
in repository llvm.
from 2ab66137f5f AMDGPU/GlobalISel: RegBankSelect for WWM/WQM
new e93a6479cb4 [NFC][InstCombine] Improve test coverage for ((~x) + y) + [...]
new cd8d93f1695 AMDGPU/GlobalISel: Improve icmp selection coverage.
new d12e3c69f0d AMDGPU/GlobalISel: Fail on store to 32-bit address space
new 40142ff2183 AMDGPU/GlobalISel: Fix RegBankSelect for G_BUILD_VECTOR
new 52b2604d062 AMDGPU/GlobalISel: Fix RegBankSelect for G_FCANONICALIZE
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lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 55 +-
lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 2 +
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 4 +-
.../AMDGPU/GlobalISel/inst-select-icmp.s64.mir | 595 +++++++++++++++++++++
.../AMDGPU/GlobalISel/inst-select-implicit-def.mir | 6 +-
...gcn.icmp.mir => regbankselect-build-vector.mir} | 36 +-
.../GlobalISel/regbankselect-fcanonicalize.mir | 35 ++
...ld-inc-of-add-of-not-x-and-y-to-sub-x-from-y.ll | 52 +-
8 files changed, 745 insertions(+), 40 deletions(-)
create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir
copy test/CodeGen/AMDGPU/GlobalISel/{regbankselect-amdgcn.icmp.mir => regbankselec [...]
create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
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tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-mainline-allmodconfig
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discards c1031a00f 0: update: binutils-gcc-linux: all
new 0557f45c6 0: update: binutils-gcc-linux: all
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01-reset_artifacts/console.log | 68 +-
02-prepare_abe/console.log | 400 +-
03-build_abe-binutils/console.log | 11550 +++++++--------
04-build_abe-stage1/console.log | 15384 ++++++++++----------
05-build_linux/console.log | 652 +-
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unknown user pushed a change to branch master
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from bd6fa8c5b57 [AMDGPU] Call isLoopExiting for blocks in the loop.
new 473e2ddc8eb [mips] Add missing schedinfo for ADJCALLSTACKDOWN, ADJCALLSTACKUP
new 2b31edc15d8 [mips] Add missing schedinfo for atomic instructions
new 46a23bad8cb [mips] Add missing schedinfo for MSA and ASE instructions
new 6b9ac8abd2d GlobalISel: Add DAG compat for G_FCANONICALIZE
new b68b21c025a GlobalISel: Add GINodeEquiv for min/max
new bc712eaf908 AMDGPU/GlobalISel: Use and instead of BFE with inline immediate
new 23b47db4b09 AMDGPU/GlobalISel: Fix scc->vcc copy handling
new b137067e347 AMDGPU/GlobalISel: Use vcc reg bank for amdgcn.wqm.vote
new 2ab66137f5f AMDGPU/GlobalISel: RegBankSelect for WWM/WQM
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Summary of changes:
.../llvm/Target/GlobalISel/SelectionDAGCompat.td | 5 +
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 67 +++++---
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 4 +-
lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 +-
lib/Target/Mips/MipsDSPInstrInfo.td | 1 +
lib/Target/Mips/MipsInstrInfo.td | 11 +-
lib/Target/Mips/MipsMSAInstrInfo.td | 7 +-
lib/Target/Mips/MipsScheduleP5600.td | 22 +++
.../AMDGPU/GlobalISel/inst-select-anyext.mir | 36 +++++
.../CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir | 114 ++++++++++----
.../GlobalISel/inst-select-fcanonicalize.mir | 169 +++++++++++++++++++++
.../CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir | 39 +++++
.../CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir | 83 ++++++++++
.../CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir | 83 ++++++++++
.../CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir | 83 ++++++++++
.../CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir | 83 ++++++++++
.../CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir | 48 +++++-
.../AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir | 31 ++++
...-vote.mir => regbankselect-amdgcn.wqm.vote.mir} | 10 +-
.../AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir | 31 ++++
20 files changed, 870 insertions(+), 61 deletions(-)
create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir
create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir
create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir
create mode 100644 test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir
create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
rename test/CodeGen/AMDGPU/GlobalISel/{regbankselect-amdgcn-wqm-vote.mir => regban [...]
create mode 100644 test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
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