Tcwg-commits July 2019

tcwg-commits@lists.linaro.org

6 participants
14175 discussions

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-release-arm-next-defconfig updated (70a789612 -> eac440aa5)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-release-arm-next-defconfig in repository toolchain/ci/base-artifacts. discards 70a789612 0: update: llvm-linux: boot new eac440aa5 0: update: llvm-linux: boot This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (70a789612) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-release-arm- [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-build_llvm/console.log | 11642 +++++++++++++++---------------- 03-build_linux/console.log | 1688 ++--- 04-boot_linux/console.log | 481 +- 05-check_regression/console.log | 6 +- 06-update_baseline/console.log | 25 + console.log | 14062 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- results | 2 +- 9 files changed, 14093 insertions(+), 14041 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 5 months

[llvm] branch master updated (c8c96fc6f84 -> 5cc6baa2303)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. unknown user pushed a change to branch master in repository llvm. from c8c96fc6f84 [NFC][InstCombine] More commutative tests for "shift direct [...] new 5cc6baa2303 Revert [SLP] Look-ahead operand reordering heuristic. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: lib/Transforms/Vectorize/SLPVectorizer.cpp | 282 ++++--------------------- test/Transforms/SLPVectorizer/X86/lookahead.ll | 134 +++++------- 2 files changed, 93 insertions(+), 323 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 5 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allnoconfig updated (706b48251f6 -> d7fcee62f11)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allnoconfig in repository toolchain/ci/llvm-project. from 706b48251f6 [InstCombine] canonicalize fcmp+select to minnum/maxnum intrinsics adds 135cf982e8e Revert "[GDBRemote] Remove code that flushes GDB remote packets" adds bb0b44deaab Clean up MSVC visualization of LLVM pointer types adds fb133b0aabe Various tweaks to MSVC natvis visualizers adds d1728f89878 [X86] Add MOVHPDrm/MOVLPDrm patterns that use VZEXT_LOAD. adds fc233c9108d [X86] Add some additional load folding tests to vec_int_to_ [...] adds 4ca81a9b994 [X86] Add a DAG combine to replace vector loads feeding a v [...] adds 29fff0797b2 [X86] Improve the type checking fast-isel handling of vecto [...] adds fcda45a9eb8 [X86] Add more load folding tests for vcvt(t)ps2(u)qq showi [...] adds b739b91cd3a [clangd] Make FixIt message be consistent with the clang-ti [...] adds 0384a780549 [libcxx] [test] Add void cast to result of compare_exchange [...] adds 98722691b0b [ARM] WLS/LE Code Generation adds d4097b4a93a [SimpleLoopUnswitch] Implement handling of prof branch_weig [...] adds 9d34f4569b4 [clangd] Show better message when we rename macros. adds d2b6665e339 [DebugInfo] Avoid adding too much indirection to pointer-va [...] adds 0f82f64c832 [NFC][InstCombine] Copy test for omit urem when possible fr [...] adds f55818e3a72 [InstCombine] Omit 'urem' where possible adds 4f878fe3a7d [NFC][InstCombine] Tests for x - ~(y) -> x + y + 1 fold ( [...] adds 9cca81344c8 [clangd] Make PreambleStatusCache handle filenames more carefully adds 60300c9c7d6 [clangd] Fix unused var from r364735 adds d74f2d0a860 [benchmark] Disable CMake get_git_version adds ed13fef4774 [SelectionDAG] Do minnum->minimum at legalization time inst [...] adds 0f73709cb71 Remove null checks of results of new expressions adds 172fe5dd191 [X86] CombineShuffleWithExtract - updated description comme [...] adds 92e78b7bedb [RISCV] Add break; to the last switch case adds 881aab4dc3d [clangd] No longer getting template instantiations from hea [...] adds 4f0a3772805 Fix TestGdbRemoteLibrariesSvr4Support adds d5c3e34cb7e [NFC][InstCombine] Tests for ((~x) + y) + 1 -> y - x fold [...] adds 33c8c0ea275 [AMDGPU] Call isLoopExiting for blocks in the loop. adds 08c38f77c5f Revert "Implement xfer:libraries-svr4:read packet" adds 17c3eafb2e3 [ASTImporter] Propagate error from ImportDeclContext adds 77c04c3a577 @skipIfXmlSupportMissing TestRecognizeBreakpoint adds c12dfcf1f56 Don't check the validity of newly contructed data buffers adds 3a10810b7ab [mips] Add missing schedinfo for ADJCALLSTACKDOWN, ADJCALLSTACKUP adds c0121bf8741 [mips] Add missing schedinfo for atomic instructions adds ceb9da5bc79 [mips] Add missing schedinfo for MSA and ASE instructions adds fbf67d88de2 GlobalISel: Add DAG compat for G_FCANONICALIZE adds 01bb075c1f9 GlobalISel: Add GINodeEquiv for min/max adds 5dafcb9b118 AMDGPU/GlobalISel: Use and instead of BFE with inline immediate adds 9f992c238ab AMDGPU/GlobalISel: Fix scc->vcc copy handling adds facf69e8449 AMDGPU/GlobalISel: Use vcc reg bank for amdgcn.wqm.vote adds c23149f612d AMDGPU/GlobalISel: RegBankSelect for WWM/WQM adds 9f3645869cf [NFC][InstCombine] Improve test coverage for ((~x) + y) + [...] adds 3b7668ae4bb AMDGPU/GlobalISel: Improve icmp selection coverage. adds 89fc8bcdd6d AMDGPU/GlobalISel: Fail on store to 32-bit address space adds b5fc94f3e74 AMDGPU/GlobalISel: Fix RegBankSelect for G_BUILD_VECTOR adds 5bf850d52e0 AMDGPU/GlobalISel: Fix RegBankSelect for G_FCANONICALIZE adds 1b317685e9b AMDGPU: Convert some places to Register adds 511ad50db41 [Hexagon] Rework VLCR algorithm adds 1ad4b99d948 [ASTImporter] Mark erroneous nodes in from ctx adds 34a0b16e290 [NFC][InstCombine] Better commutative tests for "shift amou [...] adds 3f594ed1686 Fix lookup of symbols at the same address with no size vs. size adds 4f769361e35 [ASTImporter] Silence unused variable warning in Release bu [...] adds ee6539341bf [UpdateTestChecks][PowerPC] Avoid empty string when scrubbi [...] adds 535f39ce521 Revert "[lldb] [Process/NetBSD] Fix constructor after r363707" adds 28145735f7b [RISCV] Avoid save-restore target feature warning adds 2ba16011c13 Fixup r364512 adds 2b2ad9342e6 [lldb] [Process/NetBSD] Support reading YMM registers via P [...] adds baf64b65056 [lldb] [Process/NetBSD] Fix segfault when handling watchpoint adds 0856721e3a0 [lldb] [Process/NetBSD] Use global enable bits for watchpoints adds 4f64ade04cb AMDGPU/GlobalISel: Select src modifiers adds fb99fc7a689 AMDGPU: Fix tests using the default alloca address space adds 1daad91af69 AMDGPU/GlobalISel: Tolerate copies with no type set adds 2afbfb6b226 [ASTImporter] Mark erroneous nodes in shared st adds 6464280eb04 AMDGPU/GlobalISel: Select G_BRCOND for scc conditions adds fdf36729c71 AMDGPU/GlobalISel: Make s16 select legal adds 7cfd99ab15d AMDGPU/GFX10: fix scratch resource descriptor adds cda82f0bb6f AMDGPU/GlobalISel: Select G_FRAME_INDEX adds 5abf80cdfa3 [Hexagon] Custom-lower UADDO(x, 1) and USUBO(x, 1) adds 72b8d41ce81 [InstCombine] Shift amount reassociation in bittest (PR42399) adds 04d3d3bbff5 [InstCombine] (Y + ~X) + 1 --> Y - X fold (PR42459) adds 657f8c16c19 Update email address in CODE_OWNERS adds 4a9e3f15bbb [ARM] MVE: support QQPRRegClass and QQQQPRRegClass adds 2ab25f9ceb1 AMDGPU/GlobalISel: Select G_BRCOND for vcc adds 8b2e304bc57 [ARM] Fix MVE_VQxDMLxDH instruction class adds 9e9dd30de3a AMDGPU/GlobalISel: Implement select for 32-bit G_ADD adds ba41d3b1fd6 Fix -Wdouble-promotion warnings. adds 4603460a395 __threading_support: Remove (void) in favor of (). adds 90c57e00015 [docs][llvm-readelf] Expand llvm-readelf documentation adds 62d64b0c308 AMDGPU/GlobalISel: RegBankSelect for readlane/readfirstlane adds 3c125fe821c Implement LWG2221: 'Formatted output for nullptr_t' Reviewe [...] adds e3e38cce4ab [X86] Add widenSubVector to size in bits helper. NFCI. adds d810ff25888 AMDGPU/GlobalISel: Try to select VOP3 form of add adds e1006259d84 AMDGPU/GlobalISel: Select G_PHI adds 0a52e9d026a AMDGPU/GlobalISel: Complete implementation of G_GEP adds a310727830f AMDGPU/GlobalISel: Fail instead of assert when selecting loads adds 265059eaf6c AMDGPU/GlobalISel: RegBankSelect for amdgcn.writelane adds 8cae7d79b55 Summary: [Clangd] Added hidden command line option -tweaks [...] adds 732149b24eb AArch64/GlobalISel: Fix trying to select invalid MIR adds 1094e6a8143 AMDGPU/GlobalISel: RegBankSelect for DS ordered add/swap adds f01fa40a006 [ELF][RISCV] Support PLT, GOT, copy and relative relocations adds ddc57afab9e [ELF][RISCV] Support GD/LD/IE/LE TLS models adds 4dc3b2bf95b AMDGPU: Support GDS atomics adds 10c911db63e AMDGPU/GFX10: implement ds_ordered_count changes adds 6f74f557500 GlobalISel: Implement lower for min/max adds 40d1faf38f9 AMDGPU/GlobalISel: Legalize s16 fcmp adds e9345866809 [TSan] Improve handling of stack pointer mangling in {set,l [...] adds b2ea20eedd6 AMDGPU/GlobalISel: RegBankSelect for sendmsg/sendmsghalt adds b600ae37a52 [OPENMP]Fix handling of lambda captures in target regions. adds 1023a2eca3f [GlobalISel]: Allow backends to custom legalize Intrinsics adds 03ca176ab32 GlobalISel: Verify G_MERGE_VALUES operand sizes adds b7fb723ea38 [TSan] Fix initialized and declared ‘extern’ warning adds e62857786f9 [NFC][InstCombine] Add tests for "shift direction in bittes [...] adds 9470bb262b5 AMDGPU/GlobalISel: Fix allowing non-boolean conditions for [...] adds 55d2e6f1c26 [lldb] [lldbsuite] Use a unique class name for TestBacktraceAll adds ef59cb69822 AMDGPU/GlobalISel: Legalize s16 add/sub/mul adds 7f8c7209397 AMDGPU/GlobalISel: Add tests for add legalization adds e20030f6121 [X86] Avoid SFB - Fix inconsistent codegen with/without deb [...] adds 5a7d5111e58 AMDGPU/GlobalISel: Lower SALU min/max to cmp+select adds 4073b33786c AMDGPU/GlobalISel: Handle 16-bit SALU min/max adds e15770aec42 AMDGPU/GlobalISel: Custom lower control flow intrinsics adds e2c86cce3a2 AMDGPU/GlobalISel: Legalize workitem ID intrinsics adds 756d81905f6 AMDGPU/GlobalISel: Legalize workgroup ID intrinsics adds 9e8e8c60fa1 AMDGPU/GlobalISel: Lower kernarg segment ptr intrinsics adds bae3636f969 AMDGPU/GlobalISel: Handle more input argument intrinsics adds b101c39f587 Fixed two issues in clang-tidy -help. adds 5e7815b695d [X86] Correct v4f32->v2i64 cvt(t)ps2(u)qq memory isel patterns adds 73dec22c3ef AMDGPU: Revert accidental change to test adds 24edf8ef4b5 Implement P0646R1: Erase-Like Algorithms Should Return size [...] adds c9f14f29f5c GlobalISel: Try to widen merges with other merges adds d1523f7a8c2 Ensure bitset's string constructor doesn't poison the overl [...] adds 8b7a0baa20c Testing commit access through minor formatting change adds 975120a21b4 [NFC][InstCombine] More commutative tests for "shift direct [...] adds d7fcee62f11 [Core] Generalize ValueObject::IsRuntimeSupportValue No new revisions were added by this update. Summary of changes: .../clang-tidy/tool/ClangTidyMain.cpp | 4 +- clang-tools-extra/clangd/ClangdServer.cpp | 3 +- clang-tools-extra/clangd/ClangdServer.h | 7 +- clang-tools-extra/clangd/ClangdUnit.cpp | 3 +- clang-tools-extra/clangd/Diagnostics.cpp | 2 + clang-tools-extra/clangd/FS.cpp | 19 +- clang-tools-extra/clangd/SourceCode.cpp | 27 + clang-tools-extra/clangd/SourceCode.h | 8 + clang-tools-extra/clangd/XRefs.cpp | 76 +- clang-tools-extra/clangd/refactor/Rename.cpp | 43 +- .../clangd/test/fixits-duplication.test | 2 +- clang-tools-extra/clangd/tool/ClangdMain.cpp | 11 + .../clangd/unittests/ClangdUnitTests.cpp | 20 + .../clangd/unittests/DiagnosticsTests.cpp | 22 +- clang-tools-extra/clangd/unittests/FSTests.cpp | 12 +- clang-tools-extra/clangd/unittests/RenameTests.cpp | 7 + .../clangd/unittests/SourceCodeTests.cpp | 17 + clang-tools-extra/docs/clang-tidy/index.rst | 210 +-- clang/include/clang/AST/ASTImporter.h | 144 +- clang/include/clang/AST/ASTImporterSharedState.h | 80 + clang/include/clang/CrossTU/CrossTranslationUnit.h | 6 +- clang/include/clang/Sema/Sema.h | 4 + clang/lib/AST/ASTImporter.cpp | 112 +- clang/lib/CrossTU/CrossTranslationUnit.cpp | 10 +- clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 8 +- clang/lib/Frontend/ASTMerge.cpp | 6 +- clang/lib/Sema/SemaExpr.cpp | 2 + clang/lib/Sema/SemaOpenMP.cpp | 97 +- clang/lib/Tooling/CommonOptionsParser.cpp | 2 +- clang/test/Driver/riscv-features.c | 8 +- clang/test/OpenMP/nvptx_lambda_capturing.cpp | 10 +- clang/unittests/AST/ASTImporterFixtures.cpp | 45 +- clang/unittests/AST/ASTImporterFixtures.h | 28 +- clang/unittests/AST/ASTImporterTest.cpp | 367 +++- clang/utils/ClangVisualizers/clang.natvis | 54 +- compiler-rt/lib/tsan/rtl/tsan_interceptors.cc | 11 +- compiler-rt/lib/tsan/rtl/tsan_platform_linux.cc | 7 +- compiler-rt/lib/tsan/rtl/tsan_rtl.h | 1 - libcxx/include/__threading_support | 4 +- libcxx/include/bitset | 4 +- libcxx/include/forward_list | 43 +- libcxx/include/limits | 2 +- libcxx/include/list | 34 +- libcxx/include/ostream | 5 + libcxx/include/type_traits | 4 + libcxx/include/utility | 4 +- .../atomics.general/replace_failure_order.pass.cpp | 8 +- .../forwardlist/forwardlist.ops/remove.pass.cpp | 24 +- .../forwardlist/forwardlist.ops/remove_if.pass.cpp | 20 +- .../forwardlist/forwardlist.ops/unique.pass.cpp | 20 +- .../sequences/list/list.ops/remove.pass.cpp | 8 +- .../sequences/list/list.ops/remove_if.pass.cpp | 6 +- .../sequences/list/list.ops/unique.pass.cpp | 4 +- .../ostream.inserters/streambuf.pass.cpp | 7 + .../bitset.cons/string_ctor.pass.cpp | 13 + libcxx/www/cxx1z_status.html | 2 +- lld/ELF/Arch/RISCV.cpp | 154 +- lld/ELF/InputSection.cpp | 5 +- lld/ELF/Relocations.cpp | 2 +- lld/test/ELF/riscv-plt.s | 103 ++ lld/test/ELF/riscv-reloc-64-pic.s | 10 + lld/test/ELF/riscv-reloc-copy.s | 23 + lld/test/ELF/riscv-reloc-got.s | 65 + lld/test/ELF/riscv-tls-gd.s | 124 ++ lld/test/ELF/riscv-tls-ie.s | 82 + lld/test/ELF/riscv-tls-ld.s | 90 + lld/test/ELF/riscv-tls-le.s | 41 + lld/test/ELF/riscv32-reloc-32-pic.s | 23 + lld/test/ELF/riscv64-reloc-64-pic.s | 23 + .../lldb/Host/common/NativeProcessProtocol.h | 14 - lldb/include/lldb/Target/CPPLanguageRuntime.h | 2 +- lldb/include/lldb/Target/LanguageRuntime.h | 6 +- lldb/include/lldb/Target/ObjCLanguageRuntime.h | 3 +- lldb/lit/SymbolFile/Inputs/sizeless-symbol.s | 8 + lldb/lit/SymbolFile/sizeless-symbol.test | 14 + .../gdb_remote_client/TestRecognizeBreakpoint.py | 1 + .../thread/backtrace_all/TestBacktraceAll.py | 2 +- .../hello_watchlocation/TestWatchLocation.py | 1 - .../hello_watchpoint/TestMyFirstWatchpoint.py | 1 - .../watchpoint/multiple_hits/TestMultipleHits.py | 1 - .../TestWatchpointMultipleThreads.py | 2 - .../step_over_watchpoint/TestStepOverWatchpoint.py | 1 - .../watchpoint_commands/TestWatchpointCommands.py | 4 - .../command/TestWatchpointCommandLLDB.py | 2 - .../command/TestWatchpointCommandPython.py | 2 - .../condition/TestWatchpointConditionCmd.py | 1 - .../watchpoint_disable/TestWatchpointDisable.py | 1 - .../TestWatchLocationWithWatchSet.py | 1 - .../watchpoint_size/TestWatchpointSizes.py | 3 - .../test/tools/lldb-server/gdbremote_testcase.py | 29 +- .../test/tools/lldb-server/libraries-svr4/Makefile | 17 - .../TestGdbRemoteLibrariesSvr4Support.py | 130 -- .../test/tools/lldb-server/libraries-svr4/main.cpp | 15 - .../tools/lldb-server/libraries-svr4/svr4lib_a.cpp | 9 - .../tools/lldb-server/libraries-svr4/svr4lib_a.mk | 9 - .../lldb-server/libraries-svr4/svr4lib_b_quote.cpp | 9 - .../lldb-server/libraries-svr4/svr4lib_b_quote.mk | 9 - lldb/source/Core/ValueObject.cpp | 32 +- .../Plugins/ObjectFile/JIT/ObjectFileJIT.cpp | 14 +- .../RegisterContextPOSIXProcessMonitor_arm.cpp | 2 +- .../RegisterContextPOSIXProcessMonitor_arm64.cpp | 2 +- .../RegisterContextPOSIXProcessMonitor_mips64.cpp | 2 +- .../RegisterContextPOSIXProcessMonitor_powerpc.cpp | 2 +- .../RegisterContextPOSIXProcessMonitor_x86.cpp | 2 +- .../Plugins/Process/Linux/NativeProcessLinux.cpp | 2 +- .../Linux/NativeRegisterContextLinux_arm.cpp | 11 - .../Linux/NativeRegisterContextLinux_arm64.cpp | 11 - .../Linux/NativeRegisterContextLinux_mips64.cpp | 14 - .../Linux/NativeRegisterContextLinux_ppc64le.cpp | 11 - .../Linux/NativeRegisterContextLinux_s390x.cpp | 14 - .../Plugins/Process/NetBSD/NativeProcessNetBSD.cpp | 33 +- .../Plugins/Process/NetBSD/NativeProcessNetBSD.h | 4 +- .../NetBSD/NativeRegisterContextNetBSD_x86_64.cpp | 107 +- .../NetBSD/NativeRegisterContextNetBSD_x86_64.h | 10 +- .../Plugins/Process/POSIX/NativeProcessELF.cpp | 69 - .../Plugins/Process/POSIX/NativeProcessELF.h | 7 - .../Utility/RegisterContextDarwin_arm64.cpp | 4 +- .../Process/Utility/RegisterContextDarwin_i386.cpp | 3 +- .../Utility/RegisterContextDarwin_x86_64.cpp | 3 +- .../gdb-remote/GDBRemoteCommunicationClient.cpp | 7 + .../GDBRemoteCommunicationServerCommon.cpp | 1 - .../GDBRemoteCommunicationServerLLGS.cpp | 43 - .../gdb-remote/GDBRemoteCommunicationServerLLGS.h | 2 - .../SymbolFile/DWARF/DWARFASTParserClang.cpp | 3 +- lldb/source/Symbol/Function.cpp | 8 +- lldb/source/Symbol/Symtab.cpp | 10 +- lldb/source/Target/CPPLanguageRuntime.cpp | 16 +- lldb/source/Target/ObjCLanguageRuntime.cpp | 13 - llvm/CODE_OWNERS.TXT | 2 +- .../{llvm-readobj.rst => llvm-readelf.rst} | 231 +-- llvm/docs/CommandGuide/llvm-readobj.rst | 24 + .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 1 + .../llvm/CodeGen/GlobalISel/LegalizerInfo.h | 5 + llvm/include/llvm/IR/DebugInfoMetadata.h | 4 + llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 2 + .../llvm/Target/GlobalISel/SelectionDAGCompat.td | 5 + llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | 5 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 22 +- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 70 +- llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp | 6 + llvm/lib/CodeGen/HardwareLoops.cpp | 1 + llvm/lib/CodeGen/MachineVerifier.cpp | 10 + llvm/lib/CodeGen/PrologEpilogInserter.cpp | 13 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 22 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 11 + llvm/lib/IR/DebugInfoMetadata.cpp | 21 + .../Target/AArch64/AArch64InstructionSelector.cpp | 33 +- llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h | 15 +- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 161 +- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 17 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 441 +++-- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 15 +- llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 21 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 244 ++- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 18 + llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 361 +++- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h | 7 + .../Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 11 +- llvm/lib/Target/AMDGPU/DSInstructions.td | 88 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 29 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 +- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 2 + llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 7 +- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 9 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 +- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 10 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 47 +- llvm/lib/Target/ARM/ARMISelLowering.h | 2 + llvm/lib/Target/ARM/ARMInstrInfo.td | 8 + llvm/lib/Target/ARM/ARMInstrMVE.td | 15 +- llvm/lib/Target/ARM/ARMInstrThumb2.td | 10 +- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | 116 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 2 + llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 43 +- llvm/lib/Target/Hexagon/HexagonISelLowering.h | 1 + .../Hexagon/HexagonVectorLoopCarriedReuse.cpp | 220 ++- llvm/lib/Target/Mips/MipsDSPInstrInfo.td | 1 + llvm/lib/Target/Mips/MipsInstrInfo.td | 11 +- llvm/lib/Target/Mips/MipsMSAInstrInfo.td | 7 +- llvm/lib/Target/Mips/MipsScheduleP5600.td | 22 + llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 1 + .../Target/X86/X86AvoidStoreForwardingBlocks.cpp | 4 + llvm/lib/Target/X86/X86FastISel.cpp | 21 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 95 +- llvm/lib/Target/X86/X86InstrAVX512.td | 78 +- llvm/lib/Target/X86/X86InstrSSE.td | 12 + .../Transforms/InstCombine/InstCombineAddSub.cpp | 5 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 84 +- llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp | 56 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-add.mir | 56 + .../inst-select-amdgcn.kernarg.segment.ptr.mir | 19 - .../AMDGPU/GlobalISel/inst-select-anyext.mir | 36 + .../CodeGen/AMDGPU/GlobalISel/inst-select-br.mir | 21 + .../AMDGPU/GlobalISel/inst-select-brcond.mir | 198 +++ .../CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir | 170 +- .../GlobalISel/inst-select-fcanonicalize.mir | 164 ++ .../CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir | 190 +- .../AMDGPU/GlobalISel/inst-select-frame-index.mir | 38 + .../CodeGen/AMDGPU/GlobalISel/inst-select-gep.mir | 354 ++++ .../AMDGPU/GlobalISel/inst-select-icmp.s64.mir | 595 +++++++ .../AMDGPU/GlobalISel/inst-select-implicit-def.mir | 6 +- .../AMDGPU/GlobalISel/inst-select-load-smrd.mir | 44 +- .../AMDGPU/GlobalISel/inst-select-phi-invalid.mir | 31 + .../CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir | 385 ++++ .../AMDGPU/GlobalISel/inst-select-select.mir | 176 ++ .../CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir | 39 + .../CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir | 83 + .../CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir | 83 + .../CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir | 83 + .../CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir | 83 + .../CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir | 48 +- .../irtranslator-amdgpu_kernel-system-sgprs.ll | 118 +- .../AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll | 2 +- .../AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll | 18 +- .../GlobalISel/irtranslator-fast-math-flags.ll | 2 +- .../CodeGen/AMDGPU/GlobalISel/legalize-add.mir | 233 ++- .../GlobalISel/legalize-amdgcn.if-invalid.mir | 73 + .../CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir | 126 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir | 323 +++- .../CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir | 20 +- .../AMDGPU/GlobalISel/legalize-merge-values.mir | 345 +++- .../CodeGen/AMDGPU/GlobalISel/legalize-mul.mir | 285 ++- .../CodeGen/AMDGPU/GlobalISel/legalize-select.mir | 110 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sub.mir | 146 +- .../AMDGPU/GlobalISel/llvm.amdgcn.dispatch.id.ll | 19 + .../AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll | 18 + .../GlobalISel/llvm.amdgcn.implicit.buffer.ptr.ll | 17 + .../GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll | 125 ++ .../AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll | 18 + .../AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll | 106 ++ .../AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll | 92 + .../regbankselect-amdgcn.ds.ordered.add.mir | 71 + .../regbankselect-amdgcn.ds.ordered.swap.mir | 71 + .../regbankselect-amdgcn.readfirstlane.mir | 32 + .../GlobalISel/regbankselect-amdgcn.readlane.mir | 71 + .../GlobalISel/regbankselect-amdgcn.s.sendmsg.mir | 32 + .../regbankselect-amdgcn.s.sendmsghalt.mir | 32 + .../AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir | 31 + ...-vote.mir => regbankselect-amdgcn.wqm.vote.mir} | 10 +- .../GlobalISel/regbankselect-amdgcn.writelane.mir | 98 ++ .../AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir | 31 + .../GlobalISel/regbankselect-build-vector.mir | 69 + .../GlobalISel/regbankselect-fcanonicalize.mir | 35 + .../AMDGPU/GlobalISel/regbankselect-phi.mir | 1849 +++++++++++++------- .../AMDGPU/GlobalISel/regbankselect-select.mir | 1451 ++++++++++----- .../AMDGPU/GlobalISel/regbankselect-smax.mir | 170 +- .../AMDGPU/GlobalISel/regbankselect-smin.mir | 170 +- .../AMDGPU/GlobalISel/regbankselect-umax.mir | 170 +- .../AMDGPU/GlobalISel/regbankselect-umin.mir | 170 +- llvm/test/CodeGen/AMDGPU/gds-atomic.ll | 128 ++ .../AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll | 23 + llvm/test/CodeGen/AMDGPU/loop-idiom.ll | 13 +- llvm/test/CodeGen/AMDGPU/scratch-simple.ll | 65 +- llvm/test/CodeGen/AMDGPU/unroll.ll | 17 +- ...exagon_vector_loop_carried_reuse_commutative.ll | 82 + llvm/test/CodeGen/Hexagon/isel-uaddo-1.ll | 37 + llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll | 178 +- .../Thumb2/LowOverheadLoops}/cond-mov.mir | 0 .../CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll | 213 +++ .../Thumb2/LowOverheadLoops}/massive.mir | 0 .../LowOverheadLoops}/multiblock-massive.mir | 0 .../Thumb2/LowOverheadLoops}/revert-after-call.mir | 0 .../LowOverheadLoops}/revert-after-spill.mir | 0 .../Thumb2/LowOverheadLoops/revert-while.mir | 130 ++ .../Thumb2/LowOverheadLoops}/size-limit.mir | 0 .../Thumb2/LowOverheadLoops}/switch.mir | 0 .../test/CodeGen/Thumb2/LowOverheadLoops/while.mir | 131 ++ llvm/test/CodeGen/WebAssembly/f32.ll | 18 + llvm/test/CodeGen/WebAssembly/simd-arith.ll | 22 + llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir | 198 +++ llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir | 223 +++ llvm/test/CodeGen/X86/avx512dqvl-intrinsics.ll | 655 ++++++- .../CodeGen/X86/merge-consecutive-loads-128.ll | 3 +- llvm/test/CodeGen/X86/pr42452.ll | 37 + llvm/test/CodeGen/X86/vec_fp_to_int-widen.ll | 150 ++ llvm/test/CodeGen/X86/vec_fp_to_int.ll | 150 ++ llvm/test/CodeGen/X86/vec_int_to_fp-widen.ll | 794 +++++++-- llvm/test/CodeGen/X86/vec_int_to_fp.ll | 472 +++-- .../MIR/X86/prolog-epilog-indirection.mir | 130 ++ llvm/test/MachineVerifier/test_g_merge_values.mir | 28 + llvm/test/Transforms/HardwareLoops/ARM/do-rem.ll | 32 +- .../Transforms/HardwareLoops/ARM/fp-emulation.ll | 23 +- .../test/Transforms/HardwareLoops/ARM/simple-do.ll | 42 +- .../test/Transforms/HardwareLoops/ARM/structure.ll | 95 +- llvm/test/Transforms/InstCombine/add.ll | 10 +- ...ld-inc-of-add-of-not-x-and-y-to-sub-x-from-y.ll | 213 +++ .../InstCombine/fold-sub-of-not-to-inc-of-add.ll | 94 + ...ower-of-two-or-zero-when-comparing-with-zero.ll | 166 ++ .../shift-amount-reassociation-in-bittest.ll | 318 ++-- .../InstCombine/shift-direction-in-bit-test.ll | 279 +++ .../SimpleLoopUnswitch/basictest-profmd.ll | 34 + .../SimpleLoopUnswitch/trivial-unswitch-profmd.ll | 228 +++ .../CodeGen/GlobalISel/LegalizerHelperTest.cpp | 78 + llvm/utils/LLVMVisualizers/llvm.natvis | 19 +- llvm/utils/UpdateTestChecks/asm.py | 4 +- llvm/utils/benchmark/CMakeLists.txt | 7 +- llvm/utils/benchmark/README.LLVM | 2 + 297 files changed, 17529 insertions(+), 3697 deletions(-) create mode 100644 clang/include/clang/AST/ASTImporterSharedState.h create mode 100644 lld/test/ELF/riscv-plt.s create mode 100644 lld/test/ELF/riscv-reloc-64-pic.s create mode 100644 lld/test/ELF/riscv-reloc-copy.s create mode 100644 lld/test/ELF/riscv-reloc-got.s create mode 100644 lld/test/ELF/riscv-tls-gd.s create mode 100644 lld/test/ELF/riscv-tls-ie.s create mode 100644 lld/test/ELF/riscv-tls-ld.s create mode 100644 lld/test/ELF/riscv-tls-le.s create mode 100644 lld/test/ELF/riscv32-reloc-32-pic.s create mode 100644 lld/test/ELF/riscv64-reloc-64-pic.s create mode 100644 lldb/lit/SymbolFile/Inputs/sizeless-symbol.s create mode 100644 lldb/lit/SymbolFile/sizeless-symbol.test delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] copy llvm/docs/CommandGuide/{llvm-readobj.rst => llvm-readelf.rst} (57%) create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.kernarg. [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-gep.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi-invalid.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if-invalid.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.id.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.buffer.ptr.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ord [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ord [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfi [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.send [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir rename llvm/test/CodeGen/AMDGPU/GlobalISel/{regbankselect-amdgcn-wqm-vote.mir => r [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir create mode 100644 llvm/test/CodeGen/AMDGPU/gds-atomic.ll create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll create mode 100644 llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_com [...] create mode 100644 llvm/test/CodeGen/Hexagon/isel-uaddo-1.ll rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir create mode 100644 llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir create mode 100644 llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir create mode 100644 llvm/test/CodeGen/X86/pr42452.ll create mode 100644 llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir create mode 100644 llvm/test/MachineVerifier/test_g_merge_values.mir create mode 100644 llvm/test/Transforms/InstCombine/fold-inc-of-add-of-not-x-and-y [...] create mode 100644 llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll create mode 100644 llvm/test/Transforms/InstCombine/omit-urem-of-power-of-two-or-z [...] create mode 100644 llvm/test/Transforms/InstCombine/shift-direction-in-bit-test.ll create mode 100644 llvm/test/Transforms/SimpleLoopUnswitch/basictest-profmd.ll create mode 100644 llvm/test/Transforms/SimpleLoopUnswitch/trivial-unswitch-profmd.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allnoconfig updated (b8f88bc6e -> 3b931cfd9)

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This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-allnoconfig in repository toolchain/ci/base-artifacts. discards b8f88bc6e 0: update: llvm-linux: all new 3b931cfd9 0: update: llvm-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (b8f88bc6e) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/llvm-master-arm-s [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 220 +- 02-build_llvm/console.log | 11948 +++++++++++++++++----------------- 03-build_linux/console.log | 812 +-- 04-boot_linux/console.log | 2 +- 05-check_regression/console.log | 6 +- 06-update_baseline/console.log | 25 + console.log | 13013 +++++++++++++++++++------------------- jenkins/manifest.sh | 8 +- 8 files changed, 13046 insertions(+), 12988 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 5 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-allmodconfig updated (7f1c798dcc -> 54ee425275)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-allmodconfig in repository toolchain/ci/binutils-gdb. from 7f1c798dcc Automatic date update in version.in adds c444fad6da Automatic date update in version.in adds 219920a7c4 x86: drop a few dead macros adds 36cc073ef4 x86: remove ModRM.mod decoding layer from AVX512F VMOVS{S,D} adds 9c33702be7 x86: warn about insns exceeding the 15-byte limit adds d583596cc9 x86: use encoding_length() also elsewhere adds e3bba3fc75 x86: drop bogus Disp8MemShift attributes adds cd546e7bd2 x86: add missing pseudo ops for VPCLMULQDQ ISA extension adds a0a1771e89 x86: optimize EVEX packed integer logical instructions adds a80195f122 x86: StaticRounding implies SAE adds 79dec6b7ba x86-64: optimize certain commutative VEX-encoded insns adds 5641ec015a x86: optimize AND/OR with twice the same register adds c3949f432f x86: limit ImmExt abuse adds 9d3bf266fd x86: drop Vec_Imm4 adds 900e33b9cf Fix spelling error in assembler documentation. adds c550e7ba93 libctf: disambiguate hex output in dumps adds 3e10cffc98 libctf: fix hash removal adds 9658dc3963 libctf: add hash traversal helpers adds f5e9c9bde0 libctf: deduplicate and sort the string table adds f57cf0e3e3 libctf: fix spurious error when rolling back to the first snapshot adds 539300fb92 Correct the calculation of offsets for ARM exidx relocs when [...] adds a6ce99e987 Correct a typo in the description of the Align and P2align d [...] adds f2f51cd5f5 Document the .value directive supported by the x86 and x86_6 [...] adds 65392b3edd Remove is_a_field_of_this from ada_lookup_symbol adds 41be57caf3 [gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AES adds 269b4ded72 Fix bug when generating REL type relocs for assembler genera [...] adds 54ee425275 Avoid use-after-free in DWARF debug names code No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 6 + bfd/elf32-arm.c | 2 +- bfd/version.h | 2 +- gas/ChangeLog | 160 + gas/config/tc-i386.c | 232 +- gas/doc/as.texi | 6 +- gas/doc/c-aarch64.texi | 3 +- gas/doc/c-i386.texi | 26 +- gas/testsuite/gas/aarch64/illegal-sve2-aes.d | 4 - gas/testsuite/gas/aarch64/illegal-sve2.l | 18 +- gas/testsuite/gas/aarch64/illegal-sve2.s | 10 + gas/testsuite/gas/aarch64/sve2.d | 2 + gas/testsuite/gas/aarch64/sve2.s | 4 + gas/testsuite/gas/i386/avx512f_vpclmulqdq-intel.d | 4 + gas/testsuite/gas/i386/avx512f_vpclmulqdq.d | 4 + gas/testsuite/gas/i386/avx512f_vpclmulqdq.s | 5 + gas/testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d | 8 + gas/testsuite/gas/i386/avx512vl_vpclmulqdq.d | 8 + gas/testsuite/gas/i386/avx512vl_vpclmulqdq.s | 10 + gas/testsuite/gas/i386/i386.exp | 5 + gas/testsuite/gas/i386/ilp32/x86-64-sse2avx.d | 1226 +- gas/testsuite/gas/i386/optimize-1.d | 48 + gas/testsuite/gas/i386/optimize-1.s | 54 + gas/testsuite/gas/i386/optimize-1a.d | 48 + gas/testsuite/gas/i386/optimize-2.d | 70 + gas/testsuite/gas/i386/optimize-2.s | 80 + .../gas/i386/{optimize-2.d => optimize-2b.d} | 83 +- gas/testsuite/gas/i386/optimize-3.d | 8 + gas/testsuite/gas/i386/optimize-3.s | 9 + gas/testsuite/gas/i386/optimize-4.d | 48 + gas/testsuite/gas/i386/optimize-5.d | 56 + gas/testsuite/gas/i386/optimize-5.s | 9 + gas/testsuite/gas/i386/oversized16.l | 41 + gas/testsuite/gas/i386/oversized16.s | 11 + gas/testsuite/gas/i386/oversized64.l | 40 + gas/testsuite/gas/i386/oversized64.s | 10 + gas/testsuite/gas/i386/vpclmulqdq-intel.d | 4 + gas/testsuite/gas/i386/vpclmulqdq.d | 4 + gas/testsuite/gas/i386/vpclmulqdq.s | 5 + gas/testsuite/gas/i386/x86-64-avx-swap-2.d | 380 + gas/testsuite/gas/i386/x86-64-avx-swap-2.s | 393 + .../gas/i386/x86-64-avx512f_vpclmulqdq-intel.d | 4 + gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d | 4 + gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s | 5 + .../gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d | 8 + .../gas/i386/x86-64-avx512vl_vpclmulqdq.d | 8 + .../gas/i386/x86-64-avx512vl_vpclmulqdq.s | 10 + gas/testsuite/gas/i386/x86-64-optimize-2.d | 48 + gas/testsuite/gas/i386/x86-64-optimize-2.s | 54 + gas/testsuite/gas/i386/x86-64-optimize-2a.d | 48 + gas/testsuite/gas/i386/x86-64-optimize-2b.d | 48 + gas/testsuite/gas/i386/x86-64-optimize-3.d | 80 + gas/testsuite/gas/i386/x86-64-optimize-3.s | 91 + .../{x86-64-optimize-3.d => x86-64-optimize-3b.d} | 109 +- gas/testsuite/gas/i386/x86-64-optimize-4.d | 8 + gas/testsuite/gas/i386/x86-64-optimize-4.s | 9 + gas/testsuite/gas/i386/x86-64-optimize-5.d | 48 + gas/testsuite/gas/i386/x86-64-optimize-6.d | 56 + gas/testsuite/gas/i386/x86-64-optimize-6.s | 9 + gas/testsuite/gas/i386/x86-64-sse2avx.d | 93 + gas/testsuite/gas/i386/x86-64-sse2avx.s | 93 + gas/testsuite/gas/i386/x86-64-vpclmulqdq-intel.d | 16 +- gas/testsuite/gas/i386/x86-64-vpclmulqdq.d | 16 +- gas/testsuite/gas/i386/x86-64-vpclmulqdq.s | 17 +- gas/write.c | 22 +- gdb/ChangeLog | 14 + gdb/ada-exp.y | 2 +- gdb/ada-lang.c | 12 +- gdb/ada-lang.h | 2 +- gdb/dwarf2read.c | 9 +- include/ChangeLog | 5 + include/opcode/aarch64.h | 2 +- ld/ChangeLog | 6 + ld/testsuite/ld-arm/unwind-4.d | 2 + libctf/ChangeLog | 76 + libctf/Makefile.am | 2 +- libctf/Makefile.in | 12 +- libctf/ctf-create.c | 185 +- libctf/ctf-dump.c | 6 +- libctf/ctf-hash.c | 52 +- libctf/ctf-impl.h | 49 +- libctf/ctf-open.c | 2 + libctf/ctf-string.c | 330 + libctf/ctf-util.c | 35 +- opcodes/ChangeLog | 116 + opcodes/aarch64-asm.c | 4 +- opcodes/aarch64-dis-2.c | 594 +- opcodes/aarch64-dis.c | 13 +- opcodes/aarch64-tbl.h | 15 +- opcodes/i386-dis-evex-mod.h | 20 - opcodes/i386-dis-evex-prefix.h | 10 +- opcodes/i386-dis-evex-w.h | 34 +- opcodes/i386-dis.c | 22 +- opcodes/i386-gen.c | 3 - opcodes/i386-init.h | 105 +- opcodes/i386-opc.h | 4 - opcodes/i386-opc.tbl | 457 +- opcodes/i386-tbl.h | 20462 ++++++++++--------- 98 files changed, 14361 insertions(+), 12351 deletions(-) copy gas/testsuite/gas/i386/{optimize-2.d => optimize-2b.d} (56%) create mode 100644 gas/testsuite/gas/i386/oversized16.l create mode 100644 gas/testsuite/gas/i386/oversized16.s create mode 100644 gas/testsuite/gas/i386/oversized64.l create mode 100644 gas/testsuite/gas/i386/oversized64.s create mode 100644 gas/testsuite/gas/i386/x86-64-avx-swap-2.d create mode 100644 gas/testsuite/gas/i386/x86-64-avx-swap-2.s copy gas/testsuite/gas/i386/{x86-64-optimize-3.d => x86-64-optimize-3b.d} (55%) create mode 100644 libctf/ctf-string.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-allmodconfig updated (5d33b30a2 -> 0b1e5965d)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-aarch64-next-allmodconfig in repository toolchain/ci/base-artifacts. discards 5d33b30a2 0: update: binutils-gcc-linux: all new 0b1e5965d 0: update: binutils-54ee425275c759438d90c40781e3810a551f0a5f: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (5d33b30a2) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-aarch6 [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 129 +- 02-prepare_abe/console.log | 434 +- 03-build_abe-binutils/console.log | 9825 +++++++------- 04-build_abe-stage1/console.log | 15224 ++++++++++----------- 05-build_linux/console.log | 546 +- 06-boot_linux/console.log | 2 +- console.log | 26218 ++++++++++++++++++------------------ jenkins/manifest.sh | 12 +- 8 files changed, 25712 insertions(+), 26678 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 5 months

[toolchain/ci/gcc] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allnoconfig updated (b967edfe7e2 -> ccc199230b1)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allnoconfig in repository toolchain/ci/gcc. from b967edfe7e2 * config/i386/i386.md (mmx_isa): Rename x64, x64_noavx and [...] adds f45da3c5d95 * config/i386/sse.md (ssse3_abs<mode>2): Rename from abs<m [...] adds 6b18cddd747 Daily bump. adds 5b355ddd812 gcc/ adds 87ee9f7a511 2019-07-01 Richard Biener <rguenther(a)suse.de> adds ee5b48dc12d 2019-07-01 Richard Biener <rguenther(a)suse.de> adds 4606134eb0d 2019-07-01 Dominique d'Humieres <dominiq(a)gcc.gnu.org> adds 01ae1ec0045 gdbhooks.py: rename parameters to match usage adds 513fad55c57 Fix 2 clang warnings. adds 3d2484d6eea Use alternative_mask for add_insn_allocno_copies adds 8c24981087b Simplify ira_setup_alts adds 460bce5dc61 Make ira_get_dup_out_num handle more cases adds 341b1932c53 Allow earlyclobbers in ira_get_dup_out_num adds f278a92ec6a Use ira_setup_alts for conflict detection adds e967dff897f PR lto/91028 PR lto/90720 * g++.dg/lto/alias-1_0.C: Add [...] adds 487da8fffa2 [Ada] Fix formatting issues in the gnat_ugn documentation adds 0dae8dc23d5 [Ada] Crash due to missing freeze nodes in transient scope adds 7362896bd8d [Ada] Compiler abort on use of Invalid_Value on numeric pos [...] adds b0111d9409c [Ada] GNAT.Sockets: fix Get_Address when AF_INET6 is not defined adds 830a2a71658 [Ada] Implement GNAT.Graphs adds 5051fe355cc [Ada] Disable expansion of 'Min/'Max of floating point types adds 216ffc643ed [Ada] Minor reformatting adds 17fdf8c20ee [Ada] Clean up of GNAT.Dynamic_HTables adds 205a23a3a03 [Ada] Clean up of GNAT.Lists adds a0d15509f95 [Ada] Clean up of GNAT.Sets adds 175c4526c93 [Ada] Clean up of GNAT.Graphs adds 2c6b4adae55 [Ada] Fix "componant" typos in comments adds ee4279efe7c [Ada] Revert "Global => null" on calendar routines that use [...] adds 0a1ece97cc5 [Ada] Improve error message on mult/div between fixed-point [...] adds 2cf822b7be0 [Ada] gprbuild fails to find ghost ALI files adds cdee70d7970 [Ada] Incorrect definition of Win32 compatible types adds 6b4f0b7ddcc [Ada] Correct size in representation clauses documentation adds 2db33bd6f69 [Ada] Unnesting: improve handling of private and incomplete types adds bcb5ab8376f [Ada] Make No_Inline pragma effective for protected subprograms adds 830501b5a43 2019-07-01 Richard Biener <rguenther(a)suse.de> adds 866fa2d0594 [Ada] Wrong code with -gnatVa on lock-free protected objects adds bf13a79d6d4 [Ada] Cleanup references to LynuxWorks in docs and comments adds 374fdf942ed [Ada] Remove a SPARK rule about implicit Global adds b20f7e2cf7f [Ada] Crash on improper pragma Weak_External adds fe48ee0a1a7 [Ada] GNAT.Sockets: refactor Has_Sockaddr_Len adds d087b9ca787 [Ada] SPARK support for pointers through ownership adds bcb8dcf380a [Ada] Spurious error private subtype derivation adds 9d27ea41321 [Ada] Make No_Inline pragma effective for generic subprograms adds fc8ae4965c1 [Ada] More permissive use of GNAT attribute Enum_Rep adds 7a42b778e76 [Ada] Minor reformatting adds d21e66fbb83 [Ada] Spurious error on inst. of partially defaulted formal [...] adds 15a46039865 S/390: Fix vector shift count operand adds efd2d37a440 Fix changelog entry. adds 10ba1f38764 rs6000: Improve indexed addressing adds 60d7d138646 2019-07-01 Sandra Loosemore <sandra(a)codesourcery.com> adds d9f9a289e04 PR middle-end/64242 * config/sparc/sparc.md (nonlocal_got [...] adds b031d0ddbe3 PR target/90963 * config/pa/pa.md (builtin_longjmp): Rest [...] new 857ca76e646 PR middle-end/90923 - hash_map destroys elements without co [...] new acf2650a7b2 @neg<mode>2 new b16a7addc33 @fix_trunc<mode>si2_fprs new f2ce4d065d6 @abs<mode>2_internal new 33dd25d4562 @indirect_jump<mode>_nospec new 49e4b4494a5 @ctr<mode> new 8dedfb93add @eh_set_lr_<mode> new 66f1b2c57e3 @extenddf<mode>2_{fprs,vsx} new 7cb5254a4fa * config/i386/i386.md ("isa" attribute): Add sse_noavx. ( [...] new bab9b531b88 @extenddf<mode>2 new ef1c51078ee @neg<mode>2_hw new f6fd219cdf9 @abs<mode>2_hw new 2d3c0a1392f @ieee_128bit_vsx_neg<mode>2 new 7433985c06a @ieee_128bit_vsx_abs<mode>2 new ccc199230b1 * config/i386/constraints.md: Remove stalled comment w.r.t [...] The 15 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: gcc/ChangeLog | 191 + gcc/DATESTAMP | 2 +- gcc/ada/ChangeLog | 197 + gcc/ada/Makefile.rtl | 1 + gcc/ada/checks.adb | 13 + .../gnat_rm/representation_clauses_and_pragmas.rst | 25 +- .../building_executable_programs_with_gnat.rst | 4 +- gcc/ada/einfo.adb | 4 +- gcc/ada/exp_attr.adb | 17 +- gcc/ada/exp_ch7.adb | 9 +- gcc/ada/exp_ch9.adb | 4 + gcc/ada/exp_unst.adb | 38 +- gcc/ada/freeze.adb | 19 +- gcc/ada/gcc-interface/Make-lang.in | 1 + gcc/ada/gnat1drv.adb | 8 +- gcc/ada/gnat_rm.texi | 27 +- gcc/ada/gnat_ugn.texi | 18 +- gcc/ada/gsocket.h | 8 +- gcc/ada/impunit.adb | 1 + gcc/ada/libgnat/a-calend.ads | 19 +- gcc/ada/libgnat/g-dynhta.adb | 286 +- gcc/ada/libgnat/g-dynhta.ads | 71 +- gcc/ada/libgnat/g-graphs.adb | 1459 +++++ gcc/ada/libgnat/g-graphs.ads | 527 ++ gcc/ada/libgnat/g-lists.adb | 170 +- gcc/ada/libgnat/g-lists.ads | 84 +- gcc/ada/libgnat/g-sets.adb | 82 +- gcc/ada/libgnat/g-sets.ads | 54 +- gcc/ada/libgnat/g-sothco.adb | 9 +- gcc/ada/libgnat/s-win32.ads | 9 +- gcc/ada/sem_attr.adb | 8 +- gcc/ada/sem_ch12.adb | 50 +- gcc/ada/sem_ch3.adb | 17 +- gcc/ada/sem_ch4.adb | 22 +- gcc/ada/sem_ch7.adb | 2 +- gcc/ada/sem_prag.adb | 8 +- gcc/ada/sem_spark.adb | 5748 ++++++++++---------- gcc/ada/sem_spark.ads | 8 +- gcc/ada/sem_util.adb | 8 +- gcc/ada/sysdep.c | 1 - gcc/ada/uintp.adb | 89 +- gcc/ada/uintp.ads | 6 +- gcc/c/ChangeLog | 6 + gcc/c/gimple-parser.c | 9 +- gcc/config/i386/constraints.md | 1 - gcc/config/i386/i386-builtin.def | 6 +- gcc/config/i386/i386.md | 4 +- gcc/config/i386/mmx.md | 24 +- gcc/config/i386/sse.md | 8 +- gcc/config/pa/pa.md | 6 +- gcc/config/rs6000/rs6000.c | 11 +- gcc/config/rs6000/rs6000.md | 130 +- gcc/config/s390/vector.md | 2 +- gcc/config/sparc/sparc.md | 18 +- gcc/doc/invoke.texi | 43 +- gcc/doc/sourcebuild.texi | 3 + gcc/edit-context.c | 4 +- gcc/gdbhooks.py | 8 +- gcc/ggc-page.c | 6 +- gcc/hash-map-tests.c | 134 + gcc/hash-map.h | 37 +- gcc/hash-set-tests.c | 154 + gcc/hash-set.h | 12 +- gcc/hash-table.h | 14 +- gcc/ira-conflicts.c | 4 +- gcc/ira-int.h | 4 +- gcc/ira-lives.c | 9 +- gcc/ira.c | 130 +- gcc/passes.def | 7 +- gcc/testsuite/ChangeLog | 76 + gcc/testsuite/g++.dg/cpp0x/gen-attrs-67.C | 2 +- gcc/testsuite/g++.dg/lto/alias-1_0.C | 4 +- gcc/testsuite/g++.dg/lto/alias-2_0.C | 4 +- gcc/testsuite/gcc.dg/gimplefe-42.c | 18 + gcc/testsuite/gcc.dg/tree-ssa/pr77445-2.c | 8 +- .../i386/avx512vp2intersect-2intersect-1b.c | 1 + .../i386/avx512vp2intersect-2intersectvl-1b.c | 1 + gcc/testsuite/gcc.target/s390/vector/vec-shift-2.c | 24 + gcc/testsuite/gnat.dg/derived_type6.adb | 5 + gcc/testsuite/gnat.dg/derived_type6.ads | 9 + gcc/testsuite/gnat.dg/dynhash.adb | 41 +- gcc/testsuite/gnat.dg/dynhash1.adb | 8 +- gcc/testsuite/gnat.dg/enum_rep.adb | 5 + gcc/testsuite/gnat.dg/enum_rep.ads | 22 + gcc/testsuite/gnat.dg/freezing1.adb | 5 + gcc/testsuite/gnat.dg/freezing1.ads | 10 + gcc/testsuite/gnat.dg/freezing1_pack.adb | 8 + gcc/testsuite/gnat.dg/freezing1_pack.ads | 16 + gcc/testsuite/gnat.dg/generic_inst3.adb | 20 + .../gnat.dg/generic_inst3_kafka_lib-topic.ads | 7 + gcc/testsuite/gnat.dg/generic_inst3_kafka_lib.ads | 2 + gcc/testsuite/gnat.dg/generic_inst3_markets.ads | 10 + .../gnat.dg/generic_inst3_traits-encodables.ads | 8 + gcc/testsuite/gnat.dg/generic_inst3_traits.ads | 3 + gcc/testsuite/gnat.dg/linkedlist.adb | 72 +- gcc/testsuite/gnat.dg/prot7.adb | 22 + gcc/testsuite/gnat.dg/prot7.ads | 16 + gcc/testsuite/gnat.dg/sets1.adb | 48 +- gcc/testsuite/gnat.dg/weak3.adb | 11 + gcc/testsuite/gnat.dg/weak3.ads | 3 + gcc/testsuite/lib/target-supports.exp | 14 + gcc/tree-ssa-sccvn.c | 68 +- 102 files changed, 6973 insertions(+), 3716 deletions(-) create mode 100644 gcc/ada/libgnat/g-graphs.adb create mode 100644 gcc/ada/libgnat/g-graphs.ads create mode 100644 gcc/testsuite/gcc.dg/gimplefe-42.c create mode 100644 gcc/testsuite/gcc.target/s390/vector/vec-shift-2.c create mode 100644 gcc/testsuite/gnat.dg/derived_type6.adb create mode 100644 gcc/testsuite/gnat.dg/derived_type6.ads create mode 100644 gcc/testsuite/gnat.dg/enum_rep.adb create mode 100644 gcc/testsuite/gnat.dg/enum_rep.ads create mode 100644 gcc/testsuite/gnat.dg/freezing1.adb create mode 100644 gcc/testsuite/gnat.dg/freezing1.ads create mode 100644 gcc/testsuite/gnat.dg/freezing1_pack.adb create mode 100644 gcc/testsuite/gnat.dg/freezing1_pack.ads create mode 100644 gcc/testsuite/gnat.dg/generic_inst3.adb create mode 100644 gcc/testsuite/gnat.dg/generic_inst3_kafka_lib-topic.ads create mode 100644 gcc/testsuite/gnat.dg/generic_inst3_kafka_lib.ads create mode 100644 gcc/testsuite/gnat.dg/generic_inst3_markets.ads create mode 100644 gcc/testsuite/gnat.dg/generic_inst3_traits-encodables.ads create mode 100644 gcc/testsuite/gnat.dg/generic_inst3_traits.ads create mode 100644 gcc/testsuite/gnat.dg/prot7.adb create mode 100644 gcc/testsuite/gnat.dg/prot7.ads create mode 100644 gcc/testsuite/gnat.dg/weak3.adb create mode 100644 gcc/testsuite/gnat.dg/weak3.ads -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 5 months

[toolchain/ci/binutils-gdb] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allnoconfig updated (7f1c798dcc -> 54ee425275)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allnoconfig in repository toolchain/ci/binutils-gdb. from 7f1c798dcc Automatic date update in version.in adds c444fad6da Automatic date update in version.in adds 219920a7c4 x86: drop a few dead macros adds 36cc073ef4 x86: remove ModRM.mod decoding layer from AVX512F VMOVS{S,D} adds 9c33702be7 x86: warn about insns exceeding the 15-byte limit adds d583596cc9 x86: use encoding_length() also elsewhere adds e3bba3fc75 x86: drop bogus Disp8MemShift attributes adds cd546e7bd2 x86: add missing pseudo ops for VPCLMULQDQ ISA extension adds a0a1771e89 x86: optimize EVEX packed integer logical instructions adds a80195f122 x86: StaticRounding implies SAE adds 79dec6b7ba x86-64: optimize certain commutative VEX-encoded insns adds 5641ec015a x86: optimize AND/OR with twice the same register adds c3949f432f x86: limit ImmExt abuse adds 9d3bf266fd x86: drop Vec_Imm4 adds 900e33b9cf Fix spelling error in assembler documentation. adds c550e7ba93 libctf: disambiguate hex output in dumps adds 3e10cffc98 libctf: fix hash removal adds 9658dc3963 libctf: add hash traversal helpers adds f5e9c9bde0 libctf: deduplicate and sort the string table adds f57cf0e3e3 libctf: fix spurious error when rolling back to the first snapshot adds 539300fb92 Correct the calculation of offsets for ARM exidx relocs when [...] adds a6ce99e987 Correct a typo in the description of the Align and P2align d [...] adds f2f51cd5f5 Document the .value directive supported by the x86 and x86_6 [...] adds 65392b3edd Remove is_a_field_of_this from ada_lookup_symbol adds 41be57caf3 [gas][aarch64][SVE2] Fix pmull{t,b} requirement on SVE2-AES adds 269b4ded72 Fix bug when generating REL type relocs for assembler genera [...] adds 54ee425275 Avoid use-after-free in DWARF debug names code No new revisions were added by this update. Summary of changes: bfd/ChangeLog | 6 + bfd/elf32-arm.c | 2 +- bfd/version.h | 2 +- gas/ChangeLog | 160 + gas/config/tc-i386.c | 232 +- gas/doc/as.texi | 6 +- gas/doc/c-aarch64.texi | 3 +- gas/doc/c-i386.texi | 26 +- gas/testsuite/gas/aarch64/illegal-sve2-aes.d | 4 - gas/testsuite/gas/aarch64/illegal-sve2.l | 18 +- gas/testsuite/gas/aarch64/illegal-sve2.s | 10 + gas/testsuite/gas/aarch64/sve2.d | 2 + gas/testsuite/gas/aarch64/sve2.s | 4 + gas/testsuite/gas/i386/avx512f_vpclmulqdq-intel.d | 4 + gas/testsuite/gas/i386/avx512f_vpclmulqdq.d | 4 + gas/testsuite/gas/i386/avx512f_vpclmulqdq.s | 5 + gas/testsuite/gas/i386/avx512vl_vpclmulqdq-intel.d | 8 + gas/testsuite/gas/i386/avx512vl_vpclmulqdq.d | 8 + gas/testsuite/gas/i386/avx512vl_vpclmulqdq.s | 10 + gas/testsuite/gas/i386/i386.exp | 5 + gas/testsuite/gas/i386/ilp32/x86-64-sse2avx.d | 1226 +- gas/testsuite/gas/i386/optimize-1.d | 48 + gas/testsuite/gas/i386/optimize-1.s | 54 + gas/testsuite/gas/i386/optimize-1a.d | 48 + gas/testsuite/gas/i386/optimize-2.d | 70 + gas/testsuite/gas/i386/optimize-2.s | 80 + .../gas/i386/{optimize-2.d => optimize-2b.d} | 83 +- gas/testsuite/gas/i386/optimize-3.d | 8 + gas/testsuite/gas/i386/optimize-3.s | 9 + gas/testsuite/gas/i386/optimize-4.d | 48 + gas/testsuite/gas/i386/optimize-5.d | 56 + gas/testsuite/gas/i386/optimize-5.s | 9 + gas/testsuite/gas/i386/oversized16.l | 41 + gas/testsuite/gas/i386/oversized16.s | 11 + gas/testsuite/gas/i386/oversized64.l | 40 + gas/testsuite/gas/i386/oversized64.s | 10 + gas/testsuite/gas/i386/vpclmulqdq-intel.d | 4 + gas/testsuite/gas/i386/vpclmulqdq.d | 4 + gas/testsuite/gas/i386/vpclmulqdq.s | 5 + gas/testsuite/gas/i386/x86-64-avx-swap-2.d | 380 + gas/testsuite/gas/i386/x86-64-avx-swap-2.s | 393 + .../gas/i386/x86-64-avx512f_vpclmulqdq-intel.d | 4 + gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.d | 4 + gas/testsuite/gas/i386/x86-64-avx512f_vpclmulqdq.s | 5 + .../gas/i386/x86-64-avx512vl_vpclmulqdq-intel.d | 8 + .../gas/i386/x86-64-avx512vl_vpclmulqdq.d | 8 + .../gas/i386/x86-64-avx512vl_vpclmulqdq.s | 10 + gas/testsuite/gas/i386/x86-64-optimize-2.d | 48 + gas/testsuite/gas/i386/x86-64-optimize-2.s | 54 + gas/testsuite/gas/i386/x86-64-optimize-2a.d | 48 + gas/testsuite/gas/i386/x86-64-optimize-2b.d | 48 + gas/testsuite/gas/i386/x86-64-optimize-3.d | 80 + gas/testsuite/gas/i386/x86-64-optimize-3.s | 91 + .../{x86-64-optimize-3.d => x86-64-optimize-3b.d} | 109 +- gas/testsuite/gas/i386/x86-64-optimize-4.d | 8 + gas/testsuite/gas/i386/x86-64-optimize-4.s | 9 + gas/testsuite/gas/i386/x86-64-optimize-5.d | 48 + gas/testsuite/gas/i386/x86-64-optimize-6.d | 56 + gas/testsuite/gas/i386/x86-64-optimize-6.s | 9 + gas/testsuite/gas/i386/x86-64-sse2avx.d | 93 + gas/testsuite/gas/i386/x86-64-sse2avx.s | 93 + gas/testsuite/gas/i386/x86-64-vpclmulqdq-intel.d | 16 +- gas/testsuite/gas/i386/x86-64-vpclmulqdq.d | 16 +- gas/testsuite/gas/i386/x86-64-vpclmulqdq.s | 17 +- gas/write.c | 22 +- gdb/ChangeLog | 14 + gdb/ada-exp.y | 2 +- gdb/ada-lang.c | 12 +- gdb/ada-lang.h | 2 +- gdb/dwarf2read.c | 9 +- include/ChangeLog | 5 + include/opcode/aarch64.h | 2 +- ld/ChangeLog | 6 + ld/testsuite/ld-arm/unwind-4.d | 2 + libctf/ChangeLog | 76 + libctf/Makefile.am | 2 +- libctf/Makefile.in | 12 +- libctf/ctf-create.c | 185 +- libctf/ctf-dump.c | 6 +- libctf/ctf-hash.c | 52 +- libctf/ctf-impl.h | 49 +- libctf/ctf-open.c | 2 + libctf/ctf-string.c | 330 + libctf/ctf-util.c | 35 +- opcodes/ChangeLog | 116 + opcodes/aarch64-asm.c | 4 +- opcodes/aarch64-dis-2.c | 594 +- opcodes/aarch64-dis.c | 13 +- opcodes/aarch64-tbl.h | 15 +- opcodes/i386-dis-evex-mod.h | 20 - opcodes/i386-dis-evex-prefix.h | 10 +- opcodes/i386-dis-evex-w.h | 34 +- opcodes/i386-dis.c | 22 +- opcodes/i386-gen.c | 3 - opcodes/i386-init.h | 105 +- opcodes/i386-opc.h | 4 - opcodes/i386-opc.tbl | 457 +- opcodes/i386-tbl.h | 20462 ++++++++++--------- 98 files changed, 14361 insertions(+), 12351 deletions(-) copy gas/testsuite/gas/i386/{optimize-2.d => optimize-2b.d} (56%) create mode 100644 gas/testsuite/gas/i386/oversized16.l create mode 100644 gas/testsuite/gas/i386/oversized16.s create mode 100644 gas/testsuite/gas/i386/oversized64.l create mode 100644 gas/testsuite/gas/i386/oversized64.s create mode 100644 gas/testsuite/gas/i386/x86-64-avx-swap-2.d create mode 100644 gas/testsuite/gas/i386/x86-64-avx-swap-2.s copy gas/testsuite/gas/i386/{x86-64-optimize-3.d => x86-64-optimize-3b.d} (55%) create mode 100644 libctf/ctf-string.c -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 5 months

[toolchain/ci/base-artifacts] branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allnoconfig updated (c073976de -> 4ac5bc57b)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/gnu-master-arm-mainline-allnoconfig in repository toolchain/ci/base-artifacts. discards c073976de 0: update: binutils-gcc-linux: all new 4ac5bc57b 0: update: binutils-gcc-linux: all This update added new revisions after undoing existing revisions. That is to say, some revisions that were in the old version of the branch are not in the new version. This situation occurs when a user --force pushes a change and generates a repository containing something like this: * -- * -- B -- O -- O -- O (c073976de) \ N -- N -- N refs/heads/linaro-local/ci/tcwg_kernel/gnu-master-arm-ma [...] You should already have received notification emails for all of the O revisions, and so the following emails describe only the N revisions from the common base, B. Any revisions marked "omits" are not gone; other references still refer to them. Any revisions marked "discards" are gone forever. The 1 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: 01-reset_artifacts/console.log | 14 +- 02-prepare_abe/console.log | 434 +- 03-build_abe-binutils/console.log | 11323 ++++++------- 04-build_abe-stage1/console.log | 19755 +++++++++++----------- 05-build_linux/console.log | 654 +- 06-boot_linux/console.log | 2 +- console.log | 32267 ++++++++++++++++++------------------ jenkins/manifest.sh | 12 +- 8 files changed, 32208 insertions(+), 32253 deletions(-) -- To stop receiving notification emails like this one, please contact the administrator of this repository.

5 years, 5 months

[toolchain/ci/llvm-project] branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig updated (706b48251f6 -> d7fcee62f11)

by git＠git.linaro.org

This is an automated email from the git hooks/post-receive script. tcwg-buildslave pushed a change to branch linaro-local/ci/tcwg_kernel/llvm-master-arm-stable-defconfig in repository toolchain/ci/llvm-project. from 706b48251f6 [InstCombine] canonicalize fcmp+select to minnum/maxnum intrinsics adds 135cf982e8e Revert "[GDBRemote] Remove code that flushes GDB remote packets" adds bb0b44deaab Clean up MSVC visualization of LLVM pointer types adds fb133b0aabe Various tweaks to MSVC natvis visualizers adds d1728f89878 [X86] Add MOVHPDrm/MOVLPDrm patterns that use VZEXT_LOAD. adds fc233c9108d [X86] Add some additional load folding tests to vec_int_to_ [...] adds 4ca81a9b994 [X86] Add a DAG combine to replace vector loads feeding a v [...] adds 29fff0797b2 [X86] Improve the type checking fast-isel handling of vecto [...] adds fcda45a9eb8 [X86] Add more load folding tests for vcvt(t)ps2(u)qq showi [...] adds b739b91cd3a [clangd] Make FixIt message be consistent with the clang-ti [...] adds 0384a780549 [libcxx] [test] Add void cast to result of compare_exchange [...] adds 98722691b0b [ARM] WLS/LE Code Generation adds d4097b4a93a [SimpleLoopUnswitch] Implement handling of prof branch_weig [...] adds 9d34f4569b4 [clangd] Show better message when we rename macros. adds d2b6665e339 [DebugInfo] Avoid adding too much indirection to pointer-va [...] adds 0f82f64c832 [NFC][InstCombine] Copy test for omit urem when possible fr [...] adds f55818e3a72 [InstCombine] Omit 'urem' where possible adds 4f878fe3a7d [NFC][InstCombine] Tests for x - ~(y) -> x + y + 1 fold ( [...] adds 9cca81344c8 [clangd] Make PreambleStatusCache handle filenames more carefully adds 60300c9c7d6 [clangd] Fix unused var from r364735 adds d74f2d0a860 [benchmark] Disable CMake get_git_version adds ed13fef4774 [SelectionDAG] Do minnum->minimum at legalization time inst [...] adds 0f73709cb71 Remove null checks of results of new expressions adds 172fe5dd191 [X86] CombineShuffleWithExtract - updated description comme [...] adds 92e78b7bedb [RISCV] Add break; to the last switch case adds 881aab4dc3d [clangd] No longer getting template instantiations from hea [...] adds 4f0a3772805 Fix TestGdbRemoteLibrariesSvr4Support adds d5c3e34cb7e [NFC][InstCombine] Tests for ((~x) + y) + 1 -> y - x fold [...] adds 33c8c0ea275 [AMDGPU] Call isLoopExiting for blocks in the loop. adds 08c38f77c5f Revert "Implement xfer:libraries-svr4:read packet" adds 17c3eafb2e3 [ASTImporter] Propagate error from ImportDeclContext adds 77c04c3a577 @skipIfXmlSupportMissing TestRecognizeBreakpoint adds c12dfcf1f56 Don't check the validity of newly contructed data buffers adds 3a10810b7ab [mips] Add missing schedinfo for ADJCALLSTACKDOWN, ADJCALLSTACKUP adds c0121bf8741 [mips] Add missing schedinfo for atomic instructions adds ceb9da5bc79 [mips] Add missing schedinfo for MSA and ASE instructions adds fbf67d88de2 GlobalISel: Add DAG compat for G_FCANONICALIZE adds 01bb075c1f9 GlobalISel: Add GINodeEquiv for min/max adds 5dafcb9b118 AMDGPU/GlobalISel: Use and instead of BFE with inline immediate adds 9f992c238ab AMDGPU/GlobalISel: Fix scc->vcc copy handling adds facf69e8449 AMDGPU/GlobalISel: Use vcc reg bank for amdgcn.wqm.vote adds c23149f612d AMDGPU/GlobalISel: RegBankSelect for WWM/WQM adds 9f3645869cf [NFC][InstCombine] Improve test coverage for ((~x) + y) + [...] adds 3b7668ae4bb AMDGPU/GlobalISel: Improve icmp selection coverage. adds 89fc8bcdd6d AMDGPU/GlobalISel: Fail on store to 32-bit address space adds b5fc94f3e74 AMDGPU/GlobalISel: Fix RegBankSelect for G_BUILD_VECTOR adds 5bf850d52e0 AMDGPU/GlobalISel: Fix RegBankSelect for G_FCANONICALIZE adds 1b317685e9b AMDGPU: Convert some places to Register adds 511ad50db41 [Hexagon] Rework VLCR algorithm adds 1ad4b99d948 [ASTImporter] Mark erroneous nodes in from ctx adds 34a0b16e290 [NFC][InstCombine] Better commutative tests for "shift amou [...] adds 3f594ed1686 Fix lookup of symbols at the same address with no size vs. size adds 4f769361e35 [ASTImporter] Silence unused variable warning in Release bu [...] adds ee6539341bf [UpdateTestChecks][PowerPC] Avoid empty string when scrubbi [...] adds 535f39ce521 Revert "[lldb] [Process/NetBSD] Fix constructor after r363707" adds 28145735f7b [RISCV] Avoid save-restore target feature warning adds 2ba16011c13 Fixup r364512 adds 2b2ad9342e6 [lldb] [Process/NetBSD] Support reading YMM registers via P [...] adds baf64b65056 [lldb] [Process/NetBSD] Fix segfault when handling watchpoint adds 0856721e3a0 [lldb] [Process/NetBSD] Use global enable bits for watchpoints adds 4f64ade04cb AMDGPU/GlobalISel: Select src modifiers adds fb99fc7a689 AMDGPU: Fix tests using the default alloca address space adds 1daad91af69 AMDGPU/GlobalISel: Tolerate copies with no type set adds 2afbfb6b226 [ASTImporter] Mark erroneous nodes in shared st adds 6464280eb04 AMDGPU/GlobalISel: Select G_BRCOND for scc conditions adds fdf36729c71 AMDGPU/GlobalISel: Make s16 select legal adds 7cfd99ab15d AMDGPU/GFX10: fix scratch resource descriptor adds cda82f0bb6f AMDGPU/GlobalISel: Select G_FRAME_INDEX adds 5abf80cdfa3 [Hexagon] Custom-lower UADDO(x, 1) and USUBO(x, 1) adds 72b8d41ce81 [InstCombine] Shift amount reassociation in bittest (PR42399) adds 04d3d3bbff5 [InstCombine] (Y + ~X) + 1 --> Y - X fold (PR42459) adds 657f8c16c19 Update email address in CODE_OWNERS adds 4a9e3f15bbb [ARM] MVE: support QQPRRegClass and QQQQPRRegClass adds 2ab25f9ceb1 AMDGPU/GlobalISel: Select G_BRCOND for vcc adds 8b2e304bc57 [ARM] Fix MVE_VQxDMLxDH instruction class adds 9e9dd30de3a AMDGPU/GlobalISel: Implement select for 32-bit G_ADD adds ba41d3b1fd6 Fix -Wdouble-promotion warnings. adds 4603460a395 __threading_support: Remove (void) in favor of (). adds 90c57e00015 [docs][llvm-readelf] Expand llvm-readelf documentation adds 62d64b0c308 AMDGPU/GlobalISel: RegBankSelect for readlane/readfirstlane adds 3c125fe821c Implement LWG2221: 'Formatted output for nullptr_t' Reviewe [...] adds e3e38cce4ab [X86] Add widenSubVector to size in bits helper. NFCI. adds d810ff25888 AMDGPU/GlobalISel: Try to select VOP3 form of add adds e1006259d84 AMDGPU/GlobalISel: Select G_PHI adds 0a52e9d026a AMDGPU/GlobalISel: Complete implementation of G_GEP adds a310727830f AMDGPU/GlobalISel: Fail instead of assert when selecting loads adds 265059eaf6c AMDGPU/GlobalISel: RegBankSelect for amdgcn.writelane adds 8cae7d79b55 Summary: [Clangd] Added hidden command line option -tweaks [...] adds 732149b24eb AArch64/GlobalISel: Fix trying to select invalid MIR adds 1094e6a8143 AMDGPU/GlobalISel: RegBankSelect for DS ordered add/swap adds f01fa40a006 [ELF][RISCV] Support PLT, GOT, copy and relative relocations adds ddc57afab9e [ELF][RISCV] Support GD/LD/IE/LE TLS models adds 4dc3b2bf95b AMDGPU: Support GDS atomics adds 10c911db63e AMDGPU/GFX10: implement ds_ordered_count changes adds 6f74f557500 GlobalISel: Implement lower for min/max adds 40d1faf38f9 AMDGPU/GlobalISel: Legalize s16 fcmp adds e9345866809 [TSan] Improve handling of stack pointer mangling in {set,l [...] adds b2ea20eedd6 AMDGPU/GlobalISel: RegBankSelect for sendmsg/sendmsghalt adds b600ae37a52 [OPENMP]Fix handling of lambda captures in target regions. adds 1023a2eca3f [GlobalISel]: Allow backends to custom legalize Intrinsics adds 03ca176ab32 GlobalISel: Verify G_MERGE_VALUES operand sizes adds b7fb723ea38 [TSan] Fix initialized and declared ‘extern’ warning adds e62857786f9 [NFC][InstCombine] Add tests for "shift direction in bittes [...] adds 9470bb262b5 AMDGPU/GlobalISel: Fix allowing non-boolean conditions for [...] adds 55d2e6f1c26 [lldb] [lldbsuite] Use a unique class name for TestBacktraceAll adds ef59cb69822 AMDGPU/GlobalISel: Legalize s16 add/sub/mul adds 7f8c7209397 AMDGPU/GlobalISel: Add tests for add legalization adds e20030f6121 [X86] Avoid SFB - Fix inconsistent codegen with/without deb [...] adds 5a7d5111e58 AMDGPU/GlobalISel: Lower SALU min/max to cmp+select adds 4073b33786c AMDGPU/GlobalISel: Handle 16-bit SALU min/max adds e15770aec42 AMDGPU/GlobalISel: Custom lower control flow intrinsics adds e2c86cce3a2 AMDGPU/GlobalISel: Legalize workitem ID intrinsics adds 756d81905f6 AMDGPU/GlobalISel: Legalize workgroup ID intrinsics adds 9e8e8c60fa1 AMDGPU/GlobalISel: Lower kernarg segment ptr intrinsics adds bae3636f969 AMDGPU/GlobalISel: Handle more input argument intrinsics adds b101c39f587 Fixed two issues in clang-tidy -help. adds 5e7815b695d [X86] Correct v4f32->v2i64 cvt(t)ps2(u)qq memory isel patterns adds 73dec22c3ef AMDGPU: Revert accidental change to test adds 24edf8ef4b5 Implement P0646R1: Erase-Like Algorithms Should Return size [...] adds c9f14f29f5c GlobalISel: Try to widen merges with other merges adds d1523f7a8c2 Ensure bitset's string constructor doesn't poison the overl [...] new 8b7a0baa20c Testing commit access through minor formatting change new 975120a21b4 [NFC][InstCombine] More commutative tests for "shift direct [...] new d7fcee62f11 [Core] Generalize ValueObject::IsRuntimeSupportValue The 3 revisions listed above as "new" are entirely new to this repository and will be described in separate emails. The revisions listed as "adds" were already present in the repository and have only been added to this reference. Summary of changes: .../clang-tidy/tool/ClangTidyMain.cpp | 4 +- clang-tools-extra/clangd/ClangdServer.cpp | 3 +- clang-tools-extra/clangd/ClangdServer.h | 7 +- clang-tools-extra/clangd/ClangdUnit.cpp | 3 +- clang-tools-extra/clangd/Diagnostics.cpp | 2 + clang-tools-extra/clangd/FS.cpp | 19 +- clang-tools-extra/clangd/SourceCode.cpp | 27 + clang-tools-extra/clangd/SourceCode.h | 8 + clang-tools-extra/clangd/XRefs.cpp | 76 +- clang-tools-extra/clangd/refactor/Rename.cpp | 43 +- .../clangd/test/fixits-duplication.test | 2 +- clang-tools-extra/clangd/tool/ClangdMain.cpp | 11 + .../clangd/unittests/ClangdUnitTests.cpp | 20 + .../clangd/unittests/DiagnosticsTests.cpp | 22 +- clang-tools-extra/clangd/unittests/FSTests.cpp | 12 +- clang-tools-extra/clangd/unittests/RenameTests.cpp | 7 + .../clangd/unittests/SourceCodeTests.cpp | 17 + clang-tools-extra/docs/clang-tidy/index.rst | 210 +-- clang/include/clang/AST/ASTImporter.h | 144 +- clang/include/clang/AST/ASTImporterSharedState.h | 80 + clang/include/clang/CrossTU/CrossTranslationUnit.h | 6 +- clang/include/clang/Sema/Sema.h | 4 + clang/lib/AST/ASTImporter.cpp | 112 +- clang/lib/CrossTU/CrossTranslationUnit.cpp | 10 +- clang/lib/Driver/ToolChains/Arch/RISCV.cpp | 8 +- clang/lib/Frontend/ASTMerge.cpp | 6 +- clang/lib/Sema/SemaExpr.cpp | 2 + clang/lib/Sema/SemaOpenMP.cpp | 97 +- clang/lib/Tooling/CommonOptionsParser.cpp | 2 +- clang/test/Driver/riscv-features.c | 8 +- clang/test/OpenMP/nvptx_lambda_capturing.cpp | 10 +- clang/unittests/AST/ASTImporterFixtures.cpp | 45 +- clang/unittests/AST/ASTImporterFixtures.h | 28 +- clang/unittests/AST/ASTImporterTest.cpp | 367 +++- clang/utils/ClangVisualizers/clang.natvis | 54 +- compiler-rt/lib/tsan/rtl/tsan_interceptors.cc | 11 +- compiler-rt/lib/tsan/rtl/tsan_platform_linux.cc | 7 +- compiler-rt/lib/tsan/rtl/tsan_rtl.h | 1 - libcxx/include/__threading_support | 4 +- libcxx/include/bitset | 4 +- libcxx/include/forward_list | 43 +- libcxx/include/limits | 2 +- libcxx/include/list | 34 +- libcxx/include/ostream | 5 + libcxx/include/type_traits | 4 + libcxx/include/utility | 4 +- .../atomics.general/replace_failure_order.pass.cpp | 8 +- .../forwardlist/forwardlist.ops/remove.pass.cpp | 24 +- .../forwardlist/forwardlist.ops/remove_if.pass.cpp | 20 +- .../forwardlist/forwardlist.ops/unique.pass.cpp | 20 +- .../sequences/list/list.ops/remove.pass.cpp | 8 +- .../sequences/list/list.ops/remove_if.pass.cpp | 6 +- .../sequences/list/list.ops/unique.pass.cpp | 4 +- .../ostream.inserters/streambuf.pass.cpp | 7 + .../bitset.cons/string_ctor.pass.cpp | 13 + libcxx/www/cxx1z_status.html | 2 +- lld/ELF/Arch/RISCV.cpp | 154 +- lld/ELF/InputSection.cpp | 5 +- lld/ELF/Relocations.cpp | 2 +- lld/test/ELF/riscv-plt.s | 103 ++ lld/test/ELF/riscv-reloc-64-pic.s | 10 + lld/test/ELF/riscv-reloc-copy.s | 23 + lld/test/ELF/riscv-reloc-got.s | 65 + lld/test/ELF/riscv-tls-gd.s | 124 ++ lld/test/ELF/riscv-tls-ie.s | 82 + lld/test/ELF/riscv-tls-ld.s | 90 + lld/test/ELF/riscv-tls-le.s | 41 + lld/test/ELF/riscv32-reloc-32-pic.s | 23 + lld/test/ELF/riscv64-reloc-64-pic.s | 23 + .../lldb/Host/common/NativeProcessProtocol.h | 14 - lldb/include/lldb/Target/CPPLanguageRuntime.h | 2 +- lldb/include/lldb/Target/LanguageRuntime.h | 6 +- lldb/include/lldb/Target/ObjCLanguageRuntime.h | 3 +- lldb/lit/SymbolFile/Inputs/sizeless-symbol.s | 8 + lldb/lit/SymbolFile/sizeless-symbol.test | 14 + .../gdb_remote_client/TestRecognizeBreakpoint.py | 1 + .../thread/backtrace_all/TestBacktraceAll.py | 2 +- .../hello_watchlocation/TestWatchLocation.py | 1 - .../hello_watchpoint/TestMyFirstWatchpoint.py | 1 - .../watchpoint/multiple_hits/TestMultipleHits.py | 1 - .../TestWatchpointMultipleThreads.py | 2 - .../step_over_watchpoint/TestStepOverWatchpoint.py | 1 - .../watchpoint_commands/TestWatchpointCommands.py | 4 - .../command/TestWatchpointCommandLLDB.py | 2 - .../command/TestWatchpointCommandPython.py | 2 - .../condition/TestWatchpointConditionCmd.py | 1 - .../watchpoint_disable/TestWatchpointDisable.py | 1 - .../TestWatchLocationWithWatchSet.py | 1 - .../watchpoint_size/TestWatchpointSizes.py | 3 - .../test/tools/lldb-server/gdbremote_testcase.py | 29 +- .../test/tools/lldb-server/libraries-svr4/Makefile | 17 - .../TestGdbRemoteLibrariesSvr4Support.py | 130 -- .../test/tools/lldb-server/libraries-svr4/main.cpp | 15 - .../tools/lldb-server/libraries-svr4/svr4lib_a.cpp | 9 - .../tools/lldb-server/libraries-svr4/svr4lib_a.mk | 9 - .../lldb-server/libraries-svr4/svr4lib_b_quote.cpp | 9 - .../lldb-server/libraries-svr4/svr4lib_b_quote.mk | 9 - lldb/source/Core/ValueObject.cpp | 32 +- .../Plugins/ObjectFile/JIT/ObjectFileJIT.cpp | 14 +- .../RegisterContextPOSIXProcessMonitor_arm.cpp | 2 +- .../RegisterContextPOSIXProcessMonitor_arm64.cpp | 2 +- .../RegisterContextPOSIXProcessMonitor_mips64.cpp | 2 +- .../RegisterContextPOSIXProcessMonitor_powerpc.cpp | 2 +- .../RegisterContextPOSIXProcessMonitor_x86.cpp | 2 +- .../Plugins/Process/Linux/NativeProcessLinux.cpp | 2 +- .../Linux/NativeRegisterContextLinux_arm.cpp | 11 - .../Linux/NativeRegisterContextLinux_arm64.cpp | 11 - .../Linux/NativeRegisterContextLinux_mips64.cpp | 14 - .../Linux/NativeRegisterContextLinux_ppc64le.cpp | 11 - .../Linux/NativeRegisterContextLinux_s390x.cpp | 14 - .../Plugins/Process/NetBSD/NativeProcessNetBSD.cpp | 33 +- .../Plugins/Process/NetBSD/NativeProcessNetBSD.h | 4 +- .../NetBSD/NativeRegisterContextNetBSD_x86_64.cpp | 107 +- .../NetBSD/NativeRegisterContextNetBSD_x86_64.h | 10 +- .../Plugins/Process/POSIX/NativeProcessELF.cpp | 69 - .../Plugins/Process/POSIX/NativeProcessELF.h | 7 - .../Utility/RegisterContextDarwin_arm64.cpp | 4 +- .../Process/Utility/RegisterContextDarwin_i386.cpp | 3 +- .../Utility/RegisterContextDarwin_x86_64.cpp | 3 +- .../gdb-remote/GDBRemoteCommunicationClient.cpp | 7 + .../GDBRemoteCommunicationServerCommon.cpp | 1 - .../GDBRemoteCommunicationServerLLGS.cpp | 43 - .../gdb-remote/GDBRemoteCommunicationServerLLGS.h | 2 - .../SymbolFile/DWARF/DWARFASTParserClang.cpp | 3 +- lldb/source/Symbol/Function.cpp | 8 +- lldb/source/Symbol/Symtab.cpp | 10 +- lldb/source/Target/CPPLanguageRuntime.cpp | 16 +- lldb/source/Target/ObjCLanguageRuntime.cpp | 13 - llvm/CODE_OWNERS.TXT | 2 +- .../{llvm-readobj.rst => llvm-readelf.rst} | 231 +-- llvm/docs/CommandGuide/llvm-readobj.rst | 24 + .../llvm/CodeGen/GlobalISel/LegalizerHelper.h | 1 + .../llvm/CodeGen/GlobalISel/LegalizerInfo.h | 5 + llvm/include/llvm/IR/DebugInfoMetadata.h | 4 + llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 2 + .../llvm/Target/GlobalISel/SelectionDAGCompat.td | 5 + llvm/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp | 5 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 22 +- llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp | 70 +- llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp | 6 + llvm/lib/CodeGen/HardwareLoops.cpp | 1 + llvm/lib/CodeGen/MachineVerifier.cpp | 10 + llvm/lib/CodeGen/PrologEpilogInserter.cpp | 13 +- .../CodeGen/SelectionDAG/SelectionDAGBuilder.cpp | 22 +- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 11 + llvm/lib/IR/DebugInfoMetadata.cpp | 21 + .../Target/AArch64/AArch64InstructionSelector.cpp | 33 +- llvm/lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h | 15 +- llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp | 161 +- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 17 +- .../Target/AMDGPU/AMDGPUInstructionSelector.cpp | 441 +++-- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h | 15 +- llvm/lib/Target/AMDGPU/AMDGPUInstructions.td | 21 + llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 244 ++- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h | 18 + llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp | 361 +++- llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.h | 7 + .../Target/AMDGPU/AMDGPUTargetTransformInfo.cpp | 11 +- llvm/lib/Target/AMDGPU/DSInstructions.td | 88 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 29 +- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 4 +- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 2 + llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 7 +- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h | 9 +- llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 4 +- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp | 10 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 47 +- llvm/lib/Target/ARM/ARMISelLowering.h | 2 + llvm/lib/Target/ARM/ARMInstrInfo.td | 8 + llvm/lib/Target/ARM/ARMInstrMVE.td | 15 +- llvm/lib/Target/ARM/ARMInstrThumb2.td | 10 +- llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp | 116 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 2 + llvm/lib/Target/Hexagon/HexagonISelLowering.cpp | 43 +- llvm/lib/Target/Hexagon/HexagonISelLowering.h | 1 + .../Hexagon/HexagonVectorLoopCarriedReuse.cpp | 220 ++- llvm/lib/Target/Mips/MipsDSPInstrInfo.td | 1 + llvm/lib/Target/Mips/MipsInstrInfo.td | 11 +- llvm/lib/Target/Mips/MipsMSAInstrInfo.td | 7 +- llvm/lib/Target/Mips/MipsScheduleP5600.td | 22 + llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 1 + .../Target/X86/X86AvoidStoreForwardingBlocks.cpp | 4 + llvm/lib/Target/X86/X86FastISel.cpp | 21 +- llvm/lib/Target/X86/X86ISelLowering.cpp | 95 +- llvm/lib/Target/X86/X86InstrAVX512.td | 78 +- llvm/lib/Target/X86/X86InstrSSE.td | 12 + .../Transforms/InstCombine/InstCombineAddSub.cpp | 5 +- .../Transforms/InstCombine/InstCombineCompares.cpp | 84 +- llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp | 56 +- .../CodeGen/AMDGPU/GlobalISel/inst-select-add.mir | 56 + .../inst-select-amdgcn.kernarg.segment.ptr.mir | 19 - .../AMDGPU/GlobalISel/inst-select-anyext.mir | 36 + .../CodeGen/AMDGPU/GlobalISel/inst-select-br.mir | 21 + .../AMDGPU/GlobalISel/inst-select-brcond.mir | 198 +++ .../CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir | 170 +- .../GlobalISel/inst-select-fcanonicalize.mir | 164 ++ .../CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir | 190 +- .../AMDGPU/GlobalISel/inst-select-frame-index.mir | 38 + .../CodeGen/AMDGPU/GlobalISel/inst-select-gep.mir | 354 ++++ .../AMDGPU/GlobalISel/inst-select-icmp.s64.mir | 595 +++++++ .../AMDGPU/GlobalISel/inst-select-implicit-def.mir | 6 +- .../AMDGPU/GlobalISel/inst-select-load-smrd.mir | 44 +- .../AMDGPU/GlobalISel/inst-select-phi-invalid.mir | 31 + .../CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir | 385 ++++ .../AMDGPU/GlobalISel/inst-select-select.mir | 176 ++ .../CodeGen/AMDGPU/GlobalISel/inst-select-sext.mir | 39 + .../CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir | 83 + .../CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir | 83 + .../CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir | 83 + .../CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir | 83 + .../CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir | 48 +- .../irtranslator-amdgpu_kernel-system-sgprs.ll | 118 +- .../AMDGPU/GlobalISel/irtranslator-amdgpu_ps.ll | 2 +- .../AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll | 18 +- .../GlobalISel/irtranslator-fast-math-flags.ll | 2 +- .../CodeGen/AMDGPU/GlobalISel/legalize-add.mir | 233 ++- .../GlobalISel/legalize-amdgcn.if-invalid.mir | 73 + .../CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir | 126 +- .../CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir | 323 +++- .../CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir | 20 +- .../AMDGPU/GlobalISel/legalize-merge-values.mir | 345 +++- .../CodeGen/AMDGPU/GlobalISel/legalize-mul.mir | 285 ++- .../CodeGen/AMDGPU/GlobalISel/legalize-select.mir | 110 +- .../CodeGen/AMDGPU/GlobalISel/legalize-sub.mir | 146 +- .../AMDGPU/GlobalISel/llvm.amdgcn.dispatch.id.ll | 19 + .../AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll | 18 + .../GlobalISel/llvm.amdgcn.implicit.buffer.ptr.ll | 17 + .../GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll | 125 ++ .../AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll | 18 + .../AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll | 106 ++ .../AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll | 92 + .../regbankselect-amdgcn.ds.ordered.add.mir | 71 + .../regbankselect-amdgcn.ds.ordered.swap.mir | 71 + .../regbankselect-amdgcn.readfirstlane.mir | 32 + .../GlobalISel/regbankselect-amdgcn.readlane.mir | 71 + .../GlobalISel/regbankselect-amdgcn.s.sendmsg.mir | 32 + .../regbankselect-amdgcn.s.sendmsghalt.mir | 32 + .../AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir | 31 + ...-vote.mir => regbankselect-amdgcn.wqm.vote.mir} | 10 +- .../GlobalISel/regbankselect-amdgcn.writelane.mir | 98 ++ .../AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir | 31 + .../GlobalISel/regbankselect-build-vector.mir | 69 + .../GlobalISel/regbankselect-fcanonicalize.mir | 35 + .../AMDGPU/GlobalISel/regbankselect-phi.mir | 1849 +++++++++++++------- .../AMDGPU/GlobalISel/regbankselect-select.mir | 1451 ++++++++++----- .../AMDGPU/GlobalISel/regbankselect-smax.mir | 170 +- .../AMDGPU/GlobalISel/regbankselect-smin.mir | 170 +- .../AMDGPU/GlobalISel/regbankselect-umax.mir | 170 +- .../AMDGPU/GlobalISel/regbankselect-umin.mir | 170 +- llvm/test/CodeGen/AMDGPU/gds-atomic.ll | 128 ++ .../AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll | 23 + llvm/test/CodeGen/AMDGPU/loop-idiom.ll | 13 +- llvm/test/CodeGen/AMDGPU/scratch-simple.ll | 65 +- llvm/test/CodeGen/AMDGPU/unroll.ll | 17 +- ...exagon_vector_loop_carried_reuse_commutative.ll | 82 + llvm/test/CodeGen/Hexagon/isel-uaddo-1.ll | 37 + llvm/test/CodeGen/PowerPC/PR35812-neg-cmpxchg.ll | 178 +- .../Thumb2/LowOverheadLoops}/cond-mov.mir | 0 .../CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll | 213 +++ .../Thumb2/LowOverheadLoops}/massive.mir | 0 .../LowOverheadLoops}/multiblock-massive.mir | 0 .../Thumb2/LowOverheadLoops}/revert-after-call.mir | 0 .../LowOverheadLoops}/revert-after-spill.mir | 0 .../Thumb2/LowOverheadLoops/revert-while.mir | 130 ++ .../Thumb2/LowOverheadLoops}/size-limit.mir | 0 .../Thumb2/LowOverheadLoops}/switch.mir | 0 .../test/CodeGen/Thumb2/LowOverheadLoops/while.mir | 131 ++ llvm/test/CodeGen/WebAssembly/f32.ll | 18 + llvm/test/CodeGen/WebAssembly/simd-arith.ll | 22 + llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir | 198 +++ llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir | 223 +++ llvm/test/CodeGen/X86/avx512dqvl-intrinsics.ll | 655 ++++++- .../CodeGen/X86/merge-consecutive-loads-128.ll | 3 +- llvm/test/CodeGen/X86/pr42452.ll | 37 + llvm/test/CodeGen/X86/vec_fp_to_int-widen.ll | 150 ++ llvm/test/CodeGen/X86/vec_fp_to_int.ll | 150 ++ llvm/test/CodeGen/X86/vec_int_to_fp-widen.ll | 794 +++++++-- llvm/test/CodeGen/X86/vec_int_to_fp.ll | 472 +++-- .../MIR/X86/prolog-epilog-indirection.mir | 130 ++ llvm/test/MachineVerifier/test_g_merge_values.mir | 28 + llvm/test/Transforms/HardwareLoops/ARM/do-rem.ll | 32 +- .../Transforms/HardwareLoops/ARM/fp-emulation.ll | 23 +- .../test/Transforms/HardwareLoops/ARM/simple-do.ll | 42 +- .../test/Transforms/HardwareLoops/ARM/structure.ll | 95 +- llvm/test/Transforms/InstCombine/add.ll | 10 +- ...ld-inc-of-add-of-not-x-and-y-to-sub-x-from-y.ll | 213 +++ .../InstCombine/fold-sub-of-not-to-inc-of-add.ll | 94 + ...ower-of-two-or-zero-when-comparing-with-zero.ll | 166 ++ .../shift-amount-reassociation-in-bittest.ll | 318 ++-- .../InstCombine/shift-direction-in-bit-test.ll | 279 +++ .../SimpleLoopUnswitch/basictest-profmd.ll | 34 + .../SimpleLoopUnswitch/trivial-unswitch-profmd.ll | 228 +++ .../CodeGen/GlobalISel/LegalizerHelperTest.cpp | 78 + llvm/utils/LLVMVisualizers/llvm.natvis | 19 +- llvm/utils/UpdateTestChecks/asm.py | 4 +- llvm/utils/benchmark/CMakeLists.txt | 7 +- llvm/utils/benchmark/README.LLVM | 2 + 297 files changed, 17529 insertions(+), 3697 deletions(-) create mode 100644 clang/include/clang/AST/ASTImporterSharedState.h create mode 100644 lld/test/ELF/riscv-plt.s create mode 100644 lld/test/ELF/riscv-reloc-64-pic.s create mode 100644 lld/test/ELF/riscv-reloc-copy.s create mode 100644 lld/test/ELF/riscv-reloc-got.s create mode 100644 lld/test/ELF/riscv-tls-gd.s create mode 100644 lld/test/ELF/riscv-tls-ie.s create mode 100644 lld/test/ELF/riscv-tls-ld.s create mode 100644 lld/test/ELF/riscv-tls-le.s create mode 100644 lld/test/ELF/riscv32-reloc-32-pic.s create mode 100644 lld/test/ELF/riscv64-reloc-64-pic.s create mode 100644 lldb/lit/SymbolFile/Inputs/sizeless-symbol.s create mode 100644 lldb/lit/SymbolFile/sizeless-symbol.test delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] delete mode 100644 lldb/packages/Python/lldbsuite/test/tools/lldb-server/libraries [...] copy llvm/docs/CommandGuide/{llvm-readobj.rst => llvm-readelf.rst} (57%) create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir delete mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.kernarg. [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-gep.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi-invalid.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-select.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-amdgcn.if-invalid.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.id.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.dispatch.ptr.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.implicit.buffer.ptr.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.kernarg.segment.ptr.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.queue.ptr.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workgroup.id.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ord [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ord [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfi [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.send [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir rename llvm/test/CodeGen/AMDGPU/GlobalISel/{regbankselect-amdgcn-wqm-vote.mir => r [...] create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir create mode 100644 llvm/test/CodeGen/AMDGPU/gds-atomic.ll create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ds.ordered.add.gfx10.ll create mode 100644 llvm/test/CodeGen/Hexagon/hexagon_vector_loop_carried_reuse_com [...] create mode 100644 llvm/test/CodeGen/Hexagon/isel-uaddo-1.ll rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-guards.ll rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-while.mir rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] rename llvm/test/{Transforms/HardwareLoops/ARM => CodeGen/Thumb2/LowOverheadLoops} [...] create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/while.mir create mode 100644 llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir create mode 100644 llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir create mode 100644 llvm/test/CodeGen/X86/pr42452.ll create mode 100644 llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir create mode 100644 llvm/test/MachineVerifier/test_g_merge_values.mir create mode 100644 llvm/test/Transforms/InstCombine/fold-inc-of-add-of-not-x-and-y [...] create mode 100644 llvm/test/Transforms/InstCombine/fold-sub-of-not-to-inc-of-add.ll create mode 100644 llvm/test/Transforms/InstCombine/omit-urem-of-power-of-two-or-z [...] create mode 100644 llvm/test/Transforms/InstCombine/shift-direction-in-bit-test.ll create mode 100644 llvm/test/Transforms/SimpleLoopUnswitch/basictest-profmd.ll create mode 100644 llvm/test/Transforms/SimpleLoopUnswitch/trivial-unswitch-profmd.ll -- To stop receiving notification emails like this one, please contact the administrator of this repository.

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